N-bit successive approximation register analog-to-digital converter and calibration method thereof, receiver, base station and mobile device

Abstract

To provide a Successive Approximation Register Analog-to-Digital Converter (SAR ADC).SOLUTION: A SAR ADC 100 comprises a plurality of sampling cells 110, 120, 130, 140 for each bit of n bits. Each sampling cell comprises a capacitive element 111 coupled to a cell output, and further comprises a first switch circuit capable of selectively coupling a first signal 101 to the capacitive element, and a second switch circuit capable of selectively coupling one of a second signal 102 and a third signal 103, which exhibits the polarity opposite to that of the second signal, to the capacitive element. At least one comparator circuit 150 is configured to output a comparison signal based on cell output signals of the sampling cells. Additionally, the SAR ADC comprises a calibration circuit 160 configured to supply at least one corresponding control signal to each second switch circuit for controlling the second switch circuits.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] This disclosure relates to analog-to-digital conversion. In particular, examples relate to an n-bit successive approximation register analog-to-digital converter (SAR ADC) and a calibration method thereof. Further examples relate to receivers, base stations, and mobile devices. [Background technology]

[0002] The split-capacitor SAR ADC architecture has significant advantages from an analog implementation perspective. However, traditional split-capacitor SAR ADCs are difficult to calibrate because the least significant bit (LSB) weight of a split-capacitor SAR ADC is not a function of the comparator decision. As a result, it is difficult to estimate the LSB. However, the weight of the LSB is an important quantity. For example, estimating the LSB weight is important when using a split-capacitor SAR ADC in a pipeline ADC. Summary of the Invention

[0003] Therefore, there may be a need for an improved SAR ADC architecture. [Brief description of the drawings]

[0004] Some examples of apparatus and / or methods are now described, by way of example only, with reference to the accompanying drawings, in which:

[0005] [Figure 1] An example of an n-bit SAR ADC is shown. [Diagram 2] 1 shows a first example of a decision threshold. [Diagram 3] 2 shows a second example of a decision threshold. [Figure 4] 4 shows a third example of a decision threshold. [Diagram 5] 2 shows another example of an n-bit SAR ADC. [Figure 6] 1 shows an example of a base station. [Figure 7]1 illustrates an example of a mobile device. [Figure 8] 1 shows a flowchart of an example method for calibrating an n-bit SAR ADC. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0006] Various examples will now be described in more detail with reference to the accompanying drawings, in which some examples are shown and in which thicknesses of lines, layers and / or regions may be exaggerated for clarity.

[0007] Thus, while further examples are susceptible to various modifications and alternative forms, some specific examples are shown in the figures and will be described in detail below. However, this detailed description does not limit the further examples to the specific forms described. The further examples may cover all modifications, equivalents, and alternatives falling within the scope of the present disclosure. The same or similar numbers refer to similar or similar elements throughout the description of the figures and may be implemented in the same or modified form when compared to one another while providing the same or similar functionality.

[0008] When an element is referred to as being "connected" or "coupled" to another element, it will be understood that the elements may be directly connected or coupled via one or more intervening elements. When two elements A and B are coupled using "or", this shall be understood to disclose all possible combinations, i.e. A only, B only, and A and B, unless otherwise expressly or implicitly defined. Alternative expressions of the same combination are "at least one of A and B" or "A and / or B". The same applies, mutatis mutandis, to combinations of more than two elements.

[0009] Terms used herein for the purpose of describing particular examples are not intended to be limiting to further examples. Whenever singular forms such as "a," "an," "the," etc. are used and are not explicitly or implicitly defined as requiring the use of only a single element, further examples may use multiple elements to perform the same function. Similarly, when a function is described later as being performed using multiple elements, further examples may perform the same function using a single element or processing entity. It is further understood that the terms "comprise," "comprising," "including," and / or "including," when used, specify the presence of stated features, integers, steps, operations, processes, acts, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, processes, acts, elements, components, and / or groups thereof.

[0010] Unless otherwise defined, all terms (including technical and scientific terms) are used in their ordinary meaning in the art to which the example belongs.

[0011] FIG. 1 shows an example of an n-bit SAR ADC 100. In the example of FIG. 1, the SAR ADC 100 is shown as an n=4-bit ADC. Therefore, the proposed SAR ADC architecture will be described with reference to a 4-bit ADC. However, it should be noted that the proposed architecture is not limited to a 4-bit SAR ADC. In general, the proposed architecture can be used for any number of bits, n, where n>1.

[0012] The SAR ADC 100 includes a respective plurality of sampling cells for each bit of n=4 bits. That is, the SAR ADC 100 includes a plurality of sampling cells 110 for the first most significant bit (MSB) of the four bits, a plurality of sampling cells 120 for the second MSB (MSB-1) of the four bits, a plurality of sampling cells 130 for the third MSB (MSB-2) of the four bits, and a plurality of sampling cells 140 for the fourth MSB (i.e., LSB) of the four bits. In the example of FIG. 1, each of the plurality of sampling cells 110-140 includes two respective sampling cells. However, it should be noted that the proposed architecture is not limited to two sampling cells per bit. In general, any number m of sampling cells, where m>1, can be used for each bit of n bits.

[0013] 1 are a number of sampling cells 199 for dummy LSBs that allow for dummy switching during operation of the SAR ADC 100. The dummy LSB sampling cells 199 are not required for calibration and will not be described in detail below. In some examples, the dummy LSB sampling cells 199 may be omitted.

[0014] Each of the sampling cells of the plurality of sampling cells 110 to 140 (and the plurality of sampling cells 199 for the dummy LSB) is substantially identical. The structure of the sampling cell of the sampling cell 110-1 of the plurality of sampling cells 110 for the first MSB will be exemplarily described below.

[0015] The sampling cell 110-1 comprises a capacitive element 111 coupled to a cell output (node) 112 of the sampling cell 110-1 to provide a cell output signal 113. Furthermore, the sampling cell 110-1 comprises a first cell input (node) 114 for receiving the first signal 101 and a first switch circuit 115 capable of selectively coupling the first cell input 114 to the capacitive element 111. The sampling cell 110-1 further comprises a second cell input (node) 116 for receiving the second signal 102 and a third cell input (node) 117 for receiving the third signal 103. The sampling cell 110-1 comprises a second switch circuit 118 capable of selectively coupling one of the second cell input 116 and the third cell input 117 to the capacitive element 111. For example, the first switch circuit 115 and the second switch circuit 118 may be implemented as semiconductor switches (e.g., comprising one or more transistors).

[0016] The first signal 101 is a calibration signal, the second signal 102 is a first reference signal, and the third signal 103 is a second reference signal. The third signal 103 exhibits an opposite polarity to the second signal 102.

[0017] 1, the first cell input 114 of the sampling cell 110-1 is a cell input of the sampling cell used to receive an input signal to be digitized during non-calibrated operation of the SAR ADC (i.e., when the SAR ADC is not calibrated). In other words, the SAR ADC 100 uses the normal cell input of the sampling cell 110-1 to receive (input, inject) a calibration signal into the sampling cell 110-1. In other examples, the first cell input 114 may be a dedicated cell input used only to receive a calibration signal.

[0018] The SAR ADC 100 is a split-capacitor SAR ADC.

[0019] For each bit of n=4 bits, each one of the capacitive elements of the plurality of sampling cells 110 to 140 exhibits the same capacitance. As shown in FIG. 1, each capacitive element of the plurality of sampling cells 110 for the first MSB exhibits a capacitance α 3 C U / 2(C U indicates unit capacitance), and each capacitive element of the multiple sampling cells 120 for the second MSB has a capacitance α 2 C U / 2, and each capacitive element of the plurality of sampling cells 130 for the third MSB has a capacitance α 1 C U / 2, and each capacitive element of the plurality of sampling cells 140 for the fourth MSB has a capacitance α 0 C U In other words, each capacitive element of each of the plurality of sampling cells for the n=4 bits represents a bit-specific capacitance.

[0020] For each of the n=4 bits, the capacitive elements of the sampling cells 110 to 140 exhibit respective capacitances corresponding to the significance of the respective bits. That is, the capacitance α 3 C U / 2 corresponds to the significance of the first MSB. The capacitance α of the capacitive elements of the multiple sampling cells 120 for the second MSB 2 C U / 2 corresponds to the significance of the second MSB, and so on.

[0021] Therefore, for each bit of n=4 bits, the capacitive elements of different sampling cells of the plurality of sampling cells 110 to 140 exhibit different capacitances. 3 C U / 2 is the capacitance α of the capacitive elements of the multiple sampling cells 120 for the second MSB.2 C U The capacitance α of the capacitive elements of the plurality of sampling cells 120 for the second MSB is different from 2 C U / 2 is the capacitance α of the capacitive elements of the plurality of sampling cells 130 for the third MSB. 1 C U / 2, etc.

[0022] The SAR ADC 100 further comprises at least one comparator circuit coupled to (the cell output of) the sampling cells of the plurality of sampling cells 110-140. In the example of FIG. 1, four comparator circuits 150-1-150-4 are shown as the SAR ADC 100 comprising one comparator circuit for each of the n=4 bits. In an alternative example, a single (i.e., only one) comparator circuit may be used for all of the n=4 bits. The comparator circuits 150-1-150-4 are configured to output respective comparison signals 151-1-151-4 based on the cell output signals of the sampling cells of the plurality of sampling cells 110-140. Thus, when a single comparator circuit is used, the comparator circuit is configured to output a single comparison signal based on the cell output signals of the sampling cells.

[0023] In the example of Fig. 1, the cell output signals of the sampling cells of the plurality of sampling cells 110 to 140 are combined and provided to each first comparator input (node) of each of the comparator circuits 150-1 to 150-4. In addition, a comparison reference signal 152 is input to each second comparator input (node) of each of the comparator circuits 150-1 to 150-4. Each of the comparator circuits 150-1 to 150-4 is configured to compare the combined cell output signals of the sampling cells of the plurality of sampling cells 110 to 140 with the comparison reference signal 152, and is configured to generate each comparison signal 151-1 to 151-4 based on the comparison of the combined cell output signals of the sampling cells of the plurality of sampling cells 110 to 140 with the comparison reference signal 152. For example, depending on which of the comparison reference signal 152 and the combined cell output signals of the sampling cells of the multiple sampling cells 110 to 140 indicates a higher signal level, each comparison circuit 150-1 to 150-4 may adjust the signal level of each comparison signal 151-1 to 151-4 (e.g., higher or lower depending on which of the signals input to each comparator circuit indicates a higher / lower signal level).

[0024] The SAR ADC 100 further comprises a calibration circuit 160, which is configured to provide at least one respective control signal to each second switch circuit of the sampling cells of the plurality of sampling cells 110-140 to control the second switch circuit. In the example of FIG. 1, the calibration circuit 160 provides two respective control signals to each second switch circuit of each sampling cell. For example, the calibration circuit 160 provides two control signals 161-1 and 162-1 to the second switch circuit 118 of the sampling cell 110-1. However, it should be noted that in alternative examples, more or less control signals may be provided to each second switch circuit of the sampling cells of the plurality of sampling cells 110-140 to control the second switch circuit.

[0025] In the example of Fig. 1, the calibration circuit 160 includes a respective logic circuit 163-1 to 163-4 for each of the n=4 bits. For example, the logic circuits 163-1 to 163-4 may implement a respective SAR logic for each of the n=4 bits. However, it should be noted that in alternative examples, a single (i.e., only one) or less than n logic circuits implementing the SAR logic may be used. Also shown is a logic circuit 198 configured to provide a control signal to the second switch circuits of the multiple sampling cells 199 for controlling the second switch circuits of the multiple sampling cells 199 for the dummy LSB.

[0026] For calibration, the calibration circuit 160 may be configured to provide respective control signals to respective second switch circuits of the sampling cells of the plurality of sampling cells 110 to 140 to adjust the decision thresholds of the comparator circuits 150-1 to 150-4 during calibration.

[0027] The SAR ADC 100 can allow for facilitated calibration. In particular, the SAR ADC 100 can allow for facilitated estimation of the weight of the LSB (e.g., the 4th MSB in the example of FIG. 1). This will become apparent from the following description of the proposed calibration scheme.

[0028] For an n-bit SAR ADC, the proposed calibration scheme includes (n+1) calibration measurements to determine the respective weights of the sampling cells for each of the n bits. Thus, for the 4-bit SAR ADC 100 shown in FIG. 1, the calibration scheme includes five calibration measurements.

[0029] In the first calibration measurement, the calibration circuit 160 is configured to control the second switch circuits of half of the sampling cells for each of the n = 4 bits to couple each second cell input to each capacitive element, and to control the second switch circuits of the other half of the sampling cells for each of the n = 4 bits to couple each third cell input to each capacitive element. In other words, for each of the n = 4 bits, one sampling cell is controlled to couple its second cell input to its capacitive element, and the other sampling cell is controlled to couple its third cell input to its capacitive element. For example, in the case of the first MSB, the sampling cell 110-1 may be controlled to couple its second cell input to its capacitive element, and the sampling cell 110-2 may be controlled to couple its second cell input (third cell input) to its capacitive element. The sampling cells for the other bits may be controlled in the same manner.

[0030] By coupling half of each bit to the first reference signal and the remaining half to another reference signal, the thresholds of the comparator circuits 150-1 to 150-4 are initially set to 0. This is shown in FIG. 2. FIG. 2 shows an exemplary decision tree 200 of the SAR ADC 100. The initially set decision threshold 201 is 0. The decisions of the comparator circuits 150-1 to 150-4 based on the decision threshold 201 do not include information regarding the weight of the first MSB. During the first calibration measurement, the calibration circuit 160 is configured to control the first switch circuits of each of the plurality of sampling cells 110 to 140 to decouple each first cell input from each capacitive element.

[0031] Furthermore, to determine the weights of the n - 1 MSBs, the i-th calibration measurement (1 < i < n + 1) is performed. Accordingly, for the n = 4-bit SAR ADC 100 shown in FIG. 1, the calibration method further includes (n - 1 =) 3 calibration measurements (i.e., calibration measurements 2 to 4).

[0032] For each ith calibration measurement, the calibration circuit 160 is configured to control the second switch circuits of the sampling cells for the (i-1)th MSB of the n=4 bits, respectively, to sequentially couple each of the second and third cell inputs to the capacitive element. Furthermore, for i>2, the calibration circuit 160 is configured to control the second switch circuits of the sampling cells for bits up to the (i-2)th MSB, respectively, to couple a selected one of each of the second and third cell inputs to the capacitive element. Furthermore, the calibration circuit 160 is configured to control the second switch circuits of half of the sampling cells for each of the ith through nth MSBs, respectively, to couple each of the second cell inputs to the respective capacitive element, and to control the second switch circuits of the other half of the sampling cells for each of the ith through nth MSBs, respectively, to couple each of the third cell inputs to the respective capacitive element.

[0033] Further, for each i-th calibration measurement, the calibration circuit 160 is configured to control each first switch circuit of the sampling cell for each bit of the n=4 bits to couple each first cell input to each capacitive element during calibration. The calibration signal indicates a signal level that increases or decreases over time. In other words, the calibration signal allows a DC value to be swept through the SAR ADC 100.

[0034] For the second calibration measurement, the calibration circuit 160 in the example of FIG. 1 is configured to control the second switch circuits of the sampling cells 110-1 and 110-2 for the first MSB, respectively, to sequentially couple each of the second cell inputs and each of the third cell inputs to each of the capacitive elements. For example, the second switch circuits of the sampling cells 110-1 and 110-2 for the first MSB may be controlled to first (only, exclusively) couple each of the second cell inputs to each of the capacitive elements, and then (only, exclusively) couple each of the third cell inputs to each of the capacitive elements, or vice versa. Furthermore, the calibration circuit 160 is configured to control the second switch circuits of half of the sampling cells for each of the second through fourth MSBs, respectively, to couple each of the second cell inputs to each of the capacitive elements, and to control the second switch circuits of the other half of the sampling cells for each of the second through fourth MSBs, respectively, to couple each of the third cell inputs to each of the capacitive elements. For example, the second switch circuits of sampling cells 120-1, 130-1 and 140-1 may be controlled to couple each second cell input to each capacitive element, and sampling cells 120-2, 130-2 and 140-2 may be controlled to couple each third cell input to each capacitive element.

[0035] Thus, for the second calibration measurement, the decision thresholds of the comparator circuits 150-1 to 150-4 are sequentially set to decision thresholds 202 and 203 that convey information about the weights w3 of the first MSB sampling cells 110-1 and 110-2. In particular, the decision threshold 202 corresponds to +w3, and the decision threshold 203 corresponds to -w3. Since calibration signals with increasing or decreasing signal levels are input during the second calibration measurement, threshold crossings around -w3 and +w3 can be detected in the comparison signals 151-1 to 151-4 of the comparator circuits 150-1 to 150-4. Thus, two measurements -w3 and +w3 of the weights w3 of the first MSB sampling cells 110-1 and 110-2 are obtained. By subtracting the measurements -w3 and +w3 from each other, an estimate of the weights w3 of the first MSB sampling cells 110-1 and 110-2 can be obtained by the calibration circuit 160.

[0036] 1 is configured to control the second switch circuits of the sampling cells 120-1 and 120-2 for the second MSB to sequentially couple each of the second cell inputs and each of the third cell inputs to each of the capacitive elements, respectively. For example, the second switch circuits of the sampling cells 120-1 and 120-2 for the second MSB may be controlled to first (only, exclusively) couple each of the second cell inputs to each of the capacitive elements, and then (only, exclusively) couple each of the third cell inputs to each of the capacitive elements, or vice versa.

[0037] Furthermore, since i=3>2, the calibration circuit 160 is configured to control the second switch circuits of the sampling cells 110-1 and 110-2 for the first MSB, respectively, to couple a selected one of the second cell inputs and the third cell inputs to each capacitive element. The calibration circuit 160 is configured to select a selected one of the second cell inputs and the third cell inputs based on the comparison signals 151-1 to 151-4 for the first calibration measurement. For example, if the signal amplitude of the reference signal 152 is lower than the combined cell output signals of the sampling cells of the plurality of sampling cells 110 to 140 in the first calibration measurement, each of the second cell inputs may be selected as a selected one of the second cell inputs and the third cell inputs, or vice versa. In the following, it is assumed that each of the second cell inputs is selected as a selected one of the second cell inputs and the third cell inputs.

[0038] Furthermore, the calibration circuit 160 is configured to control the second switch circuits of the half of the sampling cells for the third and fourth MSBs, respectively, to couple the respective second cell inputs to the respective capacitive elements, and is also configured to control the second switch circuits of the other half of the sampling cells for the third and fourth MSBs, respectively, to couple the respective third cell inputs to the respective capacitive elements. For example, the second switch circuits of the sampling cells 130-1 and 140-1 may be controlled to couple the respective second cell inputs to the respective capacitive elements, and the sampling cells 130-2 and 140-2 may be controlled to couple the respective third cell inputs to the respective capacitive elements.

[0039] Thus, for the third calibration measurement, the decision thresholds of the comparator circuits 150-1 to 150-4 are sequentially set to decision thresholds 204 and 205 conveying information about the weight w2 of the second MSB sampling cells 120-1 and 120-2. In particular, the decision threshold 204 corresponds to w3+w2, and the decision threshold 205 corresponds to w3-w2. Since calibration signals with increasing or decreasing signal levels are input during the third calibration measurement, threshold crossings around w3-w2 and w3+w2 can be detected in the comparison signals 151-1 to 151-4 of the comparator circuits 150-1 to 150-4. Thus, two measurements w3-w2 and w3+w2 are obtained for the weight w2 of the second MSB sampling cells 120-1 and 120-2. An estimate of the weight w2 of the second MSB sampling cells 120-1 and 120-2 may be obtained by the calibration circuit 160 by subtracting the measurements w3-w2 and w3+w2 from each other. That is, DC values ​​are swept across the SAR ADC until threshold crossings around w3-w2 and w3+w2 are detected. Subtracting these values ​​gives an estimate of w2.

[0040] 1 is configured to control the second switch circuits of the sampling cells 130-1 and 130-2 of the third MSB to sequentially couple each of the second cell inputs and each of the third cell inputs to each of the capacitive elements. For example, the second switch circuits of the sampling cells 130-1 and 130-2 for the third MSB may be controlled to first (only, exclusively) couple each of the second cell inputs to each of the capacitive elements, and then (only, exclusively) couple each of the third cell inputs to each of the capacitive elements, or vice versa.

[0041] Further, since i=4>2, the calibration circuit 160 is configured to control the second switch circuits of the sampling cells 110-1 and 110-2 for the first MSB and the sampling cells 120-1 and 120-2 for the second MSB, respectively, to couple a selected one of each of the second cell inputs and each of the third cell inputs to each capacitive element.

[0042] Further, the calibration circuit 160 is configured to control the second switch circuits of the half of the sampling cells for the fourth MSB to couple each of the second cell inputs to each of the capacitive elements, and is also configured to control the second switch circuits of the other half of the sampling cells for the fourth MSB to couple each of the third cell inputs to each of the capacitive elements. For example, the second switch circuit of the sampling cell 140-1 may be controlled to couple each of the second cell inputs to each of the capacitive elements, and the sampling cell 140-2 may be controlled to couple each of the third cell inputs to each of the capacitive elements.

[0043] Thus, for the fourth calibration measurement, the decision thresholds of the comparator circuits 150-1 to 150-4 are sequentially set to decision thresholds 206 and 207 conveying information about the weight w1 of the sampling cells 130-1 and 130-2 of the third MSB. In particular, the decision threshold 206 corresponds to w3+w2+w1, and the decision threshold 207 corresponds to w3+w2-w1. Since calibration signals with increasing or decreasing signal levels are input during the fourth calibration measurement, threshold crossings around w3+w2-w1 and w3+w2+w1 can be detected in the comparison signals 151-1 to 151-4 of the comparator circuits 150-1 to 150-4. Thus, two measurements w3+w2-w1 and w3+w2+w1 are obtained for the weight w1 of the sampling cells 130-1 and 130-2 of the third MSB. An estimate of the weight w1 of the 3 MSB sampling cells 130-1 and 130-2 may be obtained by the calibration circuit 160 by subtracting the measurements w3+w2-w1 and w3+w2+w1 from each other. That is, DC values ​​are swept across the SAR ADC until threshold crossings around w3+w2-w1 and w3+w2+w1 are detected. Subtracting these values ​​gives an estimate of w1.

[0044] As described above, the calibration circuit 160 is configured to determine the respective values ​​of the weights of the (i-1)th MSB sampling cells based on the comparison signal of the i-th calibration measurement.

[0045] The final determined threshold is a linear combination of w3, w2, and w1, but not a linear combination of the nth MSB (i.e., LSB) weight w0 of the SAR ADC 100. To determine the nth MSB weight w0, the (n+1)th calibration measurement is performed.

[0046] In the (n+1)th calibration measurement, the calibration circuit 160 is configured to control the second switch circuits of the sampling cells for bits up to the (n-1)th MSB to couple selected ones of the second cell inputs and the third cell inputs to the capacitive elements. Furthermore, the calibration circuit 160 is configured to control the second switch circuits of the nth MSB (i.e., LSB) sampling cell to sequentially couple the second cell inputs and the third cell inputs to the capacitive elements.

[0047] For the (n+1)th calibration measurement, the calibration circuit 160 is again configured to control each first switch circuit of the sampling cell for each bit of the n=4 bits to couple each first cell input to each capacitive element during calibration.

[0048] In the above example, the (n+1)th calibration measurement is the fifth calibration measurement. For the fifth calibration measurement, the calibration circuit 160 in the example of Fig. 1 is configured to control the second switch circuits of the sampling cells 110-1 and 110-2 for the first MSB, the sampling cells 120-1 and 120-2 for the second MSB, and the sampling cells 130-1 and 130-2 for the third MSB, respectively, to couple a selected one of the second cell inputs and the third cell inputs to each capacitive element.

[0049] Furthermore, the calibration circuit 160 is configured to control the second switch circuits of the sampling cells 140-1 and 140-2 for the 4th MSB, respectively, to sequentially couple each second cell input and each third cell input to each capacitive element. For example, the second switch circuits of the sampling cells 140-1 and 140-2 for the 4th MSB may be controlled to first (only, exclusively) couple each second cell input and then (only, exclusively) couple each third cell input to each capacitive element, or vice versa. The initialization of the SAR ADC LSB may be performed very simply. One gate in the LSB feedback path may be added or replaced. Since the LSB uses a small capacitor, the required strength of the gate in this path is small, and the power increase to maintain low latency is small.

[0050] Thus, for the fifth calibration measurement, the decision thresholds of the comparator circuits 150-1 to 150-4 are sequentially set to decision thresholds 208 and 209 conveying information about the weights w0 of the sampling cells 140-1 and 140-2 of the fourth MSB. The decision threshold 208 is shown in FIG. 3. FIG. 3 shows a modified decision tree 300 assuming that the sampling cells 140-1 and 140-2 for the fourth MSB couple each second cell input to each capacitive element. The decision threshold 209 is shown in FIG. 4. FIG. 4 shows a modified decision tree 400 assuming that the sampling cells 140-1 and 140-2 for the fourth MSB couple each third cell input to each capacitive element.

[0051] 3 and 4, the decision threshold 208 corresponds to w3+w2+w1+w0, and the decision threshold 209 corresponds to w3+w2+w1-w0. Since calibration signals with increasing or decreasing signal levels are input during the fifth calibration measurement, threshold crossings around w3+w2+w1-w0 and w3+w2+w1+w0 can be detected in the comparison signals 151-1 to 151-4 of the comparator circuits 150-1 to 150-4. Thus, two measurements w3+w2+w1-w0 and w3+w2+w1+w0 are obtained for the weight w0 of the sampling cells 140-1 and 140-2 of the fourth MSB. An estimate of the weight w0 of the 4th MSB sampling cells 140-1 and 140-2 may be obtained by the calibration circuit 160 by subtracting the measurements w3+w2+w1-w0 and w3+w2+w1+w0 from each other. That is, DC values ​​are swept across the SAR ADC until threshold crossings around w3+w2+w1-w0 and w3+w2+w1+w0 are detected. Subtracting these values ​​gives an estimate of w0.

[0052] As described above, the calibration circuit 160 is configured to determine the weight value of the n-th MSB sampling cell based on the comparison signal of the (n+1)-th calibration measurement.

[0053] The proposed calibration scheme can be used to estimate the weights of all n bits of the SAR ADC 100. In particular, the weight w0 of the LSB of the SAR ADC 100 can be estimated.

[0054] The above SAR ADC 100 is a single-ended ADC. It should be noted that the above calibration scheme can also be used for differential SAR ADCs. An example of a differential n-bit SAR ADC 500 is shown in Figure 5. In the example of Figure 5, the SAR ADC 500 is shown as an n=4-bit ADC.

[0055] Similar to the SAR ADC 100, the SAR ADC 500 includes a plurality of sampling cells 510, 520, 530, 540 for each bit of the n=4 bits. Furthermore, the SAR ADC 500 includes at least one comparator circuit 550 coupled to (the cell output of) the sampling cells of the plurality of sampling cells 510-540. Thus, the at least one comparator circuit 550 is configured to output a comparison signal 551 based on the cell output signal of the sampling cell of the plurality of sampling cells 510-540. A residue amplifier 590 is coupled between the sampling cells of the plurality of sampling cells 510-540 and the at least one comparator circuit 550 for amplifying the cell output signal of the sampling cell.

[0056] For simplicity, the calibration circuitry of the SAR ADC 500 is not shown in Figure 5. However, as described above for the SAR ADC 100, the calibration circuitry of the SAR ADC 500 receives the comparison signal 551 of at least one comparator circuit 550 and controls the switching circuits of the sampling cells.

[0057] Thus, the structure of the SAR ADC 500 is substantially similar to the structure of the above-described SAR ADC 100. Thus, the SAR ADC 500 can be calibrated as described above.

[0058] Only the structure of the sampling cell of the SAR ADC 500 differs from that of the above-mentioned SAR ADC 100. By comparing the sampling cell 110-1 of the SAR ADC 100 with the sampling cell 510-1 of the SAR ADC 500, the differences between the sampling cells are explained below.

[0059] In the sampling cell 110-1, the first cell input 114 is used for receiving a first signal (i.e., a calibration signal) during calibration and for receiving an input signal (i.e., a fifth signal) to be digitized during uncalibrated operation of the SAR ADC 100. The sampling cell 510-1 includes an additional fourth cell input (node) 514 for receiving an input signal to be digitized during uncalibrated operation of the SAR ADC 500. Furthermore, the sampling cell 510-1 includes a third switch circuit 509 that can selectively couple the fourth cell input 514 to the capacitive element 111 of the sampling cell 510-1 based on the clock signal Φ1 to sample the input signal.

[0060] Furthermore, the sampling cell 510-1 includes an additional fifth cell input 519 for receiving a fourth signal. The fourth signal is another calibration signal and exhibits an opposite polarity to the first signal. In the example of FIG. 5, the first switch circuit 115 can selectively couple one of the first cell input 114 and the fifth cell input 519 to the capacitive element 111. Thus, the calibration circuit of the SAR ADC 500 is configured to control the first switch circuit 115 to couple a selected one of the first cell input 114 and the fifth cell input 519 to the capacitive element during calibration (e.g., for an r-th calibration measurement, where r>1). Thus, the fifth signal may be used for calibration instead of the first signal. Alternatively, calibration may be performed using one of the first signal and the fifth signal followed by the other of the first signal and the fifth signal.

[0061] It should be noted that in other examples, the differential SAR ADC 500 may instead use a sampling cell structure as described above for the SAR ADC 100. Similarly, the SAR ADC 100 may use the sampling cell structure described for the SAR ADC 500.

[0062] An example implementation using an n-bit SAR ADC according to one or more aspects of the architecture described above in relation to Figures 1-5, and one or more of the examples described above in relation to Figures 1-5, is shown in Figure 6. Figure 6 illustrates generally an example radio base station 600 (e.g. of a femtocell, picocell, microcell or macrocell) comprising the proposed n-bit SAR ADC 620.

[0063] The n-bit SAR ADC 620 is part of the receiver 610. The receiver 610 further comprises a signal generation circuit 630 coupled to the n-bit SAR ADC 620. The signal generation circuit 630 is configured to generate a first signal (e.g., indicative of a signal level that increases or decreases over time) for calibrating the n-bit SAR ADC 620.

[0064] The receiver 610 is coupled (either directly or indirectly via one or more intermediate elements such as a filter or a low noise amplifier, LNA, etc.) to an antenna element 650 of the base station 600. An n-bit SAR ADC 620 is coupled to the antenna element 650 for digitizing a radio frequency receive signal received by the antenna element 650.

[0065] Furthermore, the base station 600 comprises a transmitter 640 configured to generate a radio frequency transmission signal. The transmitter 640 can use the antenna element 650 of the base station 600 or another antenna element (not shown) to radiate the radio frequency transmission signal into the environment.

[0066] For this purpose, a base station can be provided with a SAR ADC that allows easy calibration.

[0067] The base station 600 may include further elements such as, for example, a baseband processor, an application processor, a memory, a network controller, a user interface, power management circuitry, a satellite navigation receiver, a network interface controller, or a power Tee circuitry.

[0068] In some embodiments, the application processor includes one or more central processing unit (CPU) cores and one or more cache memories, a low dropout (LDO) voltage regulator, an interrupt controller, a serial peripheral interface (SPI), an Inter-Integrated Circuit (IIC), and / or a combination of a SPI and / or a DDR3 memory. 2 C) or a universal programmable serial interface module, timer counters including a real time clock (RTC), interval and watchdog timers, general purpose input / output (IO), a Secure Digital (SD) / Multimedia Card (MMC) or similar memory card controller, a Universal Serial Bus (USB) interface, a Mobile Industry Processor Interface Alliance (MIPI) interface, and a Joint Test Access Group (JTAG) test access port.

[0069] In some aspects, the baseband processor may be implemented as, for example, a solder-down substrate containing one or more integrated circuits, a single packaged integrated circuit soldered to a main circuit board, or a multi-chip module containing two or more integrated circuits.

[0070] In some aspects, the memory may include one or more of volatile memory including dynamic random access memory (DRAM) and / or synchronous dynamic random access memory (SDRAM), and non-volatile memory (NVM) including high speed electrically erasable memory (commonly referred to as flash memory), phase change random access memory (PRAM), magnetoresistive random access memory (MRAM), and / or three-dimensional cross point (3D XPoint) memory. The memory may be implemented as one or more of a solder packaged integrated circuit, a socketed memory module, and a plug-in memory card.

[0071] In some aspects, the power management integrated circuit may include one or more of a voltage regulator, a surge protector, a power alarm detection circuit, and one or more backup power sources such as a battery or a capacitor. The power alarm detection circuit may detect one or more of a brownout (under-voltage) or surge (over-voltage) condition.

[0072] In some aspects, the power tee circuitry can provide power drawn from the network cable to provide both power and data connectivity to the base station using a single cable.

[0073] In some aspects, the network controller may provide a connection to a network using a standard network interface protocol such as Ethernet. The network connection may be provided using a physical connection that is either electrical (commonly referred to as a copper interconnect), optical, or wireless.

[0074] In some aspects, the satellite navigation receiver module may include circuitry to receive and decode signals transmitted by one or more navigation satellite constellations, such as Global Positioning System (GPS), GLObalnaya NAvigatSionnaya Sputnikovaya Sistema (GLONASS), Galileo, or / and BeiDou. The receiver may provide data to the application processor, which may include one or more of position data or time data. The application processor may use the time data to synchronize operation with other wireless base stations.

[0075] In some aspects, the user interface may include one or more physical or virtual buttons, such as a reset button, one or more indicators, such as light emitting diodes (LEDs), and a display screen.

[0076] Another example implementation using an n-bit SAR ADC according to one or more aspects of the architecture described above in connection with Figures 1-5 or one or more examples described above in connection with Figures 1-5 is shown in Figure 7. Figure 7 illustrates generally an example of a mobile device 700 (e.g., a mobile phone, a smartphone, a tablet computer, or a laptop) comprising the proposed n-bit SAR ADC 720.

[0077] The n-bit SAR ADC 720 is part of the receiver 710. The receiver 710 further comprises a signal generation circuit 730 coupled to the n-bit SAR ADC 620. The signal generation circuit 730 is configured to generate a first signal (e.g., indicative of a signal level that increases or decreases over time) for calibrating the n-bit SAR ADC 720.

[0078] The receiver 710 is coupled (either directly or indirectly via one or more intermediate elements, such as a filter or LNA) to an antenna element 750 of the mobile device 700. The n-bit SAR ADC 720 is coupled to the antenna element 750 for digitizing a radio frequency receive signal received by the antenna element 750.

[0079] Additionally, the mobile device 700 includes a transmitter 740 configured to generate a radio frequency transmit signal. The transmitter 740 can use the antenna element 750 of the mobile device 700, or a separate antenna element (not shown), to radiate the radio frequency transmit signal into the environment.

[0080] For this purpose, a mobile device can be provided with a SAR ADC that allows for easy calibration.

[0081] The mobile device 700 may include further elements such as, for example, a baseband processor, memory, a connectivity module, a near field communication (NFC) controller, an audio driver, a camera driver, a touch screen, a display driver, sensors, removable memory, a power management integrated circuit, or a smart battery.

[0082] In some embodiments, the application processor may include, for example, one or more CPU cores and one or more cache memories, LDO regulators, interrupt controllers, SPI, I 2 C, or a universal programmable serial interface module, timer counters including RTC, interval and watchdog timers, general purpose input / output (IO), SD / MMC or similar memory card controller, USB interface, MIPI interface, and JTAG test access port.

[0083] In some aspects, the baseband module may be implemented as, for example, a soldered substrate containing one or more integrated circuits, a single packaged integrated circuit soldered to a main circuit board, and / or a multi-chip module containing two or more integrated circuits.

[0084] A wireless communication circuit using a SAR ADC according to the proposed architecture or one or more examples above may be configured to operate according to one of the 3GPP standardized mobile communication networks or systems. The mobile or wireless communication system may correspond to, for example, 5G NR, Long-Term Evolution (LTE), LTE-Advanced (LTE-A), High Speed ​​Packet Access (HSPA), Universal Mobile Telecommunications System (UMTS) or UMTS Terrestrial Radio Access Network (UTRAN), evolved-UTRAN (e-UTRAN), Global System for Mobile Communication (GSM), Enhanced Data rates for GSM Evolution (EDGE) network, or GSM / EDGE Radio Access Network (GERAN). Alternatively, the wireless communication circuitry may be configured to operate according to different standards of mobile communication networks, such as Worldwide Interoperability for Microwave Access (WIMAX) networks IEEE 802.16, or Wireless Local Area Networks (WLAN) IEEE 802.11, generally, orthogonal frequency division multiple access (OFDMA) networks, time division multiple access (TDMA) networks, code division multiple access (CDMA) networks, wideband CDMA (WCDMA®) networks, frequency division multiple access (FDMA) networks, spatial division multiple access (SDMA) networks, etc.

[0085] To further illustrate the above SAR ADC calibration, Figure 8 shows a flow chart of a method 800 for calibrating one of the above n-bit SAR ADCs. For a first calibration measurement 802, the method 800 includes controlling 802-1 second switch circuits of half of the sampling cells for each bit of the n bits to couple a respective second cell input to a respective capacitive element, and controlling 802-2 second switch circuits of the other half of the sampling cells for each bit of the n bits to couple a respective third cell input to a respective capacitive element.

[0086] For the i-th calibration measurement 804 (1 < i < n + 1), method 800 includes controlling the second switch circuit of the sampling cell for the (i - 1)-th most significant bit among the n bits 804-1 to sequentially couple each second cell input and each third cell input to each capacitive element. Further, when i > 2, method 800 further includes controlling the second switch circuit of the sampling cell for the bits up to the (i - 2)-th most significant bit 804-2 to couple one of the selected ones of each second cell input and each third cell input to each capacitive element. For the i-th calibration measurement 804, method 800 includes controlling the second switch circuit of half of the sampling cells for each of the i-th to n-th most significant bits 804-3 to couple each second cell input to each capacitive element, and controlling the second switch circuit of the other half of the sampling cells for each of the i-th to n-th most significant bits 804-4 to couple each third cell input to each capacitive element.

[0087] For the (n + 1)-th calibration measurement 806, method 800 includes controlling the second switch circuit of the sampling cell for the bits up to the (n - 1)-th most significant bit 806-1 to couple one of the selected ones of each second cell input and each third cell input to each capacitive element, and controlling the second switch circuit of the sampling cell for the n-th most significant bit 806-2 to sequentially couple each second cell input and each third cell input to each capacitive element.

[0088] Method 800 can enable easy calibration of an n-bit SAR ADC.

[0089] Optionally, method 800 may include one or more optional functions, such as determining respective values ​​of sampling cell weights for the (i-1)th most significant bit based on the comparison signal of the ith calibration measurement, determining respective values ​​of sampling cell weights for the nth most significant bit based on the comparison signal of the (n+1)th calibration measurement, or selecting a selected one of each of the second cell inputs and each of the third cell inputs based on the comparison signal of the first calibration measurement.

[0090] Further details and aspects of method 800 are described in relation to the proposed technology or one or more examples above (e.g., FIGS. 1-5). Method 800 may include one or more additional optional features corresponding to one or more aspects of the proposed technology or one or more examples above.

[0091] The example described here can be summarized as follows:

[0092] Example 1 is an n-bit SAR ADC, including a respective plurality of sampling cells for each of the n bits of the SAR ADC, each sampling cell including: a capacitive element coupled to a cell output of the sampling cell to provide a cell output signal; a first cell input for receiving a first signal; a first switch circuit operable to selectively couple the first cell input to the capacitive element; a second cell input for receiving a second signal; a third cell input for receiving a third signal, the third signal exhibiting an opposite polarity to the second signal; and a second switch circuit operable to selectively couple one of the second cell input and the third cell input to the capacitive element; at least one comparator circuit coupled to the sampling cell, the at least one comparator circuit configured to output a comparison signal based on the cell output signal of the sampling cell; and a calibration circuit configured to provide at least one respective control signal to each second switch circuit of the sampling cell to control the second switch circuit.

[0093] Example 2 is an n-bit SAR ADC of Example 1. For the first calibration measurement, the calibration circuit is configured to control the second switch circuits of half of the sampling cells for each bit of the n bits to couple a second cell input to each capacitive element, and to control the second switch circuits of the other half of the sampling cells for each bit of the n bits to couple a third cell input to each capacitive element.

[0094] Example 3 is an n-bit SAR ADC of Example 2. For the i-th calibration measurement where 1 < i < n + 1, the calibration circuit is configured to control the second switch circuits of the sampling cells for the (i - 1)-th most significant bit of the n bits to sequentially couple the second cell input and the third cell input to each capacitive element. When i > 2, it controls the second switch circuits of the sampling cells for the bits up to the (i - 2)-th most significant bit to couple one of the selected second cell input and the third cell input to each capacitive element. For each of the i-th to n-th most significant bits, it controls the second switch circuits of half of the sampling cells to couple the second cell input to each capacitive element, and controls the second switch circuits of the other half of the sampling cells for each of the i-th to n-th most significant bits to couple the third cell input to each capacitive element.

[0095] Example 4 is an n-bit SAR ADC of Example 3. The calibration circuit is configured to determine the respective values of the weights of the sampling cells for the (i - 1)-th most significant bit based on the comparison signal of the i-th calibration measurement.

[0096] Example 5 is the n-bit SAR ADC of examples 3 or 4, wherein, for the (n+1)th calibration measurement, the calibration circuit is configured to: control the second switch circuits of the sampling cells for bits up to the (n-1)th most significant bit to couple selected ones of the second cell input and the third cell input to each capacitive element; and control the second switch circuits of the sampling cells for the nth most significant bit to sequentially couple the second cell input and the third cell input to each capacitive element.

[0097] Example 6 is the n-bit SAR ADC of example 5, in which the calibration circuit is configured to determine a sampling cell weight value for the n-th most significant bit based on the comparison signal of the (n+1)-th calibration measurement.

[0098] Example 7 is the n-bit SAR ADC of any one of Examples 3 to 6, wherein the calibration circuit is configured to select a selected one of the second cell input and the third cell input based on the comparison signal of the first calibration measurement.

[0099] Example 8 is the n-bit SAR ADC of any one of Examples 3 to 7, wherein the first cell input of at least one of the sampling cells is a cell input of the respective sampling cell used to receive an input signal to be digitized during uncalibrated operation of the n-bit SAR ADC.

[0100] Example 9 is the n-bit SAR ADC of any one of Examples 3 to 7, wherein at least one of the sampling cells further comprises: a fourth cell input for receiving an input signal to be digitized during uncalibrated operation of the n-bit SAR ADC; and a third switch circuit operable to selectively couple the fourth cell input to the capacitive element based on a clock signal to sample the input signal.

[0101] Example 10 is the n-bit SAR ADC of any one of Examples 3 to 9, wherein the calibration circuit is configured to selectively control each first switch circuit to couple each first cell input to a capacitive element during calibration.

[0102] Example 11 is the n-bit SAR ADC of any one of Examples 1 to 9, wherein each sampling cell includes a respective fifth cell input for receiving a fourth signal, the fourth signal exhibiting an opposite polarity to the first signal, and each first switch circuit is capable of selectively coupling one of the respective first cell input and the respective fifth cell input to a respective capacitive element.

[0103] Example 12 is the n-bit SAR ADC of Example 11, in which the calibration circuit is configured to selectively control each first switch circuit to couple a selected one of each first cell input and each fifth cell input to each capacitive element during calibration.

[0104] Example 13 is the n-bit SAR ADC of any one of Examples 1 to 12, wherein the capacitive elements of each one of the sampling cells for each bit of the n bits exhibit the same capacitance.

[0105] Example 14 is the n-bit SAR ADC of any one of examples 1 to 13, wherein capacitive elements of different ones of the plurality of sampling cells for each bit of the n bits exhibit different capacitances.

[0106] Example 15 is the n-bit SAR ADC of example 14, in which the capacitive element of each one of the sampling cells for each bit of the n bits exhibits a respective capacitance corresponding to the significance of each bit.

[0107] Example 16 is the n-bit SAR ADC of any one of Examples 1 to 15, where n>1.

[0108] Example 17 is the n-bit SAR ADC of any one of examples 1 to 16, wherein the first signal is a calibration signal, the second signal is a first reference signal, and the third signal is a second reference signal.

[0109] Example 18 is the n-bit SAR ADC of any one of Examples 1 to 17, wherein the calibration circuit is configured to provide a respective control signal to each second switch circuit of the sampling cell to adjust a decision threshold of the at least one comparator circuit during calibration.

[0110] Example 19 is a receiver comprising: the n-bit successive approximation register analog-to-digital converter of any one of Examples 1 to 18; and a signal generating circuit configured to generate a first signal.

[0111] Example 20 is the receiver of example 19, wherein the first signal indicates an increasing or decreasing signal level.

[0112] Example 21 is a base station comprising: a receiver of example 19 or 20; and at least one antenna element coupled to the receiver.

[0113] Example 22 is the base station of example 21, further comprising a transmitter configured to provide a radio frequency transmit signal to the antenna element for radiation into the environment.

[0114] Example 23 is a mobile device comprising: the receiver of example 19 or 20; and at least one antenna element coupled to the receiver.

[0115] Example 24 is the mobile device of example 23, further comprising a transmitter configured to provide a radio frequency transmit signal to the antenna element for radiation into an environment.

[0116] Example 25 is a method for calibrating an n-bit successive comparison register analog / digital converter according to any one of Examples 1 to 18, including: for a first calibration measurement, controlling a second switch circuit of half of the sampling cells for each bit of the n bits to couple a second cell input to each capacitive element; controlling a second switch circuit of the other half of the sampling cells for each bit of the n bits to couple a third cell input to each capacitive element; for an i-th calibration measurement where 1 < i < n + 1, controlling a second switch circuit of the sampling cells for the (i - 1)-th most significant bit of the n bits to sequentially couple the second cell input and the third cell input to each capacitive element; when i > 2, controlling a second switch circuit of the sampling cells for the bits up to the (i - 2)-th most significant bit to couple one of the selected second cell input and the third cell input to each capacitive element; for each of the i-th to n-th most significant bits, controlling a second switch circuit of half of the sampling cells to couple the second cell input to each capacitive element; for each of the i-th to n-th most significant bits, controlling a second switch circuit of the other half of the sampling cells to couple the third cell input to each capacitive element; for an (n + 1)-th calibration measurement, controlling a second switch circuit of the sampling cells for the bits up to the (n - 1)-th most significant bit to couple one of the selected second cell input and the third cell input to each capacitive element; and controlling a second switch circuit of the sampling cells for the n-th most significant bit to sequentially couple the second cell input and the third cell input to each capacitive element.

[0117] Example 26 is the method of Example 25, further including determining each value of the weights of the sampling cells for the (i - 1)-th most significant bit based on the comparison signal of the i-th calibration measurement.

[0118] Example 27 is the method of Example 25 or 26, further including determining the value of the weight of the sampling cells for the n-th most significant bit based on the comparison signal of the (n + 1)-th calibration measurement.

[0119] Example 28 is the method of any one of Examples 25-27, further including selecting a selected one of the second cell input and the third cell input based on the comparison signal of the first calibration measurement.

[0120] Example 29 is the method of any one of Examples 25 to 28, wherein the first signal exhibits an increasing or decreasing signal level.

[0121] The aspects and features mentioned and described in connection with one or more of the examples and figures detailed above may be combined with one or more of the other examples to replace similar features of the other examples or to introduce additional features to the other examples.

[0122] Various examples may be or relate to a computer program having program code for performing one or more of the above methods when the computer program is executed on a computer or processor. The steps, operations or processes of the various methods above may be performed by a programmed computer or processor. Examples may also include a program storage device, such as a digital data storage medium, that is readable by a machine, processor or computer and that encodes a program of machine-executable, processor-executable or computer-executable instructions. The instructions perform or cause the execution of some or all of the operations of the above methods. The program storage device may include or be, for example, a digital memory, a magnetic storage medium such as a magnetic disk and magnetic tape, a hard drive, or an optically readable digital data storage medium. Still other examples may include a computer, processor or control unit programmed to perform the operations of the above methods, or a (field) programmable logic array ((F)PLA) or a (field) programmable gate array ((F)PGA) programmed to perform the operations of the above methods.

[0123] The description and drawings merely illustrate the principles of the present disclosure. Moreover, all examples described herein are expressly intended to be for illustrative purposes only, primarily to aid the reader in understanding the principles of the disclosure and the concepts that the inventors have contributed to furthering the art. All statements herein reciting the principles, aspects, and examples of the present disclosure, as well as specific examples thereof, are intended to encompass equivalents thereof.

[0124] A functional block denoted as "means for" performing a function may refer to circuitry configured to perform the function. Thus, a "means for something" may be embodied as a "means configured for or suitable for something," such as a device or circuit configured or suitable for the respective task.

[0125] The functions of the various elements shown in the figures, including any functional blocks labeled with terms such as "means," "means for providing a signal," "means for generating a signal," etc., may be implemented in the form of dedicated hardware, such as a "signal provider," "signal processing unit," "processor," "controller," etc., and hardware on which software can execute in association with appropriate software. When provided by a processor, the functions may be provided by a single dedicated processor, a single shared processor, or multiple individual processors, some or all of which may be shared. However, the terms "processor" or "controller" are in no way limited to hardware capable of exclusively executing software, and may include digital signal processor (DSP) hardware, network processors, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), read only memory (ROM) for storing software, random access memory (RAM), and non-volatile storage. Other hardware, conventional and / or custom, may also be included.

[0126] Block diagrams may, for example, depict high level circuit diagrams embodying the principles of the present disclosure. Similarly, flowcharts, flow diagrams, state transition diagrams, pseudocode, and the like may represent various processes, operations, or steps that may be substantially represented on, for example, a computer-readable medium and executed by a computer or processor, whether or not that computer or processor is explicitly depicted. The methods disclosed herein or in the claims may be performed by a device having means for performing each of the operations of those methods.

[0127] It should be understood that the disclosure of multiple operations, processes, operations, steps or functions disclosed in this specification or claims may not be construed as being in a particular order, for example, for technical reasons, unless otherwise stated, either explicitly or implicitly. Thus, the disclosure of multiple operations or functions is not intended to limit them to a particular order, unless such operations or functions are ininterchangeable for technical reasons. Furthermore, in some instances, a single operation, function, process, operation or step may include or be divided into multiple sub-operations, sub-functions, sub-processes, sub-operations or sub-steps, respectively. Unless expressly excluded, such sub-operations may be included as part of the disclosure of this single operation.

[0128] Additionally, the following claims are hereby incorporated into the detailed description. Each claim may stand on its own as a separate example. It should be noted that while each claim may stand alone as a separate example, other examples may include combinations of dependent claims with the inventive subject matter of each dependent or independent claim (although a dependent claim may refer to a specific combination with one or more other claims in the claim). Such combinations are expressly suggested herein, unless it is stated that a specific combination is not intended. Furthermore, it is intended to include the features of a claim with respect to any other independent claim, even if that claim is not directly dependent on that claim.

Claims

1. 1. An n-bit successive approximation register analog-to-digital converter (SAR ADC), comprising: a respective plurality of sampling cells for each of the n bits of the SAR ADC, each sampling cell being: a capacitive element coupled to a cell output of the sampling cell to provide a cell output signal; a first cell input for receiving a first signal; a first switch circuit capable of selectively coupling the first cell input to the capacitive element; a second cell input for receiving a second signal; a third cell input for receiving a third signal, said third signal exhibiting an opposite polarity to said second signal; a second switch circuit capable of selectively coupling one of the second cell input and the third cell input to the capacitive element; A sampling cell including: at least one comparator circuit coupled to the sampling cell, the at least one comparator circuit configured to output a comparison signal based on the cell output signal of the sampling cell; a calibration circuit configured to provide at least one respective control signal to each second switch circuit of the sampling cells for controlling the second switch circuits; Equipped with The calibration circuitry performs, for a first calibration measurement: controlling the second switch circuits of half of the sampling cells for each bit of the n bits to couple the second cell input to a respective capacitive element; controlling the second switch circuits of the other half of the sampling cells for each bit of the n bits; coupling said third cell input to each capacitive element; It is structured as follows: The calibration circuitry calculates, for an i-th calibration measurement, where 1<i<n+1, controlling the second switch circuit of a sampling cell for the (i-1)-th most significant bit of the n bits to sequentially couple the second cell input and the third cell input to each capacitive element; controlling the second switch circuit of a sampling cell for bits up to the (i-2)th most significant bit to couple a selected one of the second cell input and the third cell input to a respective capacitive element, if i>2; controlling the second switch circuits of half of the sampling cells for each of the i-th through n-th most significant bits to couple the second cell inputs to respective capacitive elements; controlling the second switch circuits of the other half of the sampling cells for each of the i-th through n-th most significant bits to couple the third cell input to a respective capacitive element; It is structured as follows: The calibration circuit includes: determining respective values ​​of sampling cell weights for the (i-1) most significant bits based on the comparison signal of the i calibration measurement; It is structured as follows: The calibration circuit, for the (n+1)th calibration measurement, controlling the second switch circuits of the sampling cells for the bits up to the (n-1)th most significant bit to couple selected ones of the second cell input and the third cell input to respective capacitive elements; controlling the second switch circuit of the sampling cell for the nth most significant bit to sequentially couple the second cell input and the third cell input to respective capacitive elements; It is structured as follows: The calibration circuit includes: determining a weight value of a sampling cell for the n most significant bit based on the comparison signal of the (n+1) calibration measurement; It is configured as follows: n-bit SAR ADC.

2. The calibration circuit includes: selecting a selected one of the second cell input and the third cell input based on the comparison signal of the first calibration measurement. It is configured as follows:

2. The n-bit SAR ADC of claim 1.

3. the first cell input of at least one of the sampling cells being a cell input of the respective sampling cell used to receive an input signal to be digitized during a non-calibration operation of the n-bit SAR ADC; 2. The n-bit SAR ADC of claim 1.

4. At least one of the sampling cells a fourth cell input for receiving an input signal to be digitized during a non-calibrating operation of the n-bit SAR ADC; a third switch circuit operable to selectively couple the fourth cell input to the capacitive element based on a clock signal to sample the input signal.

2. The n-bit SAR ADC of claim 1.

5. The calibration circuit includes: selectively controlling each first switch circuit to couple each first cell input to the capacitive element during calibration; It is structured as follows:

2. The n-bit SAR ADC of claim 1.

6. each sampling cell includes a respective fifth cell input for receiving a fourth signal; the fourth signal exhibits an opposite polarity to the first signal; each first switch circuit is operable to selectively couple one of each of the first cell inputs and each of the fifth cell inputs to a respective capacitive element; 2. The n-bit SAR ADC of claim 1.

7. The calibration circuit includes: selectively controlling each of the first switch circuits to couple a selected one of each of the first cell inputs and each of the fifth cell inputs to a respective capacitive element during calibration; It is configured as follows:

7. The n-bit SAR ADC of claim 6.

8. the capacitive elements of each one of the sampling cells for each of the n bits exhibit the same capacitance; 2. The n-bit SAR ADC of claim 1.

9. the capacitive elements of different sampling cells among the plurality of sampling cells for each bit of the n bits exhibit different capacitances; 2. The n-bit SAR ADC of claim 1.

10. the capacitive element of each one of the sampling cells for each bit of the n bits exhibits a respective capacitance corresponding to the significance of each bit; 10. The n-bit SAR ADC of claim 9.

11. n>1, 2. The n-bit SAR ADC of claim 1.

12. the first signal is a calibration signal, the second signal is a first reference signal, and the third signal is a second reference signal.

2. The n-bit SAR ADC of claim 1.

13. The calibration circuit includes: providing a respective control signal to each second switch circuit of said sampling cells for adjusting a decision threshold of at least one of said comparator circuits during calibration; It is configured as follows:

2. The n-bit SAR ADC of claim 1.

14. 2. The n-bit SAR ADC of claim 1 ; a signal generating circuit configured to generate the first signal; A receiver comprising:

15. the first signal being indicative of an increasing or decreasing signal level; 15. The receiver of claim 14.

16. A receiver according to claim 14; at least one antenna element coupled to the receiver; A base station comprising:

17. The base station further comprises: a transmitter configured to provide a radio frequency transmit signal to the antenna element for radiation into an environment.

17. The base station of claim 16.

18. 2. A method for calibrating an n-bit SAR ADC as claimed in claim 1, comprising: For the first calibration measurement, controlling the second switch circuits of half of the sampling cells for each bit of the n bits to couple the second cell input to a respective capacitive element; controlling the second switch circuits of the other half of the sampling cells for each bit of the n bits to couple the third cell input to a respective capacitive element; For the i th calibration measurement, where 1<i<n+1, controlling the second switch circuit of a sampling cell for the (i-1)-th most significant bit of the n bits to sequentially couple the second cell input and the third cell input to each capacitive element; for i>2, controlling the second switch circuits of the sampling cells for bits up to the (i-2)th most significant bit to couple selected ones of the second cell input and the third cell input to respective capacitive elements; controlling the second switch circuits of half of the sampling cells for each of the i-th through n-th most significant bits to couple the second cell input to a respective capacitive element; controlling the second switch circuits of the other half of the sampling cells for each of the i through n most significant bits to couple the third cell input to a respective capacitive element; For the (n+1)th calibration measurement, controlling the second switch circuits of sampling cells for bits up to the (n-1)th most significant bit to couple selected ones of the second cell input and the third cell input to respective capacitive elements; controlling the second switch circuit of the sampling cell for the nth most significant bit to sequentially couple the second cell input and the third cell input to respective capacitive elements. method.

19. The method further comprising: determining respective values ​​of sampling cell weights for the (i-1) most significant bits based on the comparison signal of the i calibration measurement; 20. The method of claim 18.

20. The method further comprising: determining a weight value of a sampling cell for the n most significant bit based on the comparison signal of the (n+1) calibration measurement.

20. The method of claim 19.

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