Semiconductor structure and method of manufacturing the same - Patents.com

Abstract

The present application provides a semiconductor structure and a method for manufacturing the semiconductor structure, the semiconductor structure includes a source region, a drain region, a gate oxide layer, a gate structure and a conductive plug, the source region and the drain region are spaced apart on a substrate, the gate oxide layer is disposed between the source region and the drain region, the gate structure is disposed on the gate oxide layer, and the conductive plug is disposed at a corresponding position of the source region and the drain region, where the gate structure includes a conductive layer having a sloping side surface, and the sloping side surface faces the conductive plug. Compared with the conventional gate structure, in the technical solution of the present application, the distance between the conductive layer having a sloping side surface and the conductive plug is increased, thereby reducing the parasitic capacitance between the gate structure and the conductive plug, thereby reducing the capacitance between the gate and the source / drain region, and improving the device characteristics.

Description

[Technical field]

[0001] (CROSS-REFERENCE TO RELATED APPLICATIONS) This application claims priority to a Chinese patent application bearing application number 202110432535.6 and entitled "Semiconductor structure and method for manufacturing semiconductor structure", filed with the China Patent Office on April 21, 2021, the entire contents of which are incorporated herein by reference. [Background technology]

[0002] This application relates to, but is not limited to, semiconductor structures and methods of manufacturing semiconductor structures.

[0003] A semiconductor transistor typically includes a gate located on a substrate, and source and drain regions located at the surface of the substrate, and the source and drain regions of the transistor typically have corresponding conductive plugs configured to connect the transistor with other semiconductor devices to achieve the functionality of the transistor.

[0004] The above transistors may have various capacitances that affect the characteristics of the transistor. In particular, the capacitance between the gate and the source region and the capacitance between the gate and the drain region usually affect the high frequency characteristics of the transistor.

[0005] Therefore, there is an urgent need for a solution to reduce the capacitance between the gate and the source / drain regions of semiconductor transistors. Summary of the Invention

[0006] The present embodiments provide semiconductor structures and methods for fabricating the semiconductor structures.

[0007] An embodiment of the present application provides a semiconductor structure, the semiconductor structure including a source region, a drain region, a gate oxide layer, a gate structure and a conductive plug, the source region and the drain region being spaced apart on a substrate, the gate oxide layer being disposed between the source region and the drain region, the gate structure being disposed on the gate oxide layer, and the conductive plug being disposed at a corresponding position of the source region and the drain region, wherein the gate structure includes a conductive layer having an inclined side surface, the inclined side surface facing the conductive plug.

[0008] An embodiment of the present application provides a method for manufacturing a semiconductor structure, the method including: forming a gate oxide layer; forming a gate structure on the gate oxide layer; forming source and drain regions on opposite sides of the gate structure; and forming conductive plugs at corresponding positions of the source and drain regions, where the gate structure includes a conductive layer having an inclined side surface, the inclined side surface facing the conductive plug. [Brief description of the drawings]

[0009] [Figure 1a] 1 shows a typical semiconductor transistor structure. [Figure 1b] 1 shows a typical semiconductor transistor structure. [Figure 2a] 1 is a schematic cross-sectional view of a semiconductor structure according to Example 1 of the present application. [Figure 2b] 1 is a partial enlarged view of an existing semiconductor structure. [Figure 2c] FIG. 2 is a partially enlarged view of a semiconductor structure in an embodiment of the present invention. [Figure 3a] FIG. 2 is a schematic cross-sectional view of another semiconductor structure according to Example 1 of the present application. [Figure 3b] FIG. 2 is a schematic cross-sectional view of another semiconductor structure according to Example 1 of the present application. [Figure 4] FIG. 2 is a schematic cross-sectional view of a semiconductor structure according to Example 2 of the present application. [Diagram 5] FIG. 4 is a schematic cross-sectional view of another semiconductor structure according to Example 2 of the present application. [Figure 6a] FIG. 11 is a schematic structural diagram of an inclined side surface according to a third embodiment of the present application. [Figure 6b] FIG. 11 is a schematic structural diagram of an inclined side surface according to a third embodiment of the present application. [Figure 6c] FIG. 11 is a schematic structural diagram of another inclined side surface according to Example 3 of the present application. [Figure 6d] FIG. 11 is a schematic structural diagram of another inclined side surface according to Example 3 of the present application. [Figure 7] FIG. 1 is a schematic structural diagram of a semiconductor structure according to Example 4 of the present application. [Figure 8a] 5 is an exemplary flowchart of a method for manufacturing a semiconductor structure according to Example 5 of the present application. [Figure 8b] 5 is an exemplary flowchart of a method for manufacturing a semiconductor structure according to Example 5 of the present application. [Figure 8c] 5 is an exemplary flowchart of a method for manufacturing a semiconductor structure according to Example 5 of the present application. [Figure 9a] 8b relates to a schematic structural diagram of a semiconductor structure in a process of a manufacturing method according to the embodiment shown in FIG. [Figure 9b] 8b relates to a schematic structural diagram of a semiconductor structure in a process of a manufacturing method according to the embodiment shown in FIG. [Figure 9c] 8b relates to a schematic structural diagram of a semiconductor structure in a process of a manufacturing method according to the embodiment shown in FIG. [Figure 9d] 8b relates to a schematic structural diagram of a semiconductor structure in a process of a manufacturing method according to the embodiment shown in FIG. [Figure 9e] 8b relates to a schematic structural diagram of a semiconductor structure in a process of a manufacturing method according to the embodiment shown in FIG. [Figure 9f] 8b relates to a schematic structural diagram of a semiconductor structure in a process of a manufacturing method according to the embodiment shown in FIG. [Figure 9g] 8b relates to a schematic structural diagram of a semiconductor structure in a process of a manufacturing method according to the embodiment shown in FIG. [Figure 10a] 8c relates to a schematic structural diagram of a semiconductor structure in the process of a manufacturing method according to the embodiment shown in FIG. [Figure 10b]8c relates to a schematic structural diagram of a semiconductor structure in the process of a manufacturing method according to the embodiment shown in FIG. [Figure 10c] 8c relates to a schematic structural diagram of a semiconductor structure in the process of a manufacturing method according to the embodiment shown in FIG. [Figure 10d] 8c relates to a schematic structural diagram of a semiconductor structure in the process of a manufacturing method according to the embodiment shown in FIG. [Figure 10e] 8c relates to a schematic structural diagram of a semiconductor structure in the process of a manufacturing method according to the embodiment shown in FIG. [Figure 10f] 8c relates to a schematic structural diagram of a semiconductor structure in the process of a manufacturing method according to the embodiment shown in FIG. [Figure 11] 13 is an exemplary flowchart of a method for manufacturing a semiconductor structure according to Example 6 of the present application. [Figure 12] 13 is an exemplary flowchart of a method for manufacturing a semiconductor structure according to Example 7 of the present application. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Some embodiments of the present application are shown in the drawings above and described in more detail below. These drawings and textual description are not intended to limit the scope of the ideas of the present application in any way, but are intended to explain the concepts of the present application to those skilled in the art by reference to specific embodiments.

[0011] The terms "including" and "having" in this application are meant to be inclusive and mean that there may be other elements / components / etc. in addition to the listed elements / components / etc. The terms "first", "second", etc. are merely for labeling purposes and do not impose numerical limitations on their subject matter. In this application, unless otherwise specified, directional terms such as "upper, lower, left, right" generally refer to the upper, lower, left, and right sides shown in the drawings. "Inner, outer" refers to the inner and outer sides of each component's own contour. As can be understood, the above directional terms are relative terms and are used herein for convenience only, for example, in the example directions shown in the drawings, if the device of the symbol is turned upside down, the component described as being "upper" will become the component located "lower". In the drawings, the shapes shown may be modified according to manufacturing processes and / or tolerances. Thus, the exemplary embodiments of this application are not limited to the specific shapes shown in the drawings, and may include shape changes that occur during the manufacturing process. Moreover, different elements and regions in the drawings are shown only diagrammatically, and therefore the present application is not limited to the dimensions or distances shown in the drawings.

[0012] 1a and 1b show (by way of example only) a typical semiconductor transistor structure, with FIG. 1a being a schematic top view and FIG. 1b being a schematic cross-sectional view along the channel length direction aa' shown in FIG. 1a.

[0013] Specifically, when a certain voltage is applied to the gate structure, an inversion layer is formed on the substrate surface between the source region and the drain region, i.e., a channel of the semiconductor transistor is generated, where the channel length direction is from the source region to the drain region or from the drain region to the source region (indicated by aa' in FIG. 1a). It can be understood that the transistor structure shown above is only one possible form, and the technical solution of the present application can be applied to various transistor structures.

[0014] As shown in Fig. 1b, the semiconductor transistor structure 10 includes a substrate 12, a gate structure 14, and a source region 111 and a drain region 112 (also called source electrode and drain electrode) located on either side of the gate structure, where the gate structure 14 includes a conductive layer 16, and a gate oxide layer 13 is provided between the gate structure 14 and the substrate 12. A conductive plug 15 is provided through the dielectric layer in the region corresponding to the source region 111 and the drain region 112, and the conductive plug 15 is configured to transmit an external electrical signal to the source region 111 and the drain region 112 of the transistor.

[0015] In practical applications, various capacitances may exist in the above structure, and in particular, the capacitance between the gate and the source region and the capacitance between the gate and the drain region affect the high-frequency characteristics of the transistor. Therefore, there is an urgent need for a solution that can reduce the capacitance between the gate and the source / drain region of a semiconductor transistor.

[0016] In view of the above problems, the present application finds that the capacitance between the gate and source / drain regions of a semiconductor transistor is positively correlated with the parasitic capacitance generated between the gate conductive layer and the conductive plug, and therefore provides a solution for reducing the parasitic capacitance between the gate conductive layer and the conductive plug of a semiconductor transistor, thereby reducing the capacitance between the gate and the source / drain regions.

[0017] The following provides a detailed description of the technical solution of the present application and how it solves the above technical problems using specific examples. Some specific examples below can be combined with each other, and some examples may not repeat the same or similar concepts or processes. The following describes the embodiments of the present application with reference to the drawings.

[0018] Example 1 FIG. 2a is a schematic cross-sectional view of a semiconductor structure according to a first embodiment of the present application, the semiconductor structure being configured to reduce parasitic capacitance between a gate of a semiconductor transistor and a conductive plug. As shown in FIG. 2a, the semiconductor structure 20 includes a source region 211, a drain region 212, a gate oxide layer 23, a gate structure 24 and a conductive plug 25; The source region 211 and the drain region 212 are provided on a substrate 22 at an interval, The gate oxide layer 23 is provided between the source region 211 and the drain region 212, The gate structure 24 is disposed on the gate oxide layer 23, The conductive plugs 25 are provided at positions corresponding to the source region 211 and the drain region 212, Here, the gate structure 24 includes a conductive layer 26 having a sloping side surface, said sloping side surface facing a conductive plug 25 .

[0019] Here, the substrate 22 may be a semiconductor substrate such as single crystal silicon or polysilicon, or amorphous silicon or silicon germanium (SiGe), or may be a hybrid semiconductor structure such as silicon carbide, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide or gallium antimonide, an alloy semiconductor, or a combination thereof, but this embodiment is not limited thereto. Here, the gate structure may include at least one conductive layer. In this embodiment, the "conductive layer having an inclined side surface" refers to one or more conductive layers among the conductive layers included in the gate structure.

[0020] As shown in FIG. 2a, the substrate 22 has a source region 211 and a drain region 212 spaced apart from each other (the illustrated example is merely an example, and the actual positions of the source region and the drain region are interchangeable), and the terms "source / drain region" and "source / drain region" in this application refer to the source region and the drain region. It can be understood that the illustrated example is merely an example, for example, the gate oxide layer 23 can cover the region other than the surface of the substrate between the source region 211 and the drain region 212, and in practical applications, the gate oxide layer can be fabricated together with a dielectric layer on the surface of the substrate. A gate structure 24 is provided on the gate oxide layer 23, and the gate structure 24 is located between the source region 211 and the drain region 212 and configured to control the conduction or cutoff of the transistor according to an externally applied voltage. A conductive plug 25 provided corresponding to the source region 211 and the drain region 212 is in contact with the source region 211 and the drain region 212 and is used to transmit an electric signal to the source region and the drain region to realize the function of the transistor. Exemplarily, the gate structure 24 may further include a protective layer 245, which may protect the gate structure from damage, where the protective layer may include, but is not limited to, a silicon nitride layer.

[0021] In the present application, it has been found that in the above structure, a parasitic capacitance is formed between the conductive layer of the gate structure and the conductive plug, and the parasitic capacitance constitutes a part of the capacitance between the gate and the source / drain region. In particular, in the field of semiconductors where high integration and miniaturization are progressing, these capacitances may affect the device characteristics of semiconductor transistors. In view of this, the present application provides a semiconductor structure, in which the gate structure includes a conductive layer having an inclined side surface, and the inclined side surface faces a conductive plug, as shown in FIG. 2a. The semiconductor structure according to the present application can reduce the parasitic capacitance between the conductive layer of the gate structure and the conductive plug, thereby reducing the capacitance between the gate and the source / drain region and improving the device characteristics.

[0022] In order to understand the present application more intuitively, the present application will be described with reference to Fig. 2b and Fig. 2c. As shown in the figure, Fig. 2b is a partial enlarged view of an existing semiconductor structure, and Fig. 2c is a partial enlarged view of the semiconductor structure of the present application. Here, in the semiconductor structure shown in Fig. 2b, the gate structure 14 includes a conductive layer 16, and a conductive plug 15 is provided at a position corresponding to the source region or drain region. In the semiconductor structure shown in Fig. 2c, the gate structure 24 includes a conductive layer 26, and a conductive plug 25 is provided at a position corresponding to the source region or drain region. As can be seen from this, in the semiconductor structure shown in Fig. 2c, the conductive layer 26 has an inclined side surface, which is the side surface of the conductive layer 26 facing the conductive plug 25.

[0023] 2b and 2c, in the existing semiconductor structure, the minimum distance between the conductive layer and the conductive plug is Sm', and in the semiconductor structure according to the present application, the minimum distance between the conductive layer and the conductive plug is Sm, which is greater than Sm'. Thus, compared with a gate structure without a sloping side surface, in the semiconductor structure according to the present application, at least one conductive layer of the gate structure has a sloping side surface facing the conductive plug, so that the distance from the side surface of the conductive layer to the conductive plug is increased, thereby reducing the parasitic capacitance between the conductive layer and the conductive plug.

[0024] It should be noted that only one conductive plug is shown in the enlarged view, but it can be understood that in other semiconductor structures, even if the structural position of the conductive plug is different from that shown, the solution of the present application can be applied to the gate structure of these semiconductor structures, so that the gate structure includes at least one conductive layer, and the side of the conductive layer facing the conductive plug is an inclined side, and these solutions also belong to the solution of the embodiment of the present application. In one embodiment, the semiconductor structure further includes lightly doped regions located on both sides of the gate structure. By providing lightly doped regions on both sides of the gate, the short channel effect can be reduced.

[0025] In the semiconductor structure according to the present embodiment, the gate structure includes at least one conductive layer having an inclined side surface, and the inclined side surface faces a conductive plug. Compared with the conventional gate structure, the distance between the at least one conductive layer of the gate structure in the present application and the conductive plug is increased, thereby reducing the parasitic capacitance between the gate structure and the conductive plug, thereby reducing the capacitance between the gate and the source / drain region, and improving the device characteristics.

[0026] In the following, each part of the semiconductor structure (conductive plug and lateral isolation structure) will be described with reference to Figures 3a and 3b, respectively. It should be understood that the following embodiments of Figures 3a and 3b may be implemented in combination, or in combination with any other embodiment of the present application, and may be applied to any semiconductor structure, such as semiconductor structure 20, semiconductor structure 40, and semiconductor structure 50.

[0027] 3a is a schematic cross-sectional view of another semiconductor structure according to Example 1 of the present application, in which the structure of a conductive plug is described in this embodiment. As shown in FIG. 3a, based on any other embodiment (shown in this figure in combination with the structure shown in FIG. 2a), the semiconductor structure further includes a second dielectric layer 31 and a contact hole 32;

[0028] A second dielectric layer 31 is provided over the substrate 22 and the gate structure 24;

[0029] The contact hole 32 penetrates the second dielectric layer 31 and contacts the corresponding source region 211 and drain region 212, and the bottom of the contact hole 32 is a shallow trench structure, and the shallow trench structure is located in the corresponding source region 211 and drain region 212; Here, the conductive plug 25 includes a metal plug 251 filled in the contact hole 32 , and a barrier layer 252 located between the metal plug 251 and the inner wall of the contact hole 32 .

[0030] Specifically, the conductive plug in this embodiment is provided at a position corresponding to the source region and the drain region through the dielectric layer. Here, the conductive plug adopts an inner and outer multilayer structure, that is, the conductive plug includes an inner metal plug and a barrier layer attached between the surface of the metal plug and the inner wall of the contact hole. Here, the barrier layer is used to prevent the inner metal plug from diffusing into the substrate and contaminating the substrate, and to ensure the characteristics of the transistor. Note that the illustrated example is merely an example, and this embodiment focuses on the structure of the conductive plug, and the conductive plug according to this embodiment can be applied to other examples.

[0031] Exemplarily, a metal silicide 253 is filled between the conductive plug 25 and the inner wall of the shallow trench structure. Here, the metal silicide 253 includes, but is not limited to, cobalt silicide (CoSi). By forming the metal silicide on the inner wall of the shallow trench structure, the contact resistance between the conductive plug and the source / drain region can be reduced, and the characteristics of the transistor can be optimized.

[0032] In one embodiment, the semiconductor structure further comprises lightly doped regions located on either side of the gate structure. By providing lightly doped regions on either side of the gate, short channel effects can be reduced.

[0033] The conductive plug according to this embodiment employs an inner and outer multi-layer structure, thereby making it possible to prevent metal diffusion and ensure the device characteristics of the transistor.

[0034] 3b is a schematic cross-sectional view of another semiconductor structure according to Example 1 of the present application, in which a lateral isolation structure is described in this embodiment. As shown in FIG. 3b, based on any other embodiment (shown in combination with semiconductor structure 20 in this figure), the semiconductor structure further includes a lateral isolation structure 33; The lateral isolation structures 33 are attached to the two sides of the gate structure 24 facing the source region 211 and the drain region 212 .

[0035] Exemplarily, the lateral isolation structure may adopt a multi-layer structure. In one embodiment, the lateral isolation structure 33 includes a first isolation sidewall 331 and a second isolation sidewall 332, the first isolation sidewall 331 is attached to the side of the gate structure 24, the second isolation sidewall 332 is located on the periphery of the first isolation sidewall 331, and the top of the second isolation sidewall 332 extends to the top of the first isolation sidewall 331 to form a sealed space, and the sealed space is filled with a separation medium 333. Here, the separation medium 333 includes, but is not limited to, silicon oxide, air, etc. Here, the material of the first isolation sidewall and the second isolation sidewall may include silicon nitride.

[0036] Here, each portion of the lateral isolation structure can be located on the gate oxide layer or on the substrate. As an example, the first isolation sidewall is located on the substrate, and the isolation medium and the second isolation sidewall are located on the substrate (as in the example of FIG. 3b). As another example, the first isolation sidewall and the isolation medium are located on the gate oxide layer, and the second isolation sidewall is located on the substrate. As yet another example, the first isolation sidewall, the isolation medium and the second isolation sidewall are all located on the gate oxide layer.

[0037] The above side isolation structure may adopt a multi-layer structure considering the support effect and stress. Specifically, the first isolation sidewall and the second isolation sidewall may adopt a material with high hardness, high compactness and high dielectric constant, such as silicon nitride, to achieve a good support effect and to achieve an effective isolation and insulation effect. Furthermore, in consideration of good stress, in the side isolation structure of this embodiment, a material with good stress characteristics, such as silicon oxide, is filled between the first isolation sidewall and the second isolation sidewall. In one embodiment, filling air between the first isolation sidewall and the second isolation sidewall can achieve a better isolation and insulation effect and reduce the influence of stress. Filling air between the first isolation sidewall and the second isolation sidewall can also reduce the equivalent dielectric constant between the gate structure 24 and the conductive plug 25, thereby further reducing the parasitic capacitance between them.

[0038] In one embodiment, the semiconductor structure further includes lightly doped regions 34 located on both sides of the gate structure. Providing lightly doped regions on both sides of the gate can reduce short channel effects. Exemplarily, the area of ​​the lightly doped region 34 is determined according to the device design, for example, the lightly doped region 34 may be located under the first isolation sidewall (as in the example of FIG. 3b), or under the first isolation sidewall and the isolation medium, or under the first isolation sidewall, the isolation medium and the second isolation sidewall.

[0039] In this embodiment, by providing lateral isolation structures on both sides of the gate structure, the occurrence of short circuits between the gate and other components is avoided, and good characteristics of the transistor are ensured.

[0040] In the following, different embodiments of the gate structure will be described with reference to Example 2. Similarly, Example 2 can be implemented in various combinations with any other examples of the present application, such as in combination with examples corresponding to sloping sidewalls, conductive plugs, and lateral isolation structures.

[0041] Example 2 FIG. 4 is a schematic cross-sectional view of a semiconductor structure according to a second embodiment of the present application, in which the gate structure includes a conductive layer and a plurality of metal layers. As shown in FIG. 4, the semiconductor structure 40 includes a source region 411, a drain region 412, a gate oxide layer 43, a gate structure 44 and a conductive plug 45; The source region 411 and the drain region 412 are provided on a substrate 42 at an interval, The gate oxide layer 43 is provided between the source region 411 and the drain region 412, The gate structure 44 is disposed on the gate oxide layer 43, The conductive plugs 45 are provided at positions corresponding to the source region 411 and the drain region 412, Here, the gate structure 44 includes a first conductive layer 441 and a second conductive layer 442, the first conductive layer 441 being provided on the gate oxide layer 43, the second conductive layer 442 being provided on the first conductive layer 441, and the second conductive layer 442 including a plurality of stacked metal layers (the drawing shows an example including two metal layers), at least one of which, the metal layer 46, has an inclined side surface, and the inclined side surface faces the conductive plug 45. The metal layer here may be made of a metal such as tungsten, or a metal compound such as titanium nitride. In FIG. 4, other symbols than the structures corresponding to the above symbols refer to structures shown in related drawings in other examples, and here, these other symbols are combined with FIG. 4 to be displayed as one embodiment of the present application.

[0042] Here, the substrate 42 may be a semiconductor substrate such as monocrystalline silicon or polysilicon, or amorphous silicon or silicon germanium (SiGe), or may be a hybrid semiconductor structure such as silicon carbide, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide or gallium antimonide, an alloy semiconductor, or a combination thereof, but this embodiment is not limited thereto. Here, the gate structure includes a first conductive layer provided on the gate oxide layer, and a second conductive layer provided on the first conductive layer. Here, the second conductive layer includes a plurality of metal layers, and the "conductive layer having an inclined side surface" in this embodiment refers to one or more of the plurality of metal layers.

[0043] In practical applications, the threshold voltage of a transistor is mainly determined by the difference in work function between the gate and the gate oxide layer. Therefore, in this embodiment, the first conductive layer in direct contact with the gate oxide layer does not have a sloped side surface to ensure the matching of the work function and reduce the contact resistance. Although the first conductive layer in direct contact with the gate oxide layer is not provided with a sloped side surface in this embodiment, the present application does not exclude a solution in which a sloped side surface is formed on the side surface of the first conductive layer, in which the size of the upper edge of the first conductive layer is made smaller than the size of the lower edge, thereby optimizing the contact resistance and reducing the capacitance. In addition, in one possible embodiment, in order to optimize the characteristics of the transistor, the first conductive layer 441 includes a polysilicon layer. Specifically, the polysilicon can be doped with impurities having different polarities to change the work function and adjust the threshold voltage of the transistor. In another possible embodiment, the second conductive layer 442 includes a plurality of metal layers, including but not limited to a titanium nitride layer and a tungsten layer. In one example, the second conductive layer includes a titanium nitride layer disposed on the polysilicon layer and a tungsten layer disposed on the titanium nitride layer, where the tungsten layer has an inclined side surface, and the inclined side surface faces the conductive plug. Note that the above-mentioned possible embodiments can be implemented in combination with each other.

[0044] Similarly, compared to a gate structure without inclined side surfaces, at least one metal layer of the second conductive layer in this embodiment has inclined side surfaces, so that the distance between the metal layer with the inclined side surfaces and the conductive plug is increased, thereby reducing the parasitic capacitance between the metal layer and the conductive plug, thereby reducing the parasitic capacitance between the entire gate structure and the source or drain region connected by the conductive plug.

[0045] In the semiconductor structure according to this embodiment, the second conductive layer of the gate structure includes a plurality of metal layers, at least one of which has a sloping side face facing the conductive plug, and compared to a gate structure not having a sloping side face, the distance between the metal layer having the sloping side face in this application and the conductive plug is increased, thereby reducing the parasitic capacitance between the gate structure and the conductive plug, thereby reducing the capacitance between the gate and the source / drain region and improving device characteristics.

[0046] FIG. 5 is a schematic cross-sectional view of another semiconductor structure according to Example 2 of the present application, in which the gate structure in this example includes a dielectric layer and a metal layer. As shown in FIG. 5, the semiconductor structure 50 includes a source region 511, a drain region 512, a gate oxide layer 53, a gate structure 54 and a conductive plug 55; The source region 511 and the drain region 512 are provided on a substrate 52 at an interval, The gate oxide layer 53 is provided between the source region 511 and the drain region 512, The gate structure 54 is disposed on the gate oxide layer 53, The conductive plugs 55 are provided at positions corresponding to the source region 511 and the drain region 512, Here, the gate structure 54 includes a first dielectric layer 541 and a third conductive layer, where the first dielectric layer 541 is disposed on the gate oxide layer 53, the third conductive layer is disposed on the first dielectric layer 541, and the third conductive layer is a metal layer 56, where the metal layer 56 has an inclined side surface, and the inclined side surface faces the conductive plug 55.

[0047] Here, the substrate 52 may be a semiconductor substrate such as single crystal silicon or polysilicon, or silicon or silicon germanium (SiGe) with an amorphous structure, or may be a hybrid semiconductor structure such as silicon carbide, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide or gallium antimonide, an alloy semiconductor, or a combination thereof, but this embodiment is not limited thereto. Here, the gate structure 54 includes a first dielectric layer provided on the gate oxide layer, and a third conductive layer provided on the first dielectric layer. Here, the third conductive layer is a metal layer, such as a single metal layer or multiple metal layers. In this embodiment, a single metal layer is exemplified as the "conductive layer having an inclined side surface."

[0048] In one embodiment, the first dielectric layer 541 includes a high-k material, such as hafnium oxide or zirconium oxide. The first dielectric layer and the gate oxide layer together form a gate dielectric layer to reduce tunneling. In another embodiment, the third conductive layer provided on the first dielectric layer 541 includes a tungsten layer, the tungsten layer having a sloping side surface, the sloping side surface facing the conductive plug. The third conductive layer may be a metal, such as copper, aluminum, or titanium. Note that the two embodiments may be implemented in combination with each other.

[0049] Similarly, compared to a gate structure without inclined side surfaces, at least one metal layer of the third conductive layer in this embodiment has inclined side surfaces, thereby increasing the distance between the metal layer with inclined side surfaces and the conductive plug, thereby reducing the parasitic capacitance between the metal layer and the conductive plug, thereby reducing the parasitic capacitance between the entire gate structure and the source or drain region connected to the conductive plug.

[0050] In the semiconductor structure according to this embodiment, the gate structure includes a first dielectric layer and a third conductive layer, where the third conductive layer includes a metal layer having a sloped side surface facing the conductive plug, and compared to a gate structure not having a sloped side surface, the distance between the metal layer having a sloped side surface in this embodiment and the conductive plug is increased, thereby reducing the parasitic capacitance between the gate structure and the conductive plug, thereby reducing the capacitance between the gate and the source / drain region and improving device characteristics.

[0051] Hereinafter, different embodiments of the inclined side surface will be described with reference to Example 3. Note that the following embodiments of the inclined side surface can be applied to the conductive layer of the gate structure of any other example.

[0052] Example 3 FIG. 6a and FIG. 6b are schematic structural diagrams of the inclined side according to the third embodiment of the present application. In the drawings, the description will be made with reference to a part of the structure of FIG. 4. As shown in the drawings, based on any other embodiment, A first distance St from an upper edge of the inclined side surface to the conductive plug is greater than a second distance Sb from a lower edge of the inclined side surface to the conductive plug.

[0053] In addition, the drawings also show other structures located near the inclined side surface, such as a substrate, a gate oxide layer, a gate structure, etc., which are all illustrative and do not limit the scope of the present embodiment. Specifically, the present embodiment focuses on the structure of the inclined side surface, and the inclined side surface according to the present embodiment can be combined with any other embodiment.

[0054] As an example, as shown in Figure 6a, the surface at the intermediate position of the inclined side is substantially flat, while as another example, as shown in Figure 6b, the surface at the intermediate position of the inclined side is substantially stepped.

[0055] FIG. 6c and FIG. 6d are schematic structural diagrams of another inclined side according to the third embodiment of the present application. The drawings refer to the part of the structure in FIG. 4 for explanation. As shown in the drawings, based on any other embodiment, A first distance St from an upper edge of the inclined side surface to the conductive plug is smaller than a second distance Sb from a lower edge of the inclined side surface to the conductive plug.

[0056] As an example, the surface of the intermediate portion of the inclined side is substantially flat as shown in Fig. 6c, or as another example, the surface of the intermediate portion of the inclined side is substantially stepped as shown in Fig. 6d.

[0057] In this embodiment, the size of the lower edge of the conductive layer having the inclined side surface is smaller than the size of the upper edge. Exemplarily, the size of the upper edge of the lower adjacent layer of the conductive layer may be approximately the same as the size of the upper edge of the conductive layer (as shown in FIG. 6c) or approximately the same as the size of the lower edge of the conductive layer (as shown in FIG. 6d). Specifically, the above structure may be implemented by a related process to reduce the capacitance between the gate and the conductive plug. It should be noted that the drawings only show a structure combining the above examples and embodiments, but in reality, these examples and embodiments may be implemented separately or in different combinations, for example, the surface at the middle position of the inclined side surface is approximately flat, and the size of the upper edge of the adjacent layer is approximately the same as the size of the lower edge of the conductive layer. Exemplarily, similarly, the size of the lower edge of the upper adjacent layer of the conductive layer may be approximately the same as the size of the upper edge of the conductive layer or approximately the same as the size of the lower edge of the conductive layer.

[0058] The inclined side structure according to this embodiment can be applied to the aforementioned structure such that at least one conductive layer in the gate structure has the inclined side facing the conductive plug, and compared to a gate structure without the inclined side, the distance between the conductive layer having the inclined side in this embodiment and the conductive plug is increased, thereby reducing the parasitic capacitance between the gate structure and the conductive plug, thereby reducing the capacitance between the gate and the source-drain region, and improving the device characteristics.

[0059] Example 4 This embodiment provides an example of implementing some of the above-mentioned embodiments in combination, and Fig. 7 is a schematic structural diagram of a semiconductor structure according to embodiment 4 of the present application, which is based on the combination of the embodiment shown in Fig. 3a and Fig. 3b, embodiment 2 and embodiment 3. As shown in Fig. 7, the semiconductor structure includes a source region 711, a drain region 712, a gate oxide layer 73, a gate structure 74, a conductive plug 75, a second dielectric layer 31, a contact hole 32, a lateral isolation structure 33 and a lightly doped region 34; A source region 711 and a drain region 712 are spaced apart on a substrate 72, a gate oxide layer 73 is provided between the source region 711 and the drain region 712, a gate structure 74 is provided on the gate oxide layer 73, and conductive plugs 75 are provided at corresponding positions of the source region 711 and the drain region 712; Here, the gate structure 74 includes a first conductive layer 741 and a second conductive layer 742, the first conductive layer 741 being disposed on the gate oxide layer 73, the second conductive layer 742 being disposed on the first conductive layer 741, the second conductive layer 742 including a plurality of stacked metal layers, at least one metal layer 76 of the plurality of metal layers having an inclined side surface facing the conductive plug 75, a first distance from an upper edge of the inclined side surface to the conductive plug 75 being smaller than a second distance from a lower edge of the inclined side surface to the conductive plug 75, and a surface at an intermediate position of the inclined side surface is substantially flat; A second dielectric layer 31 is provided on the substrate 72 and the gate structure 74, a contact hole 32 penetrates the second dielectric layer 71 and contacts the corresponding source region 711 and drain region 712, a bottom of the contact hole 32 is a shallow trench structure, and the shallow trench structure is located in the corresponding source region 711 and drain region 712; Here, the conductive plug 75 includes a metal plug 751 filled in the contact hole 32, and a barrier layer 752 located between the metal plug 751 and the inner wall of the contact hole 32. A metal silicide 753 is filled between the conductive plug 75 and the inner wall of the shallow trench structure. The lateral isolation structure 33 is attached to two sides of the gate structure 74 facing the source region 211 and the drain region 212, the lateral isolation structure 33 includes a first isolation sidewall 331 and a second isolation sidewall 332, the first isolation sidewall 331 is attached to the side of the gate structure 74, the second isolation sidewall 332 is located on the periphery of the first isolation sidewall 331, and the top of the second isolation sidewall 332 extends to the top of the first isolation sidewall 331 to form a sealed space, the sealed space is filled with a separation medium 333, and the separation medium 333 may be air; Lightly doped regions 34 are located on either side of the gate structure 74 .

[0060] The description and effects of each part of the above structure have been described in detail in the above-mentioned embodiments, so reference can be made to the relevant contents of the above-mentioned embodiments and will not be repeated here.

[0061] The above-mentioned Examples 1 to 4 are illustrative descriptions of the semiconductor structure according to the present application, and hereinafter, the manufacturing method of the semiconductor structure will be described with reference to Examples 5 to 7.

[0062] Example 5 FIG. 8a is an exemplary flowchart of a method for manufacturing a semiconductor structure according to Example 5 of the present application, the semiconductor structure being configured to reduce parasitic capacitance between a gate of a semiconductor transistor and a conductive plug, and as shown in FIG. 8a, the method includes the following steps:

[0063] In step 101, a gate oxide layer is formed.

[0064] In step 102, a gate structure is formed on the gate oxide layer.

[0065] In step 103, source and drain regions are formed on either side of the gate structure.

[0066] In step 104, conductive plugs are formed in corresponding locations of the source region and the drain region, where the gate structure includes a conductive layer having a sloped sidewall, the sloped sidewall facing the conductive plug.

[0067] Exemplarily, step 102 specifically includes forming a gate structure on the gate oxide layer, the top layer of which is a protective layer, that is, the gate structure may further include a top layer that functions as a protective layer.

[0068] In one example, the gate structure includes a first conductive layer and a second conductive layer, the second conductive layer includes a plurality of metal layers, and at least one of the plurality of metal layers has an inclined side surface. As one possible embodiment, the gate structure can be obtained by the following manufacturing method, and correspondingly, as shown in FIG. 8b, step 102 can specifically include the following steps:

[0069] In step 201, a first conductive layer is formed over a gate oxide layer.

[0070] In step 202, a second conductive layer is formed on the first conductive layer, the second conductive layer including a plurality of stacked metal layers.

[0071] The next step 203 is repeatedly performed until the first conductive layer is exposed.

[0072] In step 203, if the layer now exposed in the first region is a predetermined metal layer, then etching the predetermined metal layer in the first region while adjusting the etching direction and rate so that the predetermined metal layer has sloping sides facing the source and drain regions until a next metal layer is exposed, and if the layer now exposed in the first region is not a predetermined metal layer, then etching downwardly the exposed layer in areas not covered by the first region or an overlying layer until a next metal layer is exposed, where the first region is an area other than the area between the source and drain regions.

[0073] In step 204, the first conductive layer is etched downward in the first region or in areas not covered by the overlying layer until the gate oxide layer is exposed to form the gate structure.

[0074] Specifically, the schematic structural diagram of the semiconductor structure after performing step 101 is as shown in FIG. 9a, where the substrate is represented by reference number 92, and the gate oxide layer is represented by reference number 93. The schematic structural diagram of the semiconductor structure after performing steps 201 and 202 is as shown in FIG. 9b, where the first conductive layer is represented by reference number 941, and the second conductive layer is represented by reference number 942. The schematic structural diagram of the semiconductor structure after performing step 203 is as shown in FIG. 9c, where the predetermined metal layer is represented by reference number 96. The schematic structural diagram of the semiconductor structure after performing step 204 is as shown in FIG. 9d, where the gate structure is represented by reference number 94. Illustratively, step 103 may specifically include etching the currently uncovered gate oxide layer until the substrate is exposed. Correspondingly, the schematic structural diagram of the semiconductor structure after performing this step is as shown in FIG. 9e. After etching the gate oxide layer, a source region and a drain region located on both sides of the gate structure are formed. Correspondingly, the schematic diagram of the semiconductor structure after performing step 104 is as shown in FIG. 9f, in which the source region and the drain region are denoted by reference numerals 911 and 912, respectively. Here, the protective layer is denoted by reference numeral 945 in the figure, and the protective layer may be formed after etching the gate oxide layer. Correspondingly, the schematic diagram of the semiconductor structure after performing step 104 is as shown in FIG. 9g, in which the conductive plug is denoted by reference numeral 95, and the second dielectric layer is denoted by reference numeral 31.

[0075] In another example, the gate structure includes a first dielectric layer and a third conductive layer, the third conductive layer includes a metal layer, and the metal layer has an inclined side surface. In one possible embodiment, the gate structure can be obtained by the following manufacturing method, and correspondingly, as shown in FIG. 8c, step 102 can specifically include the following steps:

[0076] In step 301, a first dielectric layer is formed over the gate oxide layer.

[0077] In step 302, a third conductive layer is formed on the first dielectric layer, the third conductive layer being a metal layer.

[0078] In step 303, the third conductive layer in the first region is etched while adjusting the etching direction and rate so that the third conductive layer has sloped sides facing the source and drain regions until the first dielectric layer is exposed, where the first region is other than the region between the source and drain regions.

[0079] In step 304, the first dielectric layer in the first region not covered by the first dielectric layer or the third conductive layer is etched downward until the gate oxide layer is exposed to form the gate structure.

[0080] Specifically, the schematic structural diagram of the semiconductor structure after performing step 101 is shown in FIG. 9a, where the substrate is represented by 92 and the gate oxide layer is represented by 93. The schematic structural diagram of the semiconductor structure after performing steps 301 and 302 is shown in FIG. 10a, where the first dielectric layer is represented by 1041 and the third conductive layer is represented by 1042. The schematic structural diagram of the semiconductor structure after performing step 303 is shown in FIG. 10b, where the third conductive layer is a metal layer and the metal layer is represented by 96. The schematic structural diagram of the semiconductor structure after performing step 304 is shown in FIG. 10c, where the gate structure is represented by 1004. Similarly, in one example, step 103 may specifically include etching the now uncovered gate oxide layer until the substrate is exposed. Correspondingly, the schematic structural diagram of the semiconductor structure after performing the step is shown in FIG. 10d. After etching the gate oxide layer, the source region and the drain region located on both sides of the gate structure are formed. Correspondingly, the schematic structural diagram of the semiconductor structure after performing this step is as shown in FIG. 10e, where the source region and the drain region are respectively represented by reference numerals 911 and 912. Here, the protective layer is represented by reference numeral 945 in the figure, and the protective layer may be formed after etching the gate oxide layer. Correspondingly, the schematic structural diagram of the semiconductor structure after performing step 104 is as shown in FIG. 10f, where the conductive plug is represented by reference numeral 95, and the second dielectric layer is represented by reference numeral 31.

[0081] In the semiconductor structure according to the present embodiment, the gate structure includes at least one conductive layer having an inclined side surface, and the inclined side surface faces a conductive plug. Compared with the conventional gate structure, in the present embodiment, the distance between the at least one conductive layer of the gate structure and the conductive plug is increased, thereby reducing the parasitic capacitance between the gate structure and the conductive plug, thereby reducing the capacitance between the gate and the source / drain region, and improving the device characteristics.

[0082] Example 6 FIG. 11 is an exemplary flowchart of a method for manufacturing a semiconductor structure according to Example 6 of the present application, which is used to manufacture a conductive plug of a semiconductor structure. As shown in FIG. 11, based on Example 5, step 104 specifically includes the following steps:

[0083] In step 1101, a second dielectric layer is formed over the substrate and the gate structure.

[0084] In step 1102, a patterned etching protection layer is formed on the second dielectric layer, the etching protection layer covering a surface of the dielectric layer except for partial regions corresponding to the source and drain regions.

[0085] In step 1103, etch downward from the exposed surface of the second dielectric layer until the surfaces of the source and drain regions are exposed, and over-etch the surfaces of the source and drain regions to form contact holes having shallow trench structures at their bottoms, the shallow trench structures being located at corresponding ones of the source and drain regions.

[0086] In step 1104, a barrier layer is formed on the inner wall of the contact hole, and a metal is filled into the contact hole covered with the barrier layer to form a conductive plug.

[0087] Exemplarily, before step 1104, the method further includes forming a metal silicide on an inner wall of the shallow trench structure at the bottom of the contact hole. According to this embodiment, the metal silicide located between the conductive plug and the inner wall of the shallow trench structure can be formed.

[0088] The conductive plug according to the present embodiment employs an inner and outer multi-layer structure to prevent metal diffusion and ensure the device characteristics of the transistor. Furthermore, by forming a metal silicide on the inner wall of the shallow trench structure, the contact resistance between the conductive plug and the source / drain region can be reduced, and the characteristics of the transistor can be optimized.

[0089] Example 7 FIG. 12 is an exemplary flowchart of a method for manufacturing a semiconductor structure according to Example 7 of the present application, which is used to manufacture a lateral isolation structure of a semiconductor structure, and as shown in FIG. 12, based on Example 5 or Example 6, after step 102, the method further includes the following steps:

[0090] In step 1201, lateral isolation structures are formed on two sides of a gate structure facing the source and drain regions.

[0091] Exemplarily, step 1201 specifically includes: forming a first isolation sidewall on a side of the gate structure facing the source region and the drain region; covering an outer wall of the first isolation sidewall with an isolation medium; and forming a second isolation sidewall on the outer wall of the isolation medium, where a top of the second isolation sidewall extends to a top of the first isolation sidewall to form a sealed space surrounding the isolation medium, where the isolation medium may include, but is not limited to, silicon oxide.

[0092] Here, each part of the lateral isolation structure may be provided on the gate oxide layer or the substrate to achieve an isolation effect. As an example, the first isolation sidewall is provided on the gate oxide layer, and the isolation medium and the second isolation sidewall are provided on the substrate. In the corresponding process, the first isolation sidewall can be formed before etching the gate oxide layer, then the gate oxide layer is etched, and finally the second isolation sidewall can be formed. As another example, the first isolation sidewall and the isolation medium are provided on the gate oxide layer, and the second isolation sidewall is provided on the substrate. In the corresponding process, the first isolation sidewall and the isolation medium can be formed before etching the gate oxide layer, then the gate oxide layer is etched, and finally the second isolation sidewall can be formed. As yet another example, the first isolation sidewall, the isolation medium, and the second isolation sidewall are all provided on the gate oxide layer. In the corresponding process, the first isolation sidewall, the isolation medium, and the second isolation sidewall can be formed before etching the gate oxide layer, then the gate oxide layer is etched, and finally the second isolation sidewall can be formed. Illustratively, the step of forming the source-drain regions may be performed after etching the gate oxide layer.

[0093] Exemplarily, step 1201 specifically includes: forming a third isolation sidewall on the side of the gate structure facing the source region and the drain region; covering the outer wall of the third isolation sidewall with a third dielectric layer; forming a fourth isolation sidewall on the outer wall of the third dielectric layer, the top of the fourth isolation sidewall extending to the top of the third isolation sidewall to form a sealed space surrounding the third dielectric layer; etching the top of the fourth isolation sidewall until the surface of the third dielectric layer is exposed to form an etching hole; etching the third dielectric layer through the etching hole until the surface of the gate oxide layer is reached; and sealing the etching hole between the top of the fourth isolation sidewall and the top of the third isolation sidewall by a rapid deposition process to form a sealed space filled with air. Similarly, each part of the side isolation structure in this embodiment can also be located on the gate oxide layer or the substrate, and the relevant contents can refer to the description of the above embodiment, and will not be described again here.

[0094] In one embodiment, in order to reduce the short channel effect, the semiconductor structure further includes a lightly doped region located on both sides of the gate structure. Correspondingly, the manufacturing method further includes forming a lightly doped region located on both sides of the gate structure. Exemplarily, the region of the lightly doped region is determined according to the device design, for example, the lightly doped region may be located under the first isolation sidewall, or under the first isolation sidewall and the isolation medium, or under the first isolation sidewall, the isolation medium and the second isolation sidewall. Correspondingly, the step of forming the lightly doped region may be performed after forming the first isolation sidewall, may be performed after forming the first isolation sidewall and the isolation medium, or may be performed after forming the second isolation sidewall, but the embodiment is not limited to the order of performing the process.

[0095] In the process example described with reference to the above embodiment of the protective layer, the step of forming the protective layer may be performed before the step of forming the lateral isolation structure, or in practical application, when the material of the protective layer is the same as the material of the isolation sidewall, the protective layer may be formed together with the process of forming the lateral isolation structure, or the protective layer may be formed after the lateral isolation structure is formed. This embodiment is not limited to the specific order of steps, that is, the process according to this embodiment can be used to form the semiconductor structure in the above embodiment.

[0096] In this embodiment, by providing lateral isolation structures on both sides of the gate structure, it is possible to avoid the occurrence of short circuits between the gate and other components, and to ensure good transistor characteristics while balancing the support effect and good stress characteristics.

[0097] Those skilled in the art can easily conceive of other embodiments of the present application by reading this specification and practicing the invention disclosed herein. This application is intended to cover any modifications, applications or adaptations of the present application, which modifications, applications or adaptations conform to the general principles of the present application and include common knowledge or conventional technical means known in the art that are not disclosed herein. The specification and examples should be considered as merely exemplary, with the true scope and spirit of the present application being indicated by the appended claims.

[0098] It should be understood that the present application is not limited to the exact construction described above and shown in the drawings, and various modifications and changes can be made without departing from the scope thereof, which should be dictated by the appended claims. [Explanation of symbols]

[0099] 10 Existing semiconductor structures 111 Source Region 112 Drain Region 12 Substrate 13 Gate oxide layer 14 Gate structure 15 Conductive plug 16 Conductive layer 20 Semiconductor Structure 211 Source Region 212 Drain Region 22 Substrate 23 Gate oxide layer 24 Gate Structure 25 Conductive plug 251 Metal plug 252 Barrier Layer 253 Metal silicide 26 Conductive layer with inclined sides 31 Second dielectric layer 32 Contact Hole 33 Side separation structure 331 1st separation side wall 332 2nd separation side wall 333 Separation media 34 Lightly doped region 40 Semiconductor Structure 411 Source Region 412 Drain Region 42 Substrate 43 Gate oxide layer 44 Gate Structure 441 First conductive layer 442 Second conductive layer 45 Conductive plug 46 Metal layer with inclined sides 50 Semiconductor Structure 511 Source Region 512 Drain Region 52 Substrate 53 Gate oxide layer 54 Gate Structure 541 First Dielectric Layer 55 Conductive plug 56 Metal layer with inclined sides 711 Source Region 712 Drain Region 72 Substrate 73 Gate oxide layer 74 Gate Structure 741 First conductive layer 742 Second conductive layer 75 Conductive plug 751 Metal plug 752 Barrier Layer 753 Metal silicide 76 Metal layer with inclined sides 911 Source Region 912 Drain Region 92 Substrate 93 Gate oxide layer 94 Gate Structure 941 First conductive layer 942 Second conductive layer 945 Protective layer 95 Conductive Plug 96 Prescribed metal layer 1004 Gate Structure 1041 First dielectric layer 1042 Third conductive layer

Claims

1. 1. A semiconductor structure comprising: a source region and a drain region spaced apart on the substrate; a gate oxide layer disposed between the source region and the drain region; a gate structure disposed on the gate oxide layer; a conductive plug provided at a position corresponding to the source region and the drain region; the gate structure includes a conductive layer having a sloped side surface, the sloped side surface facing the conductive plug; A semiconductor structure, wherein a surface at an intermediate position of the inclined side surface is stepped, and the intermediate position of the inclined side surface is located between an upper edge and a lower edge of the inclined side surface.

2. the gate structure includes a first conductive layer and a second conductive layer; the first conductive layer is disposed on the gate oxide layer, the second conductive layer is disposed on the first conductive layer, the second conductive layer includes a plurality of stacked metal layers, at least one of the plurality of metal layers has an inclined side surface facing the conductive plug; The semiconductor structure of claim 1 .

3. the first conductive layer includes a polysilicon layer, the second conductive layer includes a titanium nitride layer and a tungsten layer stacked from bottom to top, the tungsten layer having an inclined side surface facing the conductive plug; The semiconductor structure of claim 2 .

4. the gate structure includes a first dielectric layer and a third conductive layer; the first dielectric layer is disposed on the gate oxide layer, the third conductive layer is disposed on the first dielectric layer, the third conductive layer is a metal layer, the metal layer has an inclined side surface facing the conductive plug; The semiconductor structure of claim 1 .

5. the first dielectric layer comprises a high dielectric constant material and the third conductive layer comprises a tungsten layer. The semiconductor structure of claim 4.

6. a first distance from an upper edge of the inclined side surface to the conductive plug is smaller than a second distance from a lower edge of the inclined side surface to the conductive plug; The semiconductor structure of claim 1 .

7. a first distance from an upper edge of the inclined side surface to the conductive plug is greater than a second distance from a lower edge of the inclined side surface to the conductive plug; The semiconductor structure of claim 1 .

8. The semiconductor structure further comprises: a second dielectric layer disposed over the substrate and the gate structure; a contact hole penetrating the second dielectric layer and contacting the corresponding source region and the drain region, the bottom of the contact hole being a shallow trench structure, the shallow trench structure being located in the corresponding source region and the drain region; the conductive plug includes a metal plug filled in the contact hole and a barrier layer located between the metal plug and an inner wall of the contact hole; A metal silicide is filled between the conductive plug and an inner wall of the shallow trench structure. The semiconductor structure of claim 1 .

9. the gate structure further includes a protective layer, the protective layer being disposed on the gate structure; The semiconductor structure of claim 1 .

10. the gate structure further includes lateral isolation structures attached to two sides of the gate structure facing the source region and the drain region; the lateral isolation structure includes a first isolation sidewall and a second isolation sidewall; the first isolation sidewall is attached to a side of the gate structure, the second isolation sidewall is located at a periphery of the first isolation sidewall, and a top of the second isolation sidewall extends to a top of the first isolation sidewall to form an enclosed space, and the enclosed space is filled with a separation medium; the material of the first isolation sidewall and the second isolation sidewall comprises silicon nitride, and the separation medium comprises silicon oxide or air; The semiconductor structure of claim 1 .

11. 1. A method for manufacturing a semiconductor structure, comprising the steps of: forming a gate oxide layer; forming a gate structure on the gate oxide layer; forming source and drain regions on opposite sides of the gate structure; forming conductive plugs in corresponding locations of the source region and the drain region; the gate structure includes a conductive layer having a sloped side surface, the sloped side surface facing the conductive plug; A method for manufacturing a semiconductor structure, wherein a surface at an intermediate position of the inclined side surface is stepped, and the intermediate position of the inclined side surface is located between an upper edge and a lower edge of the inclined side surface.

12. forming a gate structure on the gate oxide layer forming a first conductive layer over the gate oxide layer; forming a second conductive layer on the first conductive layer, the second conductive layer including a plurality of stacked metal layers; repeatedly performing the following steps until the first conductive layer is exposed, the steps including, if the layer now exposed in the first region is a predetermined metal layer, etching the predetermined metal layer in the first region while adjusting an etching direction and rate so that the predetermined metal layer has sloped sides facing the source and drain regions until a next metal layer is exposed, and if the layer now exposed in the first region is not a predetermined metal layer, etching downwardly the exposed layer in the first region in areas not covered by the exposed layer or an overlying layer until a next metal layer is exposed, the first region being an area other than the area between the source and drain regions; and etching the first conductive layer downward in the first region or in regions not covered by an overlying layer until the gate oxide layer is exposed to form the gate structure. The method of claim 11 .

13. forming a gate structure on the gate oxide layer forming a first dielectric layer over the gate oxide layer; forming a third conductive layer on the first dielectric layer, the third conductive layer being a metal layer; adjusting an etching direction and rate while etching the third conductive layer in a first region until the first dielectric layer is exposed, the third conductive layer having sloped sides facing the source and drain regions, the first region being a region other than a region between the source and drain regions; and etching downwardly the first dielectric layer not covered by the first dielectric layer or the third conductive layer in the first region until the gate oxide layer is exposed to form the gate structure. The method of claim 11 .

14. forming conductive plugs at corresponding locations of the source region and the drain region; forming a second dielectric layer over the substrate and the gate structure; forming a patterned etching protection layer on the second dielectric layer, the etching protection layer covering a surface of the dielectric layer except for partial regions corresponding to the source region and the drain region; etching downward from the exposed surface of the second dielectric layer until the surfaces of the source and drain regions are exposed, and over-etching the surfaces of the source and drain regions to form contact holes with shallow trench structures at the bottom, the shallow trench structures being located in the corresponding source and drain regions; forming a barrier layer on an inner wall of the contact hole, and filling the contact hole covered with the barrier layer with a metal to form the conductive plug; Before forming a barrier layer on the inner wall of the contact hole, the method for manufacturing the semiconductor structure includes: forming a metal silicide on an inner wall of the shallow trench structure at the bottom of the contact hole; The method of claim 11 .

15. forming a gate structure on the gate oxide layer forming a gate structure on the gate oxide layer, the top layer of the gate structure being a protective layer; After forming a gate structure on the gate oxide layer, the method of manufacturing the semiconductor structure includes: forming lateral isolation structures on two sides of the gate structure facing the source region and the drain region; forming lateral isolation structures on two sides of the gate structure facing the source region and the drain region; forming a first isolation sidewall on a side of the gate structure facing the source region and the drain region; covering an outer wall of the first separating side wall with a separating medium; forming a second separating sidewall on an outer wall of the separation medium, the top of the second separating sidewall extending to the top of the first separating sidewall to form an enclosed space surrounding the separation medium; or forming lateral isolation structures on two sides of the gate structure facing the source region and the drain region; forming a third isolation sidewall on a side of the gate structure facing the source region and the drain region; covering an outer wall of the third isolation sidewall with a third dielectric layer; forming a fourth isolation sidewall on an outer wall of the third dielectric layer, the top of the fourth isolation sidewall extending to the top of the third isolation sidewall to form a sealed space surrounding the third dielectric layer; Etching a top of the fourth isolation sidewall until a surface of the third dielectric layer is exposed to form an etching hole; Etching the third dielectric layer through the etching holes until a surface of the gate oxide layer is reached; and sealing the etching hole between the top of the fourth isolation sidewall and the top of the third isolation sidewall by a rapid deposition process to form a sealed space filled with air. The method of claim 11 .

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