Semiconductor device, manufacturing method thereof, and electronic device

Abstract

To realize a high-withstanding voltage and high-power semiconductor device including nitride semiconductor.SOLUTION: A semiconductor device 1 includes: a barrier layer 20 with recessed parts 21 and 22 and a convex part 23 therebetween; a channel layer 30 burying the recessed and convex parts; and a barrier layer 40 on the channel layer 30. The channel layer 30 includes nitride semiconductor having a bandgap smaller than that of nitride semiconductor of the barrier layers 20 and 40. A source electrode 60 and a drain electrode 70 are provided on the channel layer 30, being respectively opposed to portions 21bb and 22bb separated from the convex part 23 of the recessed parts 21 and 22 in a first direction vertical to the channel layer 30. A gate electrode 50 is provided on the barrier layer 40, being separated from the source electrode 60 and the drain electrode 70 and opposed to the convex part 23 in the first direction. A region below the gate electrode 50 is formed to have a local quantum well (QW) structure to achieve a high withstanding voltage and suppress influences of output reduction caused by the QW structure.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present invention relates to a semiconductor device, a method for manufacturing a semiconductor device, and an electronic device. [Background technology]

[0002] Semiconductor devices using nitride semiconductors are known, such as high electron mobility transistors (HEMTs) that use a nitride semiconductor such as GaN (gallium nitride) for a channel layer (also referred to as an electron carrier transport layer) and a nitride semiconductor such as AlGaN (aluminum gallium nitride) that has a larger band gap than the nitride semiconductor of the channel layer for a barrier layer (also referred to as a barrier layer).

[0003] Known examples include HEMTs with an AlGaN / GaN heterostructure in which an AlGaN barrier layer is stacked on a GaN channel layer, and HEMTs with an AlGaN / GaN / AlGaN double heterostructure in which a GaN channel layer is sandwiched between two AlGaN barrier layers.

[0004] In addition, a technique is known for HEMTs in which an insulating mask pattern such as a silicon oxide film is provided on a part of an AlN (aluminum nitride) buffer layer, a GaN electron carrier transport layer is provided to cover the mask pattern, and an AlGaN barrier layer is provided on the GaN electron carrier transport layer. Furthermore, a technique is known in which a gate electrode is provided on the barrier layer outside the region directly above the insulating mask pattern.

[0005] Also, a heterostructure field effect transistor is known that includes a semiconductor wire having a source region, a drain region, and a channel region therebetween in the longitudinal direction. In this regard, a technique is known in which the source region, the drain region, and the channel region are each structured to have a core region and a shell region therearound, and the thickness of the shell region in the channel region is made smaller than the thickness of the shell region in the source region and the drain region. Furthermore, a technique is known in which a gate structure having a gate dielectric layer and a gate layer is provided around such a channel region. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Publication No. 11-274474 [Patent Document 2] JP 2008-159842 A [Patent Document 3] JP 2014-132643 A Summary of the Invention [Problem to be solved by the invention]

[0007] In a semiconductor device that uses a nitride semiconductor such as GaN for the channel layer and a nitride semiconductor such as AlGaN for the barrier layer, which has a larger band gap than the nitride semiconductor of the channel layer, a certain level of breakdown voltage and output can be obtained. One known technique for further increasing the breakdown voltage of a semiconductor device is to employ a quantum well (QW) structure (also called a "quantum confinement structure") in which a channel layer of a nitride semiconductor such as GaN is sandwiched between barrier layers of a nitride semiconductor such as AlN, which has a larger band gap than the nitride semiconductor of the channel layer.

[0008] However, in conventional QW structures, a strong electric field is applied to the channel layer, which can reduce the concentration of two-dimensional electron gas (2DEG) generated near the interface between the channel layer and the barrier layer, resulting in a decrease in output power. Also, in a QW structure in which the channel layer sandwiched between the barrier layers is thin overall, the resistance of the channel layer increases, which can reduce the current flowing through the channel layer and result in a decrease in output power.

[0009] Thus, in conventional semiconductor devices using nitride semiconductors, it has sometimes been impossible to obtain both a sufficiently high breakdown voltage and a sufficiently high output. In one aspect, the present invention aims to realize a semiconductor device using a nitride semiconductor, which has high breakdown voltage and high output. [Means for solving the problem]

[0010] In one embodiment, the present invention comprises a first barrier layer including a first nitride semiconductor and having a first recess and a second recess and a protrusion between the first recess and the second recess; a channel layer including a second nitride semiconductor having a smaller band gap than the first nitride semiconductor and filling the first recess and the second recess and the protrusion of the first barrier layer; and a first surface side of the channel layer opposite to the first barrier layer side, a first barrier layer that faces the first recess, the second recess, and the protrusion in a first direction perpendicular to the first surface; a second barrier layer including a third nitride semiconductor having a band gap larger than that of the second nitride semiconductor; and a front barrier layer provided on the first surface side of the channel layer. Record number The present invention provides a semiconductor device including: a source electrode that faces, in one direction, a first portion of the first recess of the first barrier layer, spaced from the convex portion; a drain electrode provided on the first surface side of the channel layer, and that faces, in the first direction, a second portion of the second recess of the first barrier layer, spaced from the convex portion; and a gate electrode that is provided on a second surface side of the second barrier layer opposite the channel layer side, spaced from the source electrode and the drain electrode, and that faces the convex portion of the first barrier layer in the first direction.

[0011] In another aspect, there is provided a method for manufacturing the semiconductor device as described above, and an electronic device including the semiconductor device as described above. Effect of the Invention

[0012] In one aspect, it is possible to realize a semiconductor device using a nitride semiconductor that has high breakdown voltage and high output. [Brief description of the drawings]

[0013] [Figure 1] 1A and 1B are diagrams illustrating an example of a semiconductor device. [Diagram 2] 1 is a diagram showing an example of an energy band structure of a semiconductor device; [Diagram 3] 11A and 11B are diagrams showing examples of evaluation results of breakdown voltage characteristics of a semiconductor device. [Figure 4] FIG. 1 is a diagram illustrating an example of a semiconductor device according to a first embodiment. [Diagram 5] 11A and 11B are diagrams illustrating an example of a current value evaluation result of a semiconductor device. [Figure 6] FIG. 1 is a diagram (part 1) illustrating a modified example of the semiconductor device according to the first embodiment. [Figure 7] FIG. 2 is a diagram (part 2) illustrating a modified example of the semiconductor device according to the first embodiment. [Figure 8] FIG. 11 is a diagram illustrating an example of a semiconductor device according to a second embodiment. [Figure 9] 13A to 13C are views (part 1) for explaining a first example of a method for forming a semiconductor device according to a third embodiment; [Figure 10] 13A to 13C are diagrams (part 2) illustrating a first example of a method for forming a semiconductor device according to a third embodiment. [Figure 11] 13A to 13C are views (part 1) illustrating a second example of the method for forming a semiconductor device according to the third embodiment. [Figure 12] 13A to 13C are diagrams (part 2) illustrating a second example of the method for forming a semiconductor device according to the third embodiment. [Figure 13]13A to 13C are diagrams illustrating an example of a semiconductor package according to a fourth embodiment. [Figure 14] FIG. 13 is a diagram illustrating an example of a power factor correction circuit according to a fifth embodiment. [Figure 15] FIG. 13 is a diagram illustrating an example of a power supply device according to a sixth embodiment. [Figure 16] FIG. 13 is a diagram illustrating an example of an amplifier according to a seventh embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] Semiconductor devices using nitride semiconductors are being developed as high-voltage, high-power devices by utilizing characteristics such as high saturation electron velocity and wide band gap. For example, GaN, which is a nitride semiconductor, has a band gap of 3.4 eV, which is larger than the band gap of Si (silicon) of 1.1 eV and the band gap of GaAs (gallium arsenide) of 1.4 eV, and has a high dielectric breakdown field. Therefore, nitride semiconductors such as GaN are promising materials for semiconductor devices that operate at high voltages and have high power, such as semiconductor devices applied to power supplies, communication devices, radar devices, etc.

[0015] As a semiconductor device using a nitride semiconductor, there have been many reports on field effect transistors (FETs), for example, HEMTs. One type of HEMT is known to use GaN as a channel layer and AlGaN as a barrier layer. In such HEMTs, a high concentration of 2DEG is generated in GaN due to spontaneous polarization of AlGaN and piezoelectric polarization generated in AlGaN due to strain caused by the lattice constant difference with GaN, thereby realizing high output. In addition, in order to further increase the withstand voltage of semiconductor devices using nitride semiconductors, a semiconductor device having an AlN / GaN / AlN QW structure has also been proposed, which strengthens carrier confinement by a large band offset between AlN and GaN.

[0016] Fig. 1 is a diagram for explaining examples of semiconductor devices. Fig. 1(A) shows a schematic cross-sectional view of a main part of a first example of a semiconductor device. Fig. 1(B) shows a schematic cross-sectional view of a main part of a second example of a semiconductor device.

[0017] 1A is an example of a HEMT. The semiconductor device 100A includes a substrate 110, a buffer layer 120A, a channel layer 130A, a barrier layer 140A, a gate electrode 150, a source electrode 160, and a drain electrode 170.

[0018] The substrate 110 may be made of various materials such as AlN, Si, sapphire, SiC (silicon carbide), or GaN. The buffer layer 120A is provided on the substrate 110 with a relatively thin thickness. The buffer layer 120A is made of a nitride semiconductor such as AlN. The channel layer 130A is provided on the buffer layer 120A with a relatively thick thickness. The channel layer 130A is made of a nitride semiconductor such as GaN. The barrier layer 140A is provided on the channel layer 130A. The barrier layer 140A is made of a nitride semiconductor having a larger band gap than the nitride semiconductor of the channel layer 130A. When the channel layer 130A is made of GaN, the barrier layer 140A is made of a nitride semiconductor such as AlN or AlGaN. The channel layer 130A is also called an electron transit layer, and the barrier layer 140A is also called an electron supply layer.

[0019] In the semiconductor device 100A, the buffer layer 120A is a layer stacked on the substrate 110 so that its thickness direction is the

[0001] direction, and the surface on the side on which the channel layer 130A is stacked is the (0001) surface, i.e., a group III polar surface. The channel layer 130A is a layer stacked on the buffer layer 120A so that its thickness direction is the

[0001] direction, and the surface on the side on which the barrier layer 140A is stacked is the (0001) surface, i.e., a group III polar surface. The barrier layer 140A is a layer stacked on the channel layer 130A so that its thickness direction is the

[0001] direction, and the surface on the opposite side to the channel layer 130A side is the (0001) surface, i.e., a group III polar surface.

[0020] The gate electrode 150, the source electrode 160, and the drain electrode 170 each include a predetermined metal. The gate electrode 150 is provided to function as a Schottky electrode. The gate electrode 150 is provided, for example, on the barrier layer 140A. The source electrode 160 and the drain electrode 170 are provided to function as ohmic electrodes. The source electrode 160 and the drain electrode 170 are connected to the channel layer 130A, for example, by penetrating the barrier layer 140A.

[0021] The substrate 110, buffer layer 120A, channel layer 130A, barrier layer 140A, gate electrode 150, source electrode 160 and drain electrode 170 as described above are provided in an active region of the semiconductor device 100A defined by an inter-element isolation region (not shown).

[0022] The semiconductor device 100A has a heterojunction structure of the channel layer 130A and the barrier layer 140A in a wide area of ​​the active region (the region where the 2DEG is generated). For convenience, such a semiconductor device 100A is also referred to as a normal semiconductor device 100A. In the semiconductor device 100A, the spontaneous polarization of the barrier layer 140A and the piezoelectric polarization generated in the barrier layer 140A due to the strain caused by the lattice constant difference with the channel layer 130A generate the 2DEG 101A near the junction interface between the channel layer 130A and the barrier layer 140A. When the semiconductor device 100A is in operation, a predetermined voltage is supplied between the source electrode 160 and the drain electrode 170, and a predetermined gate voltage is supplied to the gate electrode 150. A channel through which carrier electrons are transported is formed in the channel layer 130A between the source electrode 160 and the drain electrode 170, and the transistor function of the semiconductor device 100A is realized.

[0023] 1B shows a semiconductor device 100B which is another example of a HEMT. The semiconductor device 100B includes a substrate 110, a barrier layer 120B, a channel layer 130B, a barrier layer 140B, a gate electrode 150, a source electrode 160, and a drain electrode 170.

[0024] The substrate 110 may be made of various materials such as AlN, Si, sapphire, SiC, or GaN. The barrier layer 120B is provided on the substrate 110 with a relatively large thickness. The barrier layer 120B may be made of a nitride semiconductor such as AlN or AlGaN. The channel layer 130B is provided on the barrier layer 120B with a relatively small thickness. The channel layer 130B may be made of a nitride semiconductor having a smaller band gap than the nitride semiconductor of the barrier layer 120B. When the barrier layer 120B is made of AlN or AlGaN, the channel layer 130B may be made of a nitride semiconductor such as GaN. The barrier layer 140B is provided on the channel layer 130B. The barrier layer 140B may be made of a nitride semiconductor having a larger band gap than the nitride semiconductor of the channel layer 130B. When the channel layer 130B is made of GaN, the barrier layer 140B may be made of a nitride semiconductor such as AlN or AlGaN. The barrier layer 120B is also referred to as a back barrier layer, the channel layer 130B is also referred to as an electron transport layer, and the barrier layer 140B is also referred to as an electron supply layer.

[0025] In the semiconductor device 100B, the barrier layer 120B is a layer stacked on the substrate 110 so that its thickness direction is the

[0001] direction, and the surface on the side on which the channel layer 130B is stacked is the (0001) surface, i.e., a group III polar surface. The channel layer 130B is a layer stacked on the barrier layer 120B so that its thickness direction is the

[0001] direction, and the surface on the side on which the barrier layer 140B is stacked is the (0001) surface, i.e., a group III polar surface. The barrier layer 140B is a layer stacked on the channel layer 130B so that its thickness direction is the

[0001] direction, and the surface on the opposite side to the channel layer 130B side is the (0001) surface, i.e., a group III polar surface.

[0026] The gate electrode 150, the source electrode 160, and the drain electrode 170 each include a predetermined metal. The gate electrode 150 is provided to function as a Schottky electrode. The gate electrode 150 is provided, for example, on the barrier layer 140B. The source electrode 160 and the drain electrode 170 are provided to function as ohmic electrodes. The source electrode 160 and the drain electrode 170 are connected to the channel layer 130B, for example, through the barrier layer 140B.

[0027] The above-described substrate 110, barrier layer 120B, channel layer 130B, barrier layer 140B, gate electrode 150, source electrode 160 and drain electrode 170 are provided in an active region of the semiconductor device 100B defined by an inter-element isolation region (not shown).

[0028] The semiconductor device 100B has a QW structure in which the channel layer 130B is sandwiched between the barrier layer 120B and the barrier layer 140B in a wide range of the active region (region where 2DEG is generated). In the semiconductor device 100B, 2DEG 101B is generated near the junction interface between the channel layer 130B and the barrier layer 140B due to spontaneous polarization of the barrier layer 140B and piezoelectric polarization generated in the barrier layer 140B due to strain caused by the lattice constant difference between the barrier layer 140B and the channel layer 130B. When the semiconductor device 100B is in operation, a predetermined voltage is supplied between the source electrode 160 and the drain electrode 170, and a predetermined gate voltage is supplied to the gate electrode 150. A channel through which carrier electrons are transported is formed in the channel layer 130B between the source electrode 160 and the drain electrode 170, and the transistor function of the semiconductor device 100B is realized.

[0029] In the semiconductor device 100B, due to the relatively large band offset between the channel layer 130B and the barrier layers 120B and 140B, the confinement of electrons is enhanced, the diffusion of electrons into the inner part of the device is restricted, and the generation of leakage current via the inner part of the device is suppressed. In the semiconductor device 100B, high breakdown voltage is achieved by the strong confinement of electrons due to its QW structure. Also, in the semiconductor device 100B, the channel layer 130B made of GaN (<2 W / m·K) with a relatively low thermal conductivity is made thinner compared to the barrier layers 120B and 140B made of AlN (>300 W / m·K) with a relatively high thermal conductivity. Therefore, it is expected that the internal heat transfer efficiency and heat dissipation efficiency of the semiconductor device 100B are enhanced, and the deterioration of characteristics due to self-heating is suppressed.

[0030] Here, the energy band structures of a normal semiconductor device 100A without the QW structure and a semiconductor device 100B with the QW structure will be described with reference to FIG. 2. FIG. 2 is a diagram showing an example of the energy band structure of a semiconductor device.

[0031] In FIG. 2, an example of the energy band structure of the normal semiconductor device 100A as shown in FIG. 1(A) above (the “HEMT” in FIG. 2) is shown by a dotted line. Here, a semiconductor device 100A (HEMT) using GaN for the channel layer 130A and AlGaN (0 < x ≦ 1) for the barrier layer 140A is taken as an example. Further, in FIG. 2, an example of the energy band structure of the semiconductor device 100B having the QW structure as shown in FIG. 1(B) above (the “HEMT” in FIG. 2) is shown by a solid line. Here, a semiconductor device 100B (HEMT) using AlGaN (0 < y ≦ 1) for the barrier layer 120B, GaN for the channel layer 130B, and AlGaN (0 < x ≦ 1) for the barrier layer 140B is taken as an example. A ”) is shown by a dotted line. Here, GaN is used for the channel layer 130A and Al x Ga 1-x N (0 < x ≦ 1) is used for the semiconductor device 100A (HEMT A ) as an example. In FIG. 2, further, an example of the energy band structure of the semiconductor device 100B having the QW structure as shown in FIG. 1(B) above (the “HEMT” in FIG. 2) is shown by a solid line. Here, Al B ”) is shown by a solid line. Here, AlGaN (0 < y ≦ 1) is used for the barrier layer 120B, GaN is used for the channel layer 130B, and AlGaN (0 < x ≦ 1) is used for the barrier layer 140B for the semiconductor device 100B (HEMT B ”) is shown by a solid line. Here, AlGaN (0 < y ≦ 1) is used for the barrier layer 120B, GaN is used for the channel layer 130B, and AlGaN (0 < x ≦ 1) is used for the barrier layer 140B for the semiconductor device 100B (HEMT y Ga 1-y N (0 < y ≦ 1) is used for the barrier layer 120B, GaN is used for the channel layer 130B, and Al x Ga 1-x N (0 < x ≦ 1) is used for the semiconductor device 100B (HEMT B) is taken as an example. In Fig. 2, Ec represents the conduction band and Ef represents the Fermi level.

[0032] In a normal semiconductor device 100A (HEMT A ), on a relatively thick GaN channel layer 130A, Al with a larger bandgap than GaN x Ga 1-x N (0 < x ≤ 1) barrier layer 140A is laminated. On the other hand, in a semiconductor device 100B (HEMT B ) having a QW structure, a relatively thin GaN channel layer 130B is sandwiched between a barrier layer 120B of Al y Ga 1-y N (0 < y ≤ 1) and a barrier layer 140B of Al x Ga 1-x N (0 < x ≤ 1).

[0033] In a semiconductor device 100B (HEMT B ) having a QW structure, as shown in Fig. 2, compared with a normal semiconductor device 100A (HEMT A ), the conduction band Ec of the channel layer 130B is lifted by the barrier layer 120B. As a result, in a semiconductor device 100B (HEMT B ), the 2DEG 101B generated by the conduction band Ec falling below the Fermi level Ef is less than the 2DEG 101A generated in a normal semiconductor device 100A (HEMT A ), and the current value decreases. Furthermore, in a semiconductor device 100B (HEMT B ), the depth at which the 2DEG 101B is generated (current path CP B ) is shallower than the depth at which the 2DEG 101A of a normal semiconductor device 100A (HEMT A ) is generated (current path CP A ).

[0034] In the semiconductor device 100B having the QW structure, the current value is lower under the same operating conditions as the normal semiconductor device 100A, or a higher current density is required to obtain the same current value as the normal semiconductor device 100A. On the other hand, however, the semiconductor device 100B realizes a high breakdown voltage due to the strong confinement of electrons by the QW structure.

[0035] FIG. 3 is a diagram showing an example of the results of evaluation of the breakdown voltage characteristics of a semiconductor device. FIG. 3 shows an example of the relationship between the drain voltage [V] and the drain current density [A / mm] of the conventional semiconductor device 100A shown in FIG. 1(A) (the “HEMT” in FIG. 3). A 3 further shows an example of the relationship between the drain voltage [V] and the drain current density [A / mm] of the semiconductor device 100B having the QW structure shown in FIG. 1(B) ("HEMT" in FIG. 3). B " ) is shown by a solid line.

[0036] As shown in FIG. 3, a semiconductor device 100B (HEMT B ) in the conventional semiconductor device 100A (HEMT A ), the breakdown voltage is improved by nearly three times. It can be said that the QW structure is effective in increasing the breakdown voltage.

[0037] As described above, in the semiconductor device 100B having the QW structure, the 2DEG concentration is lower and the current path is shallower than in the normal semiconductor device 100A. Therefore, in the semiconductor device 100B having the QW structure, the resistance of the channel layer 130B is relatively high, the current value is lowered, and the output is reduced. On the other hand, in the semiconductor device 100B having the QW structure, the 2DEG concentration is lowered, the current path is shallower, and the occurrence of leakage current is suppressed by the quantum confinement effect, thereby realizing a high breakdown voltage. Thus, in the semiconductor device 100B having the QW structure, it is possible to realize a high breakdown voltage compared to the normal semiconductor device 100A, but there is a problem that the current value is lowered and the output is reduced.

[0038] In view of the above, a configuration as shown in the following embodiment is adopted to realize a semiconductor device using a nitride semiconductor and having high breakdown voltage and high output. [First embodiment] Fig. 4 is a diagram for explaining an example of the semiconductor device according to the first embodiment. Fig. 4 is a schematic cross-sectional view of a main part of the example of the semiconductor device according to the first embodiment.

[0039] 4 is an example of a HEMT. The semiconductor device 1 includes a substrate 10, a barrier layer 20, a channel layer 30, a barrier layer 40, a gate electrode 50, a source electrode 60, and a drain electrode 70.

[0040] The substrate 10 may be made of any of various materials such as AlN, Si, sapphire, SiC, or GaN. The substrate 10 may be made of any of various materials as a base substrate, on which a layer of a nitride semiconductor such as AlN, AlGaN, or InAlGaN (indium aluminum gallium nitride) is provided.

[0041] The barrier layer 20 is provided on the substrate 10. The barrier layer 20 is made of a nitride semiconductor such as AlN, AlGaN, or InAlGaN. The barrier layer 20 is also called a back barrier layer. The barrier layer 20 may be made of one type of nitride semiconductor or two or more types of nitride semiconductors. The barrier layer 20 may have a single-layer structure of one type of nitride semiconductor or a stacked structure of two or more types of nitride semiconductors.

[0042] The barrier layer 20 is provided with a recess 21, a recess 22, and a protrusion 23 between them. For example, the recess 21 and the recess 22 are groups of trenches extending parallel to each other in the front or back direction of the paper, and the protrusion 23 is a mesa between the groups of trenches extending in the front or back direction of the paper. The recess 21 has a bottom surface 21a and a side surface 21b rising therefrom, and the recess 22 has a bottom surface 22a and a side surface 22b rising therefrom. The protrusion 23 has a surface (upper surface) 23a connecting an edge 21ba in the rising direction of the side surface 21b of the recess 21 and an edge 22ba in the rising direction of the side surface 22b of the recess 22.

[0043] The barrier layer 20 is laminated on the substrate 10 so that the thickness direction thereof is the

[0001] direction, for example. For example, the barrier layer 20 is laminated on the substrate 10 using a metal organic chemical vapor deposition (MOCVD) or metal organic vapor phase epitaxy (MOVPE) method or a molecular beam epitaxy (MBE) method, and then the recesses 21 and 22 are formed by etching, thereby forming the protrusions 23. The barrier layer 20 has a (0001) plane, i.e., a group III polar plane, on the bottom surface 21a of the recess 21 and the bottom surface 22a of the recess 22 and the top surface 23a of the protrusion 23. The direction perpendicular to the (0001) plane is the

[0001] direction.

[0044] The channel layer 30 is provided on the barrier layer 20. The channel layer 30 is made of a nitride semiconductor such as GaN, InGaN, or InN, which has a smaller band gap than the nitride semiconductor of the barrier layer 20. The channel layer 30 is also called an electron transit layer. The channel layer 30 may be made of one type of nitride semiconductor, or may be made of two or more types of nitride semiconductors. The channel layer 30 may have a single-layer structure of one type of nitride semiconductor, or may be made of a stacked structure of two or more types of nitride semiconductors.

[0045] The channel layer 30 is provided on the barrier layer 20 so as to fill the recesses 21, 22, and protrusions 23 of the barrier layer 20. The channel layer 30 is provided on the barrier layer 20 so that a surface 30a on the opposite side to the barrier layer 20 side is located above (toward the barrier layer 40 side) an upper surface 23a of the protrusions 23 of the barrier layer 20, and fills the recesses 21, 22, and protrusions 23. The recesses 21, 22, and protrusions 23 of the barrier layer 20 are not exposed from the channel layer 30. It can be said that the channel layer 30 has a recess corresponding to the protrusions 23 of the barrier layer 20, and also has a protrusion corresponding to the recess 21 of the barrier layer 20 and a protrusion corresponding to the recess 22 of the barrier layer 20.

[0046] The channel layer 30 is laminated on the barrier layer 20 so that the thickness direction thereof is the

[0001] direction. For example, the channel layer 30 is obtained by laminating the channel layer 30 on the barrier layer 20 so as to fill the recesses 21, 22 and protrusions 23 using a MOVPE method or the like. The channel layer 30 has a (0001) plane, i.e., a group III polar plane, on a surface 30a opposite to the barrier layer 20 side. The direction perpendicular to the (0001) plane is the

[0001] direction.

[0047] The barrier layer 40 is provided on the channel layer 30. The barrier layer 40 is made of a nitride semiconductor such as AlN, AlGaN, or InAlGaN having a band gap larger than that of the nitride semiconductor of the channel layer 30. The barrier layer 40 is also called an electron supply layer. The barrier layer 40 may be made of one type of nitride semiconductor or two or more types of nitride semiconductors. The barrier layer 40 may have a single-layer structure of one type of nitride semiconductor or a laminate structure of two or more types of nitride semiconductors. The barrier layer 40 may be made of the same type of nitride semiconductor as the barrier layer 20 facing the channel layer 30, or may be made of a different type of nitride semiconductor. That is, the barrier layer 40 and the barrier layer 20 may be made of nitride semiconductors having different constituent element groups or composition ratios from each other, or may be made of nitride semiconductors having the same constituent element groups and composition ratios from each other.

[0048] The barrier layer 40 is laminated on the channel layer 30 so that, for example, its thickness direction is the

[0001] direction. For example, the barrier layer 40 is obtained by being laminated on the face 30a of the channel layer 30 using a MOVPE method or the like. The barrier layer 40 has a (0001) face, i.e., a group III polar face, on the face 40a opposite to the channel layer 30 side. The direction perpendicular to the (0001) face is the

[0001] direction.

[0049] The semiconductor device 1 has a QW structure utilizing a group III polarity plane. In the semiconductor device 1, a 2DEG 101 is generated on the group III polarity plane side of the channel layer 30 near the junction interface with the barrier layer 40 due to spontaneous polarization of the barrier layer 40 and piezoelectric polarization caused by strain due to the difference in lattice constant between the barrier layer 40 and the channel layer 30.

[0050] The gate electrode 50 is provided on the opposite side of the barrier layer 40 from the channel layer 30 side. The gate electrode 50 is provided, for example, on the surface 40a of the barrier layer 40. The gate electrode 50 can be made of a metal. For example, the gate electrode 50 is a metal electrode having Ni (nickel) and Au (gold) provided thereon. The gate electrode 50 is formed by using a deposition method or the like. The gate electrode 50 functions, for example, as a Schottky electrode. A gate insulating film (not shown) using an oxide, a nitride, an oxynitride, or the like may be interposed between the gate electrode 50 and the barrier layer 40. In addition, a cap layer (not shown) using a nitride semiconductor may be interposed between the gate electrode 50 and the barrier layer 40.

[0051] The source electrode 60 and the drain electrode 70 are provided on both sides of the gate electrode 50 and spaced apart from the gate electrode 50. The source electrode 60 and the drain electrode 70 may be made of a metal. For example, the source electrode 60 and the drain electrode 70 may be metal electrodes having Ta (tantalum) and Al (aluminum) provided thereon. The source electrode 60 and the drain electrode 70 are formed by using a deposition method or the like. The source electrode 60 and the drain electrode 70 function as ohmic electrodes. The source electrode 60 and the drain electrode 70 may be connected to the channel layer 30 through the barrier layer 40. The source electrode 60 and the drain electrode 70 may be provided on a contact layer (not shown) provided to reach the channel layer 30 through the barrier layer 40, and connected to the channel layer 30 through the contact layer.

[0052] In the semiconductor device 1, the gate electrode 50 is provided at a position corresponding to the protrusion 23 of the barrier layer 20, i.e., at a position facing the protrusion 23 of the barrier layer 20 in the

[0001] direction. Here, the gate electrode 50 is provided at a position such that an edge 51 on the source electrode 60 side and an edge 52 on the drain electrode 70 side face, in the

[0001] direction, an upper surface 23a of the protrusion 23 of the barrier layer 20 from the edge 21ba on the recess 21 side to the edge 22ba on the recess 22 side. The upper surface 23a of the protrusion 23 also includes the edge 21ba on the recess 21 side and the edge 22ba on the recess 22 side.

[0053] In the semiconductor device 1, the source electrode 60 and the drain electrode 70 are provided at positions corresponding to the recesses 21 and 22 that sandwich the protrusion 23 of the barrier layer 20, i.e., at positions facing the recesses 21 and 22 of the barrier layer 20 in the

[0001] direction. Here, the source electrode 60 and the drain electrode 70 are provided at positions facing the portions 21bb and 22bb of the recesses 21 and 22 of the barrier layer 20 that are spaced apart from the protrusion 23 (or the side surface 21b of the recess 21 and the side surface 22b of the recess 22) in the

[0001] direction.

[0054] In an active region of the semiconductor device 1 defined by an element isolation region (not shown), the above-mentioned substrate 10, barrier layer 20, channel layer 30, barrier layer 40, gate electrode 50, source electrode 60 and drain electrode 70 are provided.

[0055] When the semiconductor device 1 is in operation, a predetermined voltage is supplied between the source electrode 60 and the drain electrode 70, and a predetermined gate voltage is supplied to the gate electrode 50. A channel through which carrier electrons are transported is formed in the channel layer 30 between the source electrode 60 and the drain electrode 70, and the transistor function of the semiconductor device 1 is realized.

[0056] In the semiconductor device 1, a gate electrode 50 is provided at a position facing the protrusion 23 provided in the barrier layer 20, via a part of the channel layer 30 and a part of the barrier layer 40. A source electrode 60 and a drain electrode 70 are provided at positions facing the recesses 21 and 22 provided in the barrier layer 20, via other parts of the channel layer 30, respectively. That is, the semiconductor device 1 has a configuration in which a QW structure of the protrusion 23 of the barrier layer 20, the channel layer 30, and the barrier layer 40 is adopted in a region below the gate electrode 50. The semiconductor device 1 has a configuration in which a QW structure is not adopted in the regions of the recesses 21 and 22 of the barrier layer 20 where the source electrode 60 and the drain electrode 70 are respectively provided.

[0057] Here, when a QW structure is adopted over a wide area of ​​the HEMT active region (the region where 2DEG is generated) as in the semiconductor device 100B of FIG. 1(B) above, the breakdown voltage is increased compared to the conventional semiconductor device 100A of FIG. 1(A) above which does not adopt a QW structure, but the current value decreases, and the output may decrease.

[0058] In general, when a high voltage is applied to a HEMT, an electric field tends to concentrate near the edge of the gate electrode on the drain electrode side, or near the edge of the gate field plate on the drain electrode side, which is provided as part of the gate electrode to reduce the electric field. Similarly, the current flowing through the HEMT tends to concentrate near the edge of the gate electrode (or the gate field plate provided as part of the gate electrode) on the drain electrode side. Such concentration of electric field and current near the edge of the gate electrode on the drain electrode side is one of the causes of degradation of characteristics due to insulation breakdown and overheating of the HEMT.

[0059] Therefore, in the semiconductor device 1 according to the first embodiment, a QW structure is locally adopted in the region below the gate electrode 50, and the QW structure is not adopted in the regions extending from that region to the source electrode 60 side and the drain electrode 70 side.

[0060] By adopting the QW structure locally in the region below the gate electrode 50, the advantage of high breakdown voltage due to the QW structure is enjoyed in the region below the gate electrode 50 where the electric field is likely to concentrate and insulation breakdown is likely to occur, and in the vicinity of the edge 52 of the gate electrode 50 on the drain electrode 70 side. That is, in the region below the gate electrode 50 where the electric field is likely to concentrate, the 2DEG concentration is reduced, the current path is shallowed, and the occurrence of leakage current is suppressed by the quantum confinement effect, thereby realizing a high breakdown voltage of the semiconductor device 1. Furthermore, in the semiconductor device 1 where the QW structure is locally adopted in the region below the gate electrode 50, characteristic deterioration due to self-heating is suppressed. That is, in the semiconductor device 1, in the region below the gate electrode 50 where the current is likely to concentrate and heat generation is likely to increase, the thickness of the channel layer 30 using GaN or the like having a relatively low thermal conductivity is thinner than the barrier layer 20 and the barrier layer 40 using AlN or the like having a relatively high thermal conductivity. This prevents the internal heat transfer efficiency and heat dissipation efficiency of the semiconductor device 1 from decreasing, and prevents the characteristics from deteriorating due to self-heating.

[0061] If the QW structure is adopted not only in the region below the gate electrode 50 but also in the region from the region to the source electrode 60 side and the drain electrode 70 side, the 2DEG concentration will be reduced and the current path will be shallow over a wide range of the active region (the region where the 2DEG is generated). In that case, the channel resistance will be high, the current value will be reduced, and the output will be reduced. In contrast, in the semiconductor device 1, the QW structure is not adopted outside the region below the gate electrode 50, that is, in the region from the region to the source electrode 60 side and the drain electrode 70 side. Therefore, in the semiconductor device 1, the 2DEG concentration is prevented from being reduced and the current path is prevented from being shallow over a wide range of the active region. As a result, the increase in resistance and the decrease in current value of the channel layer 30 are suppressed, and the semiconductor device 1 can achieve high output.

[0062] In the semiconductor device 1, from the viewpoint of generating a quantum effect in the region below the gate electrode 50 in which the QW structure is adopted, and from the viewpoint of suppressing deterioration of characteristics due to self-heating, it is preferable to reduce the thickness of the channel layer 30 in the region below the gate electrode 50. The thickness of the channel layer 30 in the region below the gate electrode 50, i.e., the distance from the surface 30a of the channel layer 30 in that region to the upper surface 23a of the protrusion 23 of the barrier layer 20, is preferably 50 nm or less, and more preferably 20 nm or less.

[0063] The semiconductor device 1 has a configuration in which a QW structure is locally adopted in the region below the gate electrode 50, and a QW structure is not adopted in the regions from that region to the source electrode 60 side and the drain electrode 70 side, making it possible to realize high voltage resistance and high output.

[0064] FIG. 5 is a diagram showing an example of a current value evaluation result of a semiconductor device. FIG. 5 shows an example of the relationship between the gate voltage [V] and the drain current density [A / mm] of the semiconductor device 1 in which a QW structure is locally adopted in the region below the gate electrode 50 in the active region as shown in FIG. 4 (the “HEMT” in FIG. 5). C5 further shows an example of the relationship between gate voltage [V] and drain current density [A / mm] of a normal semiconductor device 100A not employing a QW structure as shown in FIG. 1(A) ("HEMT A 5 shows an example of the relationship between the gate voltage [V] and the drain current density [A / mm] of the semiconductor device 100B in which the QW structure is entirely adopted in the active region as shown in FIG. 1B ("HEMT B " ) is shown by a dotted line.

[0065] From the relationship between the gate voltage (horizontal axis) and the drain current density (right vertical axis) shown in FIG. 5, the drain leakage current, which is important for realizing a high breakdown voltage, is A ) is a semiconductor device 100B (HEMT) that employs a QW structure. B ) is reduced. In addition, the semiconductor device 1 (HEMT) in which the QW structure is locally adopted in the region below the gate electrode 50 C ), the drain leakage current is B ) is reduced to the same extent as

[0066] Furthermore, from the relationship between the gate voltage (horizontal axis) and the drain current density (left vertical axis) shown in FIG. 5, the drain current density when the gate is opened is larger than that of the semiconductor device 100A (HEMT A ) is a semiconductor device 100B (HEMT) that employs a QW structure. B ) is reduced. In addition, the semiconductor device 1 (HEMT) in which the QW structure is locally adopted in the region below the gate electrode 50 C ), the drain current density when the gate is opened is B ), an improvement of more than 20% has been observed.

[0067] As can be seen from FIG. 5, the semiconductor device 1 can obtain a high output while maintaining a high withstand voltage, as opposed to the semiconductor device 100B, which has a higher withstand voltage than the semiconductor device 100A but a lower current value.

[0068] As described above, a QW structure is locally adopted in the region below the gate electrode 50, and a QW structure is not adopted in the regions from that region toward the source electrode 60 and the drain electrode 70, thereby realizing a high-voltage and high-output semiconductor device 1 using a nitride semiconductor.

[0069] Next, modified examples will be described. 6 and 7 are diagrams for explaining modified examples of the semiconductor device according to the first embodiment. FIG. 6(A) shows a schematic cross-sectional view of a main part of a first modified example of the semiconductor device according to the first embodiment. FIG. 6(B) shows a schematic cross-sectional view of a main part of a second modified example of the semiconductor device according to the first embodiment. FIG. 7(A) shows a schematic cross-sectional view of a main part of a third modified example of the semiconductor device according to the first embodiment. FIG. 7(B) shows a schematic cross-sectional view of a main part of a fourth modified example of the semiconductor device according to the first embodiment.

[0070] The semiconductor device 1a shown in Fig. 6(A) has a configuration in which the edges 21ba and 22ba of the protrusion 23 of the barrier layer 20 are located directly below the edge 51 of the gate electrode 50 on the source electrode 60 side and the edge 52 on the drain electrode 70 side, respectively. For convenience, the positional relationship between the edges 51 and 52 of the gate electrode 50 and the edges 21ba and 22ba of the protrusion 23 is shown by dashed lines in Fig. 6(A). The semiconductor device 1a differs from the semiconductor device 1 (Fig. 4) in having such a configuration.

[0071] The semiconductor device 1a shown in FIG. 6A also employs a QW structure locally in the region below the gate electrode 50, thereby enjoying the advantage of high breakdown voltage due to the QW structure in the region below the gate electrode 50 where the electric field is likely to concentrate and dielectric breakdown is likely to occur. Furthermore, in the semiconductor device 1a, the QW structure region is localized, thereby suppressing the effects of a decrease in current value and a decrease in output due to the QW structure. In the semiconductor device 1a, the region occupied by the QW structure is reduced compared to the semiconductor device 1, so that the effects of a decrease in current value and a decrease in output due to the QW structure are further suppressed. This realizes a semiconductor device 1a with high breakdown voltage and high output.

[0072] 6(B) differs from the semiconductor device 1a (FIG. 6(A)) in that an edge 22ba of a protrusion 23 of a barrier layer 20 is located immediately below and outside an edge 52 of a gate electrode 50 on the drain electrode 70 side. For convenience, the positional relationship between the edges 51 and 52 of the gate electrode 50 and the edges 21ba and 22ba of the protrusion 23 is shown by dashed lines in FIG. 6(B).

[0073] The semiconductor device 1b shown in FIG. 6B also employs a QW structure locally in the region below the gate electrode 50, thereby enjoying the advantage of high breakdown voltage due to the QW structure in the region below the gate electrode 50 where the electric field is likely to concentrate and dielectric breakdown is likely to occur. In the semiconductor device 1b, the edge 22ba of the protruding portion 23 of the barrier layer 20 is located directly below the outer side of the edge 52 of the gate electrode 50 on the drain electrode 70 side, so that the QW structure is provided so as to cover a wider area of ​​the electric field region spreading near the edge 52. Furthermore, in the semiconductor device 1b, the region of the QW structure is localized, thereby suppressing the influence of the decrease in current value and the decrease in output due to the QW structure. In the semiconductor device 1b, the edge 51 of the gate electrode 50 on the source electrode 60 side is aligned with the edge 21ba of the protruding portion 23 of the barrier layer 20, and the region occupied by the QW structure is reduced compared to the semiconductor device 1, thereby further suppressing the influence of the decrease in current value and the decrease in output. This realizes a semiconductor device 1b with high breakdown voltage and high output.

[0074] The semiconductor device 1c shown in FIG. 7(A) is different from the semiconductor device 1 (FIG. 4) in that another layer (intervening layer) 80 is provided between the gate electrode 50 and the barrier layer 40. The intervening layer 80 provided between the gate electrode 50 and the barrier layer 40 can be, for example, a layer using an oxide, a nitride, an oxynitride, or the like. The intervening layer 80 using an oxide, a nitride, an oxynitride, or the like functions as a gate insulating film. This realizes the semiconductor device 1c having a MIS (Metal Insulator Semiconductor) type gate structure. In addition, the intervening layer 80 provided between the gate electrode 50 and the barrier layer 40 can also be, for example, a layer using a doped (p-type or n-type) or non-doped nitride semiconductor such as GaN. The intervening layer 80 using a nitride semiconductor such as GaN functions as a cap layer. This realizes a semiconductor device 1c in which the nitride semiconductor such as the barrier layer 40 is protected by the cap layer, or a semiconductor device 1c in which the concentration of the 2DEG 101 in the channel layer 30 can be modulated.

[0075] The intermediate layer 80 may have a single-layer structure or a laminated structure. For example, a laminated gate insulating film or a laminated cap layer may be provided as the intermediate layer 80. Alternatively, a cap layer using a nitride semiconductor may be provided on the barrier layer 40, a gate insulating film using an oxide or the like may be provided on the cap layer, and the gate electrode 50 may be provided on the gate insulating film. In other words, the intermediate layer 80 may have a laminated structure of a cap layer and a gate insulating film.

[0076] 7B is different from the semiconductor device 1 (FIG. 4) in that it has a configuration in which a protective film 90 is provided to cover the barrier layer 40, etc. (not shown here, but the intermediate layer 80 if provided) and the source electrode 60 and the drain electrode 70. An opening 91 is provided in the protective film 90 at a position facing the protrusion 23 of the barrier layer 20, and a gate electrode 50 is provided in the opening 91, or in the opening 91 and on the protective film 90 on the outside thereof. When the gate electrode 50 is provided in the opening 91 and on the protective film 90 on the outside thereof, a portion on the protective film 90 may be provided as a gate field plate. This realizes a semiconductor device 1d in which the barrier layer 40, etc., and the source electrode 60 and the drain electrode 70 are protected by the protective film 90. It is also possible to interpose a part of the protective film 90 between the barrier layer 40, etc. and the gate electrode 50 without providing the opening 91 in the protective film 90, and to make the part function as a gate insulating film.

[0077] In the above description, the semiconductor devices 1, 1a, 1b, 1c, and 1d are illustrated as having a so-called asymmetric structure in which the distance between the gate electrode 50 and the drain electrode 70 is wider than the distance between the gate electrode 50 and the source electrode 60. In addition, the above method is also applicable to a so-called symmetric structure in which the distance between the gate electrode 50 and the drain electrode 70 is equal to the distance between the gate electrode 50 and the source electrode 60.

[0078] [Second embodiment] Fig. 8 is a diagram for explaining an example of a semiconductor device according to the second embodiment. Fig. 8 is a schematic cross-sectional view of a main part of the example of the semiconductor device according to the second embodiment.

[0079] 8 is an example of a HEMT. The semiconductor device 2 includes a substrate 10, a barrier layer 20, a channel layer 30, a barrier layer 40, a gate electrode 50, a source electrode 60, and a drain electrode 70. The semiconductor device 2 has a configuration in which a two-dimensional hole gas (2DHG) 102 is generated in the vicinity of a junction interface between the channel layer 30 and the barrier layer 40.

[0080] In the semiconductor device 2 in which the 2DHG 102 is generated near the junction interface between the channel layer 30 and the barrier layer 40, the barrier layer 20, the channel layer 30, and the barrier layer 40 of the nitride semiconductor are stacked on the substrate 10 so that their thickness directions are in the [000-1] direction. In this case, the barrier layer 20 has a (000-1) plane, i.e., an N-polar plane, on the bottom surface 21a of the recess 21, the bottom surface 22a of the recess 22, and the upper surface 23a of the protrusion 23. The channel layer 30 has a (000-1) plane, i.e., an N-polar plane, on the surface 30a opposite to the barrier layer 20 side. The barrier layer 40 has a (000-1) plane, i.e., an N-polar plane, on the surface 40a opposite to the channel layer 30 side. The direction perpendicular to the (000-1) plane of each of the barrier layer 20, the channel layer 30, and the barrier layer 40 is the [000-1] direction. Due to spontaneous polarization of the barrier layer 40 and piezoelectric polarization generated in the barrier layer 40 due to strain caused by the lattice constant difference with the channel layer 30, a 2DHG 102 is generated near the junction interface with the barrier layer 40 on the N-polarity side of the channel layer 30.

[0081] In the semiconductor device 2, a gate electrode 50 is provided through a part of the channel layer 30 and a part of the barrier layer 40 at a position corresponding to the protrusion 23 provided on the barrier layer 20, i.e., at a position facing the protrusion 23 of the barrier layer 20 in the [000-1] direction. A source electrode 60 and a drain electrode 70 are provided through another part of the channel layer 30 at positions corresponding to the recesses 21 and 22 provided on the barrier layer 20, i.e., at positions facing the recesses 21 and 22 (respective parts spaced apart from the protrusion 23) of the barrier layer 20 in the [000-1] direction. The semiconductor device 2 has a configuration in which a QW structure of the protrusion 23 of the barrier layer 20, the channel layer 30, and the barrier layer 40 is adopted in a region below the gate electrode 50. The semiconductor device 2 has a configuration in which a QW structure is not adopted in the regions of the recesses 21 and 22 of the barrier layer 20 where the source electrode 60 and the drain electrode 70 are respectively provided.

[0082] When the semiconductor device 2 is in operation, a predetermined voltage is supplied between the source electrode 60 and the drain electrode 70, and a predetermined gate voltage is supplied to the gate electrode 50. A channel through which carrier holes are transported is formed in the channel layer 30 between the source electrode 60 and the drain electrode 70, and the transistor function of the semiconductor device 2 is realized.

[0083] In the semiconductor device 2, a QW structure is locally adopted in a region below the gate electrode 50, and a QW structure is not adopted in regions from that region toward the source electrode 60 and the drain electrode 70. With such a configuration, the advantage of high breakdown voltage due to the QW structure is enjoyed in the region below the gate electrode 50 where the electric field is likely to concentrate and dielectric breakdown is likely to occur, and an increase in resistance and a decrease in current value of the channel layer 30 are suppressed in the outer region. This realizes a semiconductor device 2 with high breakdown voltage and high output that uses holes as carriers.

[0084] In addition, in this semiconductor device 2, the positional relationship between the edges 21ba and 22ba of the convex portion 23 of the barrier layer 20 and the edges 51 and 52 of the gate electrode 50 may be adjusted according to the examples of Figures 6(A) and 6(B) above.

[0085] 7(A), a predetermined intermediate layer 80 such as a gate insulating film or a cap layer may be provided between the gate electrode 50 and the barrier layer 40, and a protective film 90 having an opening 91 in which the gate electrode 50 is provided may be provided according to the example of Fig. 7(B). Alternatively, a protective film 90 without an opening 91 may be provided.

[0086] Furthermore, the semiconductor device 1 etc. described in the first embodiment and the semiconductor device 2 described in the second embodiment may be mounted together on a common substrate 10. [Third embodiment] A method for forming a semiconductor device will now be described as a third embodiment.

[0087] First, a first example of a method for forming a semiconductor device will be described. Figures 9 and 10 are diagrams for explaining a first example of a method for forming a semiconductor device according to the third embodiment. Figures 9(A) to 9(C) and 10(A) to 10(C) each show a schematic cross-sectional view of a main part of each step of forming a semiconductor device of the first example.

[0088] First, as shown in Fig. 9A, a barrier layer 20 is grown on a substrate 10 by MOVPE. For example, an AlN freestanding substrate is used as the substrate 10. For example, an AlN layer having a thickness of 1000 nm and an AlN layer having a thickness of 10 nm are grown on the substrate 10 as the barrier layer 20. z1 Ga 1-z1 N buffer layers (0≦z1<1) are grown sequentially.

[0089] Next, as shown in FIG. 9(B), the barrier layer 20 grown on the substrate 10 is formed with the recesses 21 and 22 and the protrusions 23 therebetween. For example, a mask (not shown) having openings in the regions where the recesses 21 and 22 are to be formed is formed on the barrier layer 20 grown on the substrate 10 using a photolithography technique. Then, the barrier layer 20 at the openings of the mask is removed by dry etching using a chlorine-based gas, and the recesses 21 and 22 are formed. The formation of the recesses 21 and 22 forms the protrusions 23 therebetween. As a result, the barrier layer 20 having the recesses 21 and 22 and the protrusions 23, that is, the barrier layer 20 having the bottom surface 21a and the bottom surface 22a, the side surfaces 21b and the side surfaces 22b, and the upper surface 23a, as shown in FIG. 9(B) is formed. After the barrier layer 20 having the recesses 21 and 22 and the protrusions 23 is formed, the mask is removed.

[0090] 9(C), a channel layer 30 is grown by MOVPE on the barrier layer 20 on which the recesses 21, 22, and protrusions 23 are formed. For example, a GaN layer having a thickness of 1000 nm is grown on the barrier layer 20. The channel layer 30 is grown so as to fill the recesses 21, 22, and protrusions 23 of the barrier layer 20, and protrusions 31 are formed at positions corresponding to the protrusions 23 of the barrier layer 20.

[0091] Next, as shown in FIG. 10(A), the channel layer 30 is planarized. For example, a mask (not shown) having openings in the regions of the protrusions 31 is formed on the channel layer 30 on which the protrusions 31 are formed as shown in FIG. 9(C) by using a photolithography technique. Then, the protrusions 31 of the channel layer 30 at the openings of the mask are removed by dry etching using a chlorine-based gas. This forms the channel layer 30 having a planarized surface 30a as shown in FIG. 10(A). After the planarized channel layer 30 is formed, the mask is removed.

[0092] 10B, a barrier layer 40 is grown on the planarized channel layer 30 by MOVPE. For example, a 10 nm thick Al z2 Ga 1-z2 An N layer (0.5≦z2≦1) is formed on the channel layer 30. As a result, a laminated structure of nitride semiconductors including the barrier layer 20, the channel layer 30 and the barrier layer 40 is formed on the substrate 10.

[0093] In forming such a laminated structure of nitride semiconductors, for example, the barrier layer 20 grown on the substrate 10 is grown and etched to have bottom surfaces 21a and 22a and top surface 23a that are group III polarity surfaces (FIGS. 9(A) and 9(B)). The channel layer 30 grown on the barrier layer 20 is grown and etched to have a surface 30a that is a group III polarity surface (FIGS. 9(C) and 10(A)). The barrier layer 40 grown on the channel layer 30 is grown to have a surface 40a that is a group III polarity surface (FIG. 10(B)). As a result, a 2DEG 101 is generated near the junction interface between the channel layer 30 and the barrier layer 40.

[0094] In addition to the AlN freestanding substrate, the substrate 10 may be a substrate of Si, sapphire, SiC, GaN, etc. Also, the barrier layer 20 (its buffer layer) and the barrier layer 40 may contain In, which is easily lattice-matched with GaN, at least in the portion that is bonded to the GaN of the channel layer 30. a Al b Ga 1-a-bN(0 < a < 0.1, b < 1) may be used.

[0095] In the growth using the MOVPE method, for the source gas, NH3 (ammonia), trimethylgallium (TMGa), trimethylaluminum (TMAl), trimethylindium (TMIn), triethylboron (TEB), etc. are used. For the carrier gas, H2 (hydrogen) is used. Depending on the nitride semiconductor to be grown, the supply and stop (switching) of the source gas and the flow rate (mixing ratio with other raw materials) during supply are appropriately set. The growth pressure is about 1 kPa to 100 kPa, and the growth temperature is about 700°C to 1500°C.

[0096] After forming a stacked structure of a nitride semiconductor including a barrier layer 20, a channel layer 30, and a barrier layer 40 on the substrate 10 as described above, using photolithography technology, a mask (not shown) that covers the region to be the active region and has an opening outside the region is formed. Then, dry etching using a chlorine-based gas or ion implantation of argon (Ar) etc. is performed on the opening of the mask, and an element isolation region (not shown) that defines the active region is formed. After the formation of the element isolation region, the mask is removed.

[0097] Next, as shown in FIG. 10(C), a source electrode 60, a drain electrode 70, and a gate electrode 50 are formed. In this case, a mask (not shown) having openings in the regions where the source electrode 60 and the drain electrode 70 are to be formed is first formed by using a photolithography technique, and the barrier layer 40 in the openings of the mask is removed by dry etching using a chlorine-based gas. Here, the openings of the mask are provided at positions corresponding to the respective parts (parts 21bb and 22bb) of the recesses 21 and 22 of the barrier layer 20 that are spaced apart from the protrusions 23, that is, at positions facing the respective parts in the

[0001] direction. Then, after removing the barrier layer 40 in the openings of the mask, a metal for electrodes is formed in the regions where the source electrode 60 and the drain electrode 70 are to be formed, that is, the regions where the barrier layer 40 has been removed, by using a photolithography technique, a deposition technique, and a lift-off technique. For example, a laminate of Ta having a thickness of 20 nm and Al having a thickness of 200 nm is formed as the metal for electrodes. Then, a heat treatment is performed in a nitrogen atmosphere at 400°C to 1000°C, for example, 550°C, to establish an ohmic connection of the metal for electrodes. 10(C), a source electrode 60 and a drain electrode 70 are formed which penetrate the barrier layer 40 and are connected to the channel layer 30. The source electrode 60 and the drain electrode 70 are formed at positions corresponding to parts of the recesses 21 and the recesses 22 of the barrier layer 20, i.e., at positions facing the respective parts in the

[0001] direction.

[0098] Alternatively, a mask having openings may be formed in the regions where the source electrode 60 and the drain electrode 70 are to be formed, the barrier layer 40 in the openings may be removed, and then a part of the channel layer 30 may be removed and a contact layer of n-type GaN or the like may be formed thereon by MOVPE. On the contact layer thus formed, the source electrode 60 and the drain electrode 70 may be formed according to the above example.

[0099] After the source electrode 60 and the drain electrode 70 are formed, a metal electrode is formed in the region where the gate electrode 50 is to be formed by using photolithography, deposition, and lift-off techniques. For example, a laminate of Ni with a thickness of 30 nm and Au with a thickness of 400 nm is formed as the metal electrode. The metal electrode is formed at a position corresponding to the protrusion 23 of the barrier layer 20, that is, at a position facing the protrusion 23 in the

[0001] direction. As a result, as shown in FIG. 10(C), a gate electrode 50 connected to the barrier layer 40 is formed at a position corresponding to the protrusion 23 of the barrier layer 20, that is, at a position facing the protrusion 23 in the

[0001] direction. The gate electrode 50 functions as a Schottky electrode.

[0100] The types of metals and layer structures used for the gate electrode 50, source electrode 60, and drain electrode 70 are not limited to the above examples, and the methods for forming them are not limited to the above examples. The gate electrode 50, source electrode 60, and drain electrode 70 may each have a single layer structure or a laminated structure. When forming the source electrode 60 and drain electrode 70, it is not necessary to perform the heat treatment as described above as long as ohmic connection is achieved by forming the metal for the electrodes. When forming the gate electrode 50, a further heat treatment may be performed after the metal for the electrodes is formed.

[0101] For example, the above steps shown as the first example provide a semiconductor device 1 as shown in FIG. 10(C). In addition to the semiconductor device 1, the semiconductor device 1a shown in Fig. 6(A) and the semiconductor device 1b shown in Fig. 6(B) can also be obtained by the same process. In this case, the positions of the recesses 21 and 22 and the protrusions 23 of the barrier layer 20 and the position of the gate electrode 50 are appropriately adjusted. This adjusts the positional relationship between the edges 21ba and 22ba of the protrusions 23 of the barrier layer 20 and the edges 51 and 52 of the gate electrode 50.

[0102] In addition, in the case of providing an intermediate layer 80 as in the semiconductor device 1c shown in FIG. 7(A) above, for example, after the formation of the barrier layer 40 and before the formation of the source electrode 60 and the drain electrode 70, a predetermined intermediate layer 80 such as a gate insulating film or a cap layer is formed.

[0103] In addition, in the case where a protective film 90 is provided as in the semiconductor device 1d shown in FIG. 7B, for example, the protective film 90 is formed after the formation of the source electrode 60 and the drain electrode 70 and before the formation of the gate electrode 50. As an example, after the formation of the source electrode 60 and the drain electrode 70, a protective film material having a thickness of 2 nm to 500 nm, for example, a thickness of 100 nm, is formed by using a plasma chemical vapor deposition (CVD) method. The protective film material may be formed by an atomic layer deposition (ALD) method, a sputtering method, or the like. For example, an oxide, nitride, or oxynitride containing at least one of Si, Al, Hf (hafnium), Zr (zirconium), Ti (titanium), Ta, and W (tungsten) is used as the protective film material. For example, SiN (silicon nitride) is formed as the protective film material. Then, a mask having an opening in a region where the gate electrode 50 is to be formed is formed on the protective film material using a photolithography technique, and the protective film material in the opening of the mask is removed by dry etching using a fluorine-based or chlorine-based gas, wet etching using hydrofluoric acid or buffered hydrofluoric acid, or the like. After etching the protective film material, the mask is removed. As a result, a protective film 90 having an opening 91 in a region where the gate electrode 50 is to be formed is formed. Then, the gate electrode 50 is formed in the opening 91 of the protective film 90, or in the opening 91 and on the protective film 90 outside it. The gate electrode 50 may be formed on the protective film 90 in which the opening 91 is not formed.

[0104] 8, the barrier layer 20, the channel layer 30, and the barrier layer 40 are grown in the N-plane. That is, the barrier layer 20 grown on the substrate 10 is grown and etched to have bottom surfaces 21a and 22a and top surface 23a of the N-polarity plane. The channel layer 30 grown on the barrier layer 20 is grown and etched to have a surface 30a of the N-polarity plane. The barrier layer 40 grown on the channel layer 30 is grown to have a surface 40a of the N-polarity plane. As a result, a 2DHG 102 is generated in the vicinity of the junction interface between the channel layer 30 and the barrier layer 40.

[0105] Next, a second example of the method for forming a semiconductor device will be described. Figures 11 and 12 are diagrams for explaining a second example of the method for forming a semiconductor device according to the third embodiment. Figures 11(A) to 11(C) and Figures 12(A) to 12(C) each show a schematic cross-sectional view of a main part of each step of forming a semiconductor device of the second example.

[0106] First, as shown in Fig. 11(A), an underlayer 11 is grown on a substrate 10 by MOVPE. For example, an AlN freestanding substrate is used as the substrate 10. For example, an AlN layer and a buffer layer are grown in sequence on the substrate 10 as the underlayer 11. Then, a channel layer 30 is grown on the underlayer 11 grown on the substrate 10 by MOVPE. For example, a GaN layer having a thickness of 1000 nm is grown on the underlayer 11.

[0107] 11(B), the substrate 10 and the underlayer 11 are removed. For example, the substrate 10 and the underlayer 11 are removed by dry etching using a chlorine-based or fluorine-based gas. By removing the substrate 10 and the underlayer 11, the surface 30b of the channel layer 30 is exposed.

[0108] 11(C), a recess 32 is formed in the channel layer 30 from which the substrate 10 and the underlayer 11 have been removed. For example, the recess 32 is formed by dry etching using a chlorine-based gas on the surface 30b side of the channel layer 30 from which the substrate 10 and the underlayer 11 have been removed. The recess 32 in the channel layer 30 is formed in correspondence with the positions where the protrusion 23 of the barrier layer 20 and the gate electrode 50 are to be formed. The thickness from the bottom of the recess 32 to the surface 30a opposite to the surface 30b is set to 50 nm or less, preferably 20 nm or less.

[0109] 12(A), a barrier layer 20 is grown on the face 30b side of the channel layer 30 where the recess 32 is formed, so as to fill the recess 32 and face 30b. For example, an AlN layer having a thickness of 1000 nm from the bottom of the recess 32 is grown as the barrier layer 20. This forms the barrier layer 20 having the recess 21 and the recess 22 as well as the protrusion 23 therebetween.

[0110] 12B, a barrier layer 40 is grown on the surface 30a side of the channel layer 30 by MOVPE. For example, a 10 nm thick Al z2 Ga 1-z2 An N layer (0.5≦z2≦1) is formed on the channel layer 30. In this way, a laminated structure of nitride semiconductors including the barrier layer 20, the channel layer 30, and the barrier layer 40 is formed.

[0111] In forming such a nitride semiconductor laminate structure, for example, the channel layer 30 is grown to have a face 30a of a group III polarity plane on the side opposite to the face 30b on which the barrier layer 20 is provided (FIG. 11(A)). The barrier layer 20 is grown to have bottom faces 21a and 22a and a top face 23a of group III polarity planes (FIG. 12(A)). The barrier layer 40 is grown to have a face 40a of a group III polarity plane (FIG. 12(B)). As a result, a 2DEG 101 is generated in the vicinity of the junction interface between the channel layer 30 and the barrier layer 40.

[0112] In addition to the AlN free-standing substrate, substrates such as Si, sapphire, SiC, and GaN may also be used for the substrate 10. Further, in the underlying layer 11 (the buffer layer) and the barrier layer 40, at least in the portion joined to the GaN of the channel layer 30, In a Al b Ga 1-a-b N (0 < a < 0.1, b < 1) may be used.

[0113] After the formation of the nitride semiconductor stack structure as shown in FIG. 12(B), in the same manner as described in the first example, an element isolation region (not shown) is formed, and as shown in FIG. 12(C), a source electrode 60, a drain electrode 70, and a gate electrode 50 are formed. The source electrode 60 and the drain electrode 70 are formed at positions corresponding to respective parts (sites 21bb and 22bb) of the recesses 21 and 22 of the barrier layer 20 that are separated from the convex portion 23, that is, at positions facing each of these parts in the

[0001] direction. In other words, the source electrode 60 and the drain electrode 70 are formed at positions corresponding to respective parts (sites 21bb and 22bb) of one side and the other side of the recess 32 of the channel layer 30 that are separated from the recess 32, that is, at positions facing each of these parts in the

[0001] direction. The gate electrode 50 is formed at a position corresponding to the convex portion 23 of the barrier layer 20, that is, at a position facing the convex portion 23 in the

[0001] direction. In other words, the gate electrode 50 is formed at a position corresponding to the recess 32 of the channel layer 30, that is, at a position facing the recess 32 in the

[0001] direction.

[0114] For example, by the above-described process shown as the second example, a semiconductor device 1e as shown in FIG. 12(C) is obtained. In addition, the formation positions of the recess 32 of the channel layer 30, the recesses 21 and 22 and the convex portion 23 of the barrier layer 20, and the formation position of the gate electrode 50 may be appropriately adjusted. Thereby, the positional relationship between the edges 21ba and 22ba of the convex portion 23 of the barrier layer 20 and the edges 51 and 52 of the gate electrode 50 is adjusted.

[0115] Furthermore, after the barrier layer 40 is formed and before the source electrode 60 and the drain electrode 70 are formed, a contact layer may be formed in the region where the source electrode 60 and the drain electrode 70 are to be formed, and the source electrode 60 and the drain electrode 70 may be formed on the contact layer. Furthermore, after the barrier layer 40 is formed and before the source electrode 60 and the drain electrode 70 are formed, a predetermined intermediate layer 80 such as a gate insulating film or a cap layer may be formed.

[0116] Furthermore, after the source electrode 60 and the drain electrode 70 are formed and before the gate electrode 50 is formed, a protective film 90 having an opening 91 may be formed, and the gate electrode 50 may be formed in the opening 91. Note that the gate electrode 50 may be formed on the protective film 90 in which the opening 91 is not formed.

[0117] Alternatively, the channel layer 30 may be grown so that its face 30a is an N-polar face (face 30b is a group III polar face), and the bottom face 21a, bottom face 22a and top face 23a of the barrier layer 20 and the face 40a of the barrier layer 40 may be grown so that they are N-polar faces. As a result, a 2DHG 102 is generated near the junction interface between the channel layer 30 and the barrier layer 40.

[0118] The semiconductor devices 1, 1a, 1b, 1c, 1d, 1e, 2, etc. having the configurations described above in the first to third embodiments can be applied to various electronic devices. As an example, the application of the semiconductor device having the above configuration to a semiconductor package, a power factor correction circuit, a power supply device, and an amplifier will be described below.

[0119] [Fourth embodiment] Here, an example of application of the semiconductor device having the above-mentioned configuration to a semiconductor package will be described as the fourth embodiment.

[0120] Fig. 13 is a diagram for explaining an example of a semiconductor package according to the fourth embodiment, which diagrammatically shows a plan view of a main part of the example of the semiconductor package according to the fourth embodiment.

[0121] 13 is an example of a discrete package. The semiconductor package 200 includes, for example, the semiconductor device 1 described in the first embodiment, a lead frame 210 on which the semiconductor device 1 is mounted, and a resin 220 that seals them.

[0122] The semiconductor device 1 is mounted on a die pad 210a of a lead frame 210 using a die attach material or the like (not shown). The semiconductor device 1 is provided with a pad 50a connected to the gate electrode 50, a pad 60a connected to the source electrode 60, and a pad 70a connected to the drain electrode 70. The pads 50a, 60a, and 70a are connected to the gate lead 211, the source lead 212, and the drain lead 213 of the lead frame 210, respectively, using wires 230 made of Al or the like. The lead frame 210, the semiconductor device 1 mounted thereon, and the wires 230 connecting them are sealed with resin 220 so that parts of the gate lead 211, the source lead 212, and the drain lead 213 are exposed.

[0123] An electrode connected to the source electrode 60 may be provided on the surface of the semiconductor device 1 opposite to the surface on which the pad 50a connected to the gate electrode 50 and the pad 70a connected to the drain electrode 70 are provided. The electrode may be connected to the die pad 210a connected to the source lead 212 by using a conductive bonding material such as solder.

[0124] For example, the semiconductor device 1 described in the first embodiment is used to obtain a semiconductor package 200 having such a configuration. Although the semiconductor device 1 is used as an example here, it is possible to obtain a semiconductor package in a similar manner using other semiconductor devices 1a, 1b, 1c, 1d, 1e, 2, etc. that function as HEMTs.

[0125] As described above, in the semiconductor device 1, etc., the QW structure is locally adopted in the region below the gate electrode 50 where the electric field, etc., is likely to concentrate, thereby achieving a high breakdown voltage due to the QW structure and suppressing the effects of a decrease in current value and a decrease in output due to the QW structure. This realizes the semiconductor device 1, etc. with high breakdown voltage and high output. A high-performance semiconductor package 200 is realized by using such a semiconductor device 1, etc.

[0126] [Fifth embodiment] Here, an example of application of the semiconductor device having the above-mentioned configuration to a power factor correction circuit will be described as the fifth embodiment.

[0127] Fig. 14 is a diagram for explaining an example of a power factor correction circuit according to the fifth embodiment. Fig. 14 shows an equivalent circuit diagram of an example of the power factor correction circuit according to the fifth embodiment. The power factor correction (PFC) circuit 300 shown in FIG. 14 includes a switch element 310, a diode 320, a choke coil 330, a capacitor 340, a capacitor 350, a diode bridge 360, and an AC power supply 370 (AC).

[0128] In the PFC circuit 300, a drain electrode of a switch element 310 is connected to an anode terminal of a diode 320 and one terminal of a choke coil 330. A source electrode of the switch element 310 is connected to one terminal of a capacitor 340 and one terminal of a capacitor 350. The other terminal of the capacitor 340 is connected to the other terminal of the choke coil 330. The other terminal of the capacitor 350 is connected to a cathode terminal of the diode 320. A gate driver is connected to the gate electrode of the switch element 310. An AC power supply 370 is connected between both terminals of the capacitor 340 via a diode bridge 360, and a DC power supply (DC) is taken out from between both terminals of the capacitor 350.

[0129] For example, the semiconductor devices 1, 1a, 1b, 1c, 1d, 1e, 2, etc. functioning as HEMTs are used in the switch element 310 of the PFC circuit 300 having such a configuration. As described above, in the semiconductor device 1 etc., the QW structure is locally adopted in the region below the gate electrode 50 where the electric field etc. is likely to concentrate, thereby achieving a high breakdown voltage due to the QW structure and suppressing the effects of a decrease in current value and a decrease in output due to the QW structure. This realizes the semiconductor device 1 etc. with high breakdown voltage and high output. A high-performance PFC circuit 300 is realized by using such a semiconductor device 1 etc.

[0130] [Sixth embodiment] Here, an example of application of a semiconductor device having the above-mentioned configuration to a power supply device will be described as the sixth embodiment.

[0131] Fig. 15 is a diagram for explaining an example of a power supply device according to the sixth embodiment. Fig. 15 shows an equivalent circuit diagram of the example of the power supply device according to the sixth embodiment. The power supply device 400 shown in FIG. 15 includes a primary side circuit 410, a secondary side circuit 420, and a transformer 430 provided between the primary side circuit 410 and the secondary side circuit 420.

[0132] The primary side circuit 410 includes the PFC circuit 300 as described in the fifth embodiment above, and an inverter circuit, for example, a full-bridge inverter circuit 440, connected between both terminals of the capacitor 350 of the PFC circuit 300. The full-bridge inverter circuit 440 includes a plurality of switch elements, for example, four switch elements 441, 442, 443, and 444.

[0133] The secondary side circuit 420 includes a plurality of switch elements, three of which, as an example here, are a switch element 421, a switch element 422, and a switch element 423. For example, the semiconductor devices 1, 1a, 1b, 1c, 1d, 1e, 2, etc. functioning as HEMTs are used for the switch element 310 of the PFC circuit 300 included in the primary side circuit 410 of the power supply device 400 having such a configuration, and for the switch elements 441-444 of the full bridge inverter circuit 440. For example, normal MIS type field effect transistors using silicon are used for the switch elements 421-423 of the secondary side circuit 420 of the power supply device 400.

[0134] As described above, in the semiconductor device 1, etc., the QW structure is locally adopted in the region below the gate electrode 50 where the electric field, etc., is likely to concentrate, thereby achieving a high breakdown voltage due to the QW structure and suppressing the effects of a decrease in current value and a decrease in output due to the QW structure. This realizes the semiconductor device 1, etc. with high breakdown voltage and high output. A high-performance power supply device 400 is realized by using such a semiconductor device 1, etc.

[0135] [Seventh embodiment] Here, an example of application of the semiconductor device having the above-mentioned configuration to an amplifier will be described as the seventh embodiment.

[0136] Fig. 16 is a diagram for explaining an example of an amplifier according to the seventh embodiment. Fig. 16 shows an equivalent circuit diagram of an example of the amplifier according to the seventh embodiment. The amplifier 500 shown in FIG. 16 includes a digital predistortion circuit 510, a mixer 520, a mixer 530, and a power amplifier 540.

[0137] The digital predistortion circuit 510 compensates for nonlinear distortion of the input signal. The mixer 520 mixes the input signal SI, for which the nonlinear distortion has been compensated, with an AC signal. The power amplifier 540 amplifies the signal obtained by mixing the input signal SI with the AC signal. In the amplifier 500, for example, by switching a switch, the output signal SO can be mixed with the AC signal in the mixer 530 and sent to the digital predistortion circuit 510. The amplifier 500 can be used as a high-frequency amplifier or a high-power amplifier.

[0138] The power amplifier 540 of the amplifier 500 having such a configuration uses the semiconductor devices 1, 1a, 1b, 1c, 1d, 1e, 2, etc. functioning as HEMTs. As described above, in the semiconductor device 1, etc., the QW structure is locally adopted in the region below the gate electrode 50 where the electric field, etc., is likely to concentrate, thereby achieving a high breakdown voltage due to the QW structure and suppressing the effects of a decrease in current value and a decrease in output due to the QW structure. This realizes the semiconductor device 1, etc. with high breakdown voltage and high output. A high-performance amplifier 500 is realized by using such a semiconductor device 1, etc.

[0139] Various electronic devices to which the semiconductor devices 1, 1a, 1b, 1c, 1d, 1e, 2, etc. are applied (such as the semiconductor package 200, the PFC circuit 300, the power supply device 400, and the amplifier 500 described in the fourth to seventh embodiments) can be mounted in various electronic devices or electronic devices. For example, the devices can be mounted in various electronic devices or electronic devices such as computers (personal computers, supercomputers, servers, etc.), smartphones, mobile phones, tablet terminals, sensors, cameras, audio equipment, measuring devices, inspection devices, manufacturing devices, transmitters, receivers, and radar devices. [Explanation of symbols]

[0140] 1, 1a, 1b, 1c, 1d, 1e, 2, 100A, 100B Semiconductor device 10,110 PCB 11 Base layer 20,40,120B,140A,140B Barrier layer 21, 22, 32 Recess 21a,22a Bottom 21b,22b side 21ba, 22ba, 51, 52 Edge 21bb,22bb part 23,31 Convex 23a Top side 30, 130A, 130B Channel layer 30a,30b,40a side 50,150 Gate electrode 50a, 60a, 70a pads 60,160 Source electrode 70,170 Drain electrode 80 Intervening layer 90 Protective film 91 Opening 101, 101A, 101B 2DEG 102 2DHG 120A Buffer Layer 200 Semiconductor Packages 210 Lead Frame 210a Die pad 211 Gate Lead 212 Source Read 213 Drain Lead 220 Resin 230 Wire 300 PFC circuit 310,421,422,423,441,442,443,444 Switching elements 320 Diode 330 Choke Coil 340,350 Capacitor 360 Diode Bridge 370 AC power supply 400 power supply 410 Primary circuit 420 Secondary circuit 430 Trans 440 Full-bridge inverter circuit 500 Amplifier 510 Digital Pre-Distortion Circuit 520,530 Mixer 540 Power Amplifier

Claims

1. a first barrier layer including a first nitride semiconductor, the first barrier layer having a first recess and a second recess and a protrusion between the first recess and the second recess; a channel layer filling the first concave portion, the second concave portion, and the convex portion of the first barrier layer and including a second nitride semiconductor having a band gap smaller than that of the first nitride semiconductor; a second barrier layer provided on a first surface side of the channel layer opposite to the first barrier layer side, facing the first concave portion, the second concave portion, and the convex portion of the first barrier layer in a first direction perpendicular to the first surface, and including a third nitride semiconductor having a band gap larger than that of the second nitride semiconductor; a source electrode provided on the first surface side of the channel layer and facing a first portion of the first recess of the first barrier layer spaced apart from the protrusion in the first direction; a drain electrode provided on the first surface side of the channel layer and facing a second portion of the second recess of the first barrier layer spaced apart from the protrusion in the first direction; a gate electrode provided on a second surface side of the second barrier layer opposite to the channel layer side, the gate electrode being spaced apart from the source electrode and the drain electrode and facing the protruding portion of the first barrier layer in the first direction; A semiconductor device comprising:

2. 2. The semiconductor device according to claim 1, wherein the gate electrode has a first edge on the source electrode side and a second edge on the drain electrode side that face a third surface of the convex portion of the first barrier layer, the third surface extending from a third edge on the first recess side to a fourth edge on the second recess side.

3. 3. The semiconductor device according to claim 1, wherein a quantum well structure is locally formed between the first barrier layer and the second barrier layer, between the convex portion of the first barrier layer and a part of the second barrier layer facing the convex portion in the first direction.

4. 4. The semiconductor device according to claim 1, wherein the thickness in the first direction of the channel layer provided between the convex portion of the first barrier layer and a part of the second barrier layer facing the convex portion in the first direction is 50 nm or less.

5. 5. The semiconductor device according to claim 1, wherein the first surface of the channel layer filling the first and second recesses and the protrusions of the first barrier layer, on a side where the second barrier layer is provided, is a group III polarity surface of the second nitride semiconductor.

6. forming a first barrier layer including a first nitride semiconductor, the first barrier layer having a first recess and a second recess and a protrusion between the first recess and the second recess; forming a channel layer including a second nitride semiconductor having a band gap smaller than that of the first nitride semiconductor by filling the first concave portion, the second concave portion, and the convex portion of the first barrier layer; forming a second barrier layer including a third nitride semiconductor having a band gap larger than that of the second nitride semiconductor on a first surface side of the channel layer opposite to the first barrier layer side; forming a source electrode on the first surface side of the channel layer, the source electrode facing a first portion of the first recess of the first barrier layer spaced apart from the protrusion in a first direction perpendicular to the first surface; forming a drain electrode on the first surface side of the channel layer, the drain electrode facing a second portion of the second recess of the first barrier layer spaced apart from the protrusion in the first direction; forming a gate electrode on a second surface side of the second barrier layer opposite to the channel layer side, the gate electrode being spaced apart from the source electrode and the drain electrode and facing the protruding portion of the first barrier layer in the first direction; 2. A method for manufacturing a semiconductor device comprising the steps of:

7. forming a channel layer having a recess on the first surface side and including a first nitride semiconductor; forming a first barrier layer on the first surface side of the channel layer, filling the recess and the first surface, the first barrier layer including a second nitride semiconductor having a band gap larger than that of the first nitride semiconductor; forming a second barrier layer including a third nitride semiconductor having a band gap larger than that of the first nitride semiconductor on a second surface side of the channel layer opposite to the first surface side; forming a source electrode on the second surface side of the channel layer, the source electrode facing a first portion of the channel layer on one side of the recess and spaced apart from the recess in a first direction perpendicular to the second surface; forming a drain electrode on the second surface side of the channel layer, the drain electrode facing a second portion of the channel layer on the other side of the recess in the first direction and spaced apart from the recess; forming a gate electrode on a third surface side of the second barrier layer opposite to the channel layer side, the gate electrode being spaced apart from the source electrode and the drain electrode and facing the recess of the channel layer in the first direction; 2. A method for manufacturing a semiconductor device comprising the steps of:

8. a first barrier layer including a first nitride semiconductor, the first barrier layer having a first recess and a second recess and a protrusion between the first recess and the second recess; a channel layer filling the first concave portion, the second concave portion, and the convex portion of the first barrier layer and including a second nitride semiconductor having a band gap smaller than that of the first nitride semiconductor; a second barrier layer provided on a first surface side of the channel layer opposite to the first barrier layer side, facing the first concave portion, the second concave portion, and the convex portion of the first barrier layer in a first direction perpendicular to the first surface, and including a third nitride semiconductor having a band gap larger than that of the second nitride semiconductor; a source electrode provided on the first surface side of the channel layer and facing a first portion of the first recess of the first barrier layer spaced apart from the protrusion in the first direction; a drain electrode provided on the first surface side of the channel layer and facing a second portion of the second recess of the first barrier layer spaced apart from the protrusion in the first direction; a gate electrode provided on a second surface side of the second barrier layer opposite to the channel layer side, the gate electrode being spaced apart from the source electrode and the drain electrode and facing the protruding portion of the first barrier layer in the first direction; An electronic device comprising a semiconductor device comprising:

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