Manufacturing method for SiC semiconductor device and SiC semiconductor device

Abstract

The present invention addresses the problem of providing a high-quality SiC semiconductor device.　To solve the above problem, the present invention provides a method of manufacturing a SiC semiconductor device, the method comprising: a growth step for forming a growth layer on an object to be treated containing a SiC single crystal; a device forming step for forming at least a part of the SiC semiconductor device in the growth layer; and a separation step for separating the at least part of the SiC semiconductor device from the object to be treated. With such a configuration, in the present invention, the at least part of the SiC semiconductor device is formed on a SiC wafer with suppressed wafer warpage, and thereafter the SiC wafer containing the corresponding part can be separated. Thus, a SiC semiconductor device having excellent economic efficiency can be manufactured while suppressing the influence of water warpage in a SiC process.

Description

[Technical field]

[0001] The present invention relates to a method for manufacturing a SiC semiconductor device and a SiC semiconductor device. [Background technology]

[0002] Silicon carbide (SiC) has superior material properties such as dielectric breakdown strength, thermal conductivity, and radiation resistance compared to silicon (Si), and research and development of SiC as a material for use in electronic devices is currently underway.

[0003] The quality of SiC semiconductor devices is affected by warpage caused by internal stress in SiC single crystal wafers. For example, the warpage can make patterning on the SiC single crystal wafer difficult. The warpage can also cause suction errors of the SiC single crystal wafer, resulting in machine stoppages and cracks in the SiC single crystal wafer, which is a major factor hindering device manufacturing.

[0004] Therefore, in the manufacture of SiC semiconductor devices, SiC wafers having a substrate thickness greater than necessary may be used, leaving room for improvement in terms of economic efficiency.

[0005] Patent Document 1 discloses an invention relating to a method for manufacturing SiC substrates having an epitaxial layer one by one, the method including growing an epitaxial layer on a seed crystal substrate and growing a SiC substrate, and further including a step of removing the obtained SiC substrate having an epitaxial layer from the seed crystal substrate. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] JP 2015-24932 A Summary of the Invention [Problem to be solved by the invention]

[0007] However, according to the description of Patent Document 1, since the SiC substrate having the obtained epitaxial layer is sent to the subsequent device fabrication process, it is difficult to say that the influence of the warpage on the manufacturing process of the SiC semiconductor device can be eliminated.

[0008] In view of the above circumstances, an object of the present invention is to provide a high-quality SiC semiconductor device. [Means for solving the problem]

[0009] In order to solve the above problems, the present invention includes a growth step of forming a growth layer on a workpiece containing a SiC single crystal, a device formation step of forming at least a part of a SiC semiconductor device in the growth layer, and a separation step of separating at least a part of the SiC semiconductor device from the workpiece. With this configuration, the present invention can separate the SiC wafer containing at least a part of a SiC semiconductor device formed on a SiC wafer with reduced wafer warpage, thereby realizing the manufacture of an economical SiC semiconductor device while suppressing the effect of wafer warpage on the SiC process.

[0010] In a preferred embodiment of the present invention, the growth step heat-treats the workpiece in an atmosphere containing Si and C. With this configuration, it is possible to manufacture high-quality SiC wafers and SiC semiconductor devices while eliminating or suppressing the occurrence of distortion, crystal defects, basal plane dislocations (BPDs), and macrostep bunching (MSBs).

[0011] In a preferred embodiment of the present invention, the growth step heat-treats the workpiece in a semi-closed space in which the SiC material is exposed. With this configuration, the present invention can manufacture a high-quality SiC wafer while eliminating or suppressing the occurrence of distortion, crystal defects, BPDs, and MSBs, and then manufacture a SiC semiconductor device.

[0012] In a preferred embodiment of the present invention, the device forming step includes a patterning step of forming a circuit pattern on the workpiece. With this configuration, the present invention can perform patterning suitably on a SiC wafer with reduced wafer warpage, and can manufacture a high-quality SiC semiconductor device.

[0013] In a preferred embodiment of the present invention, the device formation step includes a doping step of introducing dopant atoms into the workpiece. With this configuration, the present invention can perform doping appropriately on a SiC wafer with reduced wafer warpage, and can manufacture a high-quality SiC semiconductor device.

[0014] In a preferred embodiment of the present invention, the device forming step includes an insulating film forming step of introducing an insulating film into the workpiece. With this configuration, the present invention can suitably form an insulating film on a SiC wafer with reduced wafer warpage, and can manufacture a high-quality SiC semiconductor device.

[0015] In a preferred embodiment of the present invention, the device forming step includes an electrode forming step of forming an electrode on the workpiece. With this configuration, the present invention can suitably form an electrode on a SiC wafer with reduced wafer warpage, and can manufacture a high-quality SiC semiconductor device.

[0016] In a preferred embodiment of the present invention, the separation step includes a separation layer forming step of forming a separation layer inside the object to be processed, and a peeling step of peeling off a part of the object to be processed starting from the separation layer. With this configuration, the present invention can realize separation of a SiC wafer including at least a part of a SiC semiconductor device while suppressing material loss.

[0017] In a preferred embodiment of the present invention, the separation layer forming step forms the separation layer by irradiating the workpiece with a laser so that the inside of the workpiece is a focal point. With this configuration, the present invention can form a flat separation layer in the SiC single crystal, which is a starting point for peeling.

[0018] In a preferred embodiment of the present invention, an etching step is performed in which the object is etched by heat treating the object in an atmosphere containing Si element and C element. With this configuration, the present invention can manufacture high-quality SiC wafers while eliminating or suppressing the occurrence of distortion, crystal defects, BPDs, and MSBs, and can then manufacture SiC semiconductor devices.

[0019] In a preferred embodiment of the present invention, the etching step heat-treats the workpiece in a semi-closed space in which the SiC material is exposed. With this configuration, the present invention can manufacture a high-quality SiC wafer while eliminating or suppressing the occurrence of distortion, crystal defects, BPDs, and MSBs, and then manufacture a SiC semiconductor device.

[0020] In a preferred embodiment of the present invention, the method includes the steps of separating, etching, and growing in this order. With this configuration, the present invention can repeatedly manufacture higher quality SiC wafers including at least a part of a SiC semiconductor device, thereby realizing economical manufacture of SiC semiconductor devices.

[0021] In a preferred embodiment of the present invention, the separation step and the growth step are included in this order. With such a configuration, the present invention can repeatedly manufacture high-quality SiC wafers including at least a part of a SiC semiconductor device, thereby realizing the manufacture of an economical SiC semiconductor device.

[0022] In order to solve the above problems, the present invention provides a semiconductor device having a basal plane dislocation density of <100 / cm 2 The growth layer is an n-type or p-type substrate. With this configuration, the present invention can realize a high-quality SiC semiconductor device that suppresses the generation of stacking faults that cause deterioration of forward characteristics.

[0023] In a preferred embodiment of the present invention, the dopant concentration of the growth layer is 1.0×10 17 / cm3 With this configuration, the present invention can realize a high-quality SiC semiconductor device that can suppress the generation of stacking faults that cause degradation of forward characteristics, for example. Effect of the Invention

[0024] According to the present invention, a high-quality SiC semiconductor device can be provided.

[0025] Other objects, features and advantages will become apparent from a reading of the following detailed description when taken in conjunction with the drawings and the claims. [Brief description of the drawings]

[0026] [Figure 1] 1 is a schematic diagram of a manufacturing process of a SiC semiconductor device. [Diagram 2] FIG. 1 is a schematic diagram of the growth process. [Diagram 3] 1 is a schematic diagram of a part of a device formation process. [Figure 4] 1 is a schematic diagram of a part of a device formation process. [Diagram 5] FIG. 13 is a schematic diagram of an electrode formation step after a separation step. [Figure 6] FIG. 2 is a schematic diagram of the separation process. [Figure 7] FIG. 2 is a schematic diagram of an etching process. [Figure 8] 1 is a schematic diagram of a manufacturing process of a SiC semiconductor device. [Figure 9] FIG. 1 is a schematic diagram of a SiC semiconductor device. [Figure 10] FIG. 1 is a schematic diagram of raw material transport for the growth and etching steps. [Figure 11] FIG. 1 is a schematic diagram of raw material transport for the growth and etching steps. [Figure 12] FIG. 2 is a schematic diagram of a main container and a high melting point container. [Figure 13] FIG. 13 is an explanatory diagram of a method for calculating a BPD conversion rate. [Figure 14]FIG. 2 is an explanatory diagram of a SiC wafer formed in a heat treatment process. [Figure 15] FIG. 2 is an explanatory diagram of a SiC wafer formed in a heat treatment process. [Figure 16] 1 is an Arrhenius plot relating to a heat treatment process. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0027] Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings. Note that some reference numerals in the following description are not shown in the drawings. The technical scope of the present invention is not limited to the embodiments shown in the accompanying drawings, and may be modified as appropriate within the scope of the claims.

[0028] As shown in FIG. 1, one embodiment of the present invention includes a growth process S1 for forming a growth layer 10 on a workpiece 1 including a SiC single crystal, a device formation process S2 for forming at least a portion of a SiC semiconductor device 12 in the growth layer 10, and a separation process S3 for separating at least a portion of the formed SiC semiconductor device 12 from the workpiece 1. In the description of this specification, "SiC semiconductor device 12" refers to a semiconductor device that includes at least a SiC material, including a SiC device.

[0029] The workpiece 1 includes an original substrate 11 made of a SiC single crystal. The original substrate 11 may be a SiC ingot produced by a known crystal growth method such as sublimation, or may be a SiC wafer sliced ​​into a disk shape from the SiC ingot. Note that the "polytype of the SiC single crystal" in the description of this specification refers to known polytypes such as 3C, 4H, and 6H.

[0030] The cross-sectional size of the object to be processed 1 is several centimeters square, 2 inches, 3 inches, 4 inches, 6 inches, 8 inches, or 12 inches. There is no limitation on the cross-sectional size.

[0031] The surface of the object to be processed 1 may be configured to have an off angle of several degrees (for example, 0.4 to 8.0°) from the (0001) or (000-1) plane. Note that in the description of this specification, "-" refers to a bar in the notation of Miller indices.

[0032] The method of manufacturing the SiC semiconductor device 12 can be understood as follows. 1) In the growth step S1, a growth layer 10 is formed on an original substrate 11. 2) In the device formation step S2, the growth layer 10 is processed to form at least a part of a SiC semiconductor device 12. 3) In the separation step S3, at least a part of the SiC semiconductor device 12 formed in the device formation step S2 is separated from the processing target object 1.

[0033] 《Growth process S1》 As shown in Fig. 2, the growth step S1 includes an epitaxial growth step S11 and a bunching decomposition step S12 to form a growth layer 10 on an original substrate 11. Note that in this specification, a mechanism related to the growth step S1 will be described later. Also, Fig. 2 illustrates an SiC semiconductor device 12 having a field effect transistor (FET) structure.

[0034] The epitaxial growth process S11 performs crystal growth on the surface of an original substrate 11 having steps 101a and terraces 101b having a reduced terrace length W1 to form a growth layer 10 having steps 102a and terraces 102b having an increased terrace length W2, or to form a growth layer 10 having a bunched surface.

[0035] In addition, the epitaxial growth step S11 is <100 / cm 2 Crystal growth is performed to form at least a portion of the growth layer 10 so as to form a growth layer having a basal plane dislocation density (BPD density) of 100 nm or so that the BPDs in the workpiece 1 are converted to other defects / dislocations including threading edge dislocations (TEDs).

[0036] In the bunching decomposition step S12, the MSB on the surface of the object 1 is decomposed to grow the crystal of the object 1 so as to form a growth layer 10 having steps 103a and terraces 103b with a reduced terrace length W3 on the surface of the growth layer 10 having steps 102a and terraces 102b, or to form a flattened bunching-free surface. At this time, the surface of the growth layer 10 is terminated with a step having the height of a full unit in the SiC single crystal.

[0037] In the description herein, a "planarized bunching-free surface" refers to a SiC surface where the MSBs have been decomposed. In the description of this specification, "MSB" refers to steps on the SiC surface that form a height exceeding the full unit of each polytype by bunching. That is, an MSB is a bunching step exceeding four molecular layers (five molecular layers or more) in the case of 4H-SiC, and a bunching step exceeding six molecular layers (seven molecular layers or more) in the case of 6H-SiC.

[0038] The thickness of the growth layer 10 formed in one embodiment of the present invention is preferably 500 μm or less, more preferably 350 μm or less, more preferably 200 μm or less, more preferably 150 μm or less, even more preferably 120 μm or less, even more preferably 100 μm or less, even more preferably 50 μm or less, and even more preferably 20 μm or less. Moreover, the thickness is preferably 20 μm or more, more preferably 50 μm or more, more preferably 100 μm or more, more preferably 150 μm or more, even more preferably 200 μm or more, and even more preferably 350 μm or more.

[0039] Growth step S1 is <100 / cm 2 After forming the growth layer having the BPD density, SiC epitaxial growth may be further performed based on a known film formation method such as physical vapor deposition (PVD) or chemical vapor deposition (CVD). Also, the <100 / cm 2 A portion of the growth layer 10 having a BPD density of 1.0×10 may be treated as the substrate 111. The substrate 111 may be, for example, 1.0×10 17 / cm 3 The dopant concentration is equal to or greater than 100%.

[0040] In the description of this specification, the "processing target 1" refers to the processing target 1 including the growth layer 10 after the growth step S1. In addition, the "various processes on the processing target 1" in the device formation step S2 and the separation step S3 described later can be understood as "various processes on the growth layer 10 included in the processing target 1."

[0041] Device formation process S2 As shown in FIG. 3, the device formation step S2 includes a patterning step S21 for forming a circuit pattern 211 on the target object 1 on which the growth layer 10 has been formed.

[0042] <Patterning process S21> The patterning step S21 includes, for example, a resist application step of applying a photoresist, an exposure step of exposing the photoresist through a photomask, and a development step of developing the exposed photoresist.

[0043] In the resist coating step, a known photoresist containing a base resin that selectively reacts to the wavelength of a light source that can be used in the exposure step described below is coated on the object 1 to be processed. For example, when the light source is a g-line (wavelength: 436 nm), the photoresist is a polymer material containing a novolac resin and a 1,2-naphthoquinone diazide sulfonate (NQD)-based compound. Also, when the light source is an ArF laser (wavelength: 193 nm), the photoresist is a polymer material containing a base resin having an alicyclic group that can suppress light absorption around 200 nm wavelength, such as norbornene.

[0044] In the resist coating step, a photoresist is coated on the object 1 using a known resist coating device such as a spin coating device or a spray coating device. At this time, in the resist coating step, process conditions such as the rotation speed and amount of drop for spin coating are set or optimized so as to obtain a desired film thickness for the photoresist. In addition, in the resist coating step, prior to coating of the photoresist, a silicating agent that removes hydroxyl groups, such as hexamethyldisilazane (HMDS), may be applied to the surface of the object 1 to make the surface hydrophobic.

[0045] In the resist coating step, after a photoresist is applied onto the object 1 to be processed, the photoresist and the object 1 to be processed are heat-treated to perform pre-baking. In addition, in the resist coating process, process conditions such as the heating temperature and heating time for pre-baking are set or optimized so as to obtain the desired film thickness and surface roughness for the photoresist, or so as to ensure that the circuit pattern 211 is transferred satisfactorily.

[0046] In the exposure step, a part of the photoresist applied on the object 1 is exposed to light using a known exposure device such as a contact exposure device or a reduced projection exposure device including a known light source, optical system, and stage, and a photomask presenting the circuit pattern 211. The projection method related to the optical system may be a known projection method such as a lens method or a mirror method. The exposure device may perform exposure without using a tangible photomask in the form of a maskless exposure. In addition, in the exposure step, process conditions such as exposure time are appropriately set or optimized so that the circuit pattern 211 is suitably transferred.

[0047] The exposure step may employ, as a light source, g-line (436 nm wavelength), i-line (365 nm wavelength), KrF laser (248 nm wavelength), ArF laser (193 nm wavelength), F2 laser (157 nm wavelength), Kr2 laser (146 nm wavelength), Ar2 laser (126 nm wavelength), soft X-ray (EUV: Extreme Ultraviolet, wavelength up to 13.5 nm), electron beam, X-ray, etc. Also, in the exposure step, in the form of immersion lithography, pure water may be inserted between the projection optical system and the object 1 to improve the refractive index.

[0048] The exposure step may include performing post-exposure baking (PEB) by heat treating the photoresist after exposure. In the exposure step, process conditions such as the heating temperature and heating time for the baking are set or optimized so that the circuit pattern 211 is suitably transferred.

[0049] In the developing process, a part of the exposed photoresist is removed (developed) with a developer. In this case, the developing process may select the material of the developer appropriately according to the material of the photoresist. For example, the developer includes tetramethylammonium hydroxide (TMAH). In addition, in the development step, process conditions such as the developer temperature and development time are set or optimized so that the circuit pattern 211 is suitably transferred.

[0050] The development step involves post-baking the developed photoresist. In the developing step, process conditions such as the heating temperature and heating time for the baking are set or optimized so that the circuit pattern 211 is suitably transferred.

[0051] For example, the patterning step S21 may include a hard mask formation step prior to the resist application step, in which a hard mask used as a sacrificial layer is formed on the workpiece 1 based on a known film formation method such as a PVD method or a CVD method.

[0052] In the hard mask forming process, a material exhibiting high hardness and low stress can be used as the hard mask, such as silicon oxides such as SiO2 and TEOS-SiO2, silicon nitrides such as SiN and Si3N4, silicon oxynitrides such as SiON, boron nitrides such as BN, titanium nitrides such as TiN, and mixtures thereof. Note that the hard mask may be appropriately doped with an element such as B.

[0053] In the patterning step S21, a hard mask and a photoresist may be deposited in this order, or a hard mask, an anti-reflective film such as a carbon film, and a photoresist may be deposited in this order, or a film having a multi-layer structure may be deposited.

[0054] The patterning step S21 may be configured to deposit only a photoresist on the object 1 to be processed, and to transfer the circuit pattern 211 using the photoresist as a hard mask having heat resistance, etching resistance, and ion blocking ability.

[0055] The patterning step S21 may transfer the circuit pattern 211 onto the target object 1 in the form of nanoimprinting, for example, by using a mold containing a SiO 2 material.

[0056] The line width of the circuit pattern 211 formed in one embodiment of the present invention is preferably 10 μm or less, more preferably 5.0 μm or less, more preferably 2.0 μm or less, more preferably 1.0 μm or less, even more preferably 0.5 μm or less, even more preferably 0.2 μm or less, even more preferably 0.1 μm or less, even more preferably 50 nm or less, even more preferably 20 nm or less, even more preferably 10 nm or less. Also, the line width is preferably 1.0 nm or more, more preferably 10 nm or more, more preferably 20 nm or more, more preferably 50 nm or more, more preferably 0.1 μm or more, more preferably 0.2 μm or more, more preferably 0.5 μm or more, more preferably 1.0 μm or more, even more preferably 2.0 μm or more, even more preferably 5.0 μm or more.

[0057] In the device formation process S2, after the patterning process S21, a selective etching process is performed using a photoresist exhibiting the circuit pattern 211 to etch the exposed surface below the photoresist.

[0058] In the selective etching process, the exposed surface of the workpiece 1 is etched so as to exhibit material selectivity. In the description of this specification, "exhibiting material selectivity" refers to, for example, that the etching rates of the photoresist and the SiC single crystal are different from each other.

[0059] In the selective etching step, for example, the exposed surface of the object 1 to be processed is etched by wet etching. At this time, in the selective etching process, process conditions such as an etchant, an etching time, and an etching temperature are set or optimized so as to realize the desired material selectivity, surface orientation dependency, etching rate, etc. Examples of the solution containing the etchant include a TMAH solution, a potassium hydroxide (KOH) solution, a potassium permanganate (KMnO4) solution, and a hydrogen fluoride (HF) solution.

[0060] The selective etching step etches the exposed surfaces on the workpiece 1 by known thermal etching, for example reactive gas etching. At this time, in the selective etching process, process conditions such as an etchant (reactive gas), partial pressure of the reactive gas, heat treatment temperature, etc. are set or optimized to realize desired material selectivity, surface orientation dependency, etching rate, etc. The etchant is, for example, a mixture of H2, HCl, Cl2, O2, CIF3, etc.

[0061] In the selective etching step, for example, the exposed surface of the workpiece 1 is etched by known dry etching such as reactive ion etching (RIE). In the reactive ion etching, plasma is formed by a known method such as ICP or CCP, and known gases such as Ar gas, O2 gas, NF3 gas, PF3 gas, BF3 gas, CF4 gas, CHF3 gas, SF6 gas, and XeF2 are appropriately combined. In addition, in the selective etching process, process conditions such as bias power, gas type, gas partial pressure, and discharge time are set or optimized so as to realize the desired anisotropy, etching rate, and the like. In the selective etching step, anisotropic etching or deep etching may be performed so as to form a three-dimensional shape such as a U-groove or a V-groove on the object 1 to be processed.

[0062] <Doping step S22> As shown in FIG. 3, the device formation process S2 includes a doping process S22 for introducing dopant atoms into the object 1 to be processed so as to form n-type and / or p-type regions or pn junction regions in the object 1 to be processed.

[0063] The doping process S22 includes, for example, an ion implantation process in which dopant ions, which are ionized dopant atoms, are irradiated onto the workpiece 1, and an activation process in which the workpiece 1 irradiated with the dopant ions is heat-treated and activated.

[0064] The ion implantation process includes, for example, a beam extraction process of extracting an ion beam from an ion source containing a dopant element, a mass analysis process of mass-separating desired ion species from among ion species contained in the ion beam, an acceleration process of imparting acceleration energy to the ion beam containing the mass-separated ion species, and a scanning process of scanning the ion beam to which acceleration energy has been imparted and irradiating the workpiece 1. Note that the ion implantation process utilizes the circuit pattern 211, which is a sacrificial layer having ion stopping ability, to irradiate a desired region with dopant ions.

[0065] In the ion implantation process, for example, known dopant elements such as N, P, Al, and B are ionized and irradiated onto the workpiece 1. At this time, N and P elements are added to the SiC single crystal to form an n-type region, and Al and B elements are added to the SiC single crystal to form a p-type region. In addition, elements that form n-type or p-type regions in the SiC single crystal can be appropriately adopted as the dopant ions. In the ion implantation process, non-dopant elements such as C, Si, Cl, and Ar elements can also be ionized and irradiated onto the workpiece 1 in the same manner.

[0066] In the beam extraction step, an ion beam containing dopant ions is extracted from an ion source containing a dopant element disposed in a vacuum chamber so as to obtain a desired mean free path. In addition, the beam extraction step includes, for example, applying an extraction voltage to the ion source to extract the ion beam, and, in addition, in the beam extraction step, ionizing the ion source in a plasma environment to extract the ion beam. The ion source may be a solid material, a gaseous material, a liquid metal ion source (LMIS), or a combination of a solid material and a support gas to create a plasma environment that promotes ionization, the plasma environment being appropriately created based on known methods using a DC or AC power source.

[0067] The mass analysis step analyzes the mass-to-charge ratio (m / z) of the ion beam including the dopant ions extracted by the beam extraction step to separate the desired ion species by mass. For example, the mass analysis step passes the ion beam through a magnetic field while applying a voltage to the ion beam, and adjusts the voltage and / or magnetic field strength to select the m / z corresponding to the ion species. The mass analysis step can be carried out by any known mass analysis method, such as magnetic sector, quadrupole, time-of-flight (TOF), or ion trap type.

[0068] The acceleration step provides acceleration energy to the ion beam including the dopant ions so as to realize a desired ion implantation depth or a desired dopant profile. Note that the acceleration step may be performed after the mass analysis step, or may be performed before or after the mass analysis step.

[0069] In the scanning process, an ion beam containing dopant ions is scanned over at least a part of the surface of the target 1 placed in a vacuum chamber, so that an implantation angle is given to the dopant ions. In addition, the scanning process may evaluate the beam current of the ion beam irradiated to the target by using a Faraday cup or the like. The beam current and beam irradiation time are used to evaluate the dose of the ion beam. In the ion implantation process, the process conditions such as the acceleration energy, implantation angle, dose amount, etc. are set or optimized so as to form a desired dopant profile.

[0070] The ion implantation step may be a co-ion implantation step in which two or more ion species are irradiated. The two or more ion species may be, for example, a plurality of types of dopant ions, or may be a C ion and a dopant ion, and there is no limitation on the combination thereof.

[0071] In the ion implantation process, the dopant ions may be irradiated onto the workpiece 1 multiple times so as to form a desired dopant profile, or the dopant ions may be irradiated onto the workpiece 1 while changing the acceleration energy in multiple stages, or the dopant ions may be irradiated onto the workpiece 1 while heating the workpiece 1. In the ion implantation process, the workpiece 1 may be irradiated with dopant ions so as to form a box profile in which the dopant concentration is constant. Note that the "desired dopant profile" in the description of this specification may vary as appropriate depending on the structure of the SiC semiconductor device to be manufactured.

[0072] In the activation step, the object 1 irradiated with dopant ions is heat-treated in an inert atmosphere such as an Ar atmosphere so as to recover crystal damage caused by the irradiation of the dopant ions and activate the dopant ions. In addition, in the activation step, process conditions such as heating temperature, heating time, partial pressure, etc. are set or optimized so that a desired dopant profile is formed or the activation rate of the dopant ions is increased. In the activation step, for example, a carbon layer or a passivation film such as SiO2 is formed on the surface of the object 1 to prevent carbonization of the surface of the object 1 to be treated.

[0073] The doping step S22 is + and / or n ‐ To form a region, p + and / or p ‐Dopant atoms are introduced into the workpiece 1 to form a region, an n-type or p-type drift region 220, an n-type or p-type well region 221, an n-type or p-type contact region 222, an n-type or p-type body region, an n-type or p-type base region, an n-type or p-type source region, an n-type or p-type collector region, an n-type or p-type field stop region, an n-type or p-type pillar region, an n-type or p-type buffer region, an n-type or p-type recombination promotion region, an n-type or p-type buried region, a halo structure, a shallow junction structure, or a super junction structure. In addition, the doping step S22 introduces dopant atoms into the workpiece 1 to form an n-type or p-type region having a profile as seen in known Si-based electronic devices. In addition, the "regions" included in the n-type regions, drift regions, etc. in the description in this specification can be understood to be the same as the "layers" included in the n-type layers, drift layers, etc.

[0074] The dopant concentration of the n-type or p-type region formed in the doping step S22 is preferably 1.0×10 21 / cm 3 More preferably, it is 1.0×10 20 / cm 3 More preferably, it is 1.0×10 19 / cm 3 More preferably, it is 1.0×10 18 / cm 3 More preferably, it is 1.0×10 17 / cm 3 More preferably, it is 1.0×10 16 / cm 3 The dopant concentration is preferably 1.0×10 15 / cm 3 More preferably, it is 1.0×10 16 / cm 3More preferably, it is 1.0×10 17 / cm 3 More preferably, it is 1.0×10 18 / cm 3 or more, preferably 1.0×10 19 / cm 3 More preferably, it is 1.0×10 20 / cm 3 That's all. It should be noted that the dopant concentration may differ between different regions, such as, for example, the n-type contact region and the drift region.

[0075] In the doping step S22, dopant atoms may be introduced into the workpiece 1 after the patterning step S21 each time SiC epitaxial growth is performed. The SiC epitaxial growth may be performed in the growth step S1, or may be performed by a known film formation method such as a PVD method or a CVD method.

[0076] As shown in FIG. 3, the device formation step S2 may repeat a patterning step S21 and a doping step S22. In addition, the device formation step S2 may repeat the SiC epitaxial growth, the patterning step S21, and the doping step S22 based on a plurality of circuit patterns 211. Furthermore, the device formation step S2 may not include the patterning step S21, but may include the SiC epitaxial growth and doping step S22. In the device formation step S2, the photoresist and / or hard mask presenting the circuit pattern 211 is etched every time the doping step S22 is performed.

[0077] <Insulating film forming step S23> As shown in FIG. 4, the device formation process S2 includes an insulating film formation process S23 for introducing an insulating film 230 into the object to be processed 1. The insulating film 230 functions, for example, as a gate insulating film in a SiC semiconductor device having a FET structure or the like, an interlayer insulating film for element isolation, or a cap layer for adjusting the flat band voltage or the like in the gate electrode 240.

[0078] The EOT (Equivalent Oxide Thickness) of the insulating film 230 formed in the insulating film forming step S23 is preferably 100 nm or less, more preferably 50 nm or less, more preferably 20 nm or less, even more preferably 10 nm or less, even more preferably 5.0 nm or less, and even more preferably 2.0 nm or less. The EOT is preferably 1.0 nm or more, more preferably 2.0 nm or more, more preferably 5.0 nm or more, more preferably 10 nm or more, even more preferably 20 nm or more, and even more preferably 50 nm or more.

[0079] In the insulating film forming step S23, for example, the workpiece 1 is thermally oxidized using a known oxidation furnace and oxidizing species such as dry oxygen (O2) or water vapor (H2O) to form a thermally oxidized SiO2 film. At this time, in the insulating film formation process S23, process conditions such as the oxidation temperature, the oxidation time, and the partial pressure of the oxidizing gas are set or optimized so as to reduce the interface state density at the SiC / SiO2 interface, to reduce the SiC / SiO2 interface roughness, to suppress carbon residue in the thermally oxidized SiO2 film, or to promote the generation of CO gas in the thermal oxidation reaction.

[0080] In the insulating film forming step S23, after the insulating film 230 is formed, a dry process using heat treatment or a plasma environment may be performed in order to reduce the interface state density at the insulating film interface. In the insulating film forming step S23, for example, a nitriding process may be performed after forming the thermally oxidized SiO2 film so as to reduce the interface state density at the SiC / SiO2 interface. The nitriding process may be a heat treatment in a nitric oxide (NO) atmosphere, or may be a process using a plasma environment in which nitric oxide such as NO is excited.

[0081] In the insulating film forming step S23, the insulating film 230 may be formed based on a known film forming method such as a CVD method or ALD (Atomic Layer Deposition). At this time, the insulating film 230 may be configured to include a metal oxide film such as an Al2O3 film or an AlON film in addition to a Si oxide film such as a thermally oxidized SiO2 film.

[0082] <Electrode formation process S24> As shown in FIGS. 4 and 5, the device forming step S2 includes an electrode forming step S24 for forming electrodes on the processing target object 1.

[0083] The electrode formation step S24 forms electrodes on the workpiece 1, such as forming a gate electrode 240, a source electrode 241, a drain electrode 242, a base electrode, an emitter electrode, a collector electrode, an anode electrode, a cathode electrode, an ohmic electrode, or a Schottky electrode.

[0084] In the electrode formation step S24, for example, poly-Si is formed on the processing target 1 by a film formation process based on a known technique such as a CVD method. The poly-Si is processed into a gate electrode 240 adjacent to the insulating film 230 by, for example, a patterning step S21, a doping step S22, and a selective etching step. Note that in the electrode formation step S24, a metal material other than poly-Si can be used as the gate electrode 240 instead of / in addition to poly-Si.

[0085] The electrode formation process S24, for example, involves forming a metal film such as Ni on the workpiece 1 by a PVD method. The metal film is formed as a source electrode 241, which is an ohmic electrode adjacent to the n-type or p-type contact region 222, or a drain electrode 242, by, for example, a patterning process S21, a doping process S22, and a selective etching process.

[0086] In the electrode formation step S24, after forming the metal film, a silicidation reaction may be performed by heat treating the processing target 1. Note that in the electrode formation step S24, a barrier metal such as TiN or TaN may be laminated on electrodes such as the source electrode 241 and the drain electrode 242. In the electrode formation step S24, process conditions such as the heat treatment temperature and heat treatment time in the silicidation reaction are set or optimized so that a Schottky electrode is formed or an ohmic electrode is formed by the dopant segregation effect.

[0087] As shown in FIG. 5, the electrode formation process S24 may be performed after the separation process S3 by forming a metal film such as Ni on the workpiece 1 by a PVD method, and forming a drain electrode 242, which is an ohmic electrode adjacent to the n-type or p-type region, as a back electrode.

[0088] In the device formation step S2, the insulating film 23 or the electrode formed in the insulating film formation step S23 or the electrode formation step S24 may be used as the hard mask.

[0089] In addition, the "CVD method" in the description in this specification refers to known CVD methods such as thermal CVD, PECVD (Plasma-Enhanced CVD), MOCVD (Metal Organic CVD), etc., and can be adopted as a film formation technique for introducing any of the various materials that make up the SiC semiconductor device 12.

[0090] In addition, the "PVD method" in the description in this specification refers to known PVD methods such as vacuum deposition, DC sputtering, RF sputtering, magnetron sputtering, reactive sputtering, and molecular beam epitaxy (MBE), and can be appropriately adopted as a film formation method when introducing any of the various materials that make up the SiC semiconductor device 12.

[0091] The device formation step S2 may, for example, include a selective etching step followed by a doping step S22, an insulating film formation step S23, or an electrode formation step S24 to manufacture a SiC semiconductor device 12 having a trench gate structure.

[0092] In the device formation step S2, at least a part of the insulating film formation step S23 may be performed after the electrode formation step S24.

[0093] In one embodiment of the present invention, depending on the structure of the SiC semiconductor device 12, at least some of the steps included in the device formation process S2 may be performed in any order so as to realize a desired structure of the SiC semiconductor device 12.

[0094] In one embodiment of the present invention, the device formation step S2 may form a wiring region.

[0095] 《Separation process S3》 In the separation step S3, a part of the object 1 to be processed is separated. The separation process S3 can employ a method such as multi-wire saw cutting, which cuts by reciprocating multiple wires, an electric discharge machining method, which cuts by intermittently generating plasma discharges, or a method in which a laser is irradiated to form a layer that serves as the base point for cutting.

[0096] As shown in FIG. 6, the separation step S3 includes a separation layer forming step S31 of forming a separation layer 300 inside the object to be processed 1, and a peeling step S32 of peeling off a part of the object to be processed 1 starting from the separation layer 300.

[0097] <Separation layer formation step S31> In the separation layer formation process S31, a laser having a wavelength that is transparent to the workpiece 1 is irradiated and focused on the workpiece 1 so that the inside of the workpiece 1 is the focal point at a depth corresponding to the thickness of the SiC semiconductor device 12 to be separated from the top surface, thereby forming a separation layer 300. At this time, in the separation layer forming step S31, preferably, the surface of the object to be processed 1 on which the SiC semiconductor device 12 is not formed is irradiated with a laser.

[0098] The separation layer formation process S31 forms a separation layer 300 using a holding means capable of holding the workpiece 1 based on a conventional technique such as an adsorption chuck, a light source 311 capable of irradiating a pulsed laser, and a conventional focusing means 312 such as a lens capable of focusing the laser. In addition, the separation layer forming step S31 employs an infrared laser as the laser, for example. The wavelength of the laser may be a wavelength similar to ultraviolet light or a wavelength similar to visible light, and is not limited thereto. In the separation layer formation step S31, process conditions such as laser wavelength, laser output, laser scanning speed, beam spot diameter, pulse width, and pitch width are set or optimized so that the SiC semiconductor device 12 can be suitably separated from the object 1 to be processed.

[0099] <Peeling step S32> In the peeling step S32, the SiC semiconductor device 12, which is a part of the workpiece 1, is peeled off starting from the separation layer 300. At this time, in the peeling step S32, mechanical vibration is applied to the workpiece 1 by, for example, reciprocating a wire along the separation layer 300 or generating ultrasonic vibration, and the SiC semiconductor device 12 is peeled off from the workpiece 1 starting from the separation layer 300.

[0100] The peeling process S32 utilizes at least a portion of a holding means capable of holding the workpiece 1 based on a conventional technique such as an adsorption chuck, a vibration means formed from piezoelectric ceramics or the like and capable of generating conventional mechanical vibrations including ultrasonic vibrations, and a liquid supply means capable of supplying a liquid such as pure water, to peel off the SiC semiconductor device 12 from the workpiece 1 starting from the separation layer 300.

[0101] The separation step S3 may be performed prior to the separation layer forming step S31 or prior to the peeling step S32, in which a polymer layer serving as a stress generating layer is formed on the object 1 to be processed. At this time, the peeling step S32 may induce crack propagation in the separation layer 300 by cooling the target object 1 including the polymer layer, and peel the SiC semiconductor device 12 from the target object 1 starting from the separation layer 300. At this time, in the peeling step S32, process conditions such as the composition and film thickness of the polymer layer, the cooling temperature, the cooling rate, and the cooling time are set or optimized so that the SiC semiconductor device 12 can be suitably separated from the object to be processed 1. In this case, in the separation step S3, the polymer layer is preferably formed on the surface of the target object 1 on which the SiC semiconductor device 12 is not formed, so as to suppress the generation of stress in the SiC semiconductor device 12.

[0102] The separation step S3 can employ a known technique. In addition, the separation step S3 can employ at least a portion of the devices and methods described in patent documents such as JP 2013-49161 A, JP 2018-207034 A, JP 2017-500725 A, and JP 2017-526161 A. In addition, the separation process S3 can adopt at least some of the devices and methods described in patent documents such as JP-T-2017-526161, JP-T-2017-500725, JP-A-2018-152582, JP-T-2019-500220, and JP-T-2019-511122.

[0103] <Etching process S4> 7, the etching step S4 etches the workpiece 1 to form a flattened bunching-free surface having a reduced terrace length W3. The mechanism of the etching step S4 will be described later.

[0104] In the etching step S4, for example, the object 1 separated in the separation step S3 is heat-treated to etch the surface layer including the separation layer 300 remaining on the object 1. The separation layer 300 can be understood to include crystal dislocations 301 and damaged regions 302. At this time, the surface of the growth layer 10 can be terminated at a step exhibiting the height of a full unit in the SiC single crystal. The separation layer 300 can also be interpreted as a strained layer or a damaged layer.

[0105] The etching step S4 also includes a strained layer removal step S41 in which the object 1 is placed in a semi-closed space having an atomic ratio Si / C of 1 or less, heated, and etched. The etching step S4 also includes a bunching decomposition step S42 in which the object 1 is placed in a semi-closed space having an atomic ratio Si / C of more than 1, heated, and etched.

[0106] In the strained layer removal step S41, the separation layer 300 is etched, and the process target object 1 is etched so that the bunched surface is exposed.

[0107] In the bunching decomposition step S42, the workpiece 1 is etched to decompose the MSBs on the surface of the workpiece 1 so as to form a flattened bunching-free surface. At this time, the surface is terminated at a step having the height of a full unit in the SiC single crystal.

[0108] As shown in FIG. 8, in one embodiment of the present invention, a plurality of steps including at least a growth step S1, a device formation step S2, and a separation step S3 may be repeated in a circular manner. In addition, in one embodiment of the present invention, the growth step S1, the device formation step S2, the separation step S3, and the etching step S4 may be repeated to form a circle. In one embodiment of the present invention, at least a part of each step of the device formation step S2 may be performed after the separation step S3.

[0109] An embodiment of the present invention can fabricate SiC semiconductor devices 12 having known device structures including, by way of example, Schottky barrier diodes (SBDs), bipolar junction transistors (BJTs), FETs, insulated gate bipolar transistors (IGBTs), and combinations thereof.

[0110] As shown in FIG. 9, one embodiment of the present invention can manufacture a SiC semiconductor device 12 including an n-type or p-type substrate 111 adjacent to an electrode surface such as a drain electrode, an anode electrode, or a collector electrode. As shown in FIG. 9(a), one embodiment of the present invention can manufacture a SiC semiconductor device 12 having a FET structure including an n-type or p-type substrate 111, an n-type or p-type drift region 220, an n-type or p-type well region 221, an n-type or p-type contact region 222, an insulating film 230, a gate electrode 240, a source electrode 241, and a drain electrode 242. Moreover, as shown in FIG. 9(b), one embodiment of the present invention can manufacture a SiC semiconductor device 12 having an SBD structure including an n-type or p-type substrate 111, a low concentration region 226, an anode electrode 244, and a cathode electrode 245. The thickness of the n-type or p-type substrate 111 is not limited within the range of the thickness of the growth layer 10. The n-type or p-type substrate 111 contributes to the realization of an ohmic electrode, for example.

[0111] An embodiment of the present invention can manufacture a SiC semiconductor device 12 having a planar gate type structure. In this case, the SiC semiconductor device 12 may have a known device structure such as a FET structure or an IGBT structure.

[0112] In one embodiment of the present invention, a SiC semiconductor device 12 having a trench gate structure can be manufactured so that the JFET resistance during device operation is reduced. In this case, the SiC semiconductor device 12 may have a known device structure such as a FET structure or an IGBT structure.

[0113] According to an embodiment of the present invention, a known SiC semiconductor device 12 having a superjunction structure including an n-type or p-type pillar region can be manufactured so that the drift resistance during device operation is reduced. In this case, the SiC semiconductor device 12 may have a known device structure such as a FET structure or an IGBT structure.

[0114] An embodiment of the present invention can fabricate a SiC semiconductor device 12 that includes buried n-type or p-type regions such that electric field crowding effects are mitigated during device operation. In addition, the n-type or p-type buried region in the SiC semiconductor device 12 may be, for example, located below the gate electrode 240 along the film thickness direction, located below the source electrode 241 along the film thickness direction, or located so as to form a guard ring aligned with the n-type or p-type well region along a direction perpendicular to the film thickness direction.

[0115] One embodiment of the present invention is a basal plane dislocation density (BPD density) of <100 / cm 2 BPD density <10 / cm, including the growth layer 2 or <1.0 / cm 2 As described above, the growth layer is at least a part of the growth layer 10. The growth layer refers to at least a part of the SiC structure constituting the SiC semiconductor device 12, which includes the n-type or p-type region. The growth layer may also refer to an n-type or p-type substrate 111, for example. The growth layer is, for example, 1.0×10 17 / cm 3 That's it, 2.0 x 10 17 / cm 3 That's it, 5.0 x 10 17 / cm 3 That's it, 1.0 x 10 18 / cm 3 That's it, 2.0 x 10 18 / cm 3 or more, or 5.0 x 10 18 / cm 3 n having a dopant concentration of + Or p + Refers to the area.

[0116] The cell pitch of the SiC semiconductor device 12 manufactured in one embodiment of the present invention is preferably 10 μm or less, more preferably 5.0 μm or less, more preferably 2.0 μm or less, more preferably 1.0 μm or less, even more preferably 0.5 μm or less, even more preferably 0.2 μm or less, even more preferably 0.1 μm or less, even more preferably 50 nm or less, even more preferably 20 nm or less, even more preferably 10 nm or less. Also, the cell pitch is preferably 1.0 nm or more, more preferably 10 nm or more, more preferably 20 nm or more, more preferably 50 nm or more, more preferably 0.1 μm or more, more preferably 0.2 μm or more, more preferably 0.5 μm or more, more preferably 1.0 μm or more, even more preferably 2.0 μm or more, even more preferably 5.0 μm or more.

[0117] Mechanism of Growth Step S1 and Etching Step S4 In the following, the present specification will explain the source transport mechanism related to the heat treatment step, which is the growth step S1 or the etching step S4.

[0118] In one embodiment of the present invention, the heat treatment step heat-treats the object to be processed 1 and the SiC raw material 4 so that a temperature difference is generated between the object to be processed 1 and the SiC raw material 4. In the heat treatment step as the growth step S1, the object to be treated 1 is placed on the low temperature side, whereby crystal growth is caused in the object to be treated 1, and a growth layer 10 is formed on the surface of the object to be treated 1. In the heat treatment step as the etching step S4, the object 1 is placed on a high temperature side, whereby the object 1 is etched, and for example, the separation layer 300 is removed.

[0119] As shown in FIG. 10, the object to be processed 1 is placed on the low temperature side, so that the formation of a growth layer 10 on the back surface 1a and the etching of the SiC raw material 4 (main surface 4a) are carried out simultaneously.

[0120] In each of the growth step S1 and the etching step S4, the object to be processed 1 and the SiC raw material 4 are heat-treated in a semi-closed space in an atmosphere containing Si elements and C elements. In addition, the term "semi-closed space" in the description of this specification refers to a space in which it is possible to evacuate the inside of the space, but which is capable of containing at least a portion of the steam generated inside the space.

[0121] As shown in FIG. 11, in the target object 1 and the SiC source material 4, source material transport based on the following reactions 1) to 5) is continuously performed, and a growth layer 10 is formed.

[0122] 1) SiC(s) → Si(v) + C(s) 2) 2C(s)+Si(v)→SiC2(v) 3) C(s)+2Si(v) → Si2C(v) 4) Si(v) + SiC2(v) → 2SiC(s) 5) Si2C(v) → Si(v) + SiC(s)

[0123] Explanation of 1): When the surface of the SiC raw material 4 is thermally decomposed, Si atoms (Si(v)) are released from the surface of the SiC raw material 4. Explanation of 2) and 3): When Si atoms (Si(v)) are released, the C atoms (C(s)) remaining on the surface of the SiC raw material 4 react with the Si vapor (Si(v)) in the raw material transport space to become Si2C or SiC2, etc., and sublime into the raw material transport space. Explanation of 4) and 5): The sublimated Si2C or SiC2, etc., reaches and diffuses onto the terraces on the rear surface 1a of the workpiece 1 due to the temperature gradient, and when it reaches the steps, it takes over the polytype of the rear surface 1a, and a growth layer 10 is formed while exhibiting a step-flow growth aspect.

[0124] The growth process S1 includes a Si atom sublimation process in which Si atoms are thermally sublimated from the SiC raw material 4, and a C atom sublimation process in which C atoms remaining on the main surface 4a of the SiC raw material 4 are sublimated by bonding with Si atoms in the raw material transport space.

[0125] In the growth step S1, a growth layer 10 is formed on the rear surface 1a of the object 1 based on the step flow growth. Each step included in the growth step S1 is performed sequentially. In addition, the growth step S1 is understood to be a step based on PVT (physical vapor transport) since the transported Si2C or SiC2, etc. become supersaturated and condense to form the growth layer 10. Moreover, with such a configuration, the growth step S1 can suppress the formation of MSBs on the surface of the object 1 to obtain a planarized SiC surface with a reduced terrace length.

[0126] The etching step S4 includes a Si atom sublimation step of thermally sublimating Si atoms from the surface of the workpiece 1, and a C atom sublimation step of sublimating C atoms remaining on the surface of the workpiece 1 by bonding with Si atoms in the raw material transport space, and etches the surface of the workpiece 1. With this configuration, the etching step S4 decomposes the MSB on the surface of the workpiece 1, and a planarized SiC surface exhibiting a reduced terrace length can be obtained.

[0127] The mechanism for each of the growth step S1 and the etching step S4 can be understood as the transport of raw materials containing Si and C elements. It can be understood that the driving force for the transport of the raw material is the vapor pressure difference between the workpiece 1 and the SiC raw material 4 caused by the formed temperature gradient. Therefore, it can be understood that not only the temperature difference on the respective surfaces of the workpiece 1 and the SiC raw material 4, but also the chemical potential difference caused by the crystal structure or the like between the workpiece 1 and the SiC raw material 4 can be the driving force for the transport of the raw material.

[0128] In each of the growing step S1 and the etching step S4, the SiC raw material 4 may be a SiC ingot produced by a sublimation method or the like, a SiC wafer sliced ​​into a disk shape from the SiC ingot, or polycrystalline SiC. The SiC raw material 4 may also be a processed product such as a sintered body containing polycrystalline SiC. In each of the growing step S1 and the etching step S4, the SiC material forming the semi-closed space and the SiC material exposed within the semi-closed space can become the SiC raw material 4.

[0129] In the growth step S1, the raw material is transported such that the dopant concentration of the growth layer 10 can be adjusted by supplying a dopant gas into the semi-closed space by a dopant gas supplying means. It can be seen that if no dopant gas is supplied, the growing layer 10 inherits the dopant concentration within the semi-closed space.

[0130] The raw material transport in each of the growth step S1 and the etching step S4 is preferably performed in an environment having a gas phase species containing a Si element and a gas phase species containing a C element. Furthermore, the raw material transport in each of the growth step S1 and the etching step S4 is performed under a SiC--Si or SiC--C equilibrium vapor pressure environment.

[0131] In the description of this specification, the term "SiC-Si vapor pressure environment" refers to a vapor pressure environment in which SiC (solid) and Si (liquid phase) are in phase equilibrium via the gas phase. The SiC-Si equilibrium vapor pressure environment is formed by heat treating a semi-closed space in which the atomic ratio Si / C exceeds 1. In the description of this specification, the term "SiC-C equilibrium vapor pressure environment" refers to a vapor pressure environment in which SiC (solid phase) and C (solid phase) are in phase equilibrium via the gas phase. The SiC-C equilibrium vapor pressure environment is formed by heat treating a semi-closed space in which the atomic ratio Si / C is 1 or less.

[0132] The heat treatment temperature in each of the growth step S1 and the etching step S4 is preferably 1400°C or higher, more preferably 1500°C or higher, more preferably 1600°C or higher, more preferably 1700°C or higher, more preferably 1800°C or higher, even more preferably 1900°C or higher, even more preferably 2000°C or higher, even more preferably 2100°C or higher, and even more preferably 2200°C or higher. Furthermore, the heat treatment temperature is preferably 2300°C or less, more preferably 2200°C or less, more preferably 2100°C or less, more preferably 2000°C or less, more preferably 1900°C or less, even more preferably 1800°C or less, even more preferably 1700°C or less, even more preferably 1600°C or less, and even more preferably 1500°C or less. The growth rate and etching rate in the growth step S1 and the etching step S4, respectively, are determined by the heat treatment temperature.

[0133] The temperature gradient between the object 1 and the SiC raw material 4 in each of the growth step S1 and the etching step S4 is preferably 0.1° C. / mm or more, more preferably 0.2° C. / mm or more, more preferably 0.5° C. / mm or more, even more preferably 1.0° C. / mm or more, and even more preferably 2.0° C. / mm or more. The temperature gradient is preferably 5.0° C. / mm or less, more preferably 2.0° C. / mm or less, more preferably 2.0° C. / mm or less, more preferably 1.0° C. / mm or less, even more preferably 0.5° C. / mm or less, and even more preferably 0.2° C. / mm or less. The temperature gradient may be uniform or may have a distribution.

[0134] <Apparatuses for the Growth Step S1 and the Etching Step S4> In the following, the present specification will provide a detailed description of the apparatuses used in the growth step S1 and the etching step S4. Note that components that are basically the same as those in the previous manufacturing method will be given the same reference numerals and their description will be simplified.

[0135] As shown in FIG. 12, a manufacturing apparatus for the method of manufacturing a SiC semiconductor device includes a main body container 141, a high melting point container 142, and a heating furnace 143.

[0136] Main body container 141 is made of a material containing polycrystalline SiC, for example. Therefore, at least a part of main body container 141 can be a transport source (SiC raw material 4) in the raw material transport.

[0137] The environment inside the heated main body container 141 is preferably, for example, a vapor pressure environment of a mixture of a gaseous species containing an Si element and a gaseous species containing an C element. Examples of the gaseous species containing the Si element include Si, Si2, Si3, Si2C, SiC2, and SiC. Moreover, examples of gas phase species containing C element include Si2C, SiC2, SiC, C, and the like.

[0138] The dopant and dopant concentration of the main vessel 141 can be selected according to the dopant and dopant concentration of the growth layer 10 desired to be formed.

[0139] Furthermore, any structure can be adopted so long as it generates vapor pressure of a gaseous species containing an Si element and a gaseous species containing an C element in the internal space during heat treatment of main container 141. Examples include a structure in which SiC polycrystal is exposed on a part of the inner surface, and a structure in which SiC polycrystal is separately installed inside main container 141.

[0140] The main container 141 is provided with a mounting fixture 141a in which the object to be treated 1 can be mounted. The main container 141 is also a fitting container provided with an upper container 141c and a lower container 141b that can be fitted together. A minute gap is formed at the fitting portion between the upper container 141c and the lower container 141b, and the main container 141 is configured so that the inside of the main container 141 can be evacuated (vacuumed) through this gap.

[0141] <Si vapor supply source> Main container 141 has a Si vapor supply source. The Si vapor supply source is used for the purpose of adjusting the atomic ratio Si / C in the semi-closed space in main container 141 to exceed 1. Examples of the Si vapor supply source include solid Si (Si pellets such as Si pieces or Si powder) and Si compounds.

[0142] For example, in the case where main body container 141 is entirely made of SiC polycrystal as in one embodiment of the present invention, by installing a Si vapor supply source, the atomic ratio Si / C in main body container 141 exceeds 1. Specifically, in the case where object to be processed 1 and SiC raw material 4 satisfying a stoichiometric ratio of 1:1, and a Si vapor supply source are installed in main body container 141 made of SiC polycrystal satisfying a stoichiometric ratio of 1:1, the atomic ratio Si / C in main body container 141 exceeds 1.

[0143] The SiC-Si equilibrium vapor pressure environment according to one embodiment of the present invention is formed by heating a semi-closed space in which the atomic ratio Si / C exceeds 1. Also, the SiC-C equilibrium vapor pressure environment according to one embodiment of the present invention is formed by heating a semi-closed space in which the atomic ratio Si / C is 1 or less. The main body container 141 according to one embodiment of the present invention may be configured to appropriately accommodate predetermined members so as to create a SiC-Si equilibrium vapor pressure environment or a SiC-C equilibrium vapor pressure environment.

[0144] The heating furnace 143 is configured to heat so as to form a temperature gradient in which the temperature decreases / increases from the upper vessel 141c to the lower vessel 141b of the main vessel 141. As a result, a temperature gradient is formed in the thickness direction of the object 1 to be processed.

[0145] As shown in FIG. 12, the heating furnace 143 is equipped with a main heating chamber 143c capable of heating the workpiece 1 etc. to a temperature of 1000°C or higher and 2300°C or lower, a preliminary chamber 143a capable of preheating the workpiece to a temperature of 500°C or higher, a high-melting point container 142 capable of accommodating the main container 141, and a moving means 143b (moving stage) capable of moving this high-melting point container 142 from the preliminary chamber 143a to the main heating chamber 143c.

[0146] The main heating chamber 143c is formed in a regular hexagon in a planar cross-sectional view, and the high melting point container 142 is placed inside the main heating chamber 143c. A heater 143d (mesh heater) is provided inside the main heating chamber 143c. In addition, a multi-layer heat reflecting metal plate is fixed to the side walls and ceiling of the main heating chamber 143c (not shown). The multi-layer heat reflecting metal plate is configured to reflect heat from the heater 143d toward approximately the center of the main heating chamber 143c.

[0147] The heater 143d is installed in the main heating chamber 143c so as to surround the high melting point container 142 in which the object to be treated is accommodated. At this time, a multi-layer heat reflecting metal plate is installed on the outside of the heater 143d, so that the temperature can be raised in the range of 1000°C to 2300°C.

[0148] For example, a resistance heating type heater or a high-frequency induction heating type heater can be used as the heater 143d.

[0149] The heater 143d may be configured to form a temperature gradient in the high melting point container 142. For example, the heater 143d may be configured so that many heaters are installed on the upper side (or the lower side). The heater 143d may be configured so that the width increases toward the upper side (or the lower side). Alternatively, the heater 143d may be configured so that the power supplied to it can be increased toward the upper side (or the lower side).

[0150] The main heating chamber 143c is connected to a vacuum forming valve 143f for evacuating the inside of the main heating chamber 143c, an inert gas injection valve 143e for introducing an inert gas into the main heating chamber 143c, and a vacuum gauge 143g for measuring the degree of vacuum inside the main heating chamber 143c.

[0151] The vacuum forming valve 143f is connected to a vacuum pump (not shown) that evacuates the inside of the main heating chamber 143c to create a vacuum. By using the vacuum forming valve 143f and the vacuum pump, the degree of vacuum in the main heating chamber 143c is preferably 10 Pa or less, more preferably 1.0 Pa or less, and most preferably 10 ‐3 The pressure can be adjusted to be equal to or less than Pa. An example of the vacuum pump is a turbo molecular pump.

[0152] The inert gas injection valve 143e is connected to an inert gas supply source (not shown). The inert gas is introduced into the heating chamber 143c by the inert gas injection valve 143e and the inert gas supply source. ‐5 ~10 4 The inert gas can be introduced in the range of Pa. As the inert gas, Ar or the like can be selected.

[0153] The inert gas injection valve 143e is a dopant gas supplying means capable of supplying a dopant gas into the main body container 141. That is, by selecting a dopant gas (for example, N2 or the like) as the inert gas, the dopant concentration of the growth layer 10 can be increased.

[0154] The preliminary chamber 143a is connected to the main heating chamber 143c, and is configured to be able to move the high melting point container 142 by the moving means 143b. In this embodiment, the preliminary chamber 143a is configured to be able to be heated by residual heat of the heater 143d of the main heating chamber 143c. For example, when the main heating chamber 143c is heated to 2000°C, the preliminary chamber 143a is heated to about 1000°C, and degassing of the workpiece (the workpiece 1, the main container 141, the high melting point container 142, etc.) can be performed.

[0155] The moving means 143b is configured to be capable of placing the high melting point container 142 thereon and moving between the main heating chamber 143c and the preliminary chamber 143a.

[0156] The transfer between the main heating chamber 143c and the preliminary chamber 143a by the moving means 143b can be completed in as little as one minute, so that the temperature can be increased and decreased at a rate of 1.0 to 1000°C / min. This allows for rapid temperature increase and decrease, making it possible to observe a surface shape that does not have a low-temperature growth history during the temperature increase and decrease. In addition, in FIG. 12, the preliminary chamber 143a is disposed below the main heating chamber 143c, but the preliminary chamber 143a is not limited to this and may be disposed in any direction.

[0157] The moving means 143b according to this embodiment is a moving stage on which the high melting point container 142 is placed. The contact portion between this moving stage and the high melting point container 142 serves as a heat transfer path. This allows a temperature gradient to be formed in the high melting point container 142 such that the contact portion between the moving stage and the high melting point container 142 is the low temperature side.

[0158] In the heating furnace 143 of this embodiment, the bottom of the high melting point container 142 is in contact with the moving stage, so that a temperature gradient is provided such that the temperature decreases from the upper container 142b of the high melting point container 142 toward the lower container 142a.

[0159] The direction of the temperature gradient can be set to any direction by changing the position of the contact part between the moving stage and the high melting point container 142. For example, if a hanging type moving stage is used and the contact part is provided on the ceiling of the high melting point container 142, heat escapes upward. Therefore, the temperature gradient is provided such that the temperature increases from the upper container 142b to the lower container 142a of the high melting point container 142. Note that this temperature gradient is preferably formed along the thickness direction of the workpiece 1 and the SiC raw material 4. Also, as described above, the temperature gradient may be formed by the configuration of the heater 143d.

[0160] The vapor pressure environment of the gaseous species containing Si element in the heating furnace 143 according to this embodiment is formed by using the high melting point container 142 and a Si vapor supply material. For example, any method capable of forming an environment of the vapor pressure of the gaseous species containing Si element around the main body container 141 can be adopted in one embodiment of the present invention.

[0161] High melting point container 142 is preferably configured to contain a high melting point material having a melting point equal to or higher than the melting point of the material that constitutes main container 141 .

[0162] Examples of high-melting point container 142 include general-purpose heat-resistant material C, high-melting point metals W, Re, Os, Ta, Mo, carbides Ta9C8, HfC, TaC, NbC, ZrC, Ta2C, TiC, WC, MoC, nitrides HfN, TaN, BN, Ta2N, ZrN, TiN, borides HfB2, TaB2, ZrB2, NB2, TiB2, polycrystalline SiC, etc.

[0163] 12, like the main container 141, the high melting point container 142 is a fitting container including an upper container 142b and a lower container 142a that can fit together, and is configured to be able to accommodate the main container 141. A minute gap 43 is formed at the fitting portion between the upper container 142b and the lower container 142a, and it is configured so that the inside of the high melting point container 142 can be evacuated (vacuumed) through this gap 43.

[0164] The high-melting-point vessel 142 contains a Si vapor supplying material capable of supplying a vapor pressure of a gas phase species containing elemental Si into the high-melting-point vessel 142 .

[0165] The Si vapor supply material may be any material that generates Si vapor in the high melting point container 142 during heat treatment, and examples thereof include solid Si (Si pellets such as Si pieces or Si powder) and Si compounds. Also, the Si vapor supply material is, for example, a thin film that coats the inner wall of the high melting point vessel 142 .

[0166] When the high melting point vessel 142 is a metal compound such as TaC, the Si vapor supply material is, for example, a silicide material of metal atoms and Si atoms that constitute the high melting point vessel 142 .

[0167] High-melting-point container 142, by having a Si vapor supply material inside, can maintain a vapor pressure environment of the gas phase species containing Si element inside main container 141. This can be understood as being because the vapor pressure of the gas phase species containing Si element inside main container 141 and the vapor pressure of the gas phase species containing Si element outside main container 141 are balanced.

[0168] This specification will explain the effects of the present invention with reference to Reference Examples 1 to 3. 《Reference example 1》 Under the following conditions, the SiC single crystal substrate E10 is housed in a main body container 141, and the main body container 141 is housed in a high melting point container 142.

[0169] <SiC single crystal substrate E10> Polymorphism: 4H-SiC Board size: width (10mm), length (10mm), thickness (0.3mm) Off direction and off angle: 4° off in the <11-20> direction Growth plane: (0001) plane MSB: None Separation or distortion layer: None

[0170] Material: SiC polycrystalline Container size: diameter (60 mm), height (4.0 mm) Distance between SiC single crystal substrate E10 and SiC material: 2.0 mm Atomic ratio inside the container: Si / C: 1 or less

[0171] Material: TaC Container size: diameter (160mm), height (60mm) Si vapor supply material (Si compound): TaSi2

[0172] The SiC single crystal substrate E10 placed under the above conditions was heat-treated under the following conditions. Heating temperature: 1700℃ Heating time: 300min Temperature gradient: 1.0℃ / mm Growth rate: 5.0nm / min Vacuum degree of main heating chamber 143c: 10 ‐5 Pa

[0173] FIG. 13 is an explanatory diagram of a method for determining the conversion rate of BPDs into other defects / dislocations (TEDs, etc.) in the growth layer E11.

[0174] 13(a) shows the state where the growth layer E11 is grown by a heating process. In this heating process, the BPDs present in the SiC single crystal substrate E10 are converted to TEDs with a certain probability. Therefore, unless 100% is converted, TEDs and BPDs will be mixed on the surface of the growth layer E11.

[0175] Fig. 13(b) shows the state where defects in the growth layer E11 were confirmed using the KOH dissolution etching method. This KOH dissolution etching method is a method in which the SiC single crystal substrate E10 is immersed in molten salt (KOH, etc.) heated to about 500°C, etch pits are formed at dislocations and defects, and the type of dislocation is identified based on the size and shape of the etch pits. By this method, the number of BPDs present on the surface of the growth layer E11 is evaluated.

[0176] 13(c) shows the state in which the growth layer E11 is removed after KOH dissolution etching. In this method, the growth layer E11 is removed by thermal etching after planarization to the depth of the etch pits by mechanical polishing or CMP, thereby exposing the surface of the SiC single crystal substrate E10.

[0177] 13(d) shows the state in which defects in the SiC single crystal substrate E10 from which the growth layer E11 has been removed are confirmed using a KOH dissolution etching method. By this method, the number of BPDs present on the surface of the SiC single crystal substrate E10 is evaluated.

[0178] By comparing the number of BPDs present on the surface of the growth layer E11 (see FIG. 13(b)) with the number of BPDs present on the surface of the SiC single crystal substrate E10 (see FIG. 13(d)) using the sequence shown in FIG. 13, the BPD conversion rate of BPDs converted to other defects and dislocations by heat treatment can be obtained.

[0179] The number of BPDs present on the surface of the growth layer E11 in Reference Example 1 was approximately 0 / cm 2 The number of BPDs present on the surface of the SiC single crystal substrate E10 is 1000 / cm 2 In other words, it can be understood that BPDs are reduced or eliminated by placing the SiC single crystal substrate E10, which does not have MSB on its surface, in a semi-closed space with an atomic ratio of Si / C of 1 or less and heating it.

[0180] In reference example 1, a SiC-C equilibrium vapor pressure environment is formed within main container 141 so that the atomic ratio Si / C within main container 141 is 1 or less, and it can be understood that BPDs can also be reduced or eliminated in growth process S1.

[0181] 《Reference example 2》 Under the following conditions, the SiC single crystal substrate E10 was housed in a main container 141, and the main container 141 was further housed in a high melting point container 142.

[0182] <SiC single crystal substrate E10> Polymorphism: 4H-SiC Board size: width (10mm), length (10mm), thickness (0.3mm) Off direction and off angle: 4° off in the <11-20> direction Growth plane: (0001) plane MSB: Yes

[0183] Material: SiC polycrystalline Container size: diameter (60 mm), height (4.0 mm) Distance between SiC single crystal substrate E10 and SiC material: 2.0 mm Silicon vapor source: Silicon chip The atomic ratio of Si / C in the container exceeds 1.

[0184] By accommodating a Si piece together with a SiC single crystal substrate in main body container 141, the atomic ratio Si / C in the container exceeds 1.

[0185] Material: TaC Container size: diameter 160mm x height 60mm Si vapor supply material (Si compound): TaSi2

[0186] The SiC single crystal substrate E10 placed under the above conditions was heat-treated under the following conditions. Heating temperature: 1800℃ Heating time: 60min Temperature gradient: 1.0℃ / mm Growth rate: 68nm / min Vacuum degree of main heating chamber 143c: 10 ‐5 Pa

[0187] Fig. 14 is an SEM image of the surface of the SiC single crystal substrate E10 before the growth of the growth layer E11. Fig. 14(a) is an SEM image observed at a magnification of x1000, and Fig. 14(b) is an SEM image observed at a magnification of x100,000. It can be seen that MSBs are formed on the surface of the SiC single crystal substrate E10 before the growth of the growth layer E11, and steps with a height of 3.0 nm or more are arranged with an average terrace width of 42 nm. The step height was measured by AFM.

[0188] Fig. 15 shows SEM images of the surface of the SiC single crystal substrate E10 after the growth of the growth layer E11. Fig. 15(a) is an SEM image observed at a magnification of ×1000, and Fig. 15(b) is an SEM image observed at a magnification of ×100,000. It can be seen that no MSB is formed on the surface of the growth layer E11 of Reference Example 2, and steps of 1.0 nm (full unit cell) are regularly arranged with a terrace width of 14 nm. The step height was measured by AFM.

[0189] Therefore, it can be understood that by placing a SiC single crystal substrate E10 having MSB on its surface in a quasi-closed space with an atomic ratio Si / C exceeding 1 and heating it, a growth layer E11 in which the MSB is decomposed is formed.

[0190] In Reference Example 2, since the Si vapor supply source is installed so that the atomic ratio Si / C in main body container 141 exceeds 1, a SiC-Si equilibrium vapor pressure environment is formed in main body container 141. Therefore, it can be understood that the MSB on the surface of the SiC single crystal substrate can be decomposed even in growth step S1.

[0191] 《Reference example 3》 16 is a graph showing the relationship between the heating temperature and the growth rate when grown by the manufacturing method of the SiC single crystal substrate according to the present invention. The horizontal axis of this graph is the reciprocal of the temperature, and the vertical axis of this graph is the logarithmic growth rate. The result of placing the SiC single crystal substrate E10 in a space (inside the main body container 141) where the atomic ratio Si / C exceeds 1 and growing the growth layer E11 on the SiC single crystal substrate E10 is shown by a circle. Also, the result of placing the SiC single crystal substrate E10 in a space (inside the main body container 141) where the atomic ratio Si / C is 1 or less and growing the growth layer E11 on the SiC single crystal substrate E10 is shown by a cross.

[0192] In addition, the graph in Figure 16 shows the results of thermodynamic calculations of SiC substrate growth in a SiC-Si equilibrium vapor pressure environment using a dashed line (Arrhenius plot), and the results of thermodynamic calculations of SiC substrate growth in a SiC-C equilibrium vapor pressure environment using a two-dot chain line (Arrhenius plot).

[0193] In this method, under conditions where the vapor pressure environment between the SiC raw material and the SiC substrate is a SiC-C equilibrium vapor pressure environment or a SiC-C equilibrium vapor pressure environment, the SiC single crystal substrate E10 is grown using a chemical potential difference or a temperature gradient as the growth driving force. An example of this chemical potential difference is the partial pressure difference between the gas phase species generated on the surfaces of the SiC polycrystal and the SiC single crystal.

[0194] Here, when the growth amount is the partial pressure difference between the vapor generated from the SiC raw material (transport source) and the SiC substrate (transport destination), the SiC growth rate can be calculated by the following equation 1.

[0195]

number

[0196] Here, T is the temperature of the SiC raw material side, m i is a gas phase species (Si x C y ) is the molecular weight of the molecule, and k is the Boltzmann constant. 輸送元i -P 輸送先i is the amount of SiC deposited when the source gas becomes supersaturated, and the source gas is assumed to be SiC, Si2C, or SiC2.

[0197] Therefore, the broken line is the result of thermodynamic calculation when growing a SiC single crystal using a SiC polycrystal as a raw material in a vapor pressure environment when SiC (solid) and Si (liquid phase) are in phase equilibrium via the gas phase. Specifically, the result was obtained by thermodynamic calculation using Equation 1 under the following conditions (i) to (iv). (i) A constant volume SiC-Si equilibrium vapor pressure environment (ii) The growth driving force is the temperature gradient in the main vessel 141 and the vapor pressure difference (chemical potential difference) between the SiC polycrystal and the SiC single crystal. (iii) The raw gas is SiC, Si2C, or SiC2. (iv) The adsorption coefficient of the raw material adsorbed to the steps of the SiC single crystal substrate E10 is 0.001.

[0198] The two-dot chain line is the result of a thermodynamic calculation when a SiC single crystal is grown using a SiC polycrystal as a raw material in a vapor pressure environment when SiC (solid phase) and C (solid phase) are in phase equilibrium via the gas phase. Specifically, the result was obtained by thermodynamic calculation using Equation 1 under the following conditions (i) to (iv). (i) A constant volume SiC-C equilibrium vapor pressure environment (ii) The growth driving force is the temperature gradient in the main vessel 141 and the vapor pressure difference (chemical potential difference) between the SiC polycrystal and the SiC single crystal. (iii) The raw gas is SiC, Si2C, or SiC2. (iv) The adsorption coefficient of the raw material adsorbed to the steps of the SiC single crystal substrate E10 is 0.001. The data for each chemical species used in the thermodynamic calculations were taken from the JANAF Thermochemical Tables.

[0199] 16, it can be understood that the result (marked with a circle) of growing a growth layer E11 on the SiC single crystal substrate E10 by placing the SiC single crystal substrate E10 in a space (inside the main body container 141) where the atomic ratio Si / C exceeds 1 matches the trend of the thermodynamic calculation result of SiC growth in a SiC-Si equilibrium vapor pressure environment. Also, it can be understood that the result (marked with a cross) of growing a growth layer E11 on the SiC single crystal substrate E10 by placing the SiC single crystal substrate E10 in a space (inside the main body container 141) where the atomic ratio Si / C is 1 or less matches the trend of the thermodynamic calculation result of SiC growth in a SiC-C equilibrium vapor pressure environment.

[0200] It can be understood that in a SiC-Si equilibrium vapor pressure environment, a growth rate of 1.0 μm / min or more is achieved at a heating temperature of 1960°C. It can also be understood that a growth rate of 2.0 μm / min or more is achieved at a heating temperature of 2000°C or higher. On the other hand, in a SiC-C equilibrium vapor pressure environment, it can be understood that a growth rate of 1.0 μm / min or more is achieved at a heating temperature of 2000°C. It can also be understood that a growth rate of 2.0 μm / min or more is achieved at a heating temperature of 2030°C or higher.

[0201] According to the present invention, a high-quality SiC semiconductor device can be provided by combining the growth step S1, the device formation step S2, and the separation step S3. [Explanation of symbols]

[0202] 1: Object to be treated 1a: Back 4:SiC raw material 4a: Main surface 10: Growth layer 11: Original board 12: SiC semiconductor device formed on the growth layer 10 23: Insulating film 43:Gap 101a: Step 101b: Terrace 102a: Step 102b: Terrace 103a: Step 103b: Terrace 111: Substrate 141: Main container 141a: Installation tool 141b: Lower container 141c: Upper container 142: High melting point container 142a: Lower container 142b: Upper container 143:Heating furnace 143a: Spare room 143b: Means of transportation 143c: Main heating chamber 143d: Heater 143e: Inert gas injection valve 143f: Vacuum forming valve 143g: Vacuum gauge 211: Circuit pattern 220: Drift region 221: Well area 222: Contact area 226:Low concentration area 230: Insulating film 240: Gate electrode 241: Source electrode 242: Drain electrode 244: Anode electrode 245: Cathode electrode 300: Separation layer 301: Crystal dislocation 302 :Damage area 311 :Light source 312: Light collecting means E10: SiC single crystal substrate E11: Growth layer S1: Growth process S11: Epitaxial growth process S12: Bunching decomposition process S2: Device formation process S21: Patterning process S22: Doping process S23: Insulating film formation process S24: Electrode formation process S3: Separation process S31: Separation layer formation process S32: Peeling process S4: Etching process W1: Terrace length W2: Terrace length W3: Terrace length

Claims

1. The method includes a growth step of forming a growth layer on a workpiece including a SiC single crystal, a device formation step of forming at least a part of a SiC semiconductor device in the growth layer, and a separation step of separating at least a part of the SiC semiconductor device from the workpiece, The growth step includes a step of forming a first growth layer on the workpiece in a SiC-C equilibrium vapor pressure environment, and then a step of forming a second growth layer on the workpiece in a SiC-Si equilibrium vapor pressure environment.

2. In the step of forming the first growth layer, the SiC-C equilibrium vapor pressure environment is formed by heating a quasi-closed space having an atomic ratio Si / C of 1 or less; 2. The method for manufacturing a semiconductor device according to claim 1, wherein in the step of forming the second growth layer, the SiC-Si equilibrium vapor pressure environment is formed by heating a quasi-closed space in which an atomic ratio Si / C exceeds 1.

3. In the growth step, the workpiece is contained in a main body container made of SiC, In the step of forming the first growth layer, the SiC-C equilibrium vapor pressure environment is formed inside the main body container by heating the main body container; 3. The method for manufacturing a semiconductor device according to claim 1, wherein in the step of forming the second growth layer, a Si vapor supply source is contained in the main body container, and the main body container is heated to form the SiC-Si equilibrium vapor pressure environment inside the main body container.

4. 4. The method according to claim 1, wherein the growing step comprises heat-treating the workpiece in an atmosphere containing Si and C elements.

5. The method according to claim 4 , wherein the growing step comprises heat-treating the workpiece in a semi-closed space in which the SiC material is exposed.

6. 6. The method according to claim 1, wherein the device formation step includes a patterning step of forming a circuit pattern on the growth layer.

7. 7. The method according to claim 1, wherein the device formation step includes a doping step of introducing dopant atoms into the growth layer.

8. 8. The method according to claim 1, wherein the device formation step includes an insulating film formation step of introducing an insulating film into the growth layer.

9. 9. The method according to claim 1, wherein the device formation step includes an electrode formation step of forming an electrode on the growth layer.

10. The manufacturing method according to any one of claims 1 to 9, wherein the separation process includes a separation layer formation process of forming a separation layer inside the workpiece including the growth layer, and a peeling process of peeling off a part of the workpiece including the growth layer starting from the separation layer.

11. The manufacturing method according to claim 10 , wherein the separation layer forming step forms the separation layer by irradiating the object with a laser beam so that the inside of the object is a focal point.

12. The method according to any one of claims 1 to 11, further comprising an etching step of etching the object by heat treating the object in an atmosphere containing Si element and C element.

13. The method according to claim 12 , wherein the etching step comprises heat-treating the workpiece in a semi-closed space in which the SiC material is exposed.

14. The method according to claim 12 or 13, comprising the steps of separating, etching and growing in this order.

15. The method according to any one of claims 1 to 14, comprising the steps of: separating and growing in this order.

Images