Bump structure and manufacturing method thereof

Abstract

To provide a bump structure that is hardly damaged by enhancing a structure characteristic of a bump structure itself to be installed on a chip, and its manufacturing method.SOLUTION: A bump structure includes a first bump layer 322 and a second bump layer 324, the first bump layer is installed on a chip 30, the second bump layer is installed on the first bump layer, the hardness of the first bump layer is different from the hardness of the second bump layer, and materials of the first bump layer and the second bump layer are the same conductive material. Thus, the chip is abutted to a substrate 40 through the bump structure, the bump structure hardly gives damage to the chip when acting force is applied to the bump structure, the structure characteristic of the bump structure itself is enhances, and the bump structure itself hardly receives damage.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a bump structure and a manufacturing method thereof, and more particularly to a bump structure to be provided on a chip and a manufacturing method thereof. [Background technology]

[0002] Generally speaking, the bump structure is used to bond at least a chip to a substrate or carrier. For example, the bump structure is used to bond the photovoltaic cell chip, the control chip, the driving chip, the coding and decoding chip, and other types of chips to the corresponding substrate or carrier, and the bump structure transmits signals.

[0003] As the manufacturing process of chips becomes more and more precise, the corresponding bumps also become more and more precise, and the price of metal materials keeps rising due to inflation, so that the bumps are reduced in size, which is an inevitable trend in the industry, but the deformation of the reduced bumps when subjected to force is more serious. During the installation of the chip on the substrate or carrier, the force applied per unit area of ​​the reduced bumps is larger than that applied per unit area of ​​the non-reduced bumps, so that the deformation of the reduced bumps is larger, and even damages the components or wiring of the chip.

[0004] In view of the above problems, the present invention aims to provide a bump structure and a manufacturing method thereof that can reduce the applied force by using bump layers with different hardness, prevent the applied force from being transmitted to the chip, avoid damage to the chip, and improve the structural characteristics of the bump structure itself, making it less susceptible to damage. Summary of the Invention

[0005] One object of the present invention is to provide a bump structure and a method for manufacturing the same, in which the multiple bump layers contained in the bump structure have different hardnesses, thereby reducing the acting force received by the bump structure and avoiding damage to the chip due to the acting force being transmitted to the chip, and by improving the structural characteristics of the bump structure itself, making it less susceptible to damage.

[0006] To this end, the present invention provides a bump structure to be mounted on a chip, the bump structure comprising a first bump layer mounted on the chip and a second bump layer mounted on the first bump layer, the hardness of the first bump layer being different from that of the second bump layer, and the first bump layer and the second bump layer being made of the same conductive material, thereby reducing the force applied to the bump structure, avoiding damage to the chip caused by the force being transmitted to the chip, and improving the structural properties of the bump structure itself, making it less susceptible to damage.

[0007] To this end, the present invention provides a method for manufacturing a bump structure for placing a bump structure on a chip, the method comprising the steps of forming a first bump layer on the chip and forming a second bump layer on the first bump layer, wherein the hardness of the first bump layer is different from the hardness of the second bump layer, and the first bump layer and the second bump layer are made of the same conductive material. [Brief description of the drawings]

[0008] [Figure 1] 1 is a schematic diagram of a bump structure according to a first embodiment of the present invention; [Figure 2A] 1A to 1C are schematic diagrams illustrating a process for manufacturing the bump structure according to the first embodiment of the present invention. [Figure 2B] 1A to 1C are schematic diagrams illustrating a process for manufacturing the bump structure according to the first embodiment of the present invention. [Figure 2C] 1A to 1C are schematic diagrams illustrating a process for manufacturing the bump structure according to the first embodiment of the present invention. [Figure 2D] 1A to 1C are schematic diagrams illustrating a process for manufacturing the bump structure according to the first embodiment of the present invention. [Figure 2E]1A to 1C are schematic diagrams illustrating a process for manufacturing the bump structure according to the first embodiment of the present invention. [Figure 2F] 1A to 1C are schematic diagrams illustrating a process for manufacturing the bump structure according to the first embodiment of the present invention. [Figure 2G] 1A to 1C are schematic diagrams illustrating a process for manufacturing the bump structure according to the first embodiment of the present invention. [Figure 2H] 1A to 1C are schematic diagrams illustrating a process for manufacturing the bump structure according to the first embodiment of the present invention. [Diagram 3] FIG. 4 is a schematic diagram of a bump structure according to a second embodiment of the present invention. [Figure 4A] 5A to 5C are schematic diagrams illustrating a manufacturing process of the bump structure according to the second embodiment of the present invention. [Figure 4B] 5A to 5C are schematic diagrams illustrating a manufacturing process of the bump structure according to the second embodiment of the present invention. [Figure 4C] 5A to 5C are schematic diagrams illustrating a manufacturing process of the bump structure according to the second embodiment of the present invention. [Figure 4D] 5A to 5C are schematic diagrams illustrating a manufacturing process of the bump structure according to the second embodiment of the present invention. [Figure 4E] 5A to 5C are schematic diagrams illustrating a manufacturing process of the bump structure according to the second embodiment of the present invention. [Figure 4F] 5A to 5C are schematic diagrams illustrating a manufacturing process of the bump structure according to the second embodiment of the present invention. [Figure 4G] 5A to 5C are schematic diagrams illustrating a manufacturing process of the bump structure according to the second embodiment of the present invention. [Figure 4H] 5A to 5C are schematic diagrams illustrating a manufacturing process of the bump structure according to the second embodiment of the present invention. [Figure 4I] 5A to 5C are schematic diagrams illustrating a manufacturing process of the bump structure according to the second embodiment of the present invention. [Figure 4J] 5A to 5C are schematic diagrams illustrating a manufacturing process of the bump structure according to the second embodiment of the present invention. [Diagram 5] FIG. 11 is a schematic diagram of a bump structure according to a third embodiment of the present invention. [Figure 6A] 10A to 10C are schematic diagrams illustrating a process for manufacturing a bump structure according to a third embodiment of the present invention. [Figure 6B] 10A to 10C are schematic diagrams illustrating a process for manufacturing a bump structure according to a third embodiment of the present invention. [Figure 6C]10A to 10C are schematic diagrams illustrating a process for manufacturing a bump structure according to a third embodiment of the present invention. [Figure 6D] 10A to 10C are schematic diagrams illustrating a process for manufacturing a bump structure according to a third embodiment of the present invention. [Figure 6E] 10A to 10C are schematic diagrams illustrating a process for manufacturing a bump structure according to a third embodiment of the present invention. [Figure 6F] 10A to 10C are schematic diagrams illustrating a process for manufacturing a bump structure according to a third embodiment of the present invention. [Figure 6G] 10A to 10C are schematic diagrams illustrating a process for manufacturing a bump structure according to a third embodiment of the present invention. [Figure 6H] 10A to 10C are schematic diagrams illustrating a process for manufacturing a bump structure according to a third embodiment of the present invention. [Figure 6I] 10A to 10C are schematic diagrams illustrating a process for manufacturing a bump structure according to a third embodiment of the present invention. [Figure 6J] 10A to 10C are schematic diagrams illustrating a process for manufacturing a bump structure according to a third embodiment of the present invention. [Figure 6K] 10A to 10C are schematic diagrams illustrating a process for manufacturing a bump structure according to a third embodiment of the present invention. [Figure 7] FIG. 13 is a schematic diagram of a bump structure according to a fourth embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] In order to allow the examiner to further understand and appreciate the features and achievable effects of the present invention, the present invention will be described in detail with reference to preferred embodiments as follows.

[0010] In the specification and claims, vocabulary is used to refer to specific components. However, those skilled in the art should understand that the same components may be referred to by different nouns, and the specification and claims do not distinguish components by differences in names, but rather use the overall technical differences of the components as the basis for classification. The term "comprises" referred to in the entire specification and claims is an open term and should be interpreted as "including, but not limited to." Furthermore, the term "coupled" includes any direct and indirect connection means. Thus, when the text states that "a first device couples to a second device," it means that the first device is directly connected to the second device, or indirectly connected to the second device through other devices or other connection means.

[0011] It is known that shrinking the bumps cannot effectively reduce the acting force, which can cause damage to the chip. Therefore, the present invention proposes a bump structure and a manufacturing method thereof, and provides a bump structure including composite bump layers with different hardness to solve the problems of the prior art.

[0012] The present invention will now be described in detail by describing various embodiments of the present invention with reference to the drawings. However, the concept of the present invention can be embodied in many different patterns and should not be construed as being limited to the exemplary embodiments described herein.

[0013] First, refer to FIG. 1. FIG. 1 is a schematic diagram of a bump structure according to a first embodiment of the present invention. As shown in the figure, in this embodiment, a bump structure 32 is provided on a chip 30, which is used to bond the chip 30 to a substrate 40. A contact pad 302 is provided on the chip 30 of this embodiment. The bump structure 32 provided on the chip 30 includes a first bump layer 322 and a second bump layer 324, the first bump layer 322 is provided on the contact pad 302, and the second bump layer 324 is provided on the first bump layer 322. The hardness of the first bump layer 322 of the bump structure 32 is different from the hardness of the second bump layer 324. This can offset the force received by the bump structure 32. For example, when the hardness of the second bump layer 324 is greater than that of the first bump layer 322, the first bump layer 322 with a relatively low hardness can achieve the effect of buffering the force. When the bump structure 32 is subjected to an acting force, the second bump layer having a relatively high hardness is first 324 This can prevent the bump structure 32 from being excessively deformed by the applied force.

[0014] In detail, in this embodiment, the first bump layer 322 is disposed on the first metal layer 304, and the first metal layer 304 is disposed between the first bump layer 322 and the contact pad 302, i.e., the first metal layer 304 is disposed on the chip 30, and the first metal layer 304 may be an under bump metal (UBM) layer. Since the UBM layer is a layer that provides a signal connection function, the first bump layer 322 being disposed on the UBM layer corresponds to the first bump layer 322 being disposed on the contact pad 302. In addition, a protective layer 303 is also disposed on the chip 30, and the protective layer 303 is disposed on the contact pad 302. Since the protective layer 303 in this embodiment has a cutout, the contact pad 302 is exposed. That is, the protective layer 303 is disposed on the contact pad 302. 302 and is disposed on the chip 30. The contact pads 302, the first metal layer 304 and the first bump layer 322 correspond to the cutouts of the protective layer 303.

[0015] When the chip 30 is bonded to the substrate 40 by the bump structure 32, a connection element 402 and a dielectric layer 404 are further included between the chip 30 and the substrate 40, the dielectric layer 404 is disposed between the second bump layer 324 and the connection element 402 and filled between the chip 30 and the substrate 40, the connection element 402 is disposed on the substrate 40, and a plurality of conductive particles (not shown) are disposed in the dielectric layer 404, for example, a plurality of conductive particles are disposed in an anisotropic conductive rubber film (ACF). Thus, relatively speaking, the chip 30 is bonded to the substrate 40 by disposing the connection element 402 and the dielectric layer 404 on the substrate 40, and the bump structure 32 is bonded to the chip 30 by pressing the dielectric layer 404. Thus, a signal is transmitted between the chip 30 and the substrate 40.

[0016] The flow of manufacturing the bump structure 32 of the first embodiment will be described in detail below.

[0017] 2A-2H are schematic diagrams of the steps of manufacturing a bump structure according to a first embodiment of the present invention. As shown in the figures, the method of manufacturing a bump structure according to the present invention provides a bump structure 32 to be placed on a contact pad 302 of a chip 30. In particular, as shown in FIG. 2A, a chip 30 is provided, a contact pad 302 is placed on the chip 30, and a protective layer 303 is placed around the contact pad 302. The contact pad 302 is selected from a metal material such as aluminum. Then, as shown in FIG. 2B, a first metal layer 304 is formed on the contact pad 302 and the protective layer 303, and covers the contact pad 302 and the protective layer 303. Here, the first metal layer 304 has a single-layer structure or a composite structure including multiple sub-layers formed of different materials, and includes one (or more) layers selected from a nickel (Ni) layer, a titanium (Ti) layer, a titanium tungsten (TiW) layer, a palladium (Pd) layer, a gold (Au) layer, a silver (Ag) layer, and combinations thereof. In this embodiment, the first metal layer 304 is formed on the contact pads 302 and the protective layer 303 by a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process or a sputtering process. Then, a photoresist layer PR made of a normal photoresist material, including a positive type photoresist and a negative type photoresist, is formed on the first metal layer 304, as shown in FIG. 2C.

[0018] Next, as shown in FIG. 2D, a part of the photoresist layer PR is removed according to the placement area of ​​the bump structure 32 to form a first storage space A1. As shown in FIG. 2E, the first metal layer 304 is used to form a signal transmissionForming the first bump layer 322 on the first metal layer 304 corresponds to forming the first bump layer 322 on the contact pad 302, since the function is provided and the contamination of the solder to the chip 30 can be avoided. As shown in FIG. 2F, a second bump layer 324 is formed on the first bump layer 322, and then, as shown in FIG. 2G, the photoresist layer PR is removed, for example, by an etching solution. Then, as shown in FIG. 2H, the first metal layer 304 that exceeds the covered area of ​​the bump structure 32 is removed, for example, by etching the first metal layer 304. This results in the first bump layer 322 being formed on the contact pad 302. As shown in FIG. 2F, a second bump layer 324 is formed on the first bump layer 322, and then, as shown in FIG. 2G, the photoresist layer PR is removed, for example, by etching the first metal layer 304. 322 Only the first metal layer 304 in the underlying covered area is retained, leaving the protective layer 303 exposed.

[0019] 2E to 2 F During the process up to the step 2, the first bump layer 322 and the second bump layer 324 of this embodiment are sequentially formed on the chip 30 by a physical vapor deposition (PVD) process, an electroplating (Plating) process, or a chemical vapor deposition (CVD) process. , No. The first bump layer 322 and the second bump layer 324 are heated. It can be done . This allows the size of the crystal grains in the first bump layer 322 and the size of the crystal grains in the second bump layer 324 to be adjusted, thereby eliminating internal stress. .

[0020] After that, or during the electroplating process, different electroplating current conditions are set to perform electroplating in the same electroplating bath (not shown). This allows the size of the crystal grains of the first bump layer 322 to be different from the size of the crystal grains of the second bump layer 324. For example, electroplating is performed with a first current to form the first bump layer 322, and electroplating is performed with a second current larger than the first current to form the second bump layer 324. The smaller the electroplating current, the more likely the crystal grain size of the first bump layer 322 will be larger than the crystal grain size of the second bump layer 324. Also, the smaller the crystal grain size, the higher the hardness. Therefore, the hardness of the second bump layer 324 is greater than that of the first bump layer 322. Also, the material of the first metal layer 304 is the same conductive material as the material of the first bump layer 322 and the second bump layer 324, for example, gold, silver, copper, or tin. Furthermore, the first bump layer 322 and the second bump layer 324 may be formed by electroplating the same conductive material using different electroplating solutions. For example, cyanide / non-cyanide is used. When non-cyanide is used, the smaller the crystal lattice, the higher the hardness, but when cyanide is used, the larger the crystal lattice, the lower the hardness.

[0021] Also, see FIG. 2E. After the first bump layer 322 is formed, the first bump layer 322 can be further heated and dried. See FIG. 2F. After the second bump layer 324 is formed, the first bump layer 322 and the second bump layer 324 can be further heated and dried. Therefore, the first bump layer 322 does not undergo a relatively long heat treatment process. The longer the heating and drying time, the larger the crystal grain size becomes. The hardness of the first bump layer 322 is likely to be less than that of the second bump layer 324. Also, see Fig. 2E and Fig. 2F. By carrying out the electroplating process A first bump layer 322 and a second bump layer 324 may be formed. The higher the temperature of the electroplating solution, the larger the grain size of the formed bump layer. For example, the temperature of the electroplating solution in the first bump layer 322 is higher than the temperature of the electroplating solution in the second bump layer 324. As a result, the hardness of the first bump layer 322 is lower than the hardness of the second bump layer 324.

[0022] In addition, the materials of the first bump layer 322 and the second bump layer 324 in this embodiment are selected from the same conductive material, such as metal materials, which improves the metal affinity between the first bump layer 322 and the second bump layer 324. For example, the materials of the first bump layer 322 and the second bump layer 324 are all gold, silver, copper, etc. 、 Tin or a combination of these This improves the metal affinity between the first bump layer 322 and the second bump layer 324. When the bump structure 32 is subjected to a lateral shear stress, the bump structure 32 is prevented from being destroyed by the lateral shear stress due to a lack of metal affinity.

[0023] Furthermore, since the hardness of the second bump layer 324 is greater than the hardness of the first bump layer 322, the second bump layer 324 is more expensive The first bump layer 322 has hardness and can reduce deformation that may occur when bonding the chip 30 to the substrate 40 , and provides a damping effect to buffer the acting force coming from the substrate 40 .

[0024] In the above embodiment, the bump structure 32 of the present invention includes a first bump layer 322 and a second bump layer 324, and the manufacturing method thereof is a method in which the first bump layer 322 and the second bump layer 324 are sequentially formed on the contact pad 302. The following describes a bump structure 32A of the present invention, which further includes a first bump buffer layer 326, as shown in FIG.

[0025] More specifically, please refer to FIG. 3. FIG. 3 is a structural schematic diagram of a bump structure according to a second embodiment of the present invention. Here, the difference between FIG. 1 and FIG. 3 is that in FIG. 3, a second metal layer 306 and a first bump buffer layer 326 are further provided. The second metal layer 306 is provided between the first metal layer 304 and the first bump layer 322, and the first bump buffer layer 326 is provided between the first bump layer 322 and the second bump layer 324. The hardness of the first bump layer 322 is less than that of the first bump buffer layer 326, and the hardness of the first bump buffer layer 326 is less than that of the second bump layer 324. Thus, the bump structure 32A of this embodiment can provide a better force buffering effect. That is, only when the first bump buffer layer 326 cannot offset the remaining force, the remaining force is transferred to the first bump layer 322 to perform final buffering. From the above, the present invention provides a first bump 322. and contact pad 302, It is installed on at least one metal layer and can be installed on multiple metal layers depending on the needs of the application. Place and further providing at least one bump buffer layer between the first bump 322 and the second bump 324, buffer The effect can be enhanced.

[0026] The process for manufacturing the bump structure 32A of the second embodiment will be described below.

[0027] Here, the operation of the process of FIG. 4A to FIG. 4B in this embodiment is the same as that of FIG. 2A and FIG. 2B in the first embodiment, and the description of the chip 30 and the first metal layer 304 is omitted. Then, as shown in FIG. 4C, in this embodiment, compared with the first embodiment, a second metal layer 306 is further provided. The second metal layer 306 is disposed on the first metal layer 304 . Second metal layer 306 is gold , silver or an alloy. In this embodiment, the first metal layer 304 and the second metal layer 306 are sequentially grown on the contact pads 302 and the protective layer 303 by a physical vapor deposition process or a chemical vapor deposition process.

[0028] Further, as shown in FIG. 4D, a photoresist layer PR is formed on the second metal layer 306. FIG. 4D and FIG. 4E are the same as FIG. 2C and FIG. 2D of the first embodiment, and the description thereof will be omitted. RA second storage space A2 is formed. As shown in FIG. 4F, a first bump layer 322 is then formed in the second storage space A2 and on the second metal layer 306. That is, the first bump layer 322 is formed on the contact pad 302. As shown in FIG. 4G, a first bump buffer layer 326 is further formed on the first bump layer 322. Then, as shown in FIG. 4H, a second bump layer 324 is formed on the first bump buffer layer 326. As shown in FIG. 4I, the photoresist layer PR is removed to expose the second metal layer 306. Then, as shown in FIG. 4J, the areas of the first metal layer 304 and the second metal layer 306 that are not covered by the first bump layer 322 are removed, for example, by etching the areas of the first metal layer 304 and the second metal layer 306 that are not covered by the first bump layer 322, and a heat treatment is performed on the first bump layer 322, the second bump layer 324, and the first bump buffer layer 326. This can relieve internal stress. .

[0029] As can be seen from the above, compared with Figures 2A to 2H, Figures 4A to 4J further form a first bump buffer layer 326 and a second metal layer 306. Here, the first bump layer 322, the second bump layer 324 and the first bump buffer layer 326 are the same conductive material. The hardness of the first bump buffer layer 326 is different from the hardness of the first bump layer 322 and the second bump layer 324. For example, the hardness decreases stepwise from top to bottom, the hardness of the second bump layer 324 is 90HV, the hardness of the first bump buffer layer 326 is 70HV, and the hardness of the first bump layer 322 is 55HV.

[0030] Figure 4F - Figure 4 H In the present invention, not only is heating performed in the final step shown in FIG. 4J, but also the first bump layer 322, No. 1 A heat treatment may be performed in each step of forming the bump buffer layer 326 and the second bump layer 324. Referring to FIG. 4F, after the first bump layer 322 is formed, the first bump layer 322 is heated and dried at a first temperature. Referring to FIG. 4G, No. 1 After forming the bump buffer layer 326, the first bump layer 322 and No. 1The bump buffer layer 326 is heated and dried. Referring to FIG. 4H, after the second bump layer 324 is formed, the first bump layer 322, No. 1 The bump buffer layer 326 and the second bump layer 324 are heated and dried. No. 1 The process of forming the bump buffer layer 326 and the second bump layer 324 is performed by a physical vapor deposition (PVD) process, an electroplating process, or a chemical vapor deposition (CVD) process, which are sequentially formed on the contact pad 302, and then heated and dried at a first temperature, a second temperature, and a third temperature, respectively, and the first temperature, the second temperature, and the third temperature may be the same temperature. may be at different temperatures. This allows the hardness of the first bump buffer layer 326 to be different from the hardness of the first bump layer 322 and the second bump layer 324.

[0031] Although the above description is of the case of one bump buffer layer, the present invention can also provide multiple bump buffer layers. The following description will take the case of two bump buffer layers 326 and 328 as an example.

[0032] Please refer to FIG. 5. This is a structural schematic diagram of a bump structure according to a third embodiment of the present invention. The difference between FIG. 3 and FIG. 5 is that in FIG. 5, a second bump buffer layer 328 is further provided between the first bump buffer layer 326 and the second bump layer 324. In this embodiment, the hardness is highest from top to bottom in the second bump layer 324 and lowest in the first bump layer 322. As a result, the bump structure 32B of this embodiment further includes a second bump buffer layer 328. 328 That is, the first bump buffer layer 326 and the second bump buffer layer 328 can provide a better force buffering and damping effect. By using Further providing force buffering By doing , Reduce the effort. If there is any remaining effort, reduce the remaining effort. Conduction to the first bump layer 322 for final buffering and Reduction As can be seen from the above, at least one bump buffer layer is provided between the first bump layer 322 and the second bump layer 324 of the present invention, and multiple bump buffer layers can be provided according to the needs of use to achieve better performance. buffer The effect can be obtained.

[0033] Furthermore, as can be seen from the fact that the hardness of the first bump buffer layer 326 in the third embodiment is less than the hardness of the second bump buffer layer 328, the hardness of the bump buffer layer gradually decreases as it approaches the first bump layer 322, and the hardness of the bump buffer layer (e.g., the second bump buffer layer 328) that is farther from the first bump layer 322 is greater than the hardness of the first bump layer. 322 3. The hardness of the bump buffer layer adjacent to the first bump buffer layer 326 is greater than the hardness of the bump buffer layer adjacent to the first bump buffer layer 326.

[0034] The manufacturing process of the above-mentioned bump structure 32B will be further described below.

[0035] 6A to 6G are the same as the above-mentioned FIGS. 4A to 4G, and the description thereof will be omitted. Thereafter, as shown in FIG. 6H, a second bump buffer layer 328 is formed on the first bump buffer layer 326. Thereafter, as shown in FIG. 6I, a second bump layer 324 is formed on the second bump buffer layer 328. FIGS. 6J and 6K are the same as FIGS. 4I and 4J, with the difference being that in FIG. 6K, after the first metal layer 304 and the second metal layer 306 are removed, When the first bump layer 322, the first bump buffer layer 326, and the second bump layer 324 are heated, Second bump buffer layer 328 too Heating. Explanation of that will be omitted.

[0036] In the above embodiment, the bump structures 32, 32A, and 32B are disposed at the positions having the notches of the protective layer 303. Thus, the first metal layer 304 contacts the contact pad 302, and the contact pad 302 is bonded to the bump structures 32, 32A, and 32B through the first metal layer 304 or through the first metal layer 304 and the second metal layer 306. However, the present invention can also be applied to a dummy bump. The dummy bump is used to support the unexposed area of ​​the contact pad 302. Regarding dispersing the acting force generated during the process of bonding the chip 30 to the substrate 40, This is explained below.

[0037] Please refer to FIG. 7. FIG. 7 is a structural schematic diagram of a bump structure according to a fourth embodiment of the present invention. Here, the difference between FIG. 1 and FIG. 7 is that the protective layer 303 in FIG. 7 does not have a cutout, and the contact pad 302 is not exposed. The bump structure of this embodiment can be used for support, and when the chip 30 is bonded to the substrate 40, The applied force can be distributed, and the applied force can be applied to the bump structure of this embodiment in addition to the bump structure used for the signal transmission described above. The force is evenly distributed in the bump structure. Dispersed to prevent damage to bump structure and chip It is possible.

[0038] In summary, the present invention provides a bump structure and a manufacturing method thereof. By providing a first bump layer and a second bump layer with different hardness, acting force Further, by providing a bump buffer layer, it is possible to improve the buffer Provides better effect Acting force offset (acting force reduction) As a result, when a chip is butted against a substrate via the bump structure of the present invention, the bump structure is less likely to cause damage to the chip, and the structural properties of the bump structure itself are improved, making the bump structure itself less susceptible to damage.

[0039] Therefore, the present invention is truly novel, involves an inventive step, is industrially applicable, and undoubtedly meets the requirements for patent applications under the Patent Act.

[0040] However, the above is merely a preferred embodiment of the present invention, and does not limit the scope of the present invention. Any equivalent changes and modifications of the shape, structure, features, and spirit described in the scope of the patent application of the present invention are included in the scope of the patent application of the present invention.

[0041] 30 Chip 302 Contact Pad 303 Protective layer 304 1st metal layer 306 2nd metal layer 32 Bump structure 322 1st bump layer 324 2nd bump layer 326 First bump buffer layer 328 Second bump buffer layer 40 Substrate 402 Connection element 404 Dielectric layer

Claims

1. A bump structure provided on a chip, comprising: a first bump layer disposed on the chip; a second bump layer disposed on the first bump layer; the first bump layer and the second bump layer are made of the same conductive material; the hardness of the first bump layer is different from the hardness of the second bump layer; A bump structure in which the crystal grain size of the first bump layer is different from the crystal grain size of the second bump layer.

2. at least one bump buffer layer disposed between the first bump layer and the second bump layer; the first bump layer, the second bump layer and the at least one bump buffer layer are made of the same conductive material; The bump structure of claim 1 , wherein the at least one bump buffer layer has a hardness different from the hardness of the first bump layer and the second bump layer.

3. the hardness of the first bump layer is less than the hardness of the at least one bump buffer layer; The bump structure according to claim 2 , wherein the hardness of the at least one bump buffer layer is less than the hardness of the second bump layer.

4. the at least one bump buffer layer includes a plurality of bump buffer layers, the hardness of the first bump layer being less than a hardness of the plurality of bump buffer layers, the hardness of the plurality of bump buffer layers being less than a hardness of the second bump layer; 4. The bump structure of claim 3, wherein the hardness of the plurality of bump buffer layers gradually decreases toward the first bump layer, and the hardness of the bump buffer layers away from the first bump layer is greater than the hardness of the bump buffer layers adjacent to the first bump layer.

5. The bump structure according to claim 1 , wherein the hardness of the first bump layer is less than the hardness of the second bump layer.

6. 2. The bump structure according to claim 1, wherein the first bump layer is disposed on at least one metal layer, and the at least one metal layer is disposed on the chip.

7. Further comprising a protective layer, the protective layer is disposed on the chip and surrounding the contact pads; 2. The bump structure according to claim 1, wherein the contact pad is disposed on and in contact with the chip.

8. the first bump layer is disposed on at least one metal layer; The bump structure according to claim 7 , wherein the at least one metal layer corresponds to the notch in the protective layer.

9. 8. The bump structure according to claim 7, wherein the protection layer has a cutout, and the contact pad and the first bump layer face each other at the cutout.

10. the first bump layer is disposed on at least one metal layer facing the cut opening of the protective layer; 10. The bump structure of claim 9, wherein the at least one metal layer is disposed on and in contact with the contact pad.

11. 1. A method for manufacturing a bump structure for providing a bump structure on a chip, comprising: forming a first bump layer on the chip; forming a second bump layer on the first bump layer; the first bump layer and the second bump layer are made of the same conductive material, and the hardness of the first bump layer is different from the hardness of the second bump layer; A method for manufacturing a bump structure, wherein the crystal grain size of the first bump layer is different from the crystal grain size of the second bump layer.

12. forming at least one bump buffer layer on the first bump layer, on which the second bump layer is formed; the first bump layer, the second bump layer and the at least one bump buffer layer are made of the same conductive material; The method for manufacturing a bump structure according to claim 11 , wherein the at least one bump buffer layer has a hardness different from the hardnesses of the first bump layer and the second bump layer.

13. the hardness of the first bump layer is less than the hardness of the at least one bump buffer layer; The method for manufacturing a bump structure according to claim 12 , wherein the hardness of the at least one bump buffer layer is less than the hardness of the second bump layer.

14. the at least one bump buffer layer includes a plurality of bump buffer layers, the hardness of the first bump layer being less than a hardness of the plurality of bump buffer layers, the hardness of the plurality of bump buffer layers being less than a hardness of the second bump layer; 14. The method for manufacturing a bump structure according to claim 13, wherein the hardness of the plurality of bump buffer layers gradually decreases toward the first bump layer, and the hardness of the bump buffer layers farther from the first bump layer is greater than the hardness of the bump buffer layers close to the first bump layer.

15. after forming the first bump layer, heating the first bump layer; after forming the at least one bump buffer layer, heating the first bump layer and the at least one bump buffer layer; after forming the second bump layer, heating the first bump layer, the at least one bump buffer layer and the second bump layer; The method for manufacturing a bump structure according to claim 12, further comprising:

16. The method for manufacturing a bump structure according to claim 11 , wherein the first bump layer has a hardness lower than a hardness of the second bump layer.

17. after forming the first bump layer, heating the first bump layer; heating the first bump layer and the second bump layer after forming the second bump layer; The method for manufacturing a bump structure according to claim 11, further comprising:

18. The method for manufacturing a bump structure as claimed in claim 11, further comprising the step of forming a protective layer on the chip, the protective layer being disposed on the chip and surrounding the contact pads.

19. 20. The method for manufacturing a bump structure according to claim 18, further comprising the step of forming at least one metal layer corresponding to the cut opening of the protective layer, wherein the first bump layer is formed on the at least one metal layer and corresponds to the cut opening of the protective layer.

20. forming the first bump layer and the second bump layer by an electroplating process; The method for manufacturing a bump structure according to claim 11, wherein the first bump layer and the second bump layer are formed by performing an electroplating process using different current conditions.

21. forming the first bump layer and the second bump layer by an electroplating process; The method for manufacturing a bump structure according to claim 11, wherein the first bump layer and the second bump layer are formed by performing an electroplating process using electroplating solutions having different temperatures.

22. forming the first bump layer and the second bump layer by an electroplating process; The method for manufacturing a bump structure according to claim 11, wherein the first bump layer and the second bump layer are formed by performing an electroplating process using different electroplating solutions.

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