Superjunction power silicon carbide semiconductor devices formed by ion implantation channeling techniques and related methods

Abstract

To provide a power semiconductor device, and more particularly, provide a power semiconductor device having a superjunction structure and a method of manufacturing such a device.SOLUTION: A semiconductor device includes a drift region having an upper portion and a lower portion and a silicon carbide, a first contact at the top of the drift region, and a second contact at the bottom of the drift region, and the drift region includes a superjunction structure including a p-n junction formed at an angle of 6° to 35° from a plane perpendicular to the top surface of the drift region. The p-n junction extends within + / -1.5° of the crystalline axis of the silicon carbide material forming the drift region.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] U.S. GOVERNMENT STATEMENT OF INTEREST This invention was made with Government support under Contract No. W911NF-12-2-0064 awarded by the Army Research Laboratory. The Government has certain rights in this invention.

[0002] The present invention relates to a power semiconductor device, and more particularly to a power semiconductor device having a super junction structure and a method for manufacturing such a device. [Background technology]

[0003] Power semiconductor devices are used to carry large currents and support high voltages. A wide variety of power semiconductor devices are known in the art, including, for example, power metal oxide semiconductor field effect transistors ("MOSFETs"), bipolar junction transistors ("BJTs"), insulated gate bipolar transistors ("IGBTs"), Schottky diodes, junction barrier Schottky ("JBS") diodes, merged pn Schottky ("MPS") diodes, gate turn-off transistors ("GTOs"), MOS controlled thyristors, and a variety of other devices. These power semiconductor devices are typically fabricated from single crystal silicon semiconductor material, or, more recently, from silicon carbide-based or gallium nitride-based semiconductor materials.

[0004] A power semiconductor device can have a lateral or vertical structure. In a device with a lateral structure, the terminals of the device (e.g., the drain terminal, the gate terminal, and the source terminal in a power MOSFET device) are on the same major surface (i.e., the top or bottom surface) of the semiconductor layer structure. On the other hand, in a device with a vertical structure, at least one terminal is provided on each major surface of the semiconductor layer structure (e.g., in a vertical MOSFET device, the source may be on the top surface of the semiconductor layer structure and the drain may be on the bottom surface of the semiconductor layer structure). The semiconductor layer structure may or may not include an underlying substrate. As used herein, the term "semiconductor layer structure" refers to a structure that includes one or more semiconductor layers, such as a semiconductor substrate and / or a semiconductor epitaxial layer.

[0005] A conventional silicon carbide power device generally includes a silicon carbide substrate, such as a silicon carbide wafer, having a first conductivity type (e.g., n-type substrate), on which an epitaxial layer structure having a first conductivity type (e.g., n-type) is formed. This epitaxial layer structure (which may include one or more separate layers) serves as a drift region for the power semiconductor device. The device generally includes an "active region" that includes one or more power semiconductor devices having pn and / or Schottky junctions. The active region may be formed on and / or within the drift region. The active region acts as a primary junction for blocking voltage in a reverse bias direction and conducting current in a forward bias direction. The device may also have an edge termination region adjacent to the active region. One or more power semiconductor devices may be formed on the substrate, and each power semiconductor device generally has its own edge termination. After the substrate is fully formed and processed, the substrate may be diced to separate the individual edge terminated power semiconductor devices if multiple devices are formed on the same substrate. The power semiconductor devices may have a unit cell structure in which the active area of ​​each power semiconductor device includes a number of individual devices arranged in parallel with one another and functioning together as a single power semiconductor device.

[0006] Power semiconductor devices are designed to block (in forward or reverse blocking conditions) or pass (in forward operating conditions) large voltages and / or currents. For example, in blocking conditions, a power semiconductor device may be designed to maintain a potential of hundreds or thousands of volts. However, when the applied voltage approaches or exceeds the voltage level at which the device is designed to block, a minor level of current can begin to flow through the power semiconductor device. Such current, commonly referred to as "leakage current," can be highly undesirable. If the voltage is increased beyond the designed voltage blocking capability of the device, which can be a function of, among other things, the doping and thickness of the drift region, leakage current can begin to flow. However, current leakage can occur for other reasons, such as failure of the edge termination and / or main junction of the device. If the voltage at the device is increased to a critical level beyond the breakdown voltage, the increase in the electric field can result in uncontrollable and undesirable sudden generation of charge carriers in the semiconductor device, leading to a condition known as avalanche breakdown.

[0007] Power semiconductor devices may also begin to allow more than insignificant amounts of leakage current to flow at voltage levels lower than the design breakdown voltage of the device. In particular, leakage current may begin to flow at the edges of the active area, which may experience high electric fields due to electric field crowding effects. To reduce this electric field crowding (and the resulting leakage current), edge termination structures may be provided that surround some or all of the active area of ​​the power semiconductor device. These edge terminations can spread the electric field over a larger area, thereby reducing electric field crowding.

[0008] In vertical power semiconductor devices, the blocking voltage rating of the device is generally determined by the thickness and doping concentration of the drift region. In particular, to increase the breakdown voltage of the device, the doping concentration of the drift region is decreased and / or the thickness of the drift region is increased. Generally, during the design stage, a desired blocking voltage rating is selected, and then the thickness and doping of the drift region are selected based on the desired blocking voltage rating. Since the drift region is the current path for the device in the forward "on" state, decreasing the doping concentration and increasing the thickness of the drift region can result in a higher on-state resistance for the device. Thus, there is an inherent trade-off between on-state resistance and blocking voltage for these devices.

[0009] Superjunction drift regions have been introduced in which the drift region is divided into alternating highly doped n-type and p-type regions. In vertical semiconductor devices, these side-by-side n-type and p-type regions are often referred to as "pillars". The pillars may have a fin shape, a column shape, or other shape. The thickness and doping of these pillars may be controlled so that the superjunction acts like a pn junction with low resistance and high breakdown voltage. Thus, by using a superjunction structure, the traditional trade-off between the breakdown voltage of the device and the doping level of the drift region can be avoided. Typically, at least some of the pillars are formed by ion implantation, and so-called "deep" implants (e.g., ion implantation depths of 2.5 microns to 5 microns or more) are used to enhance the effect of the superjunction structure. In superjunction devices, the doping concentration in the drift region may be increased to lower the on-state resistance of the device with reduced impact on the breakdown voltage.

[0010] 1 is a schematic cross-sectional view of a conventional power semiconductor device in the form of a JBS diode 10 having a conventional superjunction drift region 30. As shown in FIG. 1, the JBS diode 10 includes a cathode contact 20, an ohmic contact layer 22, an n-type substrate 24, a drift region 30, a p-type blocking junction 40, a channel region 46, a Schottky contact 42, and an anode contact 44. The cathode contact 20 and the anode contact 44 may each comprise a highly conductive metal layer. The Schottky contact 42 may comprise a layer that forms a Schottky junction with the drift region 30, and may comprise, for example, an aluminum layer. The n-type substrate 24 may comprise a silicon carbide substrate heavily doped with an n-type impurity such as nitrogen or phosphorus. The ohmic contact layer 22 may comprise a metal that forms an ohmic contact to the n-type silicon carbide to form an ohmic contact to the silicon carbide substrate 24. P-type blocking junction 40 may be a p-type implanted region on top of drift region 30 that is heavily implanted with p-type dopants. A channel region 46 is located adjacent to p-type blocking junction 40. Channel region 46 is a semiconductor structure that passes current in the on state and blocks voltage in the block state. When diode 10 is in its forward on state, current flows through channel region 46.

[0011] The drift region 30 may comprise a silicon carbide semiconductor region including at least one n-type pillar 32 and at least one p-type pillar 34. The n-type pillar 32 and the p-type pillar 34 may each comprise an epitaxially grown silicon carbide region doped with n-type and p-type dopants, respectively. The number of charges in the n-type pillar 32 may be approximately equal to the number of charges in the p-type pillar 34. The n-type and p-type pillars 32, 34 may be formed, for example, by implanting ions into a predetermined portion of the drift region 30. As known to those skilled in the art, ions such as n-type or p-type dopants may be implanted into a semiconductor layer or region by ionizing a desired ion species and accelerating the ions of a predetermined kinetic energy as an ion beam toward a surface of the semiconductor layer in an ion implantation target chamber. Based on the predetermined kinetic energy, the desired ion species may penetrate to a particular depth into the semiconductor layer. Summary of the Invention

[0012] According to an embodiment of the invention, there is provided a semiconductor device including a drift region having a top and a bottom, the drift region comprising silicon carbide, a first contact at the top of the drift region, and a second contact at the bottom of the drift region. The drift region includes a superjunction structure including a p-n junction formed at an angle of 6° to 35° from a plane perpendicular to a top surface of the drift region. The p-n junction extends within + / - 1.5° of a crystallographic axis of the silicon carbide material forming the drift region.

[0013] In some embodiments, the crystal axis is one of a <11-23> crystal axis, a <-1-123> crystal axis, a <1-213> crystal axis, a <-12-13> crystal axis, a <2-1-13> crystal axis, or a <-2113> crystal axis. A pn ​​junction may comprise an interface between the p-type pillar and the n-type pillar, and the width of the p-type pillar may be approximately equal to the width of the n-type pillar. In some embodiments, the p-type pillar and the n-type pillar may each extend at least 4 microns into the drift region from a top surface of the drift region. The p-type pillar may have a doping concentration that varies by less than a factor of 10 over a portion of the p-type pillar that is at least 2.5 microns deep as a function of depth from a top surface of the drift region.

[0014] According to further embodiments of the present invention, there are provided semiconductor devices including a drift region having an upper and lower portion, the drift region comprising silicon carbide, a first contact at the upper portion of the drift region, and a second contact at the lower portion of the drift region, wherein the drift region comprises a first pillar doped with an impurity of a first conductivity type, <0001> The semiconductor device may include a first pillar having a first sidewall tilted at an angle of 10° to 13°, 15.5° to 18.5°, or 30° to 33° from the crystal axis, and a second pillar adjacent to the first pillar and doped with impurities of a second conductivity type opposite to the impurities of the first conductivity type.

[0015] In some embodiments, the first pillar and the second pillar may form a pn junction in the drift region that is at least a part of a superjunction structure in the drift region. <0001> The first pillar may have a first sidewall that is tilted at an angle of 10° to 13°, 15.5° to 18.5°, or 30° to 33° from the crystal axis. The first sidewall of the first pillar may be tilted at the same angle as the first sidewall of the second pillar. The first sidewall of the first pillar may face and directly contact the first sidewall of the second pillar.

[0016] In some embodiments, the first sidewall of the first pillar may be coplanar with the first sidewall of the second pillar. The first volume of the first pillar may be approximately equal to the second volume of the second pillar. The semiconductor device may further include a silicon carbide substrate between the drift region and the second contact. The impurities of the first conductivity type may be p-type conductivity impurities and the impurities of the second conductivity type may be n-type conductivity impurities. The silicon carbide substrate may be cut at an oblique angle, e.g., between 2° and 8°, relative to a plane defined by the <10-10> and <11-20> crystal axes. In some embodiments, the oblique angle may be about 4°.

[0017] In some embodiments, the device may further include an edge termination surrounding the first and second pillars. The first and second pillars may extend from a top surface of the drift region into the drift region by at least 4 microns. The drift region may be, for example, about 5×10 15 cm -3 ~about 5x10 16 cm -3 The first pillar may have a doping concentration that varies with depth from a top surface of the drift region by less than a factor of 10 over at least a 2.5 micron deep portion of the first pillar.

[0018] According to yet another embodiment of the present invention, there is provided a semiconductor device including a drift region having a top and a bottom, the drift region comprising silicon carbide, a first contact at the top of the drift region, and a second contact at the bottom of the drift region, the drift region including a superjunction structure having a first pillar doped with impurities of a first conductivity type, the first pillar having a first sidewall tilted at an angle of -1.5° to 1.5° from a <11-20> crystal axis, and a second pillar adjacent to the first pillar and doped with impurities of a second conductivity type opposite the impurities of the first conductivity type, the second pillar having a first sidewall tilted at an angle of -1.5° to 1.5° from the <11-20> crystal axis.

[0019] In some embodiments, the first pillar and the second pillar may have approximately the same width. The first and second pillars may extend from a top surface of the drift region into the drift region by at least 5 microns. The first pillar may have a doping concentration that varies by less than a factor of 10 over a portion of the first pillar that is at least 2.5 microns deep as a function of depth from a top surface of the drift region.

[0020] According to yet another embodiment of the present invention, there is provided a method of forming a semiconductor device in which a silicon carbide drift layer is formed on a silicon carbide substrate doped with impurities having a first conductivity type, wherein selected portions of the drift layer are implanted with impurities having a second conductivity type opposite the first conductivity type, where the impurities are implanted at an angle within + / -1.5° of one of a <11-23> crystal axis, a <-1-123> crystal axis, a <1-213> crystal axis, a <-12-13> crystal axis, a <2-1-13> crystal axis, or a <-2113> crystal axis to form second conductivity type pillars in the drift layer that are part of a superjunction structure. Selected portions of the drift layer may be implanted with impurities having a first conductivity type, where the impurities are implanted at an angle within + / -1.5° of one of the <11-23> crystal axis, the <-1-123> crystal axis, the <1-213> crystal axis, the <-12-13> crystal axis, the <2-1-13> crystal axis, or the <-2113> crystal axis to form first conductivity type pillars in the drift layer that are part of the superjunction structure and form pn junctions with the second conductivity type pillars.

[0021] In some embodiments, the first and second conductivity type pillars may each have at least one sloped sidewall. <0001> The silicon carbide substrate may have at least two sidewalls tilted at an angle of 10°-13°, 15.5°-18.5°, or 30°-33° from the crystal axis. The silicon carbide substrate may be offcut at an angle of 2°-8° from a plane defined by the <10-10> crystal axis and the <11-20> crystal axis. Each of the first and second conductivity type pillars may extend from a top surface of the drift layer into the drift layer at least 4 microns. The second conductivity type pillar may have a doping concentration that varies with depth by less than a factor of 10 throughout at least a 2.5 micron deep portion of the second conductivity type pillar. The method may further include implanting an impurity into the selected portion of the drift layer at an implant angle that is within + / - 1.5° of the <11-20> crystal axis.

[0022] According to yet another embodiment of the present invention, there is provided a method of forming a semiconductor device in which a mask is formed on a top surface of a silicon carbide drift layer after the silicon carbide drift layer is formed. Selected portions of the drift layer are implanted with an impurity having a first conductivity type, where the impurity is implanted at an angle within + / -1.5° of one of a <11-23> crystal axis, a <-1-123> crystal axis, a <1-213> crystal axis, a <-12-13> crystal axis, a <2-1-13> crystal axis, or a <-2113> crystal axis to form a first implanted region in the drift layer having the first conductivity type, the first implanted region having a first sidewall that is tilted relative to a top surface of the silicon carbide drift layer. The first sidewall forms one side of a pn junction in the drift layer that is part of a superjunction structure in the drift layer. Selected portions of the drift layer may be implanted with impurities having a second conductivity type opposite to the first conductivity type, the impurities being implanted at an angle that is within + / - 1.5° of one of the <11-23> crystal axis, the <-1-123> crystal axis, the <1-213> crystal axis, the <-12-13> crystal axis, the <2-1-13> crystal axis, or the <-2113> crystal axis to form a second implanted region in the drift layer having the second conductivity type, the second implanted region having a first sidewall that is tilted relative to a top surface of the silicon carbide drift layer.

[0023] In some embodiments, the first implanted region may comprise a p-type pillar and the second implanted region may comprise an n-type pillar in direct contact with the p-type pillar. <0001> The n-pillars may have at least two sidewalls that are tilted at an angle of 10°-13°, 15.5°-18.5°, or 30°-33° from the crystal axis. The n-pillars and p-pillars may each extend from a top surface of the drift layer into the drift layer at least 4 microns. The p-pillars may have a doping concentration that varies with depth by less than a factor of 10 over a portion of the p-pillar that is at least 2.5 microns deep.

[0024] The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate certain embodiments of the invention. [Brief description of the drawings]

[0025] [Figure 1] FIG. 1 is a schematic cross-sectional view of a conventional power semiconductor device having a super-junction drift region. [Diagram 2] FIG. 1 is a schematic diagram showing the relative positions of various crystallographic axes in 4H silicon carbide. [Figure 3A] <0001> 1 shows the lattice structure of 4H silicon carbide viewed along the crystallographic axes. [Figure 3B] The lattice structure of 4H silicon carbide viewed along the <11-23> crystallographic axis is shown. [Figure 3C] The lattice structure of 4H silicon carbide viewed along the <11-20> crystallographic axis is shown. [Figure 4] With an implantation energy of 60 keV <0001> 1 is a graph of secondary ion mass spectrometry (SIMS) data showing implanted dopant concentrations in 27Al ions implanted into 4H silicon carbide along the <11-23>, <11-20> and <11-21> crystallographic axes. [Figure 5A] FIG. 1 is a schematic plan view of a 4H silicon carbide based semiconductor device illustrating implantation angles that can result in high channeling during ion implantation. [Figure 5B] 1 is a schematic side view of a 4H silicon carbide based semiconductor device illustrating an implantation angle that can result in high channeling during ion implantation. [Figure 6A] FIG. 1 is a plan view of a semiconductor wafer having an epitaxial layer and a first ion implantation mask formed on the epitaxial layer. [Figure 6B] FIG. 2 is a plan view of a semiconductor wafer having an epitaxial layer and a second ion implantation mask formed on the epitaxial layer. [Figure 6C] FIG. 6C is a cross-sectional view taken along line 6C-6C of FIG. 6B after the second ion implantation mask is removed. [Figure 7A] FIG. 1 is a plan view of a semiconductor wafer having an epitaxial layer and a mask over the epitaxial layer. [Figure 7B] FIG. 7B is a cross-sectional view taken along line 7B-7B of FIG. 7A. [Figure 7C] FIG. 7C is a cross-sectional view taken along line 7C-7C of FIG. 7A. [Figure 8] FIG. 2 is a schematic cross-sectional view of a JBS diode having a superjunction drift region formed using a channeling ion implantation technique in accordance with an embodiment of the present invention. [Figure 9A] FIG. 1 is a schematic plan view of a power semiconductor device having a super junction drift region according to another embodiment of the present invention. [Figure 9B] FIG. 9B is a cross-sectional view taken along line 9B-9B of FIG. 9A. [Figure 10] FIG. 2 is a schematic plan view of another power semiconductor device having a super junction drift region in accordance with an embodiment of the present invention. [Figure 11] FIG. 1 is a schematic plan view of a semiconductor wafer having a plurality of power semiconductor devices in accordance with an embodiment of the present invention. [Figure 12A] 1A to 1C are schematic cross-sectional views illustrating a method of manufacturing a power semiconductor device according to an embodiment of the present invention. [Figure 12B] 1A to 1C are schematic cross-sectional views illustrating a method of manufacturing a power semiconductor device according to an embodiment of the present invention. [Figure 12C] 1A to 1C are schematic cross-sectional views illustrating a method of manufacturing a power semiconductor device according to an embodiment of the present invention. [Figure 12D] 1A to 1C are schematic cross-sectional views illustrating a method of manufacturing a power semiconductor device according to an embodiment of the present invention. [Figure 12E] 1A to 1C are schematic cross-sectional views illustrating a method of manufacturing a power semiconductor device according to an embodiment of the present invention. [Figure 12F] 1A to 1C are schematic cross-sectional views illustrating a method of manufacturing a power semiconductor device according to an embodiment of the present invention. [Figure 13] 5 is a schematic cross-sectional view of a power semiconductor device according to a further embodiment of the present invention. [Figure 14]1 is a graph of SIMS data showing implanted dopant concentration in 27Al ions implanted into 4H silicon carbide along the <11-23> crystallographic axis using techniques according to an embodiment of the present invention. [Figure 15A] FIG. 2 is a schematic plan view of a power semiconductor device having another superjunction pillar structure in accordance with an embodiment of the present invention. [Figure 15B] FIG. 2 is a schematic plan view of a power semiconductor device having another superjunction pillar structure in accordance with an embodiment of the present invention. [Figure 16] 1 is a flow chart illustrating a method of manufacturing a power semiconductor device having a super junction drift region in accordance with an embodiment of the present invention. [Figure 17] FIG. 1 is a schematic cross-sectional view of a JBS diode. [Figure 18] 18 is a graph of forward operating current-voltage (I-V'') characteristics of a JBS diode having the configuration of FIG. 17 implemented with a titanium Schottky contact and a tantalum Schottky contact. [Figure 19] 18 is a graph of reverse blocking IV characteristics for several different operating temperatures of a JBS diode having the configuration of FIG. 17 using a tantalum Schottky contact. [Figure 20] FIG. 1 is a schematic plan view of a JBS diode according to an embodiment of the present invention. [Figure 21] FIG. 21 is a cross-sectional view of the JBS diode of FIG. 20 taken along line II. [Figure 22] 21 is a cross-sectional view along line II of the JBS diode of FIG. 20 showing the doping concentration of its p-type blocking junction. [Figure 23] 4 is a graph illustrating dopant concentration as a function of implant depth for dopant implants performed at different implant energies using a channeling technique according to an embodiment of the present invention. [Figure 24] 1 is a graph of simulated electric field strength at a Schottky junction as a function of current density for both a conventional JBS diode and a JBS diode according to an embodiment of the present invention. [Diagram 25]1 is a graph showing forward operating IV characteristics of several JBS diodes according to embodiments of the present invention. [Figure 26] 26 is a graph showing the reverse blocking IV characteristics of the JBS diode used to generate the graph of FIG. 25. [Figure 27] 4 is a schematic cross-sectional view of a MOSFET according to a further embodiment of the present invention; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0026] Power semiconductor devices with superjunction drift regions have traditionally been formed in two different ways. In the first approach, a semiconductor drift region having a first conductivity type (e.g., n-type) may be epitaxially grown on a substrate, after which an etching step may be performed to form one or more trenches in the epitaxial layer to form one or more pillars of semiconductor material having the first conductivity type. The sidewalls of the trenches may then be oxidized, and the trenches may be refilled by epitaxially growing a semiconductor material doped with impurities having a second conductivity type (e.g., p-type), thereby forming one or more pillars of semiconductor material having the second conductivity type.

[0027] In a second approach to forming a superjunction drift region, a semiconductor drift region may be epitaxially grown on a substrate, and n-type and p-type dopants may then be selectively implanted into the drift region to form respective n-type and p-type pillars. The implanted dopants may be diffused throughout the pillars, for example, via thermal annealing. If necessary, multiple epitaxial growth and ion implantation steps may be performed to form a superjunction drift region having a desired thickness. Either approach may be used to form a superjunction drift region, for example, in a silicon power device. As will be apparent from the following discussion, the semiconductor pillars used to form the superjunction drift region are regions that extend vertically through at least a portion of the drift region and may have a variety of different shapes.

[0028] The above-mentioned conventional techniques for forming a superjunction drift region may not be well suited for forming a superjunction drift region in certain high bandgap semiconductor materials such as silicon carbide. For example, the first conventional fabrication method mentioned above, i.e., forming a trench in a drift region refilled with a semiconductor material of a second conductivity type, may be problematic in silicon carbide. This is because the breakdown voltage of the oxide layer formed between the n-type and p-type pillars is nearly the same as the breakdown voltage in silicon carbide. As a result, during reverse bias operation, carrier tunneling into the oxide layer may occur, resulting in leakage current through the oxide or destructive avalanche breakdown. Furthermore, in silicon carbide, the second conductivity type dopant may be non-uniformly mixed near the trench sidewalls during the epitaxial trench refill process, making it difficult to control the charge on the second conductivity type pillar.

[0029] The second aforementioned prior art technique may not work well in silicon carbide because n-type and p-type dopants do not tend to diffuse well in silicon carbide, even at high temperatures. This is also true in various other compound semiconductor materials, such as gallium nitride-based semiconductor materials, where they dissociate before thermal diffusion can occur. As a result, the ion implantation process provides the primary means for obtaining the desired dopant profile in the drift region. When dopant ions are implanted into the semiconductor layer, the ions cause damage to the crystal lattice of the semiconductor layer, which can typically only be partially repaired by thermal annealing. The depth to which the ions are implanted is directly related to the energy of the implant; i.e., ions implanted into the semiconductor layer with higher energy tend to enter the layer deeper. Thus, high energy implants are required to form deep implanted regions. However, lattice damage is also directly related to the implant energy; i.e., high energy implants tend to cause more lattice damage than low energy implants, and the uniformity of the ion implant decreases with increasing implant depth. Therefore, to form an implanted region with good doping uniformity with acceptable levels of depth and / or lattice damage, it is necessary to perform multiple successive epitaxial growth / ion implantation steps to obtain a drift layer with a sufficient thickness to achieve a breakdown voltage on the order of several kilovolts. Such multiple epitaxial growth and ion implantation steps increase the time and cost of device fabrication.

[0030] Recently, a third approach has been proposed for forming superjunction structures in 4H silicon carbide, disclosed in U.S. Patent Publication No. 2015 / 0028350, the entire contents of which are incorporated herein by reference. In this approach, n-type and p-type pillars are formed by ion implantation, which can guide ions into the crystal. <0001> The implant angle is carefully controlled to be less than 2° from the crystal axis. This technique has been shown to result in junction depths of up to 4 microns with implant energies of 900 keV, and can provide an economically viable method for producing power semiconductor devices with blocking voltages in the range of 600-1200 volts. However, this technique is generally not considered scalable to produce devices with higher blocking voltages.

[0031] Embodiments of the present invention are based on the recognition that the depth and quality of an ion implantation step in 4H silicon carbide and other high band gap and / or compound semiconductor materials is a function of the lattice structure as viewed along the longitudinal axis of the ion beam. In particular, there is a specific geometric relationship between the lattice structure of silicon carbide (or other material) and the ion beam that can result in large channels that are particularly useful for obtaining deep dopant ion implantation depths and more uniform dopant concentrations as a function of depth. By implanting ions directly along these channels, implanted regions can be formed in silicon carbide that exhibit good uniformity as a function of depth using lower energy implants, resulting in reduced lattice damage.

[0032] According to some embodiments, ion implantation may be performed along the <11-23> crystallographic axis of the 4H silicon carbide layer structure or along symmetrically equivalent crystallographic axes. The symmetrically equivalent crystallographic axes to the <11-23> crystallographic axis are the <-1-123> crystallographic axis, the <1-213> crystallographic axis, the <-12-13> crystallographic axis, the <2-1-13> crystallographic axis, and the <-2113> crystallographic axis. Each of these six symmetrically equivalent crystallographic axes is <0001> The lattice structure is tilted at 17 degrees from the crystal axis. As will be described in detail herein, along these six crystal axes, relatively large channels appear in the crystal structure that facilitate deep implantation of dopants by ion implantation. As another example, ion implantation may be performed along the <11-20> crystal axis, which exhibits very large channels with a low surface density of atoms when viewed along the implantation axis. It has been demonstrated that even deeper ion implantation can be achieved (for a given ion implantation energy) by performing ion implantation along such channels in the lattice structure, which may be used to result in lower cost and / or higher performance power semiconductor devices.

[0033] When ions are implanted into a semiconductor material, the implanted ions tend to scatter as they collide with atoms in the crystal lattice of the semiconductor material. When the implantation direction is oriented at an oblique angle to each of the major axes of the crystal lattice, the atoms in the crystal lattice may appear to have a random distribution with respect to the implantation direction. As a result, the probability of collisions between the implanted ions and the atoms in the crystal lattice may be fairly uniform with increasing depth. However, if the implantation direction is along (or very close to) the major axes of the crystal lattice, the atoms in the crystal lattice may be "aligned" with respect to the implantation direction. When the atoms are aligned in this way as viewed along the longitudinal axis of the ion beam, channels appear in the crystal lattice where the atoms are not located. When ions are implanted along these channels, the implanted ions tend to move down the channels in the crystal structure. This reduces the probability of collisions between the implanted ions and the atoms in the crystal lattice, especially near the surface of the semiconductor layer. As a result, the implantation depth of the ion implantation (and thus the depth of the superjunction structure formed by such ion implantation) can be significantly increased, achieving devices with increased breakdown voltages and good on-state resistance levels. As used herein, the term "implantation depth" refers to the depth at which the concentration of implanted dopants reaches 10 14 cm -3 This refers to the depth from the surface of the crystal below which ions are implanted.

[0034] In many, if not most, ion implantation applications, it is undesirable to increase the depth of implantation by channeling, since the depth of implantation may be greater than the desired depth of the implanted region. As a result, in silicon carbide processing, it is conventional to form a sacrificial screen layer, such as an amorphous silicon dioxide layer, over the layer to be implanted when implanting ions along or near the crystallographic axis of a semiconductor layer, and to implant ions into the semiconductor layer through the amorphous screen layer. The screen layer has the effect of randomizing the direction of the implanted ions, thereby reducing channeling effects in the lattice structure of the underlying layer.

[0035] Generally, channeling occurs in silicon carbide when the implantation direction is within about 2° of the crystallographic axes of the silicon carbide crystal, and especially when the implantation direction is within + / - 1° of the crystallographic axes. When the implantation direction is offset from the crystallographic axes by more than + / - 1°, the channeling effect is significantly reduced, and when the implantation direction is offset from the crystallographic axes of the silicon carbide crystal by more than about 2°, the atoms in the crystal lattice may appear randomly distributed relative to the implantation direction.

[0036] In accordance with some embodiments of the present invention, there is provided a power semiconductor device having a superjunction drift region formed by implanting ions along a <11-23> crystal axis or along a symmetrically equivalent crystal axis (i.e., one of the <11-23> crystal axis, the <-1-123> crystal axis, the <1-213> crystal axis, the <-12-13> crystal axis, the <2-1-13> crystal axis, and the <-2113> crystal axis). Each of these six crystal axes is <0001> The superjunction drift region may include alternating pillars that are relatively heavily doped with p-type and n-type impurities. Because the pillars may have a relatively high doping density, the on-state resistance of the semiconductor device may be significantly reduced. Also, the drift region may be made thicker, which may increase the breakdown voltage of the device. Thus, semiconductor devices according to embodiments of the present invention may exhibit higher breakdown voltages than conventional devices while also having lower drift region resistances when the devices are in their on-state.

[0037] According to a further embodiment, a semiconductor device is provided that includes a 4H silicon carbide drift region having an upper portion and a lower portion. A first contact is formed on the upper portion of the drift region and a second contact is formed on the lower portion of the drift region. The drift region includes a superjunction structure that includes a pn junction that is formed at an angle between 6° and 35° from a plane perpendicular to a top surface of the drift region. In other embodiments, the angle may be between 10° and 30° from a plane perpendicular to a top surface of the drift region. In yet other embodiments, the angle may be between 14° and 20° from a plane perpendicular to a top surface of the drift region. In yet another embodiment, the angle may be between 6° and 15° from a plane perpendicular to a top surface of the drift region. The pn junction extends within + / - 1.5° of a crystal axis of the 4H silicon carbide material forming the drift region.

[0038] According to a further embodiment, a semiconductor device is provided that includes a 4H silicon carbide drift region having an upper portion and a lower portion, a first contact is formed on the upper portion of the drift region and a second contact is formed on the lower portion of the drift region, the drift region includes a first pillar doped with an impurity of a first conductivity type, the first pillar having: <0001> The semiconductor device has a first sidewall that is inclined at an angle of 15.5° to 18.5° from the crystal axis. The drift region is provided with a second pillar that is doped with impurities of a second conductivity type opposite to the impurities of the first conductivity type. The first and second pillars may be adjacent to each other.

[0039] According to yet another embodiment, a semiconductor device is provided that includes a 4H silicon carbide drift region having an upper portion and a lower portion. A first contact is formed on the upper portion of the drift region, and a second contact is formed on the lower portion of the drift region. The drift region includes a superjunction structure including a first pillar doped with impurities of a first conductivity type, the first pillar having a first sidewall tilted at an angle of -1.5° to 1.5° from a <11-20> crystal axis. The drift region further includes a second pillar adjacent to the first pillar and doped with impurities of a second conductivity type opposite the first conductivity type, the second pillar having a first sidewall tilted at an angle of -1.5° to 1.5° from the <11-20> crystal axis.

[0040] Also provided are methods of forming the aforementioned semiconductor devices, according to which dopant impurities are implanted into selected portions of a top surface of a drift region of the semiconductor device at an angle within + / - 1.5° of either the <11-23> crystal axis (or a symmetrically equivalent crystal axis) or the <11-20> crystal axis to form one or more pillars of a superjunction structure within the drift region.

[0041] Example embodiments of the present invention will now be described with reference to the accompanying drawings, in which it will be appreciated that the features of the different embodiments disclosed herein may be combined in any manner to provide many further embodiments.

[0042] FIG. 2 is a schematic diagram showing the relative positions of various crystallographic axes in 4H silicon carbide. As shown in FIG. 2, the <10-10> crystallographic axis is <0001> The <11-20> crystal axis is perpendicular to the <11-23> crystal axis. <0001> The <11-23> axis is perpendicular to the <11-20> axis. <0001> It is offset from the crystal axis by approximately 17°.

[0043] FIG. 3A to FIG. 3C are <0001> 3A shows the lattice structure of 4H silicon carbide along the <11-23>, <11-20> and <11-23> crystal axes, respectively. As shown in FIG. 3A, the atomic density at the surface (atoms are represented by small circles in FIG. 3A) is relatively low, which is a favorable condition for deeper ion implantation depths. There are multiple channels between the atoms, which allow channeling of the implanted ions to a relatively deep depth into the semiconductor material. However, the channels themselves have a relatively small cross-sectional area. Relatively speaking, the smaller the cross-sectional area of ​​the channels, the shallower the implantation depth. Thus, <0001> Although ion implantation along the crystal axis achieves channeling, the achievable implantation depth is still limited.

[0044] Figure 3B shows the lattice structure of 4H silicon carbide viewed along the <11-23> crystal axis. The lattice structure appears the same as shown in Figure 3B when viewed along any of the <-1-123> crystal axis, the <1-213> crystal axis, the <-12-13> crystal axis, the <2-1-13> crystal axis, and the <-2113> crystal axis. Considering the hexagonal lattice of 4H silicon carbide, all six of the crystal axes listed above are <0001> They are offset from the crystal axis by 17 degrees and are spaced apart from each other in 60 degree increments. <0001> A vector offset 17 degrees from the crystal axis forms a cone that rotates through 360 degrees. The <11-23>, <-1-123>, <1-213>, <-12-13>, <2-1-13>, and <-2113> crystal axes all extend along this cone and are spaced 60 degrees apart from each other. At the maximum rotation angle around this cone, the lattice structure appears "overcrowded" with atoms packed closely together throughout. However, as shown in connection with FIG. 3B, at six different positions corresponding to the <11-23>, <-1-123>, <1-213>, <-12-13>, <2-1-13>, and <-2113> crystal axes, the atoms "align" so that separate channels appear in the lattice structure. As can be seen from Figure 3B, along these six crystallographic axes the atomic density at the surface is increased compared to the example of Figure 3A, which generally results in increased scattering of ions. However, preferably the channels provided between the atoms have a larger cross-sectional area compared to the channels in the example of Figure 3A. As shown herein, this allows for increased implantation depth.

[0045] As can be seen from FIG. 3C, when 4H silicon carbide is viewed along the <11-20> crystal axis, the atomic density at the surface is very low, resulting in channels with large cross-sectional areas in the lattice structure. Such a structure may allow for very deep implantation depths. Unfortunately, however, the <11-20> crystal axis is generally nearly perpendicular to the major surface of the silicon carbide wafer when the wafer is cut in a conventional manner, and therefore it may be difficult to provide silicon carbide wafers having major surfaces along the <11-20> crystal axis or at a relatively small inclination from the <11-20> crystal axis. Thus, ion implantation along the <11-20> crystal axis may not be an option for many applications.

[0046] Figure 4 shows the results of a 60 keV implant. 271 is a graph of data obtained by secondary ion mass spectrometry (SIMS) showing implanted dopant concentration in 4H silicon carbide with respect to Al ions, where the ions are <0001> , <11-23> and <11-20> crystal axes. Identical results to those shown for the <11-23> crystal axis in FIG. 4 are expected for implantation along any of the <-1-123>, <1-213>, <12-13>, <2-1-13> and <-2113> crystal axes. As shown in FIG. 4, dopant ions are <0001> When implanted along a crystal axis, the dopant concentration falls off relatively rapidly with depth into the implanted layer, and the dopant concentration is reduced by three orders of magnitude from the surface dopant at a depth of about 0.8 microns. On the other hand, when dopant ions are implanted along the <11-23> crystal axis, the dopant concentration falls off more slowly, exhibiting a more uniform dopant concentration. Furthermore, the dopant concentration remains within three orders of magnitude of the surface dopant concentration to a depth of about 2.0 microns, which is <0001> 250% deeper than for ions implanted along the crystallographic axis. When dopant ions are implanted along the <11-20> crystallographic axis, the dopant concentration falls off at a very slow rate with depth within the implanted layer and remains quite uniform. In this case, the dopant concentration remains within three orders of magnitude of the surface dopant concentration to a depth of about 3.2 microns, which is <0001> 400% deeper than with ions implanted along the crystallographic axis. This data indicates that deeper implants can be achieved by implanting ions along the <11-23> crystallographic axis and / or the <11-20> crystallographic axis (or symmetrically equivalent crystallographic axes). As previously mentioned, implantation along the <11-20> crystallographic axis is not currently commercially viable for some applications. Although not shown in Figure 4, if channeling is not used, the implant concentration is 10 at a depth of approximately 0.2 microns. -2 It should be noted that in FIG. 4, ion implantation was performed at a low implant energy of 60 keV, and it is speculated that with higher implant energies (e.g., in the range of 500-900 keV), very deep implants (and therefore deep superjunction structures) can be achieved in 4H silicon carbide devices.

[0047] Conventionally, 4H silicon carbide wafers are cut from a boule of bulk 4H silicon carbide material at a small offset angle from the plane defined by the <10-10> and <11-20> crystal axes. This offset angle is often referred to as the "offcut" angle. Although the boule is sometimes cut directly along the plane defined by the <10-10> and <11-20> crystal axes, higher quality silicon carbide epitaxial layers can generally be grown when the silicon carbide wafer is cut at a small offcut angle from this plane. Offcut angles of about 2 degrees to about 8 degrees are common. Thus, for example, if a 4H silicon carbide wafer is cut at an angle of 4° from the plane defined by the <10-10> and <11-20> crystal axes and implanted along the <11-23> crystal axis (tilted toward the <11-23> crystal axis), ions should be implanted at an angle of 13° from the top surface of the wafer. A similar adjustment of the implant angle (from 17°) is required if ions are to be implanted along one of the other five crystal axes that are symmetrically equivalent to the <11-23> crystal axis.

[0048] According to an embodiment of the present invention, there is provided a power semiconductor device having a superjunction drift region formed at least in part by ion implantation. In some embodiments, the dopant ions used to form the n-type and / or p-type pillars of the superjunction are: <0001> The ions may be implanted along the <11-23> crystal axis or a symmetrically equivalent crystal axis at an angle of 17° from the crystal axis. This is illustrated in relation to Figures 5A and 5B, which are plan and side views of a 4H silicon carbide wafer 50 having an epitaxially grown 4H silicon carbide layer 52 formed thereon. As shown in Figures 5A-5B, ions are implanted into at least a portion of the epitaxial layer 52 using an ion implantation device. In the example of Figures 5A-5B, the wafer 50 is cut at an angle of 4° from the plane defined by the <10-10> and <11-20> crystal axes (tilted towards the <11-23> crystal axis), as shown diagrammatically in Figure 5B. The top surface of the wafer 50 is cut at an angle of 4° from the plane defined by the <10-10> and <11-20> crystal axes (tilted towards the <11-23> crystal axis). ... <0001> The wafer 50 is tilted at an angle of 13° relative to the ion implantation device 54 so that the epitaxial layer 52 is implanted (at an implantation angle of 17° from the crystal axis). As shown in FIG. 5A, the wafer 50 is rotated relative to the ion implantation device 54 to one of six positions 56-1 to 56-6, where channels appear in the crystal lattice when viewed along the implantation axis (as previously described, these channels appear along the <11-23> crystal axis, the <-1-123> crystal axis, the <1-213> crystal axis, the <-12-13> crystal axis, the <2-1-13> crystal axis, and the <-2113> crystal axis). To align the wafer 50 with the implantation beam, Rutherford backscattering can be used to precisely control the implantation angle (e.g., to a resolution of 0.1°). Although not shown in FIGS. 5A-5B, an implantation mask may be provided on the epitaxial layer 52 to define the regions of the epitaxial layer 52 that are to be implanted. Ions may be implanted directly into epitaxial layer 52 through the openings in the mask without first passing through a screen layer.

[0049] One result of implanting the wafer at an angle to the top surface of the wafer is that the n-type and p-type pillars of the superjunction structure are formed at an angle to the top surface of epitaxial layer 52. This feature of devices according to certain embodiments of the invention is described in further detail with reference to Figures 6A-6C and 7A-7C.

[0050] Referring first to Figures 6A-6C, Figures 6A and 6B are plan views of a 4H silicon carbide structure 100 including a 4H silicon carbide substrate 102 on which a 4H silicon carbide epitaxial layer 104 has been grown. The substrate 102 is cut at an angle of 4° from the plane defined by the <10-10> and <11-20> crystal axes, where the wafer is tilted 4° toward the <11-23> crystal axis. Figure 6C is a cross-sectional view taken along line 6C-6C of Figure 6B. As shown in Figure 6A, a first mask 110 is formed on the upper surface of the epitaxial layer 104, the first mask 110 having elongated openings 112 formed therein. N-type dopants are selectively implanted into the epitaxial layer 104 through the openings 112 in the first mask 110. As shown in Figure 6B, in a subsequent processing step, the first mask 110 is removed and a second mask 120 having elongated openings 122 is formed on the top surface of the epitaxial layer 104. P-type dopants are selectively implanted into the epitaxial layer 104 through the openings 122 in the second mask 120. The second mask 120 may cover the areas of the epitaxial layer 104 exposed by the first mask 110 so that an ion implantation step can form alternating n-type and p-type pillars in the epitaxial layer 104. Each mask 110, 120 may cover the entire surface of the epitaxial layer 104 except for the areas under the openings 112, 122. An arrow 130 is provided in each of Figures 6A-6C to indicate the direction of implantation. As shown, in the example of Figures 6A-6C, the implant direction is approximately perpendicular to the elongated openings 112, 122 in the masks 110, 120. The ions are implanted at an angle of 13° to the top surface of the epitaxial layer 104.

[0051] In the cross-sectional view of Figure 6C, the second mask 120 is not shown for simplicity. As can be seen in Figure 6C, when n-type dopants are implanted into the epitaxial layer 104, n-type pillars 140 are formed in the epitaxial layer 104. These n-type pillars 140 extend through the epitaxial layer 104 at an angle such that the dopant ions are implanted at an angle of 13° to the top surface of the epitaxial layer 104, and thus the n-type dopants penetrate below the masked areas. Similarly, when p-type dopants are implanted into the epitaxial layer 104, the p-type dopants form p-type pillars 150 in the epitaxial layer 104. The p-type pillars 150 also extend through the epitaxial layer 104 at an angle. The angled nature of the n-type and p-type pillars 140, 150 is readily apparent in the cross-section of Figure 6C. Regions 106 of epitaxial layer 104 that are not implanted may be, for example, lightly doped n-type or undoped.

[0052] It will be appreciated that the orientation of the elongated openings 112, 122 in the masks 110, 120 can be rotated relative to the position of the ion implantation equipment since the elongated openings 112, 122 in the masks 110, 120 can be formed in any selected orientation. Figures 7A-7C show pillar structures in another structure 100' including a 4H silicon carbide substrate 102' on which a 4H silicon carbide epitaxial layer 104' is grown. In the case of Figures 7A-7C, the implant angle is rotated 90° relative to the implant angle shown in the case of Figures 6A-6C. In particular, Figure 7A shows a top view of a 4H silicon carbide structure 100' having a mask 110' thereon that includes elongated openings 112'. Structure 100' includes a substrate 102' cut at an angle of 4° from the plane defined by the <10-10> and <11-20> crystal axes, where the wafer is tilted 4° toward the <11-23> crystal axis. Arrow 130' in FIG. 7A indicates the implantation direction. As shown, implantation direction 130' is parallel to the longitudinal axis of elongated opening 112' in mask 110'.

[0053] 7B and 7C are cross-sectional views taken along lines 7B-7B and 7C-7C, respectively, of FIG. 7A. As shown in FIG. 7B, each n-pillar 140' of epitaxial layer 104' has a sloped end. Although not shown, each p-pillar 150' has the same shape. The slope of the end of each pillar 140', 150' can also be seen in FIG. 7C, which is a cross-sectional view just beyond the respective ends of elongated apertures 112'. As shown in FIG. 7C, the bottoms of pillars 140', 150' extend into the cross-section due to the 13° implant angle relative to the top surface of epitaxial layer 104', while the top of epitaxial layer 106' along the cross-section is undoped.

[0054] Thus, as indicated by the previous discussion, the n-type and p-type pillars do not have to be sloped. In some cases, the sidewalls of the pillars may be sloped with respect to the top surface of the epitaxial layer 104, as shown in Figures 6A-6C. In other cases, the endwalls of the pillars may be sloped, as shown in Figures 7A-7C. Although not shown in the figures, it will be appreciated that in other cases where the implant direction is between the directions 130, 130' shown in the previous examples, both the sidewalls and endwalls of the pillars may be sloped. In either case, such pillars are referred to herein as "slanted pillars."

[0055] The use of channeling to increase ion implantation depth not only allows for deeper implants, but can also reduce the lateral distribution of the implant, resulting in better process control and smaller feature sizes. Additionally, a much thinner implant mask may be used when channeled ion implants are performed, since the implant energy may be lower than would otherwise be required to achieve a similar implant coverage. In some cases, the implant mask may be less than half the thickness that would otherwise be required to obtain a similar implant coverage.

[0056] For example, to achieve a junction depth of 3.5 microns in 4H silicon carbide without channeling, it may be necessary to perform the implant with an implant energy of 5 MeV. At such implant energies, a SiO2 mask having a thickness of 5.0 microns is typically used to ensure that ions are implanted only in unmasked regions. If the implant energy is reduced to 750 keV, a SiO2 mask having a thickness of about 2.0 microns may be used. It is believed that with channeling techniques according to embodiments of the present invention, significantly smaller implant energies can be used (i.e., implant energies of less than 100 kEV may be sufficient to achieve an implant depth of 3 microns or more). Thus, in some embodiments, the ion implant mask may be significantly thinner than a mask used with a non-channeling implant to achieve a similar implant depth, and the use of such a thinner mask can reduce device fabrication time and manufacturing costs.

[0057] Another possible consequence of the tilted pillars shown in Figures 6C, 7B, and 7C above is that the tilted geometry can perturb the symmetry of the device (compared to conventional superjunction structures), potentially reducing the breakdown field, for example, at corner regions of the device. <0001> It was found that good electric field symmetry could be achieved using an implant angle of 13° from the crystal axis.

[0058] FIG. 8 is a schematic cross-sectional view of a power semiconductor device in the form of a JBS diode 200 having a superjunction drift region formed using channeling ion implantation techniques in accordance with an embodiment of the present invention.

[0059] As shown in FIG. 8, the JBS diode 200 includes a substrate 210, a drift region 220 including a superjunction structure, a contact layer, a blocking junction 240, and a channel region 250.

[0060] The substrate 210 may comprise a 4H silicon carbide semiconductor wafer having an upper surface 212 and a lower surface 214. The substrate 210 may be doped with an n-type impurity (i.e., an n+ silicon carbide substrate). The impurities may include, for example, nitrogen or phosphorus. The doping concentration of the substrate 210 may be, for example, 1×10 18 atoms / cm 3 ~1×10 21 atoms / cm 3 Substrate 210 may be of any suitable thickness (eg, between 100 and 500 microns thick).

[0061] The drift region 220 may comprise, for example, a silicon carbide drift region 220 epitaxially grown on the top surface 212 of the substrate 210. In an exemplary embodiment, the drift region 220 may be between 3 and 100 microns thick. The drift region 220 includes a superjunction structure comprising at least a first n-type silicon carbide pillar 224 and a first p-type silicon carbide pillar 226. Although not shown in FIG. 8, it is understood that more than one n-type pillar 224 and / or more than one p-type pillar 226 may be provided. The number of pillars 224, 226 provided is a function of the width selected for the pillar. Typically, each n-type pillar 224 and p-type pillar 226 has the same width, although embodiments of the present invention are not so limited. The superjunction drift region 220 may be designed in some embodiments to provide charge balance between the alternating n-type pillars 224 and p-type pillars 226.

[0062] As shown in FIG. 8, n-type pillar 224 and p-type pillar 226 each comprise an inclined pillar. Each pillar 224, 226 may be inclined at an angle α with respect to the top surface of substrate 210. If JBS diode 200 is formed on a 4° offcut 4H silicon carbide wafer using the implantation orientation shown in FIGS. 6A-6C, angle α may be 13°. As previously mentioned, an implantation angle of about 13°, such that ions are implanted along the <11-23> crystallographic axis, may achieve a high level of channeling when implanting a 4H silicon carbide wafer cut at an angle of 4° from the plane defined by the <10-10> and <11-20> crystallographic axes.

[0063] Although Figure 8 shows the entire drift region as being implanted, it will be appreciated that this need not be the case. For example, in other embodiments, only the upper portion of drift region 220 may be implanted. An example of a power semiconductor device according to an embodiment of the invention having a drift region that is not implanted throughout its depth will now be described with reference to Figure 13. It will also be appreciated that the doping concentration of the implanted portion of the drift region tends to decrease with increasing distance from the top surface of the device.

[0064] 8, the contact layers include an ohmic contact layer 230 on the bottom surface 214 of the substrate 210, a cathode contact 232 on the ohmic contact layer 230, a Schottky contact layer 234 on the top surface of the drift region 220, and an anode contact 236 on the Schottky contact layer 234. The ohmic contact layer 230 may comprise a material that forms an ohmic contact to the substrate 210. For example, if the substrate 210 comprises a highly doped n-type silicon carbide substrate 210, the ohmic contact layer 230 may comprise a silicon / cobalt layer. The cathode contact 232 may comprise a highly conductive metal contact, such as a silver layer. In some embodiments, the cathode contact 232 may comprise a multi-layer metal structure, such as a Ti / Ni / Ag structure. In some embodiments, the substrate 210 may be partially or completely removed prior to the formation of the ohmic contact layer 230 and the cathode contact 232.

[0065] The Schottky contact layer 234 may comprise a conductive layer that forms a Schottky contact with the silicon carbide drift region 220. In some embodiments, the Schottky contact layer 234 may comprise a nickel layer. The anode contact 236 may comprise a highly conductive metal contact, such as an aluminum layer.

[0066] The blocking junction 240 may comprise a heavily doped p-type region on top of the drift region 220. As shown in FIG. 8, in some embodiments, the blocking junction 240 may substantially or completely cover the top surface of the p-type silicon carbide pillar 226. The blocking junction 240 may also partially cover the top surface of the n-type silicon carbide pillar 224. The blocking junction 240 may help reduce the electric field and shield the Schottky contact 234 from the electric field when the JBS diode 200 operates in a blocking state. A channel 250 may be provided between the n-type silicon carbide pillar 224 and the Schottky contact 234. Current flows through the channel 250 when the JBS diode 200 is in its on-state. The blocking junction 240 may incorporate, for example, a MOSFET, a JFET, a BJT, or a thyristor type structure to allow a controllable flow of current through the device.

[0067] The pillars 224, 226 may extend much deeper than pillars included in the superjunction structure of conventional 4H silicon carbide semiconductor devices. This is because the n-type and p-type dopants are implanted into the silicon carbide at angles that allow channeling to occur so that the dopant ions can be implanted deeper into the device, as described above with respect to Figures 3A-3C in a single ion implantation step. As described above, these deeper implants allow for faster fabrication of power semiconductor devices with thick superjunction drift layers. While the thicker drift layer increases the voltage blocking capability of the device, the superjunction structure helps reduce or eliminate any offset increase in the on-state resistance of the device that would otherwise result from increasing the thickness of the drift layer.

[0068] 9A is a schematic plan view of a power semiconductor device 300 having a super junction drift region in accordance with an embodiment of the present invention, in which the upper metallization and active structures of the device 300 have been removed to show the semiconductor pillar structure.

[0069] As shown in FIG. 9A, the semiconductor device 300 includes a semiconductor drift region 320 having a plurality of interleaved n-type and p-type silicon carbide pillars 324 and 326. In the embodiment of FIG. 9A, each n-type silicon carbide pillar 324 comprises a bar or "fin" shaped pillar extending along a first direction (y-axis direction) on the top surface of the substrate 302 (see FIG. 9B). Each p-type silicon carbide pillar 326 similarly comprises a rod-like pillar extending along a first direction (y-axis direction) on the top surface of the substrate 302. As shown, the n-type and p-type pillars 324 and 326 are arranged in an interleaved manner. Portions of the drift region 320 other than the pillars 324, 326 may comprise, for example, lightly doped n-type silicon carbide surrounding the n-type and p-type pillars 324, 326.

[0070] As also shown in FIG. 9A, multiple guard rings 360 surround the n-type and p-type silicon carbide pillars 324, 326. The guard rings 360 may comprise edge termination structures. As known to those skilled in the art, when a power semiconductor device is operated in an off-state, leakage current may begin to flow at the edges of the active areas as the voltage is increased. The leakage current tends to flow at these edge regions because the electric field crowding effect at the edges of the device may result in an increase in the electric field at these regions. As previously mentioned, if the voltage at the device is increased to a critical level beyond the breakdown voltage, the increase in the electric field may result in a sudden generation of charge carriers in the semiconductor device, leading to an avalanche breakdown. When an avalanche breakdown occurs, the current may increase rapidly and become uncontrollable, and the avalanche breakdown event may even damage or destroy the semiconductor device.

[0071] To reduce this electric field crowding (and the resulting increase in leakage current), edge termination structures such as guard rings 360 may be provided that surround some or all of the active area of ​​the power semiconductor device. These edge termination structures may be designed to spread the electric field over a larger area, thereby reducing field crowding. Guard rings are one known type of edge termination structure. As shown in FIG. 9B, which is a cross-sectional view taken along line 9B-9B of FIG. 9A, the guard rings 360 may comprise spaced p-type trenches 360 formed on top of the lightly doped n-type edge portion 328 of the silicon carbide drift region 320 that surrounds the active area of ​​the semiconductor device 300. The lighter doped n-type edge 328 of the silicon carbide drift region 320 may be doped during the growth of the drift region 320 (in which case the entire drift layer 320 begins lightly doped and then the more heavily doped n-type and p-type pillars 324, 326 are formed in the drift layer by ion implantation). Although Figures 9A and 9B show the power semiconductor device 300 using two guard rings 360 as the edge termination structure, it is understood that any suitable edge termination structure may be used. For example, in other embodiments, the guard rings 360 may be replaced by a junction termination extension. It is also understood that in some embodiments the edge termination structure may be omitted.

[0072] 9A and 9B, the n-pillars 324 are formed by ion implantation, it is understood that in other embodiments, the drift region may be grown as an n-type layer with a doping concentration consistent with the desired doping for the n-pillars, and the p-pillars may then be formed by ion implantation. FIG. 10 is a schematic plan view of a power semiconductor device 400 having a superjunction drift region 420 according to an embodiment of the present invention thus formed (without overlying metallization and active structures). As shown in FIG. 10, in this embodiment, the n-pillars 424 may be directly connected to the periphery of the drift region 420, including the junction termination structure 460. This is because the drift region 420 may be uniformly doped n-type except for the portions of the drift region where p-type dopants are implanted to form the p-pillars 426.

[0073] 11 is a schematic plan view of a 4H silicon carbide wafer 480 having a number of power semiconductor devices 400' formed thereon in accordance with an embodiment of the present invention. Power semiconductor devices 400' are similar to power semiconductor devices 400 previously described, but include an additional guard ring and also have pillars formed slightly differently. It will be appreciated that any of the power semiconductor devices in accordance with an embodiment of the present invention may be used in place of power semiconductor devices 400'.

[0074] The power semiconductor devices 400' may be formed, for example, in rows and columns on a wafer 480. The wafer 480 may be cut from a boule of material such that the top surface of the wafer 480 is along a crystallographic plane that runs in the <10-10> crystallographic direction (top to bottom in the plan view of FIG. 11) and along the <11-20> crystallographic direction (left to right in the plan view of FIG. 11). Although not shown in FIG. 11, more typically, the wafer 480 is cut at a small offcut angle from this plane, for example an offcut angle of 4°. As shown in FIG. 11, the power semiconductor devices 400' may be oriented on the wafer 480 such that their rod-shaped pillars run perpendicular to the <11-20> crystallographic direction and parallel to the <10-10> crystallographic direction in some embodiments. Other orientations may be used.

[0075] As previously discussed with reference to Figures 5A-5B, the ion implantation device is set at a particular angle relative to a plane defined by a top surface of a wafer structure (e.g., a 4H silicon carbide wafer with an epitaxially grown silicon carbide drift layer thereon) that is being used to form one or more power semiconductor devices, and at a desired rotation angle about the circumference of the wafer structure. These angles are selected so that a channel exists in the crystal lattice of the wafer structure along the axis of implantation (i.e., along the direction that the ions are bombarded into the crystal lattice). However, once the ion implantation device is set at the appropriate angular relationship to the wafer structure, it will be appreciated that the ion beam is much smaller than the wafer, such that the ion implantation device can only implant a small portion of the wafer structure.

[0076] In accordance with an embodiment of the present invention, an ion implantation device may be moved in a first direction (e.g., along the <11-20> crystal axis) to implant ions at desired locations across a first "row" of a wafer structure. This is shown diagrammatically in FIG. 11 by a first row 470 illustrating areas of the wafer that may be implanted as the ion implantation device is moved along the first direction. The ion implantation device does not implant ions at all locations along this first row, but instead implants ions only at locations where the particular type of ion to be implanted is to be implanted. Once all suitable locations within the first row 470 have been implanted, the wafer may be moved in a second direction relative to the ion implantation device such that the ion implantation device can then be moved horizontally to implant ions at suitable locations across a second row, such as row 472 in FIG. 11. In this manner, all suitable areas of the wafer 480 may be implanted at the appropriate angle at which channeling occurs.

[0077] 12A-12F are schematic cross-sectional views illustrating a method of manufacturing a power semiconductor device 500 according to an embodiment of the present invention. As shown in FIG 12A, an n-type drift region 520 is epitaxially grown on a 4H silicon carbide substrate 510. In some embodiments, the drift region 520 is doped with n-type impurities, for example at 1x10 15 / cm 3 ~1x10 19 / cm 312B, a first ion implantation mask 502 may then be formed on the drift region 520, which may then be patterned, for example, by photolithography. Referring to FIG. 12C, n-type dopants may be implanted into the drift region 520 to form a plurality of n-type pillars 524. The n-type dopants may be implanted at an angle relative to the top surface of the drift region 520 to implant ions into channels that appear at a selected angle in the crystal lattice. For example, the n-type dopant ions may be implanted along the <11-23> crystal axis or along one of five other symmetrically equivalent crystal axes along which large channels are found in the lattice structure. The ion implantation techniques described above with respect to FIG. 11 may be used to implant n-type dopant ions into all regions of the wafer including the power semiconductor device 500, where the n-type dopants are implanted into the drift region to form a superjunction structure. When the n-type dopant ions are implanted at an angle to the top surface of device 500, n-type pillar 524 has a pair of sloping sidewalls (only one of which is visible in FIG. 12C).

[0078] The first ion implantation mask 502 may then be removed. Referring to FIG. 12D, a second ion implantation mask 504 may then be formed on the drift region 520, which may then be patterned, for example, by photolithography. Referring to FIG. 12E, p-type dopants may be implanted into the drift region 520 to form a number of p-type pillars 526 (only one of which is shown in FIG. 12E). The p-type dopants may also be implanted at a predefined angle relative to the top surface of the drift region 520 to implant ions into channels that appear at a selected angle in the crystal lattice. For example, the p-type dopant ions may be implanted at the same angle as the n-type dopants. The ion implantation technique described above with respect to FIG. 11 may be used to implant p-type dopant ions into all regions of the wafer including the power semiconductor device 500, where the p-type dopants are implanted into the drift region to form a superjunction structure. When p-type dopant ions are implanted at an angle to the top surface of device 500, p-type pillar 526 has a pair of sloping sidewalls (only one of which is visible in FIG. 12E). P-type pillar 526 may be in direct contact with n-type pillar 524.

[0079] The second ion implantation mask 504 may then be removed. Through these steps, a semiconductor device is formed having one or more n-type silicon carbide pillars 524 and one or more p-type silicon carbide pillars 526 that together form a superjunction structure in the drift region 520.

[0080] 12F, a heavily doped p-type region may be formed at least on top of the p-type silicon carbide pillar 526 to form a blocking junction 540. The blocking junction 540 defines a channel region 550 on top of the n-type silicon carbide pillar 524. When the semiconductor device 500 is in its on state, current flows through the channel region 550. Contact structures may also be added to the device. Referring again to FIG. 12F, the contact structure may include, for example, an ohmic contact layer 530 on the bottom surface of the substrate 510, a cathode contact 532 on the ohmic contact layer 530, a Schottky contact layer 534 on the top surface of the drift region 520, and an anode contact 536 on the Schottky contact layer 534.

[0081] Another exemplary device 600 according to an embodiment of the present invention is shown in Figure 13. The device 600 shown in Figure 13 is a power DMOSFET having various regions that may be formed by ion implantation.

[0082] As shown in FIG. 13, device 600 includes an n+ substrate 602 and approximately 1.5×10 16 cm -3 and an n-type drift layer 604 having a doping concentration of about 7×10. The drift layer 604 has a thickness of about 5 microns. 16 cm -3 and an n-type current spreading layer 606 having a doping concentration of 0.1 to 0.5 V over the drift layer 604. The drift layer 604 and the n-type current spreading layer 606 together may form the drift region of the device 600.

[0083] A p+ well region 608 is formed in the n-type diffusion layer 606, and an n+ source region 610 is formed in the p+ well region 608. The n+ source region 610 has a thickness of about 1×10 20 cm -3 Similarly, the p+ well region 608 is degenerately doped to have a doping concentration greater than about 1×10 20 cm -3The n+ source region 610 is degenerately doped to have a doping concentration greater than that of the p+ well region 608. An n-type JFET implant region 612 is formed in the n-type current spreading layer 606 adjacent to the p+ well region 608. The n-type JFET region 612 has a doping concentration greater than that of the n-type current spreading layer 606. A gate insulating layer 620 is formed on the n-type current spreading layer 606 and a gate contact 614 is formed on the gate insulating layer 620. A source contact 618 is formed on the n+ source region 610 and contacts the p+ well region 608. A drain contact 622 is formed on the substrate 602.

[0084] The device 600 further includes a deep p implant region 650 below the p+ well 608. The deep p implant region 650 has a depth of about 1×10 17 cm -3 The deep p-type implant region 650 may have a doping concentration of about 1.5 μm. The deep p-type implant region 650 may extend to a depth of about 4.5 microns into the drift region. The deep p-type layer 650 need not be very deep, but may extend completely through the n-type diffusion layer 606. The deep p-type implant region 650 may be formed by channeling ion implantation as described above. The deep p-type implant region 650 may comprise p-type pillars. The portions of the current spreading layer 606 adjacent to the deep p-type implant region 650 may comprise n-type pillars. These pillars may form a superjunction structure in the drift region. The pillars may be tilted pillars.

[0085] Due to this superjunction structure, the top end of the drift region (i.e., n-type diffusion layer 606) can be doped more heavily than would otherwise be possible in a conventional structure, allowing device 600 to have a lower on-state resistance at a given blocking voltage than would otherwise be possible.

[0086] As previously mentioned, the implant angle relative to the top surface of the 4H silicon carbide layer structure is determined by the manner in which the 4H silicon carbide wafers forming the substrate are cut from the boule. <0001> If the wafer is cut along a plane perpendicular to the <10-10> and <11-20> crystal axes, the implant angle may be about 17°. If the 4H silicon carbide wafer is cut at a 4° angle from the plane defined by the <10-10> and <11-20> crystal axes, the implant angle will be about 13° or about 21° depending on the direction of the 4° offcut (if the implant is along the <11-23> crystal axis). The implant angles at the five crystal axes symmetrically equivalent to the <11-23> crystal axis may be determined by simple geometry for such an offcut wafer. It is likewise recognized that the wafer may be cut at angles other than 4° from the plane defined by the <10-10> and <11-20> crystal axes, resulting in a corresponding change in the implant angle relative to the plane defined by the top surface of the silicon carbide layer structure. In general, the implant angle is expected to be within the range of about 6° to about 35° from the plane defined by the top surface of the silicon carbide layer structure.

[0087] FIG. 14 shows 1 cm sectional views of several 4H silicon carbide layer structures formed using ion implantation techniques according to embodiments of the present invention. -3 Winning 27 FIG. 14 is a graph of SIMS data showing the concentration of Al. The dopant ions were implanted along the <11-23> crystallographic axis. The ions were implanted with implant energies of 600 keV and 900 keV. As can be seen from FIG. 14, implantation depths of approximately 5.5 to 6.5 microns were achieved in all four cases. These implantation depths far exceed those achievable using similar implant energies and conventional techniques.

[0088] It is also understood that embodiments of the present invention are not limited to superjunction structures implemented using fin-like pillars of n-type and p-type material in the drift region. For example, Figures 15A and 15B show two further examples of superjunction structures that may be formed using channeling ion implantation techniques according to embodiments of the present invention having other shapes of p-type and n-type regions in the drift region. In particular, Figure 15A is a schematic plan view of the top surface of the drift region of a power semiconductor device 700 including a superjunction structure in the form of alternating circular rings of n-type 724 and p-type 726 material as opposed to fin-shaped pillars. Similarly, Figure 15B is a schematic pillar-schematic plan view of the top surface of the drift region of a power semiconductor device 750 including a superjunction structure in the form of multiple columnar pillars of n-type 774 and p-type 776 material formed in a checkerboard pattern. In either case, the rings or pillars may be <0001> At an angle of 17° to the crystal axis or <0001> This includes sidewalls at other angles that facilitate deep channeling of dopant ions, such as a 90° angle from the crystal axis (ie, along the <11-20> crystal axis).

[0089] Ion implantation techniques according to embodiments of the present invention may be used to form devices with superjunctions having thicknesses of, for example, 2 microns to 10, 15, 20 microns or more, with such superjunctions being formed using a single ion implantation step for each type of dopant ion being implanted. The alternating n-type and p-type pillars in the drift region may have widths of, for example, 1 micron to 50 microns. Additionally, the process may be repeated multiple times with the pillars formed at each step of the process aligned to form devices with even deeper implants. For example, after the ion implantation process shown in Figures 12A-12E is performed, another silicon carbide layer may be epitaxially grown on the first epitaxial layer. The ion implantation step may then be repeated on this second epitaxial layer to form an even thicker drift region with the superjunction structure extending throughout. This growth process and subsequent implants may be repeated an additional number of times.

[0090] FIG. 16 is a flow chart illustrating a method of fabricating a power semiconductor device having a superjunction drift region according to an embodiment of the present invention. As shown in FIG. 16, the process may begin with the formation of a 4H silicon carbide drift layer doped with impurities having a first conductivity type on a 4H silicon carbide substrate (block 790). The drift layer may be formed, for example, by epitaxial growth. In some embodiments, the silicon carbide substrate may be an off-cut silicon carbide wafer that is cut at an angle of, for example, 2° to 8° from a plane defined by the <10-10> and <11-20> crystal axes of the silicon carbide substrate. In some embodiments, the silicon carbide substrate may be off-cut at other angles, or may alternatively be cut along a plane defined by the <10-10> and <11-20> crystal axes.

[0091] Next, impurities having a second conductivity type opposite the first conductivity type are implanted into selected portions of the drift layer (block 795). The drift layer may have a flat top surface, and the impurities may be implanted into selected portions of the flat top surface of the drift layer using an ion implantation mask. The impurities may be implanted at an angle that is within + / - 1.5° of the <11-23> crystal axis or one of five other symmetrically equivalent crystal axes to facilitate deep channeling of the dopant ions of the second conductivity type. This implantation step may form at least one pillar of the second conductivity type in the drift layer that is part of the superjunction structure. The pillar of the second conductivity type may have sidewalls that are sloped with respect to the top surface of the 4H silicon carbide drift layer.

[0092] While the above embodiment examples describe certain preferred ion implantation angles that may result in deep channeling of dopant ions, it is understood that other angles that may also result in such channeling may be used. For example, at the rotation angle about the aforementioned cone defined by an angle of 17° at the midpoint between the aforementioned six crystal axes at which the channel shown in FIG. 3B above is formed, <0001> It is believed that some channeling occurs when implantation is performed at an angle of 17° from the crystal axis, and it is understood, therefore, that the present disclosure is not limited to the implantation angles specifically identified above.

[0093] According to yet another embodiment of the present invention, different portions of a 4H silicon carbide wafer can be implanted with different rotation angles. For example, referring again to FIG. 5A, in 4H silicon carbide there are six symmetrically equivalent crystal axes with a lattice structure that appears as shown in FIG. 3B. In some embodiments, different portions of the wafer may be implanted with different ones of these rotation angles. Such techniques may be used, for example, such that all of the pillars formed are tilted inward toward the center of the wafer. Since the end pillars may experience different electric fields, it may be advantageous to tilt the pillars away from the edge of the wafer.

[0094] Although embodiments of the present invention have been described with reference to example embodiments in the form of JBS diodes and power MOSFETs, it will be appreciated that other power semiconductor devices, such as Schottky diodes, JFETs, BJTs, PiN diodes, metal-semiconductor field effect transistors (MESFETs), GTOs, IGBTs, MOS-controlled thyristors, and other power semiconductor devices may be formed with a superjunction drift region according to embodiments of the present invention.

[0095] Although the preceding embodiments of the present invention have been described primarily with respect to 4H silicon carbide devices, it will be appreciated that the preceding techniques may be used with other types of silicon carbide, including 2H, 6H, 3C, and 15R silicon carbide. Thus, it will be appreciated that the implant angle may be appropriately varied for 2H and 6H silicon carbide, and that the crystallographic axis and implant angle may be appropriately varied for 3C and 15R silicon carbide. For example, the <11-23> crystallographic axis (and its equivalents) is the same as the <11-23> crystallographic axis in 4H silicon carbide. <0001> It forms an angle of 17° with the crystal axis, but is not aligned with the <11-23> crystal axis (or its equivalent crystal axis). <0001> The angle between the crystal axes is about 31.4° for 2H silicon carbide and about 11.5° for 6H silicon carbide. Thus, the aforementioned sidewalls of the various semiconductor pillars <0001> The degree to which the crystal axes are tilted may depend on the type of silicon carbide used.

[0096] As mentioned above, according to some embodiments, when 4H silicon carbide is used, the pillars formed are: <0001> The pillars may have sidewalls that are tilted at an angle of 15.5° to 18.5° from the crystal axis. If 2H silicon carbide is used instead of 4H silicon carbide, the implant angle can be changed appropriately and the pillars may have <0001> The pillars may have sidewalls that are tilted at an angle of, for example, 30° to 33° to the crystal axis. Similarly, if 6H silicon carbide is used instead of 4H silicon carbide, the implant angle can be appropriately changed and the pillars may have sidewalls that are tilted at an angle of, for example, 30° to 33° to the crystal axis. <0001> The sidewalls may be inclined at an angle of, for example, 10° to 13° relative to the crystal axes. It will thus be appreciated that the embodiments of the invention described above with respect to 4H silicon carbide are equally applicable to other types of silicon carbide with appropriate adjustments to provide different angles between the crystal axes.

[0097] For 3C silicon carbide, and using the cubic notation for the structure, <001> The 45° tilt away from the crystal axis is <110> This can result in high channeling along the crystal planes of the group. <001> The tilt of 35.3° away from the crystal axis is <111> This can result in a high degree of channeling along the crystal planes of the group. Thus, for 3C silicon carbide, the pillars <001> It may have sidewalls that are inclined at an angle of, for example, 34° to 37° or 43° to 47° to the crystal plane.

[0098] According to further embodiments of the present invention, there is provided a power silicon carbide based junction barrier Schottky (JBS) diode that may provide improved performance. The JBS diodes according to these embodiments of the present invention may have deep implanted p-type wells into which p-type dopants such as aluminum, boron, gallium, indium, etc. are implanted. In some embodiments, these p-wells may have a depth of greater than 2 microns. In other embodiments, the p-wells may have a depth of greater than 3 microns. For example, the p-wells may have a depth of 3-5 microns in some embodiments and 2-5 microns in other embodiments. The doping profile of the deep implants may be selected to provide a quasi-charge balance in the n-type drift layer of the device, thereby improving performance.

[0099] The aforementioned JBS diodes and various other power semiconductor devices according to embodiments of the present invention may be fabricated using a multi-step channeling ion implantation technique to form deeply implanted regions having a unique desired doping profile. These devices formed using these techniques may be silicon carbide power semiconductor devices in some embodiments. These power semiconductor devices according to embodiments of the present invention may achieve improved performance, such as reduced power loss, lower leakage current, and / or improved reverse breakdown voltage performance, as compared to conventional power semiconductor devices. In some embodiments, the devices may be formed using a two-step ion implantation process in which ions are implanted using a channeling technique in at least one of the two ion implantation steps. A first step of the multi-step ion implantation process may implant ions at a relatively high implantation energy, while a second step of the multi-step ion implantation process may implant ions at a lower implantation energy. Using this technique, a desired implantation profile may be achieved that improves device performance.

[0100] These embodiments of the invention will now be described in more detail with reference to Figures 17 to 27.

[0101] FIG. 17 is a cross-sectional view of a power semiconductor device in the form of a JBS diode 800. As shown in FIG. 17, the JBS diode 800 includes a cathode contact 820, an ohmic contact layer 822, an n-type substrate 824, a drift region 830, a plurality of p-type blocking junctions 840 that define a channel region 846, a Schottky contact 842, and an anode contact 844. The n-type substrate 824 may comprise a silicon carbide substrate that is heavily doped with n-type impurities such as nitrogen or phosphorus. The drift region 830 may be an epitaxially grown n-type silicon carbide semiconductor region. The cathode contact 820 and the anode contact 844 may each comprise a highly conductive metal layer. The Schottky contact 842 may comprise a layer that forms a Schottky junction with the drift region 830, and may comprise, for example, a titanium layer. Ohmic contact layer 822 may comprise a metal that forms an ohmic contact to n-type silicon carbide to form an ohmic contact to silicon carbide substrate 824. P-type blocking junction 840 may comprise a p-type implanted region on top of drift region 830 that is heavily implanted with p-type dopants. Channel region 846 is located adjacent p-type blocking junction 840. Channel region 846 conducts current when JBS diode 800 is in its forward on state and blocks voltage when JBS diode 800 is in its reverse blocking state.

[0102] Figure 18 is a graph showing the forward (on-state) current-voltage (IV) characteristics of the JBS diode 800 of Figure 17. As shown in Figure 18, a JBS diode has a turn-on voltage or "knee" voltage of approximately 0.9 volts, which is the forward voltage at which the JBS diode 800 begins to conduct current. The power dissipated in the JBS diode 800 is a function of this knee voltage.

[0103] It may be desirable to reduce the power loss of the JBS diode 800. Since the power loss varies linearly with voltage, one possible means to reduce the power loss is to reduce the knee voltage. It has been found that the knee voltage of the silicon carbide power JBS diode 800 of FIG. 17 can be reduced by using tantalum instead of titanium to form the Schottky contact 842. In particular, as also shown in FIG. 18, when the JBS diode 800 is formed with a tantalum Schottky contact 842, the knee voltage can be reduced to about 0.6 volts. This reduction in the knee voltage can potentially result in significantly less power loss.

[0104] Unfortunately, however, when the tantalum Schottky contact 842 is used, the reverse leakage current of the JBS diode 800 increases significantly, especially at higher temperature levels. This occurs because tantalum has a lower Schottky barrier height compared to titanium, and this reduction in Schottky barrier height allows for an increase in the reverse leakage current, especially when the device is operating at high temperatures. The reverse leakage performance of the JBS diode 800 with the tantalum Schottky contact 842 is shown in FIG. 19. As can be seen in FIG. 19, at 25° C., the JBS diode 800 with the tantalum Schottky contact 842 exhibits a reverse blocking voltage of over 800 volts, which is acceptable for many applications. However, when the temperature is increased to 100° C., the reverse blocking voltage is reduced to about 650 volts. Furthermore, when the temperature is increased to 150° C., the reverse blocking voltage is only about 500 volts. Conversely, the JBS diode 800 with the titanium Schottky contact 842 exhibits a reverse breakdown voltage of over 800 volts at 150° C. Thus, while the use of tantalum Schottky contacts 842 can advantageously reduce the knee voltage of the JBS diode 842, the associated reduction in Schottky barrier height results in an unacceptable increase in reverse leakage current and, therefore, a reduction in the reverse blocking voltage of the device.

[0105] One technique that can be used to reduce the reverse leakage current and therefore increase the reverse breakdown voltage is to increase the depth of the implanted p-type blocking junction 840 formed in the top surface of the drift region 830 below the Schottky contact 842. The use of a deeper implanted p-type blocking junction can shield the Schottky interface (i.e., the junction between the Schottky contact 800 and the underlying semiconductor regions 840, 846) from high electric fields during reverse bias operation, thereby allowing the use of a tantalum Schottky contact 842 that has a lower Schottky barrier height compared to titanium, aluminum, or other Schottky contact metals used in conventional devices. However, the use of a deeper implanted p-type blocking junction can introduce two additional problems. First, a deeper blocking junction can increase the on-state resistance of the device 800, which acts to increase power losses. Second, a deeper p-type blocking junction may reduce the effective depth of the drift region 830, which can reduce the reverse breakdown voltage of the JBS diode 800.

[0106] According to an embodiment of the present invention, a deep p-type implant may be performed to form a p-type blocking junction, where the implant region has a doping profile that may be carefully selected to achieve quasi-charge balance with respect to the n-type drift region. In this manner, a superjunction structure may be formed in the drift region. The superjunction structure may act like a series of pn junctions that exhibit low resistance while still maintaining a high reverse breakdown voltage. The superjunction structure may be formed to extend only partially through the drift region to avoid a possible reduction in reverse breakdown voltage that may occur if the thickness of the drift region is effectively greatly reduced by the superjunction structure. Such an embodiment of the present invention will now be described in more detail with reference to Figures 20-22.

[0107] In particular, Figure 20 is a schematic plan view of a JBS diode 900 according to an embodiment of the invention with the upper metal layer omitted to better show the structure of the underlying semiconductor layers. Figure 21 is a cross-sectional view of the JBS diode 900 of Figure 21 along line II with the upper metal layer included in the view of Figure 21. Figure 22 is a cross-sectional view of the JBS diode 900 of Figure 20 along line II showing the doping concentration throughout the device. The upper metal layer is also included in Figure 22 for clarity.

[0108] 20 and 21, a JBS diode 900 includes a cathode contact 920, an ohmic contact layer 922, an n-type substrate 924, a drift region 930, a plurality of p-type blocking junctions 940 that define a channel region 946, a Schottky contact 942, and an anode contact 944. The cathode contact 920, the ohmic contact layer 922, the substrate 924, the drift region 930, and the anode contact 944 are identical to their corresponding elements in the JBS diode 800 of FIG. 17 and will not be described further. The JBS diode 900 also includes a guard ring 950 that serves as an edge termination for protection against avalanche breakdown.

[0109] The JBS diode 900 differs from the JBS diode 800 in that in some embodiments it may include a tantalum Schottky contact 942. As previously discussed, the use of such a tantalum Schottky contact 942 may reduce the knee voltage of the diode 900, thereby resulting in a lower power loss level during forward on-state operation. Additionally, the JBS diode 900 includes a p-type blocking junction 940 that extends further into the drift region 930 and has a different doping profile. As a result of the deeply implanted p-type blocking junction 940, the channel region 946 of the JBS diode 900 differs from the channel region 846 of the JBS diode 800 in that the channel region 846 may extend several times further into the drift region 930. Although guard rings are not shown in the JBS diode 800, it will be appreciated that the guard ring 950 included in the JBS diode 900 may extend deeper into the drift region 930 than any corresponding guard ring in the JBS diode 800.

[0110] FIG. 22 is a schematic cross-sectional view along line II of FIG. 20 showing the doping profile of the p-type blocking junction 940 and guard ring 950. In FIG. 22, the p-type regions correspond to the cross-hatched regions, where three different types of cross-hatching are used to indicate regions of high, medium, and low doping concentrations. It can be seen that FIG. 22 is schematic in nature and that the regions of different doping concentrations do not change abruptly as suggested in FIG. 22, but instead change gradually. Similarly, it can be seen that the p-type dopants are present in low concentrations in the n-type regions due to scattering during ion implantation and / or due to diffusion. It can therefore be seen that FIG. 22 is schematic in nature and is provided to show the general shape and doping concentration of the p-type regions, as opposed to being an absolutely precise representation of the doping concentrations.

[0111] 22, at the top of the drift region 930, the implanted p-type blocking junction 940 can have a high p-type dopant concentration. For example, in some embodiments, the top of the implanted p-type blocking junction 940 can have a high p-type dopant concentration of 5×10 17 cm -3 The upper portion of each p-type blocking junction having a relatively high doping concentration may extend, for example, from about 0.5 to about 1.5 microns into the drift region 830 from the upper surface of the drift region 830. The lower portion of the p-type blocking junction 940 below the upper portion may have a doping concentration that is adapted to at least quasi-balance the charge of the adjacent n-type portion of the drift region 930. This doping concentration may be significantly lower than the doping concentration of the upper portion of the p-type blocking junction 940. For example, in some embodiments, the lower portion of the p-type blocking junction 940 may have a doping concentration that is at least 100 times lower than the doping concentration of the upper portion of the p-type blocking junction 940. In other embodiments, the lower portion of the p-type blocking junction 940 may have a doping concentration that is at least 1000 times lower than the doping concentration of the upper portion of the p-type blocking junction 940. In some cases, the lower portion of the p-type blocking junction 940 may have a doping concentration that is at least 1×10 17 cm -3 In one example embodiment, the top of each p-type blocking junction 940 may have a doping concentration of less than 1×10 18 cm -3 and the bottom of each p-type blocking junction 940 may have a doping concentration greater than 7×10 16 cm -3 In one particular embodiment, the top of each p-type blocking junction 940 may have a doping concentration of less than 2×10 18 cm -3 and the bottom of each p-type blocking junction 940 may have a doping concentration of about 3×10 16 cm -3 ~about 5x10 16 cm -3 The doping concentration may be

[0112] The heavily doped upper portion of each p-type blocking junction may generate a strong electric field during reverse blocking operation that can withstand a high reverse voltage. The moderately doped lower portion of each p-type blocking junction 940 may have a doping concentration selected to achieve quasi-charge balance with the n-type channel region 946 interposed therebetween. The lower portion of the channel region 946 and the lower portion of the p-type blocking junction 940 may form a superjunction structure with a series of pn junctions that exhibit low resistance while still maintaining a high reverse breakdown voltage. The p-type blocking junction 940 extends only partially through the drift region 930. It has been found that devices having the above-described structure and doping profile may exhibit significantly improved performance, as can be seen in Figures 23-26. By "quasi-charge balance" it is meant that the charge of the p-type blocking junction 940 is approximately equal to the charge of the channel region 946. It has been found that as long as these charges are roughly equal - for example, within 20% of each other - the lower part of the p-type blocking junction 940 and the channel region 946 therebetween act like a superjunction, thereby reducing the traditional trade-off between on-state resistance and reverse voltage blocking performance.

[0113] In some embodiments, the dopant profile shown in FIG. 22 may be achieved using a multi-step ion implantation process. One or more of these ion implantation steps may use channeling techniques. In some embodiments, the p-type dopant is <0001> The implant may be along the crystal axis. As mentioned above, silicon carbide wafers are typically <0001> They are cut offset as opposed to being cut at an angle perpendicular to the crystal plane. <0001> When implanted along a crystal plane, channeling occurs, allowing deeper implantation.

[0114] The dopant is added when forming the substrate. <0001> by implanting ions in a direction perpendicular to the top surface of the substrate after cutting the wafer perpendicular to the crystal planes, or by tilting the ion implantation device with respect to the substrate to compensate for off-axis cut wafers; <0001> The dopants may be implanted along the crystal axis. <0001> 23 is a graph showing dopant concentration as a function of depth in an n-type silicon carbide layer when implanted along a crystal axis. In FIG. 23, curve 960 shows dopant concentration as a function of depth for an implant energy of 100 keV, curve 962 shows dopant concentration as a function of depth for an implant energy of 300 keV, curve 964 shows dopant concentration as a function of depth for an implant energy of 500 keV, curve 966 shows dopant concentration as a function of depth for an implant energy of 700 keV, and curve 968 shows dopant concentration as a function of depth for an implant energy of 900 keV. Each of the five ion implantation processes shown in FIG. 23 implants dopant concentration as a function of depth into the n-type 4H silicon carbide drift region. 27 Al+ ions at approximately 1x10 13 cm -2 In this case, the implantation was performed at room temperature. 27 The Al+ ions act as p-type dopants in silicon carbide.

[0115] As shown in Figure 23, for each of the five implantation processes, the dopant concentration is very low near the surface, where the deeper the low dopant region extends into the drift region, the higher the implantation energy used. For example, when an implantation energy of 900 keV is used, the dopant concentration is negligible up to a depth of about 0.3 microns from the top surface of the drift region, and the dopant concentration is 1x10 to a depth of about 0.8 microns. 16 cm -3 does not reach.

[0116] The dopant concentration is very low near the surface, but the concentration rises rapidly with increasing depth. As is evident from FIG. 23, the lower the implant energy, the faster the dopant concentration rises with increasing depth. The dopant concentration peaks at the height of this rapid rise for all five implant energies, exhibiting a small localized peak, after which the dopant concentration slowly decreases over the extended depth. This characteristic of the doping profile is important, because it <0001> This is because channeling implants along the crystal axis means that it is possible to form deep implants that have a relatively constant concentration over a significant depth range. At the end of the region of relatively constant doping concentration, the dopant concentration then rapidly decreases toward zero, as can be seen on the right side of each curve in FIG.

[0117] Thus, each of the curves 960, 962, 964, 966, and 968 of FIG. 23 has a relatively flat region that exhibits relatively little variation in dopant concentration (e.g., 0-500% variation). This aspect of the implant profile can be used to create a moderately doped lower portion of each p-type blocking junction because it can have a nearly constant doping profile that quasi-charge balances the n-type channel region 946 between the lower portions of the p-type blocking junctions 940. For example, in one example embodiment, the implant profile is approximately 5x10 doped at a depth of about 1 micron to about 3 microns, as shown by curve 968 of FIG. 16 cm -3 A 900 keV p-type dopant implant may be performed as a first ion implantation step to form the lower portion of the p-type blocking junction 940 having a dopant concentration of about 2×10 ions. This may then be followed by a second ion implantation step using, for example, an implant energy of 100 keV. As shown in FIG. 23, this results in a dopant concentration of about 2×10 ions from just below the surface to a depth of about 1 micron. 17 cm -322. In this manner, a series of channeling implants may be used to obtain the doping profile shown in FIG. 22. Here, the term "substantially constant doping profile" means that the doping concentration varies by less than half an order of magnitude.

[0118] The multi-step channeling implantation described above with reference to FIG. 23 may have several advantages. First, the implantation may be performed at room temperature, thereby reducing manufacturing costs. Furthermore, channeling implantation may result in a significant reduction in damage to the silicon carbide crystal, since the ions penetrate deep into the crystal with a large reduction in scattering (which causes crystal damage) and are primarily slowed down and stopped in the crystal lattice due to electron cloud interactions. The p-type dopants may achieve very high activation levels, such as activation levels of over 95%, since channeling implantation facilitates more consistent ion implantation into electrically active locations in the crystal lattice. Channeling implantation allows for the formation of deep junctions with a relatively flat doping profile. This doping profile may facilitate the formation of generally charge-balanced superjunction structures deep in the drift region, which may reduce the on-resistance of the JBS diode (or other device) and may reduce the electric field strength at the Schottky junction, allowing the use of Schottky contacts with lower Schottky barrier heights. Additionally, the multi-step nature of the ion implantation process allows for the formation of a more heavily doped p-type region at the top surface of the drift region that supports high reverse blocking voltage levels.

[0119] 24 is a graph of simulated electric field strength at the Schottky junction as a function of current density for several JBS diodes having p-type blocking junctions formed using conventional ion implantation techniques and for several JBS diodes formed using the aforementioned channeling ion implantation technique according to an embodiment of the present invention. As previously mentioned, if the electric field at the Schottky junction is too high, high leakage currents can result during reverse bias operation if a Schottky contact metal such as tantalum, which has a low Schottky barrier height, is used to form the Schottky contact. As shown in FIG. 24, with conventional state-of-the-art JBS diodes, the electric field strength at the Schottky junction is 8-9x10 -6 A / micron current density is approximately 1.4x10 6 V / cm. Meanwhile, at the same current density, the electric field strength at the Schottky junction in the JBS diode according to the embodiment of the present invention is about 9x10 5 V / cm~1x10 6 V / cm, or about a 40% reduction. This reduction in the electric field is sufficient to enable the use of Schottky contact metals with lower Schottky barrier heights, such as tantalum.

[0120] FIG. 25 is a graph showing forward operating IV characteristics of several JBS diodes according to embodiments of the present invention. As shown in FIG. 25, the forward on-state current-voltage characteristics result in a knee voltage of approximately 0.7 volts. FIG. 26 is a graph showing reverse blocking IV characteristics of the JBS diodes used to generate the data included in FIG. 25. As shown in FIG. 26, each device exhibits a reverse blocking voltage level of over 750 volts. Additionally, all three JBS diodes exhibit extremely low leakage current levels and very sharp breakdown characteristics, both of which are desirable.

[0121] It has also been found that the dose of the p-type implant may involve a trade-off between the forward voltage level and the reverse leakage current of the device. In particular, a higher Al dose tends to more effectively shield the Schottky interface, and thus may lower the reverse leakage current. On the other hand, a lower Al dose can further reduce the knee voltage at which the device begins to conduct during forward bias operation, thereby resulting in a lower power dissipation level.

[0122] While the previous examples have focused on JBS diodes, it will be appreciated that multi-step channeling implants according to embodiments of the present invention can be used to fabricate other devices, such as PiN diodes. It will also be appreciated that the implantation techniques discussed herein can be used to form deeply implanted termination structures, such as the deeply implanted guard ring 950 included in the JBS diode 900 of Figures 20-21. Furthermore, these techniques may also be used in other devices, such as MOSFETs, in which a deep p-well may be provided to enable a JFET region with a lower resistance. An example of such a device will now be described with reference to Figure 27.

[0123] 27 is a cross-sectional view of a unit cell 1000 of a power MOSFET according to a further embodiment of the present invention. As shown in FIG. 27, the unit cell 1000 may be implemented on a heavily doped (n+) single crystal n-type silicon carbide substrate 1010. A lightly doped (n-) silicon carbide drift region 1020 is provided on the substrate 1010. The silicon carbide drift region 1020 is typically formed by epitaxial growth on the silicon carbide substrate 1010. An n-type silicon carbide current spreading layer 1030 is formed on the n-type silicon carbide substrate 1010. - The current spreading layer 1030 is formed on the silicon carbide drift layer 1020. The current spreading layer 1030 is formed of a lightly doped n - To provide a moderately doped current spreading layer 1030 having a doping concentration that exceeds the doping concentration of the silicon carbide drift layer 1020, n -The n-type silicon carbide drift layer 1020 may be formed, for example, by epitaxial growth, after the formation of the silicon carbide drift layer 1020. A pair of spaced apart p-type silicon carbide wells 1040 ("p-wells") may then be formed on the top surface of the n-type current spreading layer 1030. The p-wells 1040 may be formed by implanting p-type ions into the upper region of the n-type current spreading layer 1030 using the multi-step channeling ion implantation technique described above. Each p-well 1040 may have a heavily doped upper portion 1042 and a more moderately doped lower portion 1044. An n-type silicon carbide JFET region 1050 may be provided in the upper central portion of the current spreading layer 1030 between the p-wells 1040, and may be formed by ion implantation.

[0124] The upper portion 1042 of each p-well 1040 may be highly doped. For example, in some embodiments, the upper portion 1042 of each p-well 1040 may be highly doped. 17 cm -3 ~1x10 20 cm -3 The lower portion 1044 of each p-well 1040 may have a doping concentration of 5×10. The lower portion 1044 of each p-well 1040 may have a moderate doping concentration. For example, in some embodiments, the lower portion 1044 of each p-well 1040 may have a doping concentration of 5×10. 16 cm -3 ~5x10 17 cm -3 The lower portion 1044 of each p-well 1040 may be quasi-charge balanced with the n-type current spreading layer 1030 to form a superjunction structure. This allows the JFET region 1050 to be more heavily doped without decreasing the on-state resistance and without increasing the electric field strength in the gate oxide. The doping concentration of the JFET region 1050 may be, for example, an order of magnitude or more greater than the doping concentration of the remainder of the current spreading layer 1030.

[0125] A heavily doped (n+) n-type silicon carbide region 1060 is formed in the upper portion 1042 of each p-well 1040. The heavily doped (n+) n-type silicon carbide region 1060 acts as a source region for the two individual transistors included in the unit cell 1000, while the current spreading layer 1030, the drift region 1020, and the substrate 1010 together act as a common drain region for the unit cell 1000. A channel region is provided in each p-well 1040 between the source region 1060 and the JFET region 1050. A gate insulating layer 1070 (e.g., a silicon oxide layer) is provided on the JFET region 1050, a portion of the p-well 1040, and a portion of the n-type silicon carbide region 1060. A semiconductor or metal gate electrode 1080 is provided on the gate insulating layer 1070. In some embodiments, a gate insulating layer 1070 may surround the gate electrode 1080 .

[0126] A source contact 1090 (e.g., a metal layer) that acts as a common source contact is provided on the n+ source regions 1060, and a drain contact 1095 (e.g., another metal layer) that acts as a common drain contact is provided on the back side of the n+ silicon carbide substrate 1000.

[0127] The above-described ion implantation technique according to embodiments of the present invention can exhibit many advantages. As previously described, the technique may be used to form p-type blocking junctions, p-wells, and other implanted regions having doping profiles that can result in improved device performance. Furthermore, the use of channeling doping techniques can result in much higher dopant activation levels, such as levels greater than 95%, which can result in more consistent and / or repeatable doping, as well as a reduced amount of time required for doping, since less dopant is required to achieve a given level of activated dopant.

[0128] While the above description describes example embodiments with respect to semiconductor devices having an n-type substrate and channel in the n-type portion of the drift layer, it is understood that devices of the opposite conductivity type can be formed simply by reversing the conductivity of the n-type and p-type layers in each of the above embodiments. It is therefore understood that the present invention covers both n-type and p-type devices. Similarly, it is understood that each power semiconductor device formed in accordance with the ion implantation techniques disclosed herein will generally comprise a plurality of individual devices arranged in parallel within a unit cell structure.

[0129] The embodiments of the present invention have been described above with reference to the accompanying drawings, in which embodiments of the present invention are shown. It is understood, however, that the present invention may be embodied in many different forms and should not be construed as being limited to the above-described embodiments. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like numbers refer to like elements throughout.

[0130] Although terms such as first, second, etc. are used throughout this specification to describe various elements, it is understood that these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, a first element can be referred to as a second element, and similarly, a second element can be referred to as a first element, without departing from the scope of the present invention. The term "and / or" includes any and all combinations of one or more of the associated listed items.

[0131] The terms used herein are for the purpose of describing particular embodiments only and are not intended to be limiting of the present invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms unless the context clearly indicates otherwise. It is further understood that the terms "comprise", "comprising", "including" and / or "comprising", when used herein, specify the presence of stated features, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof.

[0132] When an element, such as a layer, region, or substrate, is referred to as "on" or "extending into" another element, it is understood that it may be directly on or extend directly into the other element, or that intervening elements may be present. In contrast, when an element is referred to as "directly on" or "extending directly into" another element, there are no intervening elements. When an element is referred to as "connected" or "coupled" to another element, it is understood that it may be directly connected or coupled to the other element, or that intervening elements may be present. In contrast, when an element is referred to as "directly connected" or "directly coupled" to another element, there are no intervening elements.

[0133] Relative terms such as "lower" or "upper" or "upper" or "lower" or "top" or "bottom" or "horizontal" or "lateral" or "vertical" may be used herein to describe the relationship of one element, layer or region to other elements, layers or regions as shown in the figures. It is understood that these terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.

[0134] Embodiments of the present invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the present invention. The thicknesses of layers and regions in the drawings may be exaggerated for clarity. Additionally, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected.

[0135] Some embodiments of the invention are described in connection with semiconductor layers and / or regions that are characterized as having a conductivity type, such as n-type or p-type, which refers to the majority carrier concentration in the layer and / or region. Thus, n-type material has a majority equilibrium concentration of negatively charged electrons, while p-type material has a majority equilibrium concentration of positively charged holes. Some materials may be designated with a "+" or "-" (as in n+, n-, p+, p-, n++, n--, p++, p-) to indicate a relatively larger ("+") or smaller ("-") concentration of majority carriers compared to other layers or regions. However, such designations do not imply the presence of any particular concentration of majority or minority carriers within the layer or region.

[0136] In the drawings and specification there are disclosed exemplary embodiments of the invention, and although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being set forth in the following claims.

Claims

1. a drift region having a first conductivity type; a plurality of implant regions having a second conductivity type above the drift region; 1. A junction barrier Schottky (JBS) diode comprising: at least a portion of each implanted region is a channeling ion implantation implanted region, the implanted region above the drift region including a blocking junction of the JBS diode; an upper portion of each of the plurality of implanted regions having a first doping concentration and a lower portion of each of the plurality of implanted regions having a second doping concentration; the first doping concentration is greater than the second doping concentration; the lower portion of each of the plurality of implanted regions is in quasi-charge equilibrium with an adjacent portion of each of the drift regions to form a superjunction structure within the drift region. JBS diode.

2. 2. The JBS diode of claim 1, wherein the upper portion of each of the plurality of implanted regions comprises a channeling ion implantation implantation region.

3. 2. The JBS diode of claim 1, wherein the upper portion of each of the plurality of implanted regions extends 0.5 to 1.5 microns into the drift region and the lower portion of each of the plurality of implanted regions extends at least 1 micron below its respective upper portion.

4. The top portion of each of the plurality of implanted regions is at least 5×10 １７ cm －３ 2. The JBS diode of claim 1 having a doping concentration of

5. The lower portion of each of the plurality of implanted regions is 1×10 １６ cm －３ ~1x10 １７ cm －３ 2. The JBS diode of claim 1 having a doping concentration of 6. The JBS diode of claim 1, further comprising a tantalum Schottky contact.

7. the drift region comprises a silicon carbide material; 2. The JBS diode of claim 1, wherein a first sidewall of each implanted region extends within + / - 1.5 degrees of one of the following crystallographic axes of the silicon carbide material of the drift region: <11-23>, <-1-123>, <1-213>, <-12-13>, <2-1-13>, or <-2113>.

8. 2. The JBS diode of claim 1, wherein each of the plurality of implanted regions having the second conductivity type has a columnar or circular shape.

9. 2. The JBS diode of claim 1, wherein each of the implanted regions has a first sidewall and a second sidewall that are both sloped at the same angle of between 6° and 35° from a first plane that is perpendicular to a top surface of the drift region.

10. A JBS diode as described in claim 1, further comprising a substrate at a bottom surface of the drift region and having the first conductivity type at a higher doping concentration than the drift region, and the implantation region extends only partially through the drift region.

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