Optoelectronic semiconductor chips and components

Abstract

In at least one embodiment, the optoelectronic semiconductor chip (1) comprises: - a support (2); - a semiconductor layer sequence (3) of the support (2) with at least one active zone (33) for generating radiation (R); - an optical high refractive index layer (4) on a coupling-out facet (34) of the semiconductor layer sequence (3) for coupling out the radiation; - a low refractive index coating (5) directly on an outer surface (45) of the high refractive index layer (4) for total internal reflection of the radiation (R); - the semiconductor layer sequence (3) is configured to guide the radiation (R) in the active zone (33) perpendicular to a growth direction (G) of the semiconductor layer sequence (3) and - the high refractive index layer (4) is configured to deflect the radiation (R) at its outer surface (45) parallel to the growth direction (G).

Description

[Technical field]

[0001] An optoelectronic semiconductor chip is provided, as well as a component having such an optoelectronic semiconductor chip. [Background technology]

[0002] In the documents US 2009 / 0097519 and WO 2019 / 170636 semiconductor lasers are found which have obliquely oriented deflection facets. Summary of the Invention [Problem to be solved by the invention]

[0003] It is an object of the present invention to provide optoelectronic semiconductor chips and components that can be efficiently manufactured. [Means for solving the problem]

[0004] This problem is solved, inter alia, by an optoelectronic semiconductor chip and a component having the features of the independent claims. Preferred further embodiments are the subject of the dependent claims.

[0005] According to at least one embodiment, the optoelectronic semiconductor chip comprises a support. The support may be a component that mechanically carries and supports the semiconductor chip. The support may be used to electrically connect the semiconductor chip.

[0006] According to at least one embodiment, the optoelectronic semiconductor chip comprises a semiconductor layer sequence in which one or more active zones for generating radiation are arranged. The at least one active zone comprises in particular at least one pn junction and / or at least one quantum well structure. The term quantum well does not develop any sense regarding the dimensionality of the quantization. The term quantum well thus includes, for example, multidimensional quantum wells, one-dimensional quantum wires and quantum dots which are to be considered as zero-dimensional as well as any combination of these structures.

[0007] The semiconductor layer sequence is preferably based on a III-V compound semiconductor material. The semiconductor material is, for example, a nitride-based compound semiconductor material, such as Al n In 1-n-m Ga m N, or a phosphide-based compound semiconductor material, such as Al n In 1-n-m Ga m P, or similarly an arsenic compound semiconductor material, such as Al n In 1-n-m Ga m As or for example, Al n Ga m In 1-n-m As k P 1-k , and in each case, 0 ≦ n ≦ 1, 0 ≦ m ≦ 1, and n + m ≦ 1, as well as 0 ≦ k < 1. For example, 0 < n ≦ 0.8, 0.4 ≦ m < 1 and n + m ≦ 0.95 as well as 0 < k ≦ 0.5 are applied to at least one layer or all layers of the semiconductor layer sequence.

[0008] In this context, the semiconductor layer sequence can include dopants and additional components. However, for simplicity, the essential components of the crystal lattice of the semiconductor layer sequence, namely Al, As, Ga, In, N, or P, are mentioned above, and they may be partially replaced and / or supplemented by small amounts of additional substances.

[0009] Preferably, the semiconductor layer sequence is based on the material systems Al n In 1-n-m Ga m N or Al n In 1-n-m Ga m As. The radiation generated by the active zone during operation is, in particular, in the spectral region of 350 nm or more and 600 nm or less, or in the spectral region of 590 nm or more and 960 nm or less.

[0010] According to at least one embodiment, the optoelectronic semiconductor chip comprises an optical high-refractive index layer, which at least one high-refractive index layer is arranged on at least one coupling-out facet of the semiconductor layer sequence, the at least one coupling-out facet serving for a radiation outcoupling of radiation from the semiconductor layer sequence.

[0011] According to at least one embodiment, the optoelectronic semiconductor chip comprises an optical high-refractive index layer. The low-refractive index coating is preferably arranged directly on the outer surface of the high-refractive index layer, the outer surface facing away from the semiconductor layer sequence. In interaction with the high-refractive index layer, the low-refractive index coating serves for total internal reflection of radiation.

[0012] According to at least one embodiment, the semiconductor layer sequence is configured to guide radiation in the active zones perpendicular to the growth direction of the semiconductor layer sequence. For this purpose, the semiconductor layer sequence can comprise a waveguide and a surrounding cladding layer, at least one active zone being located in the waveguide. The term parallel means, for example, that the radiation is guided at an angle of at most 15° or at most 5° or at most 2° to the plane normal to the growth direction.

[0013] According to at least one embodiment, the high refractive index layer is configured to deflect radiation at an outer surface parallel to the growth direction, for example with an angular tolerance of at most 45°, or at most 15°, or at most 5°.

[0014] In at least one embodiment, an optoelectronic semiconductor chip comprises a carrier, a semiconductor layer sequence on the carrier with at least one active zone for generating radiation, an optically high refractive index layer on an out-coupling facet of the semiconductor layer sequence for out-coupling radiation, and an optically low refractive index coating directly on an outer surface of the high refractive index layer for total internal reflection of radiation. The semiconductor layer sequence is configured to guide radiation in the active zone perpendicular to the growth direction of the semiconductor layer sequence. The high refractive index layer is configured to redirect radiation at its outer surface parallel to the growth direction, the high refractive index layer and the low refractive index coating cooperating, whereby an interface between the high refractive index layer and the low refractive index coating is configured for total internal reflection of radiation.

[0015] In particular, the semiconductor chip is a surface-emitting laser with a horizontal cavity, also referred to as HCSEL. "Surface-emitting" means that the emission surface is oriented perpendicular to the growth direction of the semiconductor layer sequence, and "horizontal" can mean a direction parallel to the emission surface. The semiconductor chip described herein therefore preferably incorporates a deflection element, in particular formed from a combination of a high-refractive index layer and a low-refractive index coating, with the associated output coupling facet forming, for example, a 45° deflection prism or oriented parallel to the growth direction. The semiconductor chip can therefore be designed cost-effectively as a laser, since LED-like processes can be used in the production and no special laser processes such as scribing and breaking are required.

[0016] In addition to the extremely cost-effective wafer-level processing without the separate processes that would otherwise be required for mirror coating with lasers, many applications are possible, for example pumping of wavelength conversion materials in projection applications. Other possible applications are in the aerospace sector as well as in the automotive sector or in general lighting. Furthermore, the surface emission allows for particularly flat packages and therefore high synergies with LED packaging technology.

[0017] According to at least one embodiment, the optoelectronic semiconductor chip is a semiconductor laser, i.e., in operation, the semiconductor chip is configured to emit coherent radiation.

[0018] According to at least one embodiment, at the wavelength of maximum intensity of the radiation, the high refractive index coating has a refractive index at least 0.6, or at least 0.8, or at least 1.0 higher than the low refractive index coating, particularly at room temperature, i.e., 300K, or at the intended operating temperature of the semiconductor chip.

[0019] According to at least one embodiment, the difference in refractive index between the active zone and the high refractive index layer is at most 0.3 or at most 0.2 or at most 0.1 or at most 0.05. This is especially true at room temperature, i.e. 300 K, or at the intended operating temperature of the semiconductor chip.

[0020] According to at least one embodiment, the high refractive index layer is disposed directly on the out-coupling facet, the out-coupling facet being oriented transverse to the growth direction, for example the angle between the growth direction and the out-coupling facet is at least 15° or at least 30° and / or at most 75° or at most 60°, e.g. 45°.

[0021] According to at least one embodiment, the optoelectronic semiconductor chip further comprises one or more out-coupling mirrors directly at the out-coupling facet, where at least one out-coupling mirror is in particular a Bragg mirror.

[0022] According to at least one embodiment, the high refractive index layer is placed directly on the out-coupling mirror, with the out-coupling facets oriented parallel to the growth direction, e.g. the terms parallel or perpendicular are applied here and below in particular with an angular error of at most 15° or at most 10° or at most 5°.

[0023] According to at least one embodiment, the high-index layer is a planarization layer for the out-coupling facet and / or the out-coupling mirror. That is, the high-index layer can reduce the unevenness or roughness of the out-coupling facet. In other words, the high-index layer may be smoother and / or flatter on the surface facing away from the out-coupling facet than the out-coupling facet itself. In any case, the out-coupling facet averaged over the unevenness or roughness is preferably a flat surface.

[0024] According to at least one embodiment, the high refractive index layer is an angle correction layer relative to the out-coupling facet, so that the angle between the outer surface and the out-coupling facet is between 0.1° and 20°, or between 0.2° and 10°, or between 0.2° and 3°, i.e. the high refractive index layer allows the out-coupling direction of the radiation to be set and / or adjusted more accurately compared to the out-coupling facet itself.

[0025] According to at least one embodiment, the optoelectronic semiconductor chip further comprises a radiation-directly reflecting metallization on the side of the low refractive index coating facing away from the out-coupling facet, which makes it possible to still utilize a portion of the radiation generated in the semiconductor layer sequence that passes through the low refractive index coating.

[0026] According to at least one embodiment, the support is a growth substrate of the semiconductor layer sequence, whereby the radiation is emitted through the support.

[0027] According to at least one embodiment, the carrier is a replacement carrier to which the semiconductor layer sequence is attached by means of fastening means, i.e. it is possible to replace the growth substrate of the semiconductor layer sequence with the replacement carrier or to provide the replacement carrier in addition to the growth substrate, in which case radiation can be emitted away from the carrier, in particular away from the replacement carrier, due to the outer surface.

[0028] According to at least one embodiment, the carrier has a recess with respect to the semiconductor layer sequence, whereby the carrier has a support surface facing the out-coupling facet, in which case a low refractive index coating can be applied to the support surface and the high refractive index layer can rest on the low refractive index coating.

[0029] According to at least one embodiment, the semiconductor layer sequence, viewed in plan and in at least one area not having an active zone, is attached to the low refractive index coating deposited on the substrate by fastening means, which can be based on at least one metal.

[0030] According to at least one embodiment, the further facet of the semiconductor layer sequence which is located opposite the coupling-out facet is oriented obliquely to the growth direction or the further facet is oriented parallel to the growth direction.

[0031] According to at least one embodiment, the further support surface assigned to the further facet is oriented parallel to the growth direction, so that the further support surface is configured to reflect a radiation component of the radiation reaching the further support surface from the active zone back to the active zone.

[0032] According to at least one embodiment, the optoelectronic semiconductor chip further comprises an optical system for beam correction of the beam. The optical system is arranged, for example, completely or partially above the outer surface in plan view. In plan view, the optical system may be larger than the outer surface. It is possible to manufacture the optical system from the support.

[0033] Further disclosed is a component having at least one optoelectronic semiconductor chip as described in connection with one or more of the above embodiments. Accordingly, features of components for optoelectronic semiconductor chips are also disclosed, and vice versa.

[0034] In at least one embodiment, the component includes a plurality of optoelectronic semiconductor chips and a mounting platform, the semiconductor chips being mounted on the mounting platform and optics of the semiconductor chips aligning the directions of radiation of the semiconductor chips with respect to one another.

[0035] In the following, the optoelectronic semiconductor chip described herein and the components described herein will be described in more detail with reference to the drawings based on exemplary embodiments. The same reference numerals indicate the same elements in the individual drawings. However, no reference is made to scale, but rather individual elements may be shown exaggeratedly large for better understanding. [Brief description of the drawings]

[0036] [Figure 1] 1 shows a schematic cross-sectional view parallel to the longitudinal cavity direction of an exemplary embodiment of an optoelectronic semiconductor chip as described herein. [Diagram 2] 2A-2D show schematic cross-sectional views of process steps for manufacturing the optoelectronic semiconductor chip of FIG. [Diagram 3] 2A-2D show schematic cross-sectional views of process steps for manufacturing the optoelectronic semiconductor chip of FIG. [Figure 4] 2A-2D show schematic cross-sectional views of process steps for manufacturing the optoelectronic semiconductor chip of FIG. [Diagram 5] 2A-2D show schematic cross-sectional views of process steps for manufacturing the optoelectronic semiconductor chip of FIG. [Figure 6] 1 illustrates a schematic cross-sectional view of an exemplary embodiment of an optoelectronic semiconductor chip as described herein; [Figure 7] 1 illustrates a schematic top view of an exemplary embodiment of an optoelectronic semiconductor chip as described herein. [Figure 8] 1 illustrates a schematic top view of an exemplary embodiment of an optoelectronic semiconductor chip as described herein. [Figure 9] 1 illustrates a schematic top view of an exemplary embodiment of an optoelectronic semiconductor chip as described herein. [Figure 10] 1 illustrates a schematic top view of an exemplary embodiment of an optoelectronic semiconductor chip as described herein. [Figure 11] 1 illustrates a schematic top view of an exemplary embodiment of an optoelectronic semiconductor chip as described herein. [Figure 12] 1 illustrates a schematic top view of an exemplary embodiment of an optoelectronic semiconductor chip as described herein. [Figure 13] 1 illustrates a schematic top view of an exemplary embodiment of an optoelectronic semiconductor chip as described herein. [Figure 14] 1 illustrates a schematic top view of an exemplary embodiment of an optoelectronic semiconductor chip as described herein. [Figure 15] 1 illustrates a schematic top view of an exemplary embodiment of an optoelectronic semiconductor chip as described herein. [Figure 16] 1 illustrates a schematic top view of an exemplary embodiment of an optoelectronic semiconductor chip as described herein. [Figure 17] 1A-1D show schematic cross-sectional views of process steps for fabricating an exemplary embodiment of an optoelectronic semiconductor chip as described herein. [Figure 18] 1A-1D show schematic cross-sectional views of process steps for fabricating an exemplary embodiment of an optoelectronic semiconductor chip as described herein. [Figure 19] 1A-1D show schematic cross-sectional views of process steps for fabricating an exemplary embodiment of an optoelectronic semiconductor chip as described herein. [Figure 20] 1A-1D show schematic cross-sectional views of process steps for fabricating an exemplary embodiment of an optoelectronic semiconductor chip as described herein. [Figure 21] 1A-1D show schematic cross-sectional views of process steps for fabricating an exemplary embodiment of an optoelectronic semiconductor chip as described herein. [Figure 22] 1A-1D show schematic cross-sectional views of process steps for fabricating an exemplary embodiment of an optoelectronic semiconductor chip as described herein. [Figure 23]1A-1D show schematic cross-sectional views of process steps for fabricating an exemplary embodiment of an optoelectronic semiconductor chip as described herein. [Figure 24] 1A-1D show schematic cross-sectional views of process steps for fabricating an exemplary embodiment of an optoelectronic semiconductor chip as described herein. [Diagram 25] 1A-1D show schematic cross-sectional views of process steps for fabricating an exemplary embodiment of an optoelectronic semiconductor chip as described herein. [Figure 26] 1A-1D show schematic cross-sectional views of process steps for fabricating an exemplary embodiment of an optoelectronic semiconductor chip as described herein. [Figure 27] 1A-1D show schematic cross-sectional views of process steps for fabricating an exemplary embodiment of an optoelectronic semiconductor chip as described herein. [Figure 28] 1A-1D show schematic cross-sectional views of process steps for fabricating an exemplary embodiment of an optoelectronic semiconductor chip as described herein. [Figure 29] 1 illustrates a schematic top view of an exemplary embodiment of an optoelectronic semiconductor chip as described herein. [Diagram 30] 1 illustrates a schematic top view of an exemplary embodiment of an optoelectronic semiconductor chip as described herein. [Diagram 31] 1 illustrates a schematic top view of an exemplary embodiment of an optoelectronic semiconductor chip as described herein. [Diagram 32] 1 illustrates a schematic top view of an exemplary embodiment of a component with an optoelectronic semiconductor chip as described herein. [Diagram 33] 1 illustrates a schematic top view of an exemplary embodiment of a component with an optoelectronic semiconductor chip as described herein. [Diagram 34] 1 illustrates a schematic top view of an exemplary embodiment of a component with an optoelectronic semiconductor chip as described herein. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0037] In Fig. 1 an exemplary embodiment of an optoelectronic semiconductor chip 1 is shown. The semiconductor chip 1 is preferably a laser diode chip. The semiconductor chip 1 comprises a semiconductor layer sequence 3, for example made of AlInGaN. For example, an active zone 33 of the semiconductor layer sequence 3 is configured for generating blue light, green light and / or near-ultraviolet radiation R during operation. The active zone 33 can be embedded in a waveguide of the semiconductor layer sequence 3, which can be limited by cladding layers of the semiconductor layer sequence 3, which are not explicitly shown. The semiconductor layer sequence 3 can still be arranged on a growth substrate 21 as a carrier 2.

[0038] The semiconductor layer sequence 3 has two coupling-out facets 34 which are oriented at approximately 45° to the growth direction G of the semiconductor layer sequence 3, such that the semiconductor layer sequence 3 narrows in the direction away from the growth substrate 21. Radiation generated in the active zone 33 leaves the semiconductor layer sequence 3 through the coupling-out facets 34.

[0039] An optical high-refractive index layer 4 is arranged directly on each of the out-coupling facets 34. The high-refractive index layer 4 has the same or approximately the same refractive index as the semiconductor layer sequence 3. The high-refractive index layer 4 is made, for example, of NbO or LiNbO and can be applied by a sol-gel process or is made of ZnS or also of sputtered amorphous GaN. The outer surface 45 of the high-refractive index layer 4 is relatively smooth and can be oriented at exactly 45° to the growth direction G. The high-refractive index layer 4 thus allows for a correction of the orientation of the out-coupling facets 34 and a smoothing of the out-coupling facets 34.

[0040] Directly on the outer surface 45 is an optically low refractive index coating 5. The low refractive index coating 5 is preferably electrically insulating and is made, for example, of SiO2 or a fluoride such as MgF or CaF. The low refractive index coating 5 may be relatively thin. Upon interaction of the high refractive index layer 4 and the low refractive index coating 5, the outer surface 45 is configured for total internal reflection of the radiation R.

[0041] The fastening means 63 is optionally arranged laterally adjacent to the high refractive index layer 4. The fastening means 63 is preferably electrically conductive and may be solder. The fastening means 63 allows for an electrical contact and mechanical connection of the semiconductor layer sequence 3 to an alternative support 22 as further support 2. The alternative support 22 is preferably structured to match the high refractive index layer 4 and is made, for example, from sapphire. The active zone 33 is thus located in a recess 24 of the further support 2, 22.

[0042] For further electrical contacting of the semiconductor layer sequence 3, the low refractive index coating 5 can be perforated at a contact side 30 of the semiconductor layer sequence 3 facing the alternative support 22, so that electrical contact means 64 can pass through the semiconductor layer sequence 3 through the low refractive index coating 5. At the support side 25 of the alternative support 22, the low refractive index coating 5 is optionally arranged directly on the alternative support 22.

[0043] In the direction away from the semiconductor layer sequence 3, the support surface 25 may be followed by a region which is oriented perpendicularly to the growth direction G. The support surface 25 may be followed by another region which is oriented away from the growth substrate 21. This region may optionally be followed by further regions which extend in a direction away from the growth substrate 21.

[0044] Additionally, a gap 8 can be optionally disposed at the interface 30 between the low index coating 5 and the high index layer 4 .

[0045] Thus, radiation R generated in the active zone 33 passes through the out-coupling facets 34 into the high refractive index layers 4 and reaches the respective outer surfaces 45. At the outer surfaces 45, the radiation R is directed by total internal reflection towards the growth substrate 21 and is emitted, for example, from two regions of the emission surface 37 of the growth substrate 21.

[0046] 2-5 illustrate an exemplary manufacturing process for the optoelectronic semiconductor chip 1 shown in FIG.

[0047] 2, the semiconductor layer sequence 3 is applied to the growth substrate 21 and patterned in such a way that the active zones 33 only remain in the regions between the pre-facets 35. The structuring of the semiconductor layer sequence 3 is carried out by dry etching, since by wet etching it is difficult to produce the correct angle of the out-coupling facets 34, for example 45°. However, due to the dry etching the pre-facets 35 are relatively rough.

[0048] In an optional step shown in FIG. 3, the pre-facets 35 are smoothed to form the output coupling facets 34 .

[0049] According to FIG. 4, the optically high refractive index layer 4 is formed and patterned. In this process, an outer surface 45 and openings for electrical contact means are formed. The high refractive index layer 4 can therefore be oriented planarly, perpendicular to the growth direction G at the contact surface 30, except for the openings. For example, the outer surface 45 is oriented at an angle of 45° to the growth direction G. Close to the substrate 2, outside the area where radiation R is incident on the outer surface 45, the high refractive index layer 4 can optionally have lateral faces extending parallel to the growth direction G.

[0050] The tolerance with which an angle of the out-coupling facet 34 of, for example, 45° relative to the growth direction G in Figures 2 and 3 can be produced is, for example, 0.5°. In contrast, due to the high refractive index layer 4 being of a different material, the angle of the outer surface 45 can be produced with a tolerance of, for example, only 0.1° or only 0.05°. The angle between the outer surface 45 and the associated out-coupling facet 34 is therefore, for example, at least 0.1° and / or at most 3°.

[0051] In figure 5 the further support 2, 22 is shown to be provided with a pre-structuring and to be provided with a low refractive index coating 5. Likewise the low refractive index coating 5 is already structured and optionally has electrical contact means 64 arranged thereon.

[0052] In further process steps not shown, the components of FIGS. 4 and 5 are assembled to arrive at the semiconductor chip 1 of FIG.

[0053] 2-5 can therefore be used to create etched out-coupling facets 34 in combination with a high index layer 4 to make perfect side surfaces to account for any imprecision in the angle of the etch. Thus, forming the facets by scribing and breaking is not necessary to achieve the desired high precision in the side surface angle with associated cost savings.

[0054] 6 shows another exemplary embodiment of the semiconductor chip 1. In this case, there is another facet 36 opposite to the single out-coupling facet 34. The further facet 36 is oriented parallel to the growth direction G. Also, on the further facet 36, the high-refractive index layer 4 is directly present, but the low-refractive index coating 5 is not present. Instead of the low-refractive index coating 5, an end mirror coating 65, for example a Bragg mirror, is present. The further facet 36 oriented parallel to the growth direction G thus has another support surface 26 associated with it, as well as the associated side of the high-refractive index layer 4.

[0055] The end mirror coating 65 can start from the opening for the electrical contact means 64. As an alternative to the illustration in Fig. 6, it is also possible that the end mirror coating 65 does not replace the low refractive index coating 5, but is additionally provided on the side of the low refractive index coating 5 facing the semiconductor layer sequence 3.

[0056] In all other respects the comments for Figs. 1-5 apply equally to Fig. 6 and vice versa.

[0057] 7 and 8 show a top view of the semiconductor layer sequence 3, where the further supports 2, 22 and the low refractive index coating 5 are not depicted for the sake of simplicity.

[0058] 7, the part of the semiconductor layer sequence 3 that remains after the production of the outcoupling facets 45 is shaped as a truncated pyramid, i.e. all lateral facets in this part of the semiconductor layer sequence 3 are oriented transversely to the growth direction G and, for example, have an angle of approximately 45° to the growth direction G.

[0059] In contrast, FIG. 8 shows that facets not in contact with radiation R can be oriented parallel or nearly parallel to the growth direction G.

[0060] In Figures 7 and 8, two of the outcoupling facets 34 are present in each case, as for example illustrated in relation to Figure 1. However, it is equally possible to apply the structures of Figures 7 and 8 to a semiconductor chip 1 having only one outcoupling facet 45, see for example Figure 6 for a semiconductor chip 1 having a further facet 36.

[0061] In all other respects the comments for Figs. 1-6 apply equally to Figs. 7 and 8 and vice versa.

[0062] The exemplary embodiments of Figures 9 and 10 are particularly directed to GaN-based HCSELs having etched facets on the emitting surface 37 and low power density, emitting, for example, blue or green radiation R. In particular, by using these semiconductor chips 1 as shown in Figures 9 and 10, a hermetic package or housing that is hermetically sealed around the semiconductor chip 1 can be omitted.

[0063] Due to their high power density and narrow radiation emission pattern, GaN-based lasers usually require a hermetically sealed housing to protect the out-coupling facet, which entails considerable costs. By out-coupling through the support 2 and redirecting the radiation R inside the support 2, particularly in the case of the semiconductor chip 1 according to Figs. 9 and 10, the path of the radiation R is enlarged, whereby the power density of the emitting surface 37 is reduced to such an extent that a hermetic encapsulation is no longer necessary.

[0064] The out-coupling facet 34 and / or the further facet 36 can be produced by etching as in the previous embodiment. Furthermore, an integrated on-chip TIR deflection mirror is provided to realize the surface emitter according to the HCSEL concept. TIR stands for Total Internal Reflection. Overall this means significant cost savings and performance advantages compared to other approaches and solutions, e.g. by bonding external deflection mirrors or prisms.

[0065] According to figures 9 and 10, an AlInGaN based semiconductor layer sequence 3 is deposited on a substrate 2, which is for example a growth substrate 21 made of GaN with a refractive index of about 2.46. The out-coupling facet 34 and the opposite further facet 36 are oriented parallel to each other and in the growth direction G. The out-coupling facet 34 is preferably provided with a highly reflective Bragg mirror as end mirror coating 65. The further facet 36 preferably has a highly reflective Bragg mirror as end mirror coating 65. The out-coupling facet 34 is provided directly with an out-coupling mirror 61, which preferably has a lower reflectivity for the radiation R, for example a reflectivity of at least 30% and / or at most 80%. The out-coupling mirror 61 and / or the end mirror coating 65 may also serve as a passivation of the facets 34, 36.

[0066] The optically high-refractive index layer 4 is arranged directly on the face of the out-coupling mirror 61 facing away from the semiconductor layer sequence 3 and is made, for example, from NbO having a refractive index of about 2.44 or from ZnS having a refractive index of about 2.47. The outer face 45 is oriented, for example, at an angle of 45° to the growth direction G.

[0067] The outer surface 45 is directly coated with, for example, SiO x , MgF or CaF, and preferably has a refractive index of at most 2.0. The low refractive index coating 5 preferably has a constant layer thickness over the area of ​​the outer surface 45 in contact with the radiation R.

[0068] Optionally, a reflective metallization 62 or a Bragg mirror is arranged directly on the face of the low-refractive index coating 5 facing away from the semiconductor layer sequence 3. The reflective metallization 62 is made, for example, from Al, Ag, Au or, depending on the wavelength of the radiation R, from the layer system Cr-Au.

[0069] In order to sufficiently reduce the power density of the radiation R at the emission surface 37, the support 2 preferably has a thickness of at least 200 μm and / or a maximum of 2 mm. For example, the thickness of the support 2 is 0.3 mm.

[0070] The effective thickness of the high refractive index layer 4 in the plane of the active zone 33 and in the direction parallel to the active zone 33 is, for example, at least 2 μm or at least 8 μm and / or at most 0.2 mm or at most 0.1 mm or at most 30 μm. That is to say, the effective thickness of the high refractive index layer 4 may be much smaller than the thickness of the substrate 2.

[0071] For example, the low refractive index coating 5 has a thickness of at least 0.2 μm and / or at most 2 μm.

[0072] The radiation surface 37 of the support 2 is optionally provided with an anti-reflection coating 66, for example SiO x , or SiO x N y A λ / 4 layer is provided.

[0073] A first electrical contact layer 91 and a second electrical contact layer 92 , which are preferably metal layers for example, are arranged on the carrier 2 at the emission surface 37 and the contact surface 30 of the semiconductor layer sequence 3 .

[0074] According to Fig. 9, the carrier 2 has a top carrier surface 20 on which the semiconductor layer sequence 3 is arranged which is flat. However, the carrier top surface 20 can also be structured in order to be able to adjust the thickness of the carrier 2 according to specific requirements, see Fig. 10. For example, the carrier 2 is thicker in the region of the semiconductor layer sequence 3 than in the region of the low refractive index coating 5.

[0075] The refractive index of NbO and GaN is very well matched, so that no disturbing reflection occurs at the corresponding interface during the NbO / GaN transition. In addition, NbO, as an amorphous material, can be easily etched to produce, for example, a 45° outer surface 45.

[0076] Figure 11 shows a top view of the semiconductor chip 1 according to figure 9. The semiconductor layer sequence 3 can thus be rectangular when viewed from above and all facets can be oriented parallel to the growth direction G.

[0077] In all other respects the comments for Figs. 1-8 apply equally to Figs. 9-11 and vice versa.

[0078] 12 shows an exemplary embodiment of a semiconductor chip 1, in which the semiconductor layer sequence 3 is based on the material system AlInGaAs and the active zones 33 are configured for generating red or near-infrared radiation R. As in all other embodiments, the semiconductor layer sequence 3 can comprise several active zones 33. The active zones 33 can all be configured for generating radiation R of the same wavelength or for generating radiation R of different wavelengths.

[0079] Fig. 12 further shows that an optical system 7 can be fabricated on the support 2. The optical system 7 is, for example, a collimating lens. Such an optical system 7 can also be present in all other embodiment examples. In particular, the semiconductor chip 1 of Fig. 1 is a GaAs-based HCSEL configured for pulsed operation with etched facets 34, 36.

[0080] For example, a pulsed GaAs laser for LiDAR applications, in particular a triple-stack laser with three active zones 33 and thus a thick epitaxially grown semiconductor layer sequence 3, if realized as an HCSEL, requires a gradient of exactly 45° over the entire semiconductor layer sequence 3, which is difficult to achieve due to the different materials of the active zones 33. If this is not guaranteed, high losses will result, especially for deeper active zones 33 and associated waveguides. It is difficult to achieve a gradient of 45° exactly over the entire thickness of the semiconductor layer sequence 3, especially if it is only part of the resonator that is still tilted.

[0081] In the GaAs-based semiconductor chip 1 of FIG. 12, the facets 34, 36 are also etched to provide an HCSEL, featuring an integrated on-chip TIR deflection mirror. This represents a significant cost-saving and performance advantage compared to other approaches and solutions, such as using external deflection mirrors, bonded prisms, etc. With this concept, it is possible to achieve efficiencies of the same order of magnitude as the standard edge emitter approach. This is especially true since the 45° outer surface 45 is outside the actual cavity. Another advantage is that deviations from the ideal 45° tilt in the concept described here can be compensated for by compensating the optics 7 of the emission surface 37. This also applies to semiconductor chips 1 with only one active zone 33.

[0082] In the semiconductor chip 1 shown in Fig. 12, the support 2 is in particular a GaAs growth substrate 21 having a refractive index of about 3.6, which is transparent for wavelengths above about 870 nm. The optically high-index layer 4 is likewise made, for example, of NbO, which has a refractive index of about 2.28, which is high in comparison with the low-index coating 5, which has a refractive index of less than 2.0. The low-index coating 5 is made, for example, of SiO x , MgF, or CaF. The reflective metallization 62 is for example of Al, Ag, Au, or Cr-Au.

[0083] In order to prevent reflection of radiation R at the interface between the support upper surface 20 and the high refractive index layer 4, an anti-reflective coating 66 is preferably present between the support 2 and the high refractive index layer 4. The anti-reflective coating 66 is particularly suitable when the high refractive index layer 4 is made of SiO x N y or in the case of NbO, for example TiO x In this case, the SiO x N y In particular, it may have a refractive index of about 1.75. Instead of a single layer anti-reflection coating 66, a multi-layer system such as a Bragg layer sequence may also be used.

[0084] The optical system 7 may also include fast axis correction and / or may be configured for angular correction for a 90° deflection of the radiation R. The optical system 7 is, for example, glued or bonded or etched into the support 2.

[0085] In all other respects the comments for Figs. 1-11 apply equally to Fig. 12 and vice versa.

[0086] 13 shows that the low-index coating 5 can also be designed as a stack of Bragg layers, i.e. in this case the low-index coating 5 does not have to act as a total reflection coating interacting with the high-index coating 4. The same applies to all other embodiments.

[0087] In all other respects the comments for FIG. 12 apply equally to FIG. 13 and vice versa.

[0088] 14 shows that the high index layer 4, the low index coating 5 and the optional reflective metallization 62 do not need to be planarized at the contact surface 30. The same applies to all other embodiments.

[0089] 14 further shows that the optical system 7 does not have to be a convex or biconvex converging lens, but may also be formed by a meta-optic or a diffractive optical element or may include corresponding components. The same applies to all other embodiments.

[0090] In all other respects the comments for Figs. 12 and 13 apply equally to Fig. 14 and vice versa.

[0091] 15, the growth substrate 21 has been replaced by a substitution substrate 22. The emitting surface 37 is therefore located on the surface of the high refractive index layer 4 facing away from the substrate 2. An anti-reflection coating 66 may also be present.

[0092] In all other respects the comments for Figs. 12-14 apply equally to Fig. 15 and vice versa.

[0093] In Figure 16 it is shown that, based on Figure 15, the low refractive index coating 5 can be designed as a Bragg mirror in the same way as in Figure 13. In all other respects the comments in Figures 13 and 15 apply in the same way as in Figure 16 and vice versa.

[0094] Figures 17 to 28 show a method for manufacturing a semiconductor chip 1 that is configured as shown in Figure 15, except for the optional formation of a reflective metallization 62. For example, Figure 17 shows that a semiconductor layer sequence 3 with an active region 33 is successively grown on a growth substrate 21.

[0095] According to Fig. 18, the semiconductor layer sequence 3 is patterned in such a way that an out-coupling facet 34 and a further facet 36 are formed. These facets 34, 36 are aligned parallel to the growth direction G. The facets 34, 36 are not produced by scribing and breaking but by etching. This etching may comprise or may be a wet-chemical and / or dry-chemical process.

[0096] 19, an end mirror coating 65 and an output coupling mirror 61 are produced on the facets 34, 36. The end mirror coating 65 and the output coupling mirror 61 are preferably Bragg mirrors.

[0097] 20, the starting layer 41 for the high refractive index layer is deposited. The starting layer 41 can be deposited over a large area and optionally only on the output coupling mirror 61.

[0098] Figure 21 shows that the high index layer 4 has been patterned by etching to form an outer surface 45. Now, referring to Figure 22, a low index coating 5 is produced, preferably with a constant layer thickness.

[0099] At least one metal for the optional reflective metallization 62 is then applied. In contrast to the case shown in Fig. 15, this metal can also be applied relatively thickly over large areas. In contrast to what is shown in Fig. 23, this metal can also be arranged on the side of the end mirror coating 65 facing away from the semiconductor layer sequence 3. The thickness of the reflective metallization 62 in the direction parallel to the growth direction G can be the same as or greater than the thickness of the semiconductor layer sequence 3.

[0100] In an optional step in FIG. 24, the layers 4 , 5 , 62 can be planarized so that they are flush with the semiconductor layer sequence 3 and the mirrors 61 , 65 in the direction away from the growth substrate 21 .

[0101] 25, rebonding is performed in such a way that an alternative support 22, for example made of Si or Ge, is attached to the side of the semiconductor layer sequence 3 facing away from the growth substrate 21. After attachment of the alternative support 22, the growth substrate 21 is removed.

[0102] In the step of FIG. 26, an anti-reflective coating 66 is applied, resulting in the emitting surface 37 .

[0103] Finally, FIG. 28 shows that electrical contact layers 91 , 92 are attached to the replacement substrate 22 and to the semiconductor layer sequence 3 .

[0104] The process of FIGS. 17-28 is used as an example for manufacturing a semiconductor chip 1 similar to that shown in FIG. 15, but can of course be adapted to the manufacturing requirements of semiconductor chips 1 according to other embodiments.

[0105] In particular, Figures 29 to 31 relate to an exemplary embodiment of the semiconductor chip 1 provided with anti-beam tilt optics 7, i.e. optics that can compensate for misalignment of the outer surface 45 with respect to the support 2 and / or undesired tilt of the radiation R. This allows for an efficient realization of the HCSEL design.

[0106] Errors in the realization of the outer surface 45 in the etching process result in a tilt or skew of the radiation angle, also referred to as inclination. For example, a variation of + / - 1° in the outer surface 45 means a tilt of + / - 5° of the emitted radiation R, due to, for example, differences in refractive index. This is highly undesirable for many applications requiring conditioning, collimation, and / or focusing of the radiation R.

[0107] By incorporating an appropriate lens design, for example in the GaN substrate 21, the inclination of these output beams can be compensated, for example similar to radial LEDs. In particular, not only is the laser mode typically only a few 100 nm to 2 μm wide at its start, but also the support 2 is particularly thick, so that the size of the beam at the 45° outer surface 45 can be assumed to be a point source for the lens design. The thickness of the support well defines the spacing of the lens surfaces. For example, etching techniques can be used to realize suitable radial lens shapes. Other lens shapes can also be, for example, meta-optical or diffractive structures. Another advantage is that here compression and / or fast axis collimation or pre-collimation can be performed or integrated into the optical function.

[0108] Correspondingly, tilt correction is shown in figure 29. To simplify the drawing, the high index layer 4 and the low index coating 5 are only shown very diagrammatically.

[0109] As is also possible in all other exemplary embodiments, the further facet 36 may also be oriented at an angle of 45° to the growth direction G. As is also possible in all other exemplary embodiments, the output coupling mirror 61 may also be arranged between the carrier 2 and a region of the semiconductor layer sequence 3 which has at least one active zone 33.

[0110] In all other respects the comments for Figs. 1-28 apply equally to Fig. 29 and vice versa.

[0111] According to FIG. 30, in addition to the tilt correction, fast axis correction is also performed.

[0112] Furthermore, a light emitting layer 67 may be present in place of the anti-reflection coating 66 for wavelength modification of the radiation R, as is also possible in all other exemplary embodiments.

[0113] In all other respects the comments for FIG. 29 apply equally to FIG. 30 and vice versa.

[0114] FIG. 31 shows that the optical system 7 can be designed as a diffractive optical element or a meta-optical system.

[0115] In all other respects the comments for FIGS. 29 and 30 apply as for FIG. 31.

[0116] 32 shows an exemplary embodiment of a component 10 including a semiconductor chip 1 according to one of the preceding exemplary embodiments. The semiconductor chip 1 is arranged on a mounting platform 11, for example a ceramic substrate. The mounting platform 11 is provided with a conductive coating 12 for electrically contacting the semiconductor chip 1. For example, the electrical contact is made by means of an electrical connection 15, which can be a bonding wire.

[0117] The semiconductor chip 1 is thus mounted, for example, in an SMD package, which may have contact surfaces on the underside for soldering to a printed circuit board. The package substrate, i.e. the mounting platform 11, may be a ceramic, for example made from AlN, which has electrical vias between its main sides. Besides the two electrical contacts, a further potential-free contact for heat dissipation may be mounted on the underside.

[0118] For mechanical protection, the semiconductor chip 1 can be encapsulated in an unpatterned package, for example with an organic encapsulant such as epoxy resin or silicone. If required, further optical elements, for example lenses, can be part of the component 10 or the package.

[0119] In all other respects the comments for FIGS. 29-31 apply analogously to FIG.

[0120] The housing substrate or mounting platform 11 can also be a metal leadframe made of Cu, for example a QFN housing, for which there may be leadframe portions 14 mechanically connected to each other by a support material 13.

[0121] In all other respects the comments for FIG. 32 apply as for FIG.

[0122] The component 10 according to FIG. 34 includes a number of semiconductor chips 1, whereby all semiconductor chips 1 may be of identical structure or different types of semiconductor chips 1 may be attached, for example generating radiation R of different colors.

[0123] That is, several semiconductor chips 1 are assembled and contacted on a common assembly platform 11. The electrical connections of several semiconductor chips 1 are made, for example, as a series circuit. This allows the use of commercially available drivers and reduces the required wire cross-section. Several electrical strings per mounting platform 11 are possible.

[0124] The common mounting platform 11 may be designed as an SMD package, for example based on at least one ceramic as shown in Fig. 32. Alternatively, the mounting platform 11 may be designed as a printed circuit board made of a metal substrate, for example Al or Cu, a dielectric with high thermal conductivity, and a structured conductor surface.

[0125] For mechanical protection, the semiconductor chip 1 can again be encapsulated, for example with an organic sealant such as epoxy resin or silicone. Further optical elements, for example lenses, can also be part of the structure.

[0126] Components 10 may include suitable components, not shown, such as an NTC for temperature monitoring.

[0127] In the case of a printed circuit board as mounting platform 11, support 13 may have solder pads or connectors for electrical contacts and drill holes for mounting to a heat sink, not shown.

[0128] The optical system 7 in particular allows the radiation directions of the individual semiconductor chips 1 to be precisely aligned with one another. For this purpose, the optical system 7 can be optionally individually adapted to the respective requirements, i.e. at the level of the semiconductor chip.

[0129] Components shown in the figures preferably follow one another in the order shown and immediately follow one another unless specifically stated otherwise. Components that are not in contact with one another in the figures are preferably separated. When lines are shown parallel to one another, the associated faces are preferably aligned parallel to one another as well. Furthermore, the relative positions of the shown components with respect to one another are accurately reproduced in the figures unless otherwise indicated.

[0130] The invention described herein is not limited by the description based on the embodiments, but rather any novel feature and any combination of features, including in particular any combination of features in the claims, is included in the invention even if this feature or combination itself is not explicitly recited in the claims or embodiments.

[0131] This patent application claims priority from German patent application No. 10 2021 113 856.6, the disclosure content of which is incorporated herein by reference. [Explanation of symbols]

[0132] 1. Optoelectronic semiconductor chip 2 Support 20 Top surface of support 21 Growth Substrate 22 Alternative supports 23 Fastener 24 Notch 25 Support surface 26 More Support Surfaces 3 Semiconductor layer sequence 30 Contact surface 33 Active Zone 34 Output Joint Facets 35 Prefset 36 More Facets 37 Radiating Surface 4. Optically high refractive index layer 41 Starting layer for high refractive index layer 45 Outer surface of high refractive index layer 5. Optical low refractive index coating 61 Output coupling mirror 62 Reflective Metallization 63 Fixing means 64 Electrical contact means 65 End mirror coating 66 Anti-reflective coating 67 Light-emitting layer 7 Optical system 8. Gap 91 First Electrical Contact Layer 92 Second Electrical Contact Layer 10. Components 11 Implementation Platform 12 Conductive Coating 13 Support material 14 Lead frame part 15 Electrical Connections G Growth direction of the semiconductor layer sequence

Claims

1. An optoelectronic semiconductor chip (1), - support (2), a semiconductor layer sequence (3) on said substrate (2) having at least one active zone (33) for generating radiation (R), an optically high-refractive index layer (4) on a coupling-out facet (34) of the semiconductor layer sequence (3) for coupling out the radiation, and - an optical low refractive index coating (5) applied directly to the outer surface (45) of said high refractive index layer (4) for total internal reflection of said radiation (R), the semiconductor layer sequence (3) is configured to guide the radiation (R) in the active zone (33) perpendicular to a growth direction (G) of the semiconductor layer sequence (3), - said high refractive index layer (4) is configured to deflect said radiation (R) on said outer face (45) parallel to said growth direction (G); - said support (2) is an alternative support (22) and said radiation (R) is emitted away from said support (2) by said outer surface (45); the carrier (2) has a recess (24) for the semiconductor layer sequence (3), whereby the carrier (2) has a support surface (25) facing the out-coupling facet (34), the low refractive index coating (5) is arranged on the support surface (25) and the high refractive index layer (4) is arranged on the low refractive index coating (5), an optoelectronic semiconductor chip (1), in which the semiconductor layer sequence (3) seen in plan view and in at least one region not having an active zone (33) is fixed by fixing means (63) to the low refractive index coating (5) arranged on the carrier (2).

2. 2. An optoelectronic semiconductor chip (1) according to claim 1, which is a semiconductor laser, in which the high refractive index layer (4) has a refractive index at least 0.6 higher than the low refractive index coating (5) at the wavelength of maximum intensity of the radiation (R).

3. the difference in refractive index between said active zone (33) and said high refractive index layer (4) is at most 0.3, 2. The optoelectronic semiconductor chip (1) according to claim 1, wherein the high refractive index layer (4) is arranged directly on the out-coupling facet (34), the out-coupling facet (34) being oriented at an angle to the growth direction (G).

4. 2. The optoelectronic semiconductor chip (1) of claim 1, wherein the high refractive index layer (4) is an angle correction layer for the output coupling facet (34) such that the angle between the outer surface (45) and the output coupling facet (34) is greater than or equal to 0.1° and less than or equal to 20°.

5. the low refractive index coating (5) is perforated on a contact surface (30) of the semiconductor layer sequence (3) facing the carrier (2), whereby electrical contact means (64) are led through the low refractive index coating (5) to the semiconductor layer sequence (3), 2. The optoelectronic semiconductor chip (1) according to claim 1, wherein at the support surface (25) of the support (2), the low refractive index coating (5) is arranged directly on the support (2).

6. 6. An optoelectronic semiconductor chip (1) according to claim 5, wherein a gap (8) is provided at the interface (30) between the low refractive index coating (5) and the high refractive index layer (4).

7. An optoelectronic semiconductor chip (1) as described in claim 6, wherein the support (2) includes a first region and a second region, in the first region, the support (2) has a constant thickness and the electrical contact means (64) is present, and in the second region, the thickness of the support (2) varies and includes the support surface (25).

8. 8. An optoelectronic semiconductor chip (1) according to claim 7, wherein said fastening means (63) is based on at least one metal or is a metal alloy.

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