III-nitride surface emitting lasers and methods of fabrication

Abstract

The vertical cavity surface-emitting laser (VCSEL) comprises a light-emitting III-nitride active region containing quantum wells (QWs), each of which has a thickness greater than 8 nm, a cavity length of at least 7λ or at least 20λ (λ is the peak wavelength of light emitted from the active region), layers with reduced surface roughness, and tunnel junction inter-cavity contacts. The VCSEL is flip-chip bonded using In-Au bonding. This is the first report of a VCSEL capable of continuous wave operation.

Description

[Technical field]

[0001] (CROSS REFERENCE TO RELATED APPLICATIONS) This application claims the benefit under 35 USC Section 119(e) of the following co-pending and commonly assigned U.S. Provisional Patent Application No. 62 / 566,843 (Attorney Docket No. 30794.662-US-P1(2018-250)), filed October 2, 2017 by Charles Forman, SeungGeun Lee, Erin Young, Jared Kearns, Steven P. DenBaars, James S. Speck, and Shuji Nakamura, entitled "III-NITRIDE SURFACE-EMITTING LASER AND METHOD OF FABRICATION," which is incorporated herein by reference:

[0002] FIELD OF THEINVENTION The present invention relates to a vertical cavity surface emitting laser (VCSEL) and a method for making the same. [Background technology]

[0003] (Note: this application refers to several different publications, as indicated throughout this specification by one or more reference numbers in square brackets, e.g., [x]. A list of these different publications, ordered according to their reference numbers, can be found below in the section entitled "References." Each of these publications is incorporated herein by reference.)

[0004] Vertical-cavity surface-emitting lasers (VCSELs) are semiconductor laser diodes that emit light perpendicular to the substrate. This design has many advantages over edge-emitting lasers and light-emitting diodes, such as low threshold current, circular mode profile, high-speed direct modulation, the ability for single-longitudinal mode operation, and two-dimensional array capability ([1]). In contrast to arsenide- and phosphide-based devices, electrically injected III-nitride VCSELs are relatively difficult to fabricate, and only eight research groups have successfully demonstrated these devices in the past decade ([2]-

[26] ). Although the majority of reports concern c-plane, m-plane VCSELs have also been demonstrated ([4],

[10] ,

[12] ,

[15] ,

[24] ) and have many advantages, such as the absence of the quantum-confined Stark effect, higher material gain, and anisotropic gain leading to 100% polarization ratio. III-nitride based devices emit at wavelengths in the ultraviolet and visible spectrum that lead to new applications in solid-state lighting, visible light communications, displays, projectors, and sensors. However, m-plane VCSEL devices have not been able to achieve continuous wave operation. The present invention fulfills this need. Summary of the Invention [Means for solving the problem]

[0005] To overcome the limitations in the prior art discussed above, as well as other limitations that will become apparent upon reading and understanding of this specification, embodiments of the present invention disclose VCSELs bonded to flip-chip substrates using Au-In solid-liquid interdiffusion (SLID) bonding. SLID bonding solves the cracking problems found in conventional VCSEL devices formed using Au-Au thermocompression bonding, and greatly improves VCSEL yields (because SLID is performed at lower temperatures and bonding forces). Additionally, SLID bonding allows for a much thicker metal path for heat transport so that continuous wave operation of the VCSELs can be achieved.

[0006] In further embodiments, the III-nitride VCSEL included an active region having a thick quantum well (QW) (e.g., >8 nm or >9 nm thick). Thicker QWs are possible on semipolar or nonpolar m-plane GaN, as opposed to standard c-plane GaN.

[0007] An embodiment of the present invention has been demonstrated, achieving continuous wave (CW) operation at room temperature. The embodiment is a dual dielectric DBR m-plane VCSEL with MBE grown tunnel junction contacts and ion implanted apertures (similar to reference [5]) with an active region comprising a two period multiple quantum well (MQW) with 14 nm QWs and 1 nm barriers. Improved thermal performance and yield for this device structure was achieved using indium-gold flip chip bonding (instead of gold-gold bonding). The embodiment has a longer cavity length (23 λ instead of 7 λ, where λ is the wavelength of light emitted by the VCSEL), and was fabricated using improved molecular beam epitaxy (MBE) regrowth conditions and by removing oxide residues after photoelectrochemical (PEC) etching.

[0008] However, a VCSEL can be embodied in many ways, including but not limited to the following examples. 1. A VCSEL on a mounting (e.g., a flip chip substrate) with a thermally conductive joint between the mounting and the VCSEL, the joint including a thermally conductive metal layer, whereby heat generated during operation of the VCSEL is transferred from the VCSEL to the mounting, and the VCSEL emits continuous wave electromagnetic radiation. 2. The device of example 1, wherein the thermally conductive bond is crack-free or contains fewer cracks than a bond between the VCSEL and the mounting formed using Au-Au thermocompression bonding. 3. The element of any one or combination of the preceding embodiments, wherein the thermally conductive joint comprises a metal formed from a liquid metal phase. 4. The device as recited in one or any combination of the preceding examples, wherein the VCSEL is bonded to the mounting by solid-liquid interdiffusion bonding (e.g., achieved by a brief liquid phase of one low melting point metal and immediate solidification induced by diffusion and mixing with a second high melting point metal to produce an intermetallic phase). 5. The device of any one or any combination of the preceding embodiments, wherein the VCSEL comprises a first mirror and a second mirror defining a cavity for electromagnetic radiation, and the VCSEL is bonded to the mounting by forming a bond comprising a metal layer in a liquid state around the periphery of the first mirror. 6. The device of any one or combination of the preceding embodiments, wherein the VCSEL comprises a first mirror and a second mirror defining a cavity for electromagnetic radiation, the junction including a metal layer, and one of the first mirror or the second mirror being embedded in the metal layer. 7. The device of any one or combination of the preceding embodiments, wherein the VCSEL comprises a first mirror and a second mirror defining a cavity for electromagnetic radiation, and the junction includes a metal layer molded around the first mirror or the second mirror to act as a mold for the metal layer. 8. The element according to one or any combination of the preceding embodiments, wherein the joint comprises an intermetallic compound having a solid phase including two or more metallic elements. 9. The element of any one or combination of the preceding embodiments, wherein the junction comprises a first metal diffused into the second metal to mix with the second metal, the first metal having a lower melting point than the second metal. 10. The device of any one or combination of the preceding embodiments, wherein the first metal comprises indium and the second metal comprises gold. 11. The VCSEL according to one or any combination of the preceding embodiments, comprising a light emitting III-nitride active region including quantum wells (QWs), each of the quantum wells having a thickness greater than 8 nm. 12. The VCSEL of example 11, wherein the quantum well has a thickness in the range of 8 to 20 nm. 13. The VCSEL as recited in one or any combination of the preceding embodiments, wherein the active region has a non-polar or semi-polar crystal orientation. 14. The VCSEL of any one or combination of the preceding embodiments, wherein the VCSEL has a cavity length of at least 7λ, where λ is the peak wavelength of light emitted from the active region when light is within the active region, the peak wavelength being the wavelength of light having the highest intensity. 15. The VCSEL as recited in example 4, wherein the cavity length is within the range of 20λ to 100λ. 16. The VCSEL of one or any combination of Examples 1-5, wherein the VCSEL further comprises an active region between a first III-nitride n-type layer and a III-nitride p-type layer, a second III-nitride n-type layer forming a tunnel junction with the III-nitride p-type layer, a contact layer for the tunnel junction, and a top surface of the contact layer having a root-mean-square (RMS) surface roughness of less than 2 nanometers (nm) when the VCSEL is a nonpolar device, or less than 1 nm when the VCSEL is a semipolar device. 17. The VCSEL as recited in one or any combination of the preceding embodiments, wherein the active region is between a III-nitride n-type layer and a III-nitride p-type layer, and wherein after etching to at least partially remove the substrate on which the active region is grown, an n-side surface of the III-nitride layer is exposed, and the n-side surface is surface treated to have an RMS surface roughness of less than 1 nm. 18. The VCSEL of example 16 or 17, wherein the surface roughness is over an area of ​​5 μm×5 μm, 1 μm×1 μm, or 10 μm×10 μm. 19. The VCSEL of Examples 16-17, wherein the surface treatment removes oxide residue after etching. 20. The VCSEL as described in one or any of Examples 1-19, further comprising a mirror, a metal layer on the mirror, a flip-chip substrate, a bonding layer on the flip-chip substrate comprising gold, and a bonded interface between the bonding layer and the metal layer, wherein the bonded interface comprises indium bonded to the gold. 21. The device of any of the previous examples, further comprising a first charge injection layer coupled to the light-emitting active region, the active region emitting light in response to electrons and holes injected into the active region through the charge injection layer. 22. A VCSEL comprising a light emitting III-nitride active region including quantum wells (QWs), each of the quantum wells having a thickness greater than 8 nm. 23. The VCSEL of example 22 in combination with one or any combination of examples 1-10 or 11-21. 24. A method of fabricating a vertical cavity surface emitting laser (VCSEL) structure, the method including: growing a sacrificial layer on a semipolar or nonpolar III-nitride substrate; growing a III-nitride VCSEL structure including an active region between an n-type layer and a p-type layer, the active region including a quantum well having a thickness greater than 8 nm; growing a tunnel junction structure on the p-type III-nitride using an indium surfactant at a temperature less than 750° C.; depositing a mirror on the p-type side of the VCSEL structure; coating sidewalls of the active region with a dielectric layer; depositing a metal on the mirror; flip-chip bonding a flip-chip substrate to the metal on the mirror using solid-liquid interdiffusion bonding; photoelectrochemically etching the sacrificial layer to at least partially remove the nonpolar or semipolar III-nitride substrate; and using a surface treatment to remove rough residues on the n-type side of the VCSEL structure or on the surface of the n-type layer exposed during the etch. 25. The method of example 24, wherein removing comprises treating the surface with Tergitol detergent or KOH. 26. The method of example 24 or 25, wherein the VCSEL structure is grown with a cavity length of at least 7λ, where λ is the peak wavelength of light emitted from the active region when light is within the active region, the peak wavelength being the wavelength of light having the highest intensity. 27. The method of embodiment 24, 25, or 26, wherein the surface of the n-type layer has a root-mean-square (RMS) surface roughness of less than 1 nm after the surface treatment. 28. The method of example 27, wherein the surface roughness is over an area of ​​5 μm×5 μm, 1 μm×1 μm, or 10 μm×10 μm. 30. The method of any of examples 24-28, wherein the VCSEL emits continuous wave electromagnetic radiation. 31. VCSELs emit continuous wave electromagnetic radiation. 32. The VCSEL of example 31, wherein the VCSEL comprises a Group III nitride. 33. A vertical cavity surface emitting laser (VCSEL), the VCSEL comprising a light emitting III-nitride active region including quantum wells (QWs), each of the quantum wells having a thickness greater than 8 nm. The present invention provides, for example, the following: (Item 1) An element, the element comprising: A mounting part, a vertical cavity surface emitting laser (VCSEL) on the mounting portion; a thermally conductive joint between the mounting portion and the VCSEL; Equipped with The junction comprises a thermally conductive metal layer whereby heat generated during operation of the VCSEL is transferred from the VCSEL to the mounting portion, the VCSEL emitting continuous wave electromagnetic radiation. (Item 2) Item 2. The device of item 1, wherein the thermally conductive bond is crack-free or contains fewer cracks than a bond between the VCSEL and the mounting formed using Au-Au thermocompression bonding. (Item 3) Item 14. The device of item 1, wherein the thermally conductive joint comprises a metal formed from a liquid metal phase. (Item 4) Item 2. The device of item 1, wherein the VCSEL is bonded to the mounting portion by solid-liquid interdiffusion bonding. (Item 5) the VCSEL comprises a first mirror and a second mirror defining a cavity for the continuous wave electromagnetic radiation; 2. The device of claim 1, wherein the VCSEL is bonded to the mounting by forming the bond with a metal layer in a liquid state around the first mirror. (Item 6) 2. The device of claim 1, wherein the VCSEL comprises a first mirror and a second mirror defining a cavity for the continuous wave electromagnetic radiation, the thermally conductive junction comprises a metal layer, and one of the first mirror or the second mirror is embedded within the metal layer. (Item 7) 2. The device of claim 1, wherein the VCSEL comprises a first mirror and a second mirror defining a cavity for the electromagnetic radiation, and the thermally conductive junction comprises a metal layer molded around the first mirror or the second mirror to act as a mold for the metal layer. (Item 8) Item 1 . The element of item 1 , wherein the thermally conductive joint comprises an intermetallic compound having a solid phase including two or more metallic elements. (Item 9) Item 2. The element of item 1, wherein the thermally conductive joint comprises a first metal diffused into a second metal so as to intermix with the second metal, the first metal having a lower melting point than the second metal. (Item 10) Item 10. The device of item 9, wherein the first metal comprises indium and the second metal comprises gold. (Item 11) the VCSEL includes a light emitting III-nitride active region that emits the continuous wave electromagnetic radiation in response to an electrical current input into the active region; the light emitting III-nitride active region comprises quantum wells (QWs), each of the quantum wells having a thickness greater than 8 nm; The element according to any one of items 1 to 10. (Item 12) Item 12. The device according to item 11, wherein the thickness is in the range of 8 to 20 nanometers (nm). (Item 13) Item 13. The device according to any one of items 1 to 12, wherein the VCSEL has a non-polar or semi-polar crystal orientation. (Item 14) the VCSEL has a cavity length of at least 7λ, where λ is a peak wavelength of the continuous wave electromagnetic radiation emitted from an active region of the VCSEL as measured within the active region; the peak wavelength is the wavelength of the continuous wave electromagnetic radiation having the highest intensity; 14. The element according to any one of items 1 to 13. (Item 15) Item 15. The element according to item 14, wherein the cavity length is in the range of 20λ to 100λ. (Item 16) The VCSEL is the active region between a first Group III-nitride n-type layer and a Group III-nitride p-type layer; a second III-nitride n-type layer forming a tunnel junction with the III-nitride p-type layer; a contact layer for the tunnel junction; an upper surface of the contact layer; Further comprising: Item 16. The device of any one of items 1 to 15, wherein the top surface of the contact layer has a root mean square (RMS) surface roughness of less than 2 nanometers (nm) when the VCSEL is a non-polar device, or a RMS surface roughness of less than 1 nm when the VCSEL is a semi-polar device. (Item 17) the active region is between a Group III-nitride n-type layer and a Group III-nitride p-type layer; an n-side surface of the III-nitride layer is exposed after etching to at least partially remove the substrate on which the active region was grown; Item 17. The device according to any one of items 1 to 16, wherein the n-side surface is surface treated to have an RMS surface roughness of less than 1 nm. (Item 18) 18. The element according to item 16 or 17, wherein the surface roughness is over an area of ​​5 μm×5 μm, 1 μm×1 μm, or 10 μm×10 μm. (Item 19) Item 18. The device of item 17, wherein the surface treatment removes oxide residues after the etching. (Item 20) A VCSEL, comprising: a first mirror and a second mirror defining a cavity for electromagnetic radiation emitted from the VCSEL; A flip chip substrate; a metal layer between the VCSEL and the flip-chip substrate; Equipped with The VCSEL, wherein the metal layer comprises indium and gold, and the first mirror or the second mirror is embedded within the metal layer. (Item 21) Item 21. The VCSEL of item 20, wherein the mirror comprises a distributed Bragg reflector including a dielectric layer. (Item 22) 1. A method of fabricating a vertical cavity surface emitting laser (VCSEL) structure, the method comprising: bonding the VCSEL to the mounting portion using a metal; The joining step comprises: providing a metal layer on the mounting portion, the metal layer comprising a first metal and a second metal; heating the metal layer such that the first metal is in a liquid metal state; disposing the VCSEL on the metal layer containing the first metal in the liquid state; allowing the metal layer to solidify and form a bond between the VCSEL and the mounting; A method comprising: (Item 23) the VCSEL comprises a first mirror and a second mirror defining a cavity for electromagnetic radiation emitted from the VCSEL; 23. The method of claim 22, wherein the positioning includes positioning the first mirror on the first metal layer using force or pressure while the first metal layer is in the liquid metal state, whereby the first metal layer is embedded within the metal layer after the metal layer solidifies. (Item 24) 24. The method of claim 22 or 23, wherein the VCSEL is bonded to the mounting by solid-liquid interdiffusion bonding, the first metal comprising indium and the second metal comprising gold. (Item 25) 1. A method of fabricating a vertical cavity surface emitting laser (VCSEL) structure, the method comprising: Growing a sacrificial layer on a semipolar or nonpolar III-nitride substrate; growing a III-nitride VCSEL structure including an active region between an n-type layer and a p-type layer, the active region including a quantum well having a thickness greater than 8 nm; growing a tunnel junction structure on the p-type III-nitride using an indium surfactant at a temperature below 750° C.; depositing a mirror on a p-type side of the VCSEL structure; coating sidewalls of the active area with a dielectric layer; depositing a metal on the mirror; flip-chip bonding a flip-chip substrate to the metal on the mirror using solid-liquid interdiffusion bonding; photoelectrochemically etching the sacrificial layer to at least partially remove the nonpolar or semipolar III-nitride substrate; using a surface treatment to remove rough residues on the n-type side of the VCSEL structure or on the surface of the n-type layer exposed during the etching; A method comprising: (Item 26) 26. The method of claim 25, wherein said removing comprises treating said surface with Tergitol detergent or KOH. (Item 27) 27. The method of claim 25 or 26, wherein the VCSEL structure is grown with a cavity length of at least 7λ, where λ is the peak wavelength of light emitted from the active region when the light is within the active region, the peak wavelength being the wavelength of the light having the highest intensity. (Item 28) 28. The method according to any one of items 25 to 27, wherein the surface of the n-type layer has a root-mean-square (RMS) surface roughness of less than 1 nm after the surface treatment. (Item 29) 29. The method of claim 28, wherein the surface roughness is over an area of ​​5 μm×5 μm, 1 μm×1 μm, or 10 μm×10 μm. (Item 30) 30. The method of any one of claims 25 to 29, wherein the VCSEL emits continuous wave electromagnetic radiation. (Item 31) VCSELs emit continuous wave electromagnetic radiation. (Item 32) Item 32. The VCSEL of item 31, wherein the VCSEL comprises a Group III nitride. (Item 33) 1. A vertical cavity surface emitting laser (VCSEL), the VCSEL comprising a light emitting III-nitride active region including quantum wells (QWs), each of the quantum wells having a thickness greater than 8 nm. [Brief description of the drawings]

[0009] Reference is now made to the drawings, in which like reference numbers represent corresponding parts throughout: [Figure 1A] FIG. 1A is a schematic diagram of a III-nitride VCSEL structure prior to flip-chip bonding. [Figure 1B] FIG. 1B shows the completed structure after processing. [Figure 2-1] FIG. 2 is a process flow for fabricating the device of FIG. 1B. [Figure 2-2] FIG. 2 is a process flow for fabricating the device of FIG. 1B. [Figure 2-3] FIG. 2 is a process flow for fabricating the device of FIG. 1B. [Figure 2-4] FIG. 2 is a process flow for fabricating the device of FIG. 1B. [Figure 2-5] FIG. 2 is a process flow for fabricating the device of FIG. 1B. [Diagram 3] FIG. 3 is an exemplary bonding process flow. [Figure 4A] Figure 4A shows photodetector measurements of pulsed IV and IL curves of a VCSEL with an aperture diameter of 6 μm and a cavity length of 23 λ. Ith was 12 mA (42.4 kA / cm2) and the maximum output power was 700 μW. [Figure 4B] Figure 4B is the IV and IL curves generated by integrating the spectrometer intensity. By matching the spectrometer optical fiber to the emission peak, the spontaneous emission measured below threshold is greatly reduced compared to the large area photodetection measurement. [Figure 5A]5A-5B are spectra under pulsed operation near the threshold current (FIG. 5A) and for currents up to 42.1 mA (FIG. 5B) of a VCSEL with an aperture diameter of 6 μm and a cavity length of 23λ. [Figure 5B] 5A-5B are spectra under pulsed operation near the threshold current (FIG. 5A) and for currents up to 42.1 mA (FIG. 5B) of a VCSEL with an aperture diameter of 6 μm and a cavity length of 23λ. [Figure 6A] 6A-6B show the IV and IL curves (FIG. 6A) and spectra at different currents (FIG. 6B) of a VCSEL with an aperture diameter of 6 μm and a cavity length of 23λ in CW operation. [Figure 6B] 6A-6B show the IV and IL curves (FIG. 6A) and spectra at different currents (FIG. 6B) of a VCSEL with an aperture diameter of 6 μm and a cavity length of 23λ in CW operation. [Figure 7] 7A-7B are optical microscope images of the VCSEL aperture as a function of current at a short integration time (FIG. 7A) and at a longer integration time (FIG. 7B). [Figure 8] Figure 8 shows the spectrum under CW operation for a VCSEL with an aperture diameter of 6 μm and a cavity length of 23 λ. The spontaneous emission range red-shifts with increasing current. [Figure 9] FIG. 9 is a thermal model of a VCSEL bonded to a flip-chip substrate using Au-Au thermocompression bonding. [Figure 10] FIG. 10 is a FIB cross section revealing a crack in a metal contact in a VCSEL bonded to a substrate using Au-Au thermocompression bonding. [Figure 11] 11A and 1B are thermal models showing that cracks in a VCSEL bonded to a substrate and in its metal contacts severely impair thermal performance. [Figure 12] FIG. 12 is an image of a VCSEL bonded to a flip-chip substrate using Au-In solid-liquid interdiffusion (SLID) bonding. [Figure 13] FIG. 13 is a schematic diagram of the Au—In phase. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] In the following description of the preferred embodiment, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. It is to be understood that other embodiments may be utilized and structural changes may be made without departing from the scope of the present invention.

[0011] (Technical description) This disclosure describes a III-nitride VCSEL with a tunnel junction intracavity contact and an ion implant aperture, as shown in FIGS. 1(a)-1(b).

[0012] FIG. 1A illustrates a VCSEL structure 100 prior to flip-chip bonding, the VCSEL structure 100 including a substrate 102, a sacrificial layer 104 on or above the substrate 102, an n-type layer 106 on or above the sacrificial layer 104, an etch stop layer 108 on or above the n-type layer 106, an n-type layer 110 on or above the etch stop layer 108, an active layer 112 on or above the n-type layer 110, an electron blocking layer 114 on or above the active layer 112, a p-type layer 116 on or above the electron blocking layer 114, and a p-type layer 116 on or above the p-type layer 116. ++ p-type layer 118 (having a higher p-type dopant concentration than p-type layer 116); ++ An n-type layer 120 on or above the type layer 118 , a mirror 122 on or above the n-type layer 120 , and a metal layer 124 on or above the n-type layer 120 .

[0013] FIG. 1B illustrates the VCSEL 100b after processing, which includes a second mirror 126 on or above the etch stop layer 108, an etch stop layer 108 on or above the n-type layer 106, a second metal layer 128 on or above the n-type layer 106, an n-type layer 110 on or above the etch stop layer 112, an active layer 114 on or above the n-type layer 110, an electron blocking layer 114 on or above the active layer 112, a p-type layer 118 on or above the electron blocking layer 114, and a p-type layer 116 on or above the p-type layer 116. ++ p-type layer 118 (having a higher p-type dopant concentration than p-type layer 120); ++ An n-type layer 120 on or above the type layer 118 , a first mirror 122 on or above the n-type layer 120 , and a first metal layer 124 on or above the n-type layer 120 .

[0014] Both the structure 100 and the VCSEL 100b also include a current aperture 130 and a dielectric layer 132 on a sidewall 134.

[0015] The following sections describe the important design changes and major performance improvements enabled by the present invention compared to the m-plane VCSEL reported in

[10] . As a result, the present disclosure is the first report of an m-plane VCSEL lasing under continuous wave (CW) operation at room temperature. A. Improved Active Region Design with Thicker Quantum Wells

[0016] The present invention discloses the use of thicker quantum wells (e.g., two MQWs, i.e., 14 nm QWs and 1 nm barriers) compared to seven MQWs (with 3 nm QWs and 1 nm barriers) described in

[10] . Important improvements resulting from the use of thicker QWs include higher gain enhancement factors: thicker QWs have more active gain medium aligned with the optical field, which means that modal gain is increased with thicker QWs. The well thickness examples used herein are the widest QW thicknesses reported for III-nitride VCSELs, since most reports are for the c-plane, which limits thickness due to the quantum confined Stark effect (QCSE). m-plane oriented QWs allow much thicker QWs due to the absence of QCSE.

[0017] (B. Improved flip chip bonding using indium-gold (In-Au) bonding instead of Au-Au bonding) In one or more embodiments, flip-chip bonding using (In-Au) is used as an alternative to Au-Au bonding as described in

[10] . Conventional m-plane VCSELs have not been able to achieve CW operation due to poor thermal performance. The main path for heat transport is through a thin metal contact around the bottom dielectric distributed Bragg reflector (DBR) to the flip-chip substrate. Cross-sectional SEM analysis of Au-Au bonded devices reveals the presence of cracks and voids in the main metal path for heat transport that likely prevent CW operation. The cracks and voids were caused by the high temperature and pressure required for Au-Au bonding.

[0018] Key improvements resulting from using In-Au bonding: · In-Au bonding can be performed at significantly lower forces and temperatures compared to Au-Au bonding. · In-Au bonded devices have fewer cracks and there is a much more robust path for heat transport in In-Au bonded devices.

[0019] As a result, the use of In-Au junctions improves thermal performance and enables CW VCSEL operation.

[0020] (C. Longer cavity length) In one or more embodiments, the VCSEL has a cavity longer than 7λ (eg, 23λ instead of 7λ).

[0021] Heat generated in the active area cannot flow directly to the flip-chip substrate due to the insulating bottom dielectric DBR. The primary path for heat flow is through the p-side thin metal contact through the bottom DBR.

[0022] COMSOL thermal modeling shows that increasing the cavity length greatly improves the thermal performance. GaN has a thermal conductivity of 130 W / mK, therefore increasing the cavity length aids in the heat distribution throughout the cavity, resulting in a lower active region temperature. A thicker cavity length has a smaller resonant mode spacing, which ensures matching of the resonant modes with the gain spectrum. This is especially helpful during CW operation when the gain spectrum is significantly red-shifted.

[0023] D. Improved MBE / MOCVD Tunnel Junction Regrowth In one or more embodiments, the VCSEL includes MBE tunnel junction regrowth using an indium surfactant at a lower growth temperature (e.g., growth at less than 750° C.). In one or more embodiments, the tunnel junction regrowth temperature is 740° C. Reference

[10] describes 750° C. growth without an indium surfactant.

[0024] Key improvements resulting from growth with indium surfactants: Molecular beam epitaxy (MBE) regrowth optimization experiments show that a slightly lower growth temperature improves the electrical properties and the addition of an indium surfactant improves the surface morphology. · The root mean square (RMS) roughness of the MBE tunnel junction regrowth was 1.5-2 nm for the demonstrated CW VCSELs.

[0025] The present design results in lower series resistance and lower turn-on voltage, which contributes to CW operation.

[0026] Maintaining a smooth surface morphology is crucial for VCSELs to minimize scattering losses. In addition to scattering losses, roughness reduces the reflectivity of the DBR as the roughness propagates throughout the DBR. Ideally, the RMS roughness should be less than 1 nm or at least less than 6 nm over an area of, for example, 5 μm×5 μm, 1 μm×1 μm, or 10 μm×10 μm (devices with an RMS roughness of 6 nm did not reach the threshold for lasing).

[0027] While the MBE regrowth is relatively rough on the m-plane, it is much smoother on the semipolar orientation. Thus, semipolar oriented VCSELs can be fabricated. Another method to obtain a smooth surface on the m-plane is the regrowth of the tunnel junction by metal organic chemical vapor deposition (MOCVD).

[0028] (E. Removal of Oxide Residue After PEC Undercut Etch) After PEC undercut etching to remove the original m-plane GaN substrate, rough oxide residues were found on the GaN surface. The previous design

[10] did not perform any treatment to remove the residual oxide.

[0029] The presence of a rough oxide layer may explain some of the problems with the conventional design

[10] . The conventional device

[10] had a higher voltage which could be attributed to the n-electrode contacting oxide residue. Conventional devices

[10] exhibited filament oscillations that could be explained by the presence of non-uniform oxide residues within the aperture.

[0030] The CW VCSELs described herein have a root mean square (RMS) roughness of less than 1 nm on the n-side after removal of the PEC oxide residue. The most effective method for removing the residue was to soak the sample in Tergitol detergent and gently wipe the sample with a foam swab.

[0031] The method was performed on a VCSEL as described herein.

[0032] Other methods of residue removal include immersing (or treating) the sample in an aqueous KOH solution (i.e., 45% KOH for 30 minutes). Lower molarity KOH can be used if it is heated. This removed most of the residue, indicating that the residue is likely some form of gallium oxide remaining after the PEC etch. While most of the residue can be removed with KOH, there were remaining cube-like features that could not be removed using KOH. These features are likely indium oxide or hydroxide and can be removed by wiping with Tergitol. Other methods of residue removal include treating the sample with HCl.

[0033] Important improvements observed after removing oxide residue include: A smooth surface on the n-side with an RMS roughness smaller than 1 nm (e.g., over an area of ​​5 μm x 5 μm, 1 μm x 1 μm, or 10 μm x 10 μm). · Improved (reduced) turn-on voltage and series resistance. Elimination of filamentation and observation of well-defined lateral optical modes.

[0034] F. Steps for Fabricating the Device a. Exemplary Method FIG. 2, with reference also to FIGS. 1A and 1B, illustrates a method of fabricating a VCSEL.

[0035] Block 200 represents obtaining a substrate 102 (e.g., a III-nitride substrate such as a GaN substrate). For device 100b measured in Results Section G, a substrate 102 comprising an m-plane GaN substrate with a 1° miscut in the negative c-direction was used.

[0036] Block 202 represents optionally growing a template layer (e.g., a GaN template) on or above the substrate 102. For the devices measured in Results Section G, the template is a GaN layer having a thickness of 1264.6 nm.

[0037] Block 204 represents the growth of one or more sacrificial layers 104 on the template. In one embodiment, the sacrificial layer is a single quantum well. In another embodiment, the sacrificial layer comprises a multiple quantum well (MQW). For the devices measured in Results Section G, a sacrificial 3-period MQW (absorption λ=415 nm) with 5 nm QWs and 7 nm barriers was grown on the template.

[0038] Block 206 includes an n-type layer 106 (e.g., an n-type layer having a higher n-type dopant concentration than n-type layer 110) on or above the sacrificial layer 104. ++ GaN or n ++ For device 100b measured in Results Section G, n ++ The -GaN layer had a thickness of 26 nm.

[0039] Block 208 represents depositing an etch stop layer 108 (e.g., an n-type AlGaN layer or n-AlGaN). For device 100b measured in Results Section G, the etch stop layer 108 is deposited after the n-type AlGaN layer of block 206. ++ The n-AlGaN layer has a thickness of 15 nm on the n-GaN layer.

[0040] Block 210 represents depositing a first n-type III-nitride layer 110 (eg, n-GaN or n-type GaN) on the etch stop layer 108 (eg, n-AlGaN).

[0041] Block 212 represents depositing an active region including a III-nitride active layer 112 on the first III-nitride layer 110. Examples include, but are not limited to, a III-nitride layer including one or more InGaN / GaN QWs. For the devices measured in Results Section G, the active region is a two period InGaN / GaN MQW including 14 nm thick QWs and 1 nm barriers, with the indium and gallium composition being such that the QWs have a band gap such that the peak absorption of the QWs is at a wavelength of 405 nm. In one or more examples, the QWs have a thickness of at least 8 nm, for example, in the range of 8-20 nm.

[0042] Block 214 represents optionally depositing an electron blocking layer 114 (e.g., p-type AlGaN or p-AlGaN) on the active region (e.g., III-nitride layer 112). For the devices measured in Results Section G, the electron blocking layer 114 is a p-AlGaN layer having a thickness of 5 nm.

[0043] Block 216 represents depositing a p-type layer 116 (e.g., a p-type III-nitride layer such as p-GaN) on the electron blocking layer 114 (e.g., p-AlGaN). For the device measured in Results Section G, the p-GaN layer has a thickness of 62 nm.

[0044] Block 218 is a p-type GaN layer on p-type layer 116 (e.g., p-GaN). ++ A mold layer 118 (e.g., p ++ -GaN layer). For the devices measured in Results Section G, ++ The GaN layer has a thickness of 14 nm.

[0045] Block 220 represents optionally performing photoluminescence to verify the wavelength and quality of the active region.

[0046] Block 222 represents annealing the grown structure to activate the p-GaN. For the results presented herein, the structure was thermally annealed at 600° C. for 15 minutes.

[0047] Block 224 represents optionally performing electroluminescence using soldered indium contacts to ascertain the optical output power, wavelength, full width at half maximum (FWHM), and voltage characteristics of the device structure.

[0048] Block 226 represents removing the indium contacts, if necessary. For the devices measured in Results Section G, aqua regia was used to remove the indium contacts.

[0049] Block 228 then deposits dielectric 132 (e.g., SiN x 1 represents depositing a PEC layer (to protect the active area during the PEC etch) and etching to expose the sidewalls 134 of the active area. For the devices measured in Results Section G, a dry etch was performed to expose the sidewalls 134 of the III-nitride active layer 112, including the MQWs.

[0050] Block 230 represents depositing a mask that defines a current aperture 130 in the device structure 100. For device 100b measured in Results Section G, a Ti / Au hard mask was deposited over the aperture and an aluminum ion implant was performed to serve as the current aperture.

[0051] Block 232 represents removing the mask. For the devices measured in Results Section G, the Ti / Au hard mask was removed using aqua regia.

[0052] The layers deposited up to this point were grown by MOCVD.

[0053] Block 234 represents growing the tunnel junction inter-cavity contact 120a by molecular beam epitaxy (MBE) (e.g., n++ -N between GaN layers + -GaN layer). For the devices measured in Results section G, the following layers were used: ++ GaN layer (1E19cm -3 doping concentration, thickness of 39.5972 nm), followed by n + GaN (2.5E18cm -3 doping concentration, 61.7376 nm thickness), followed by n ++ GaN (1.1E20cm -3 doping concentration of 0.1 μm and a thickness of 39.5972 nm) are grown by MBE, and the top final layer is the contact layer for the tunnel junction (n ++ GaN).

[0054] Block 236 represents performing an etch (e.g., a dry etch) to remove the MBE regrown material deposited on the sidewalls (when growing contact 120) to prevent a current leakage path. For the devices measured in Results Section G, a dry etch was performed.

[0055] Block 238 represents depositing a protective layer 132 (e.g., a dielectric such as SiNx, silicon nitride, etc.) on the sidewalls 134. For the devices measured in Results Section G, ion beam deposition (IBD) deposits a SiN x A protective layer 132 containing

[0056] Block 240 represents depositing a mirror 122 (e.g., a distributed Bragg reflector DBR) on the p-side / p-type side 170 of the device structure 100. For the devices measured in Results Section G, IBD was used to deposit a 16 period (16P) SiO2 / Ta2O5 (66.8 / 45.6 nm) DBR on the p-side.

[0057] Block 242 represents etching to expose the sidewalls 140 of the MQW-containing sacrificial layer 104. For the devices measured in Results Section G, a dry etch was performed to expose the sidewalls 142 of the sacrificial MQW.

[0058] Block 244 represents depositing p-type contact (p-contact) 124 and cathode 144 for the PEC etch. For the devices measured in Results Section G, 20 nm / 1000 nm of Ti / Au was deposited to serve as both the p-contact 124 and the cathode for the PEC etch.

[0059] Block 246 represents preparing the flip chip substrate 136 (e.g., sapphire). For the devices measured in Results Section G, a metal layer 138 comprising 20 nm / 100 nm / 100 nm / 15,000 nm / 100 nm Ti / Ni / Au / In / Au was deposited on double-sided polished sapphire 146 to serve as the flip chip substrate 136. The purpose of the top 100 nm Au layer of metal layer 138 was to prevent oxidation of the indium (indium readily diffuses into the gold layer and forms AuIn2 as-deposited).

[0060] Block 248 represents flip-chip bonding the flip-chip substrate 136 to the grown epitaxial structure 100 under suitable conditions. For the device measured in Results Section G, flip-chip bonding was performed under the following conditions: temperature of 210° C., force of 30 Newtons, for 300 seconds. Steps may include selecting a metal alloy system with a sufficiently low melting temperature for the bonding process.

[0061] Block 250 represents the removal of the original substrate 100. For the example illustrated in Figure 1B, the original GaN substrate was removed by performing a PEC etch to selectively etch the sacrificial MQWs. For the devices measured in Results Section G, the PEC etch was performed using 1M KOH and a 390 nm LED array.

[0062] Block 252 represents removing any rough residue (presumably gallium oxide) that appears after the PEC undercut etch. For the devices measured in Results Section G, wiping the samples with Tergitol detergent was performed to remove the rough residue from the n-GaN n-side surfaces 150, 152. Immersing the samples in KOH can also remove most of the oxide.

[0063] Block 254 represents depositing the n-contact 128. For device 100a measured in Results Section G, 10 / 500 nm of Ti / Au was deposited to serve as the n-contact.

[0064] Block 256 represents depositing a mirror 126 (e.g., a DBR) on the n-side 148 of the device 100a. For the device 100a measured in Results Section G, a 12 period SiO2 / Ta2O5 (66.8 / 45.6 nm) DBR was deposited on the n-side 148 using IBD.

[0065] Block 258 represents the end result, namely, the VCSEL 100a (eg, as illustrated in FIG. 1B).

[0066] b. Exemplary Embodiments Steps may be added or omitted such that the VCSEL 100 may be embodied in many ways, including but not limited to the following examples (see FIGS. 1A, 1B, and 12). 1. A VCSEL 100a on a mounting (e.g., a flip chip substrate 136): A thermally conductive joint 160, 1200 is between the mounting and the VCSEL 100a, the joint 160, 1200 including a thermally conductive metal layer 138, whereby heat generated during operation of the VCSEL is transferred from the VCSEL to the mounting, and the VCSEL emits continuous wave electromagnetic radiation. 2. The device 100a described in Example 1, wherein the thermally conductive joint 160, 1200 is crack-free or contains fewer cracks than a joint between the VCSEL and the mounting formed using Au-Au thermocompression bonding. 3. The element 100a as in one or any combination of the preceding embodiments, wherein the thermally conductive joint 160, 1200 comprises a metal formed from a liquid metal phase. 4. The device 100a according to one or any combination of the preceding embodiments, wherein the VCSEL 100a is bonded to the mounting by solid-liquid interdiffusion bonding (e.g., achieved by a short liquid phase of one low melting point metal (e.g., indium) and immediate solidification caused by diffusion and mixing with a second high melting point metal (e.g., gold), creating an intermetallic phase). 5. The device 100a of any one or combination of the preceding embodiments, wherein the VCSEL comprises a first mirror 122 defining a cavity for electromagnetic radiation emitted from the VCSEL and a second mirror 126, and the VCSEL 100a is bonded to the mounting by forming a bond 160, 1200 including a metal layer 138 in a liquid state around the first mirror 122. In one or more embodiments, the metal layer 138 is conformal with the first mirror 122. 6. The device according to one or any combination of the previous embodiments, wherein the VCSEL 100a comprises a first mirror 122 and a second mirror 126 defining a cavity for electromagnetic radiation, the junction 160, 1200 includes a metal layer 138, and one of the first mirror 122 or the second mirror 126 is embedded in the metal layer 138. 7. The element 100a according to one or any combination of the preceding embodiments, wherein the VCSEL comprises a first mirror 122 and a second mirror 126 defining a cavity for electromagnetic radiation emitted from the VCSEL, and the junction 160, 1200 includes a mold for the metal layer 138, the metal layer 138 being molded around the first mirror 122 or the second mirror 126. 8. The element 100a according to one or any combination of the preceding embodiments, wherein the joint 160, 1200 comprises an intermetallic compound having a solid phase including two or more metallic elements. 9. The element 100a according to one or any combination of the preceding embodiments, wherein the junction 160, 1200 comprises a first metal diffused into the second metal so as to mix with the second metal, the first metal having a lower melting point than the second metal. 10. The element 100a according to one or any combination of the preceding embodiments, wherein the first metal comprises indium and the second metal comprises gold. 11. A VCSEL 110a as described in one or any combination of the preceding examples, comprising a light emitting III-nitride active region 112 including quantum wells (QWs), each of the quantum wells having a thickness greater than 8 nm (however, thicknesses less than 8 nm are also possible while achieving continuous wave emission of electromagnetic radiation). 12. The VCSEL of example 11, wherein the quantum well has a thickness in the range of 8 to 20 nm. 13. The VCSEL 100a as described in one or any combination of the preceding embodiments, wherein the active region 112 has a non-polar or semi-polar crystal orientation. 14. The VCSEL 100a according to one or any combination of the preceding embodiments, wherein the VCSEL has a cavity length L of at least 7λ (λ is the peak wavelength of the light / electromagnetic radiation emitted from the active region when the light / electromagnetic radiation is within the active region), the peak wavelength being the wavelength of the light / electromagnetic radiation having the highest intensity. 15. The VCSEL 100a according to Example 14, wherein the cavity length L is within a range of 20λ to 100λ. 16. The VCSEL 100a according to one or any combination of Examples 1-15, wherein the VCSEL further comprises: an active region 112 between a first III-nitride n-type layer 110 and a III-nitride p-type layer 116; a second III-nitride n-type layer 120 forming a tunnel junction with the III-nitride p-type layer; the second III-nitride n-type layer comprising a contact layer for the tunnel junction; and an upper surface 162 of the contact layer (or an upper surface 162 of layer 120) having a root-mean-square (RMS) surface roughness of less than 2 nanometers (nm) when the VCSEL is a nonpolar device, or less than 1 nm when the VCSEL is a semipolar device. 17. The VCSEL 100a as claimed in one or any combination of the preceding embodiments, wherein the active region 112 is between the III-nitride n-type layer 110 and the III-nitride p-type layer 116, and wherein after etching, n-side surfaces 150, 152 of the III-nitride n-type layers 110, 106 are exposed and the substrate 102 on which the active region 112 / VCSEL 100 structure was grown is at least partially removed, and the n-side surfaces 150, 152 are surface treated to have an RMS surface roughness of less than 1 nm. 18. The VCSEL 100a of Example 16 or 17, wherein the surface roughness of the surface 162 and / or the surfaces 150, 152 is over an area of ​​5 μm×5 μm, 1 μm×1 μm, or 10 μm×10 μm (μm being micrometers). 19. The VCSEL 100a of Examples 16-17, wherein the surface treatment removes oxide residue after etching. 20. The VCSEL 100a as described in one or any of Examples 1-19, further comprising a mirror 122, a metal layer 124 on the mirror 122, a flip-chip substrate 136, a bonding layer 160, 1200 on the flip-chip substrate 136 comprising gold, and a bonded interface between the bonding layer 160, 1200 and the metal layer 124, wherein the bonded interface comprises indium bonded to gold. 21. The device 100a of any of the previous embodiments, further comprising charge injection layers 110, 116 coupled to a light-emitting active region 112, the active region emitting light in response to electrons and holes (electrons through layer 110 and holes through layer 116) injected into the active region through the charge injection layers 110, 116. 22. The VCSEL 100a, wherein the VCSEL 100a comprises a light emitting III-nitride active region including quantum wells (QWs), each of the quantum wells having a thickness greater than 8 nm. 23. The VCSEL 100a of example 22 in combination with one or any combination of examples 1-10 or 11-21. 24. A method of fabricating a vertical cavity surface emitting laser (VCSEL) structure, the method including: growing a sacrificial layer on a semipolar or nonpolar III-nitride substrate; growing a III-nitride VCSEL structure including an active region between an n-type layer and a p-type layer, the active region including a quantum well having a thickness greater than 8 nm; growing a tunnel junction inter-cavity contact 120a on the p-type III-nitride using an indium surfactant at a temperature less than 750° C.; depositing a mirror on the p-type side of the VCSEL structure; coating sidewalls of the active region with a dielectric layer; depositing a metal on the mirror; flip-chip bonding a flip-chip substrate to the metal on the mirror using solid-liquid interdiffusion bonding; photoelectrochemically etching the sacrificial layer to at least partially remove the nonpolar or semipolar III-nitride substrate; and using a surface treatment to remove rough residues on the n-type side of the VCSEL structure or on the surface of the n-type layer exposed during the etch. 25. The method of example 24, wherein removing comprises treating the surface with Tergitol detergent or KOH. 26. The method of example 24 or 25, wherein the VCSEL structure is grown with a cavity length of at least 7λ, where λ is the peak wavelength of light emitted from the active region when light is within the active region, the peak wavelength being the wavelength of light having the highest intensity. 27. The method of embodiment 24, 25, or 26, wherein the surface of the n-type layer has a root-mean-square (RMS) surface roughness of less than 1 nm after the surface treatment. 28. The method of example 27, wherein the surface roughness is over an area of ​​5 μm×5 μm, 1 μm×1 μm, or 10 μm×10 μm. 29. The method of any of examples 24-28, wherein the VCSEL emits continuous wave electromagnetic radiation. 30. The method or device according to one or any combination of the preceding Examples 1-29, wherein the mirrors 122, 126 are thermally insulating and / or comprise a dielectric.

[0067] FIG. 1A shows the device structure prior to the flip-chip bonding step. After flip-chip bonding to the sapphire substrate, the original m-plane GaN substrate was removed via PEC etching. FIG. 1(b) shows the fully completed device. This device used sapphire as the flip-chip substrate, but sapphire is not a good heat sink. Better choices for flip-chip substrates are copper, SiC, diamond, AlN, and other materials with high thermal conductivity.

[0068] In one or more embodiments, the VCSEL has a cavity length of at least 7λ, in the range of 7λ to 100λ, or in the range of 20λ to 100λ, where λ is the peak wavelength of light emitted in and from the active region. In one or more embodiments, a VCSEL having a cavity length of at least 7λ is capable of emitting continuous wave electromagnetic radiation.

[0069] c. Further Exemplary Bonding Method Embodiments 3 illustrates a method of fabricating a VCSEL according to one or more embodiments that includes bonding the VCSEL to a mounting using a metal.

[0070] Block 300 represents providing a metal layer over the mounting portion, the metal layer including a first metal and a second metal.

[0071] Block 302 represents heating the metal layer such that the first metal is in a liquid metal state.

[0072] Block 304 represents the step of positioning a VCSEL on a metal layer that includes a first metal in a liquid state.

[0073] Block 306 represents allowing the metal layer to solidify, forming a bond between the VCSEL and the mounting.

[0074] Block 308 represents the end result, a VCSEL on a mount. The VCSEL on a mount / method can be embodied in many ways, including but not limited to the following examples. 1. A method, wherein the VCSEL comprises a first mirror and a second mirror defining a cavity for electromagnetic radiation emitted from the VCSEL, and the positioning includes positioning the first mirror over a metal layer using a force or pressure when the first metal layer is in a liquid metal state such that the first mirror becomes embedded within the metal layer after the metal layer solidifies. 2. The method of example 1, wherein steps 300-308 are mounted such that the VCSEL is bonded to the mounting portion by solid-liquid interdiffusion bonding, the first metal comprising indium and the second metal comprising gold. 3. A method of providing a VCSEL on a mounting portion according to one or any combination of Examples 1-21 in part b of Section F entitled "Exemplary Embodiments" above.

[0075] In one embodiment, the thickness of the bonding metal layer 160, 1200 that worked best was about 2 microns thick Indium on the flip chip substrate (and about 1 micron Au on the GaN device). In one or more embodiments, the bottom DBR mirror is about 1.8 microns thick, so in one or more embodiments, a bonding metal 160, 1200 thickness of 2-3 microns will allow the bottom DBR 122 to be fully embedded in the metal. Thinner bonding metal thicknesses may also work in some embodiments, but may provide a thinner path for heat transport.

[0076] G. Results and Characterization IL, IV, and spectra were measured under both pulsed and CW operation. For light-emitting diodes with comparable active region designs, pulse spectra were acquired at step temperatures up to 60° C. to obtain the peak emission wavelength shift with increasing temperature.

[0077] The VCSEL achieved lasing under both pulsed and CW operation. The lasing was stable for more than 20 minutes under CW operation. The following sections present the results during electroluminescence under pulsed and CW operation.

[0078] (a. Pulse operation measurement (10kHz pulse repetition, 500ns pulse width)) Figure 4A illustrates that the peak output power for the 6 μm aperture diameter VCSEL shown in Figure 1 was 700 μW. Although not shown, the highest output power for a 10 μm aperture diameter element was 1 mW. The best conventional m-plane VCSELs had a peak output power of 550 μW

[10] .

[0079] The laser emission from the device (fabricated according to FIG. 1) was polarized along the α direction with a polarization ratio of 100%.

[0080] FIG. 4B shows that the threshold current is about 12 mA (42.4 kA / cm 2 ), the kink in the LI at threshold at 12 mA in FIG. 2(a) is less pronounced because the large area photodetector measures additional light escaping the element from areas not covered with metal, including the sidewalls and top surface of the element. The kink in the LI at threshold at 12 mA in FIG. 2(b) is much better defined because the spectrometer optical fiber is aligned to the lasing peak, which minimizes the measured spontaneous emission below threshold.

[0081] The differential efficiency of devices fabricated according to Figures 1A-1B improves at currents greater than 30 mA due to the emergence of dominant longer wavelength longitudinal modes (differential efficiency below 30 mA: ηd = 0.267%, differential efficiency above 30 mA: ηd = 0.775%). This is more than twice the differential efficiency of conventional m-plane VCSELs, which had a value of ηd = 0.26% (

[10] ).

[0082] The device fabricated according to Figures 1A-1B had a series resistance of Rd = 27.3 Ω, which is improved (smaller) compared to a conventional m-plane VCSEL, which had a value of Rd = 37 Ω (

[10] ).

[0083] Figures 5A-5B show that the onset of lasing occurs between 11.4 and 15.1 mA, which is consistent with the threshold current of 12 mA from the IL curve in Figure 4B. Both the 406 nm and 412 nm lasing modes emerge at 15.1 mA. The 406 nm lasing mode is likely to emerge first at a lower current than the 412 nm mode. As the current is increased, the increased temperature causes the peak gain wavelength to red-shift. This results in the longer wavelength mode increasing in intensity as the shorter wavelength mode decreases in intensity.

[0084] FIG. 5A illustrates that at 17.7 mA, the 406 nm mode decreases in intensity while the 412 nm mode increases in intensity. The effect of temperature-induced red-shift of the emission was further investigated by measuring the spectra at various pulse widths. FIGS. 5A-5B correspond to a 500 ns pulse width, but for a 100 ns pulse width, the peak emission wavelength was 412 nm instead of 419.3 nm. For a 1,000 ns pulse width, the threshold current was lower than 11 mA. Longer pulse widths cause more heating, which red-shifts the gain and lowers the threshold for the longer wavelength modes.

[0085] As shown in FIG. 5B, the dominant lasing mode emerges at 419.3 nm at 33.2 mA. The peak spontaneous emission wavelength is 402 nm, but the longer wavelength mode dominates in intensity. Possible explanations include that the longer wavelength experiences lower levels of optical loss because (1) the longer wavelength has a much lower level of loss from the ion-implanted region and (2) the TMM model indicates that the longer wavelength has less mode overlap with the highly absorbing tunnel junction in this design.

[0086] (b. Continuous Wave (CW) Operation) 6A-6B illustrate that the threshold current is about 10 mA, corresponding to a lasing wavelength of 412 nm. The LI kink at 10 mA is obscured by measurements of the spontaneous emission power using a large area photodetector as previously described.

[0087] Measuring the spectrum provides further insight into and validation of the threshold for lasing, as shown in Figure 6B, which shows that the onset of lasing occurs at 11.5 mA, FWHM=0.74 nm, and the 412 nm mode increases in intensity up to a current of 15.1 mA where the lasing mode emerges at a wavelength of 420 nm. The lasing mode at 420 nm has a FWHM=1.5 nm (spectrometer limit).

[0088] Unlike the pulsed measurements, the lasing mode at 406 nm does not appear during CW operation due to the red-shifted peak gain. For the longer wavelength lasing mode, the lasing wavelength is 419.69 nm at 15.1 mA, which red-shifts to 420.44 nm at 19.9 mA. This corresponds to a shift in the Fabry-Perot wavelength with temperature of about 0.016 nm / °C, which is comparable to reported values ​​(

[15] ).

[0089] At CW operation at 13.5 mA, the differential efficiency is good (average differential efficiency ηd=0.4095%, peak differential efficiency ηd=1.11392%) due to the emergence of a lasing mode at 420 nm.

[0090] (c. Modal structure) The lateral mode structure of devices fabricated according to Figures 1A-1B is a much improved version of conventional m-plane VCSELs, which exhibit filament oscillation (a probability distribution of oscillations within the aperture) (

[10] ).

[0091] The lateral mode illustrated in Figure 7A shows a well-defined lasing mode in the center of the aperture. The improved lateral mode profile can be attributed to the following: Optimization of MBE regrowth, which can improve current spreading and uniformity Removal of oxide residue after PEC etching

[0092] FIG. 7B is an image of the mode captured with a longer integration time to show the spontaneous emission more clearly.

[0093] (d. Thermal impedance) Conventional m-plane VCSELs have not been able to achieve CW operation due to poor thermal performance. Under CW operation, increased temperature red-shifts the gain spectrum away from the cavity resonance, which prevents lasing. The poor thermal performance is mainly due to the adiabatic dielectric DBR on the p-side. Thermal modeling using COMSOL predicts that only a small amount of heat flux occurs through the dielectric DBR. The main path for heat transport is bypassing the dielectric DBR, through the metal contacts, and to the flip-chip substrate. Cross-sectional SEM analysis revealed the presence of cracks and voids in the main metal path for heat transport, which likely prevents CW operation.

[0094] As illustrated herein, CW VCSEL operation has been achieved using a design that improves thermal performance. · Longer cavity length (e.g. 23λ instead of 7λ). Improved flip chip bonding using Indium-Gold bonding instead of Au-Au bonding. In-Au bonding can be performed at much lower forces and temperatures compared to Au-Au bonding. This results in less cracking in the device and there is a much more robust path for heat transport.

[0095] FIG. 8 illustrates the heating effect by plotting the spectrum under CW operation. The spontaneous emission range red-shifts with increasing current due to increased active region temperature. At 9 mA, the spontaneous emission is centered at 405.3 nm and red-shifts to 416 nm at a current of 25 mA. The FWHM is 19.1 nm at 9 mA and spreads to a value of 29.9 nm at 25 mA. The shift of the peak emission wavelength with increasing temperature was found to be 0.048 nm / °C by measuring the spectrum of the m-plane LED at step temperatures up to 60°C. Assuming a linear shift of 0.048 nm / °C, the VCSEL active region temperature can be estimated by its peak spontaneous emission wavelength. At 15 mA, the active region temperature is about 180°C. At 19 mA, the active region temperature is about 226°C. Based on these calculations, the thermal impedance is about 1,500°C / W. A similar analysis was performed on a VCSEL with a cavity length of 7λ, which has a thermal impedance of about 3,000° C. / W.

[0096] (e. Solid-liquid interdiffusion (SLID) bonding) Conventional GaN VCSELs fail to lasing under CW operation due to their poor thermal performance, which is due in particular to the adiabatic dielectric DBR mirror on the bottom side of the device. The COMSOL thermal model (Figure 9) shows that the main path for heat transport is around the bottom DBR, through the thin metal contact, and towards the flip-chip substrate. Figure 10 shows a FIB cross section revealing a crack in the metal contact. The thermal model illustrated in Figures 11A and 11B shows that a crack in the metal contact significantly reduces thermal performance.

[0097] Au-Au thermocompression bonding forms bonds through atomic diffusion and requires relatively high temperatures and bonding forces since the melting temperature for gold is 1,064° C. Cracking of entire VCSEL devices has been caused by Au-Au pressure bonding due to the high temperatures and forces required for Au-Au thermocompression bonding. However, Au-Au thermocompression bonding is performed below the melting temperature of Au and does not contain a molten liquid phase during bonding since gold has a much higher melting temperature.

[0098] Techniques that incorporate a liquid metal phase during bonding, such as SLID bonding, allow flip-chip bonding with significantly lower bonding forces and help overcome some of the problems posed by Au-Au thermocompression bonding. The relatively soft joining metals used for SLID can reduce cracking by providing cushioning when the joining surfaces are forced together. Utilizing a liquid metal phase during bonding to completely embed the p-DBR in the metal, thereby creating a thicker metal path for heat transport. Unlike Au-Au thermocompression bonding, utilizing a liquid metal phase during bonding (as is possible with Au-In SLID bonding) allows the bottom insulating DBR (p-DBR) to be completely embedded in the bonding metal. Embedding the insulating p-DBR in metal creates a much thicker metal path for heat transport, especially compared to m-plane VCSELs where heat flow is impeded through a cracked 1 μm thick gold contact along the sidewall of the bottom DBR (as fabricated using Au-Au thermocompression bonding).

[0099] FIG. 12 illustrates a VCSEL bonded to a flip-chip substrate using a SLID, illustrating that the SLID softens the bond, reduces cracking, and allows for a thicker metal path for heat transport.

[0100] FIG. 13 (Au-In phase diagram) illustrates the advantage of using Au-In SLID bonding, since Au-In alloys have a unique low temperature liquid phase greater than about 156° C. for In-rich alloys (greater than 54 wt%). This allows flip chip bonding at much lower temperatures and forces compared to Au-Au or Au-Sn bonding, while also incorporating a liquid metal phase. As seen in the phase diagram, Au-In alloys with In compositions greater than 54% consist of a mixture of In phase and AuIn2 intermetallic compounds (53.8 wt% In) with a solidus temperature of 156° C. Above 156° C., the mixture forms a liquid phase with AuIn2 particles. For compositions of 36.8 to 54 wt% In, the alloy becomes a mixture of AuIn (36.79 wt% In) and AuIn2 intermetallic compounds, and the solidus temperature is much higher with a value of 495.4° C. This significant difference in solidus temperatures is a particularly useful feature because it allows for a relatively low temperature liquid phase of greater than 156°C during joining (for >54 wt% In alloys), while the final alloy can be designed to have a lower In composition so that it can withstand temperatures up to 495.4°C without melting (for 36.8-54 wt% In alloys).

[0101] Other types of bonds such as Au-Sn, Au-Ge, and Au-Si eutectic alloys may also work, but Au-In alloys have the lowest temperature liquid phase. Pure indium bonds may also be employed, but the resulting bond is only stable up to about 156° Celsius (the melting temperature of indium). Au-In SLID bonds can be made so that the Au-In alloy after bonding has a lower In composition, and therefore the bond is stable up to about 495° Celsius.

[0102] Gold-tin (Au-Sn) alloys are another possible alternative because they have a very low melting temperature of 280° C. in a eutectic composition of 80% Au and 20% Sn. However, 280° C. is not much lower than the temperatures used in conventional Au-Au bonding experiments, and therefore cracking may remain a problem.

[0103] (H. Advantages and Improvements) Nonpolar III-nitride VCSELs are very promising due to their unique properties such as higher material gain and 100% polarization ratio. Thicker QWs are desirable for III-nitride VCSELs to maximize the gain enhancement factor. Compared to c-plane, nonpolar and semipolar orientations allow for thicker quantum wells, i.e., thicknesses >9 nm.

[0104] This disclosure details the fabrication method for the first m-plane VCSEL that achieved lasing under CW operation at room temperature. All previous m-plane III-nitride VCSELs were only able to lasing under pulsed operation. The key performance improvements of the present invention compared to previous m-plane VCSEL designs

[10] are summarized in Table 1. [Table 1]

[0105] Further information regarding embodiments of the present invention can be found in [27-30].

[0106] (Terminology) GaN, and its ternary and quaternary compounds incorporating aluminum and indium (AlGaN, InGaN, AlInGaN), are generally referred to herein by the terms (Al,Ga,In)N, III-nitrides, III-N, III-nitrides, nitrides, Al, Ga, In ... (1-x-y) In y Ga xN (where 0 < x < 1, 0 < y < 1), or AlInGaN is referred to. All of these terms are equivalent and are intended to be broadly construed to include the nitrides of the respective single species of Al, Ga, and In, as well as the binary, ternary, and quaternary compositions of such group III metal species. Thus, these terms include the compounds AlN, GaN, and InN, and the ternary compounds AlGaN, GaInN, and AlInN, and the quaternary compound AlGaInN as species included within such terminology. When two or more of the (Ga, Al, In) component species are present, all possible compositions including stoichiometric ratios as well as "off-stoichiometric" ratios (with respect to the relative molar fractions present in each of the (Ga, Al, In) component species present in the composition) can be employed within the broad scope of the present invention. Thus, it should be understood that the following discussion of the present invention mainly referring to GaN materials is applicable to the formation of various other (Al, Ga, In)N material species. Further, (Al, Ga, In)N materials within the scope of the present invention may further include small amounts of dopants and / or other impurities or inclusion materials. Boron (B) may also be included.

[0107] One approach to eliminating the spontaneous and piezoelectric polarization effects in GaN or group III nitride based optoelectronic devices is to grow the group III nitride device on a nonpolar plane of the crystal. Such planes contain an equal number of Ga (or group III atoms) and N atoms and are charge neutral. Further, subsequent nonpolar layers are equivalent to each other, and thus, the bulk crystal will not be polarized along the growth direction. Two such groups of symmetrically equivalent nonpolar planes in GaN are the {11-20} group, which is collectively known as the a-plane, and the {1-100} group, which is collectively known as the m-plane. Thus, nonpolar group III nitrides are grown along a direction perpendicular to the (0001) c-axis of the group III nitride crystal.

[0108] Another approach to reducing polarization effects in (Ga,Al,In,B)N devices is to grow the devices on semipolar planes of the crystal. The term "semipolar plane" (also referred to as "semipolar plane") can be used to refer to any plane that cannot be classified as a c-plane, an a-plane, or an m-plane. In crystallographic terms, a semipolar plane can include any plane that has at least two nonzero h, i, or k Miller indices and one nonzero l Miller indices.

[0109] Some commonly observed examples of semipolar planes include the (11-22), (10-11), and (10-13) planes. Other examples of semipolar planes in the wurtzite crystal structure include, but are not limited to, the (10-12), (20-21), and (10-14). The polarization vector of the nitride crystal does not lie within such a plane or perpendicular to such a plane, but rather is tilted at an angle relative to the normal to the plane. For example, the (10-11) and (10-13) planes are at 62.98° and 32.06° to the c-plane, respectively.

[0110] The gallium or Ga face of GaN is + or (0001) plane, and the nitrogen or N-face of the GaN or III-nitride layer is c - Or the (000-1) plane.

[0111] The prefix "n-" (e.g., n-GaN) denotes n-type, and the prefix "n ++ The prefix "p-" (e.g., p-GaN) denotes a p-type dopant concentration, and the prefix "p-" (e.g., p-GaN) denotes a p-type dopant concentration. ++ -" (e.g., p++-GaN) represents a higher p-type dopant concentration.

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[0113] (Conclusion) The description of the preferred embodiments of the present invention now concludes. The foregoing description of one or more embodiments of the present invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teachings. It is intended that the scope of the present invention be limited not by the detailed description for carrying out the invention, but rather by the claims appended hereto.

Claims

1. An element, the element comprising: A mounting part, a vertical cavity surface emitting laser (VCSEL) on the mounting portion, the VCSEL including a cavity defined by a first mirror and a second mirror, the cavity including a plurality of Group III-nitride layers, at least one of the first mirror and the second mirror being a distributed Bragg reflector (DBR) mirror positioned between the mounting portion and the plurality of Group III-nitride layers; a thermally conductive joint between the mounting portion and the VCSEL; Equipped with the thermally conductive junction comprises a metal layer disposed from a surface of the DBR mirror to a surface of one of the III-nitride layers and is thermally conductive, heat generated during operation of the VCSEL is transferred from the VCSEL to the mounting, and the VCSEL emits continuous wave electromagnetic radiation; the metal layer comprises an alloy, the alloy comprising a first metal diffused into a second metal so as to intermix with the second metal, the first metal having a lower melting point than the second metal; The element, wherein the first metal comprises indium and the second metal comprises gold.

2. The device of claim 1 , wherein the DBR mirror is embedded within the layer of metal.

3. The device of claim 1 , wherein the DBR mirror serves as a mold for the layer of metal.

4. The device of claim 1 , wherein the thermally conductive joint comprises an intermetallic compound having a solid phase containing two or more metallic elements.

5. the VCSEL includes a light emitting III-nitride active region that emits the continuous wave electromagnetic radiation in response to a current input into the active region; The device of any one of claims 1 to 4, wherein the light emitting III-nitride active region comprises a plurality of quantum wells (QWs), each of the plurality of quantum wells having a thickness greater than 8 nm.

6. the VCSEL includes a light emitting III-nitride active region that emits the continuous wave electromagnetic radiation in response to a current input into the active region; 10. The device of claim 1 , wherein the light emitting III-nitride active region comprises a plurality of quantum wells (QWs), each of the plurality of quantum wells having a thickness in the range of 8 to 20 nanometers (nm).

7. The device of claim 6 , wherein the light emitting III-nitride active region has a nonpolar or semipolar crystal orientation.

8. the VCSEL has a cavity length of at least 7λ, where λ is a peak wavelength of the continuous wave electromagnetic radiation emitted from an active region of the VCSEL, measured within the active region; The device of claim 5 , wherein the peak wavelength is the wavelength of the continuous wave electromagnetic radiation having the highest intensity.

9. The device of claim 8, wherein the cavity length is in the range of 20λ to 100λ.

10. The VCSEL is the active region between a first Group III-nitride n-type layer and a Group III-nitride p-type layer; a second Group III-nitride n-type layer forming a tunnel junction with the Group III-nitride p-type layer; a contact layer for the tunnel junction; an upper surface of the contact layer; Further comprising:

6. The device of claim 5, wherein the top surface of the contact layer has a root-mean-square (RMS) surface roughness of less than 2 nanometers (nm) when the VCSEL is a nonpolar device, or a RMS surface roughness of less than 1 nm when the VCSEL is a semipolar device.

11. The device of claim 10 , wherein the surface roughness is over an area of ​​5 μm×5 μm, 1 μm×1 μm, or 10 μm×10 μm.

12. An element, the element comprising: a VCSEL including a first mirror and a second mirror defining a cavity and a plurality of Group III-nitride layers for electromagnetic radiation emitted from the VCSEL; A flip chip substrate; a metal layer between the VCSEL and the flip-chip substrate; Equipped with the metal layer includes indium and gold; the metal layer comprises an alloy, the alloy comprising the indium diffused into the gold so as to intermix with the gold; the first mirror or the second mirror is embedded in the metal layer such that the metal layer is provided from a surface of the first mirror or the second mirror to a surface of one of the III-nitride layers.

13. The device of claim 12 , wherein the first mirror and the second mirror each comprise a distributed Bragg reflector including a dielectric layer.

14. 1. A method for fabricating a vertical cavity surface emitting laser (VCSEL) structure, comprising: The method comprises: obtaining a VCSEL, the VCSEL including a plurality of Group III-nitride semiconductor layers, a first mirror on the plurality of Group III-nitride semiconductor layers, and a second mirror, the first mirror and the second mirror defining a cavity for electromagnetic radiation emitted from the VCSEL; bonding the VCSEL to a mounting portion using a metal layer, the metal layer being provided from a surface of the first mirror to a surface of one of the plurality of Group III nitride semiconductor layers; Including, The joining step comprises: providing the metal layer on the mounting portion, the metal layer comprising a first metal and a second metal, the first metal including indium and the second metal including gold, the first metal having a lower melting point than the second metal; heating the metal layer such that the first metal is in a liquid metal state; disposing the VCSEL on the metal layer containing the first metal in the liquid metal state; allowing the metal layer to solidify and form a bond between the VCSEL and the mounting; Including, whereby the metal layer comprises an alloy, the alloy comprising the first metal diffused into the second metal so as to intermix with the second metal, and the VCSEL emits continuous wave electromagnetic radiation.

15. 15. The method of claim 14, wherein the placing comprises positioning the first mirror onto the metal layer using force or pressure while the first metal is in the liquid metal state, and the first metal becomes embedded within the metal layer after the metal layer solidifies.

16. 1. A method of fabricating a vertical cavity surface emitting laser (VCSEL) structure, the method comprising: Growing a sacrificial layer on a semipolar or nonpolar III-nitride substrate; growing a plurality of Group III-nitride layers on the sacrificial layer, the plurality of Group III-nitride layers including an active region between an n-type layer and a p-type layer, the active region including a quantum well having a thickness greater than 8 nm; growing a tunnel junction structure on the p-type layer using an indium surfactant at a temperature below 750° C.; depositing a mirror on a p-type side of the plurality of Group III-nitride layers; coating sidewalls of the active area with a dielectric layer; depositing an Au—In alloy on a surface of one of the III-nitride layers from a surface of the mirror to a p-type side of the III-nitride layers; flip-chip bonding a flip-chip substrate to the Au—In alloy using solid-liquid interdiffusion bonding; removing at least partially the semipolar or nonpolar III-nitride substrate by photoelectrochemically etching the sacrificial layer; using a surface treatment to remove rough residues on the n-type sides of the III-nitride layers or on surfaces of the n-type layers exposed during the etching; Including, This produces a VCSEL structure that emits continuous wave electromagnetic radiation.

17. 17. The method of claim 16, wherein removing using the surface treatment comprises treating the surface with Tergitol detergent or KOH.

18. 18. The method of claim 16 or claim 17, wherein the VCSEL structure is grown with a cavity length of at least 7λ, where λ is a peak wavelength of light that is emitted from the active region when the light is within the active region, the peak wavelength being the wavelength of the light that has the highest intensity.

19. The method according to any one of claims 16 to 18, wherein the surface of the n-type layer has a root-mean-square (RMS) surface roughness of less than 1 nm after the surface treatment.

20. 20. The method of claim 19, wherein the surface roughness is over an area of ​​5 μm×5 μm, 1 μm×1 μm, or 10 μm×10 μm.

21. 10. The VCSEL of claim 1, wherein the VCSEL comprises a light emitting III-nitride active region including a plurality of quantum wells (QWs), each of the plurality of quantum wells having a thickness greater than 8 nm.

22. The method of claim 14 , wherein the VCSEL is bonded to the mounting by solid-liquid interdiffusion bonding.

23. 15. The method of claim 14, wherein the VCSEL is bonded to the mounting by forming the bond including the metal layer in the liquid metal state around a periphery of the first mirror.

24. the VCSEL comprises an active region between a Group III-nitride n-type layer and a Group III-nitride p-type layer; an n-side surface of the III-nitride n-type layer is exposed after etching to at least partially remove a substrate on which the active region was grown; 15. The method of claim 14, wherein the n-side surface is surface treated to have an RMS surface roughness of less than 1 nm.

25. 25. The method of claim 24, wherein the surface treatment removes oxide residues after the etching.

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