Electrostatic protection structure and manufacturing method thereof

Abstract

The present invention relates to an electrostatic protection structure and a manufacturing method thereof, the electrostatic protection structure includes a substrate, a buried layer, a first deep well, a second deep well, and a third deep well, in which a well region of an opposite conductivity type and a heavily doped region of the same conductivity type are provided in the first deep well, a well region of the same conductivity type and a heavily doped region are provided in the second deep well and the third deep well, respectively, the first deep well, the first well region, and the second well region are floating, the first heavily doped region is pulled out and connected to an electrostatic voltage, and the sixth heavily doped region is grounded. When a positive voltage is input to the electrostatic port, the first highly doped region, the first well region, the second highly doped region, the third highly doped region, the second well region, and the fourth highly doped region form transistors connected in series with each other, thereby realizing a forward withstand voltage, and when a negative voltage is input to the electrostatic port, the buried layer, the second deep well, the third well region, the fourth well region, the third deep well, the substrate, and the first deep well form a parasitic transistor, and the first deep well and the first well region form a diode, thereby realizing a reverse withstand voltage by the parasitic transistor and the diode.

Description

[Technical field]

[0001] The present invention relates to the field of semiconductor technology, and in particular to an electrostatic protection structure and a method for fabricating the same.

[0002] This application claims priority based on a Chinese patent application bearing application number 2021106585184 and title "Electrostatic protection structure and manufacturing method thereof" filed with the China Patent Office on June 15, 2021, the entire contents of which are incorporated herein by reference. [Background technology]

[0003] This discussion is merely intended to provide background information related to the present invention and does not necessarily constitute exemplary technology.

[0004] As the application of high-voltage devices in integrated circuits becomes more and more widespread, the requirements for their electrostatic discharge (ESD) protection capabilities are also increasing. In general, high-voltage electrostatic protection structures are constructed by connecting multiple low-voltage devices in series to achieve the requirement of withstanding high voltages. Summary of the Invention [Problem to be solved by the invention]

[0005] However, while conventional high-voltage electrostatic protection structures usually have no problems with withstanding forward voltages, they cannot withstand high reverse voltages, and there is a problem that the forward ESD protection capability and the reverse ESD protection capability do not match.

[0006] According to some embodiments of the present invention, an electrostatic protection structure and method for fabricating the same are provided. [Means for solving the problem]

[0007] an upper surface layer of the first deep well, a first well region and a second well region which are separated from each other and which are arranged in a floating state, the first well region and the second well region being both of the second conductivity type; an upper surface layer of the first well region, a first high concentration doping region and a second high concentration doping region which are separated from each other, the second well region and the third well region being arranged in a floating state, the first well region and the second well region being arranged in a floating state, the first well region and the second well region being arranged in a floating state, the first well region and the second well region being arranged in a floating state, the first well region and the second well region being arranged in a floating state, the first well region and the second well region being arranged in a floating state, the first well region and the second well region being arranged in a floating state, the first well region and the second well region being arranged in a floating state, the first well region and the second well region being arranged in a floating state, the second well region and the second well region being arranged in a floating state, the second well region and the first ... second well region being arranged in a third highly doped region and a fourth highly doped region, the first highly doped region, the second highly doped region, the third highly doped region, and the fourth highly doped region are of a first conductivity type, the first highly doped region is led out as a first electrode and connected to an electrostatic port, the second highly doped region is led out as a second electrode, and the third highly doped region is led out as a third electrode and electrically connected to the second electrode, The fourth heavily doped region is pulled out as a fourth electrode, a third well region of a second conductivity type is provided on an upper surface layer of the second deep well, a fifth heavily doped region of a second conductivity type floating is provided on an upper surface layer of the third well region, a fourth well region of a first conductivity type is provided on an upper surface layer of the third deep well, and a sixth heavily doped region of a first conductivity type is provided on an upper surface layer of the fourth well region, and the sixth heavily doped region is pulled out and grounded together with the fourth electrode.

[0008] In one embodiment, the first conductivity type is P type, the second conductivity type is N type, and when an electrostatic voltage is input to the electrostatic port, the first heavily doped region, the first well region, and the second heavily doped region together constitute a first PNP transistor, the third heavily doped region, the second well region, and the fourth heavily doped region together constitute a second PNP transistor, and the first PNP transistor and the second PNP transistor are connected in series with each other.

[0009] In one embodiment, when the electrostatic voltage is a positive voltage, the first electrode functions as an emitter of the first PNP transistor, the second electrode functions as a collector of the first PNP transistor, the first well region functions as a base of the first PNP transistor, the third electrode functions as an emitter of the second PNP transistor, the fourth electrode functions as a collector of the second PNP transistor, and the second well region functions as a base of the second PNP transistor.

[0010] In one embodiment, when the electrostatic voltage is a negative voltage, the first electrode functions as a collector of the first PNP transistor, the second electrode functions as an emitter of the first PNP transistor, the first well region functions as a base of the first PNP transistor, the third electrode functions as a collector of the second PNP transistor, the fourth electrode functions as an emitter of the second PNP transistor, and the second well region functions as a base of the second PNP transistor.

[0011] In one embodiment, the number of the first heavily doped region, the second heavily doped region, the third heavily doped region, and the fourth heavily doped region is at least two, and the first heavily doped regions are separated from each other, the second heavily doped regions are separated from each other, the third heavily doped regions are separated from each other, and the fourth heavily doped regions are separated from each other.

[0012] In one embodiment, the first heavily doped regions are electrically connected to each other and function as the first electrode, the second heavily doped regions are electrically connected to each other and function as the second electrode, the third heavily doped regions are electrically connected to each other and function as the third electrode, and the fourth heavily doped regions are electrically connected to each other and function as the fourth electrode.

[0013] In one embodiment, at least one fifth well region is further provided between the first well region and the second well region in an upper surface layer of the first deep well, the fifth well region is separated from the first well region and the second well region, the fifth well region is of a second conductivity type, a seventh heavily doped region and an eighth heavily doped region of the first conductivity type are provided in an upper surface layer of each of the fifth well regions, the seventh heavily doped region in each of the fifth well regions is electrically connected to the eighth heavily doped region in the adjacent fifth well region, the seventh heavily doped region adjacent to the first well region is electrically connected to the second heavily doped region, and the eighth heavily doped region adjacent to the second well region is electrically connected to the third heavily doped region.

[0014] In one embodiment, a plurality of sixth well regions are further provided in the upper surface layer of the first deep well, the plurality of sixth well regions are alternately arranged with the first well region and the second well region, and the sixth well regions are of a first conductivity type.

[0015] In one embodiment, the second deep well is an annular structure surrounding the outer periphery of the first deep well, and the third deep well is an annular structure surrounding the outer periphery of the second deep well.

[0016] A method for manufacturing an electrostatic protection structure includes providing a substrate of a first conductivity type, forming a buried layer of a second conductivity type opposite to the first conductivity type in the substrate, forming a first deep well of the first conductivity type arranged in a floating manner on an upper surface of the buried layer, forming a second deep well of a second conductivity type on the upper surface of the buried layer, the second deep well being partially in contact with the substrate and adjacent to the first deep well and located on the outer periphery of the first deep well, forming a third deep well of the first conductivity type on the buried layer, the third deep well being in complete contact with the substrate and adjacent to the second deep well and located on the outer periphery of the second deep well, forming a first well region and a second well region of a second conductivity type separated from each other and arranged in a floating manner on an upper surface layer of the first deep well, forming a first highly doped region and a second highly doped region separated from each other on an upper surface layer of the first well region, a first heavily doped region, a second heavily doped region, a third heavily doped region, and a fourth heavily doped region, the first heavily doped region, the second heavily doped region, the third heavily doped region, and the fourth heavily doped region being of a first conductivity type; the first heavily doped region being drawn out as a first electrode and connected to an electrostatic port; the second heavily doped region being drawn out as a second electrode; the third heavily doped region being drawn out as a third electrode and electrically connected to the second electrode; and the fourth heavily doped region forming a third well region of a second conductivity type in an upper surface layer of the second deep well and a floating fifth highly doped region of the second conductivity type in an upper surface layer of the third well region; forming a fourth well region of a first conductivity type in an upper surface layer of the third deep well and a sixth highly doped region of the first conductivity type in an upper surface layer of the fourth well region, and drawing out the sixth highly doped region and grounding it together with the fourth electrode.

[0017] The details of one or more embodiments of the invention are set forth in the drawings and description which follow. Other features, objects, and advantages of the invention will become apparent from the description, drawings, and claims. [Brief description of the drawings]

[0018] In order to more clearly describe the technical solutions in the embodiments or exemplary technologies of the present invention, the drawings necessary for the description of the embodiments or exemplary technologies will be briefly described below. The drawings in the following description are only some embodiments of the present invention, and it is obvious that a person skilled in the art can obtain other drawings based on these drawings without creative efforts. [Figure 1] FIG. 1 is a schematic cross-sectional view of an electrostatic protection structure according to an embodiment of the present invention; [Diagram 2] FIG. 1 is a schematic cross-sectional view of an electrostatic protection structure according to an embodiment of the present invention; [Diagram 3] FIG. 1 is a schematic cross-sectional view of an electrostatic protection structure according to an embodiment of the present invention; [Figure 4] FIG. 1 is a schematic cross-sectional view of an electrostatic protection structure according to an embodiment of the present invention; [Diagram 5] FIG. 1 is an equivalent schematic diagram of an electrostatic protection structure according to an embodiment; [Figure 6] FIG. 1 is a schematic cross-sectional view of an electrostatic protection structure according to an embodiment of the present invention; [Figure 7] 1 is a flowchart of a method for manufacturing an electrostatic protection structure in one embodiment. [Figure 8] 1 is a flowchart of a method for manufacturing an electrostatic protection structure in one embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0019] In order to facilitate an understanding of the present invention, the present invention will now be described more fully with reference to the accompanying drawings, in which preferred embodiments of the present invention are illustrated. However, the present invention may be embodied in many different forms and is not limited to the embodiments set forth herein. Rather, these embodiments are provided so that the disclosure of the present invention will be more thorough and complete.

[0020] Unless otherwise defined, all technical and scientific terms used herein have the meanings commonly understood by those skilled in the art. In this specification, the terms used in the present specification are used only for the purpose of describing specific examples, and are not intended to limit the present invention.

[0021] It should be understood that when an element or layer is referred to as being "on," "adjacent," "connected to," or "coupled to" another element or layer, it may be directly on, directly adjacent to, or directly connected to the other element or layer, or there may be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that the use of terms such as first, second, third, etc. to describe various elements, components, regions, layers, conductivity types, and / or portions, such elements, components, regions, layers, conductivity types, and / or portions, is not intended to be limited by these terms. These terms are used to distinguish one element, component, region, layer, conductivity type, or portion from another element, component, region, layer, conductivity type, or portion. Thus, without departing from the teachings herein, a first element, component, region, layer, or portion described below may be referred to as a second element, component, region, layer, or portion. For example, a first conductivity type may be referred to as a second conductivity type, and similarly, a second conductivity type may be referred to as a first conductivity type. The first and second conductivity types may be different conductivity types, e.g., the first conductivity type may be P type and the second conductivity type may be N type, or the first conductivity type may be N type and the second conductivity type may be P type.

[0022] Spatial relationship terms such as "under...", "below...", "below", "under...", "above...", "above" are used herein to describe the relationship of one element or feature to another element or feature depicted in the figures. It should be understood that in addition to the orientation depicted in the figures, the spatial relationship terms also include different orientations of the device during use and operation. For example, if the device in the figures is flipped, the orientation of the element or feature "under," "under" or "below" the other element or feature is described as changing to "above" the other element or feature. Thus, the exemplary terms "under..." and "under..." can include two orientations such as above and below. It should be noted that the device may include other orientations (e.g., rotated 90 degrees or other orientations) and the spatial terms used herein should be interpreted accordingly.

[0023] As used herein, the singular forms "a," "one," and "said" can include the plural forms unless the context clearly indicates otherwise. It should be further understood that terms such as "comprising" or "having" specify the presence of a stated feature, whole, step, operation, component, portion, or combination thereof, but do not exclude the possible presence or addition of one or more other features, wholes, steps, operations, components, portions, or combinations thereof. At the same time, as used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0024] 1 is a schematic diagram of an electrostatic protection structure according to an embodiment of the present invention. The electrostatic protection structure 10 includes a substrate 100, a buried layer 200, a first deep well 300, a second deep well 400, and a third deep well 500.

[0025] In this embodiment, the substrate 100 is of a first conductivity type, and an implanted buried layer 200 is formed within the substrate 100, the buried layer 200 being of a second conductivity type opposite to the first conductivity type. Illustratively, in this embodiment, the first conductivity type is P-type, and the second conductivity type is N-type.

[0026] In this embodiment, the first deep well 300 is located on the buried layer 200, is arranged floating, and is of a first conductivity type.

[0027] Here, the first deep well 300 and the buried layer 200 have opposite conductivity types, and the first deep well 300 and the buried layer 200 have different doping concentration gradients, so that a PN junction can be formed between the first deep well 300 and the buried layer 200. Therefore, when the electrostatic protection structure is connected to an electrostatic voltage, the space between the first deep well 300 and the buried layer 200 can serve as one of the potential paths for electrostatic discharge.

[0028] Here, a first well region 310 and a second well region 320 that are separated from each other and arranged floating are provided on an upper surface layer of a first deep well 300, and both the first well region 310 and the second well region 320 are of a second conductivity type. A first highly doped region 311 and a second highly doped region 312 that are separated from each other are provided on an upper surface layer of the first well region 310, and a third highly doped region 321 and a fourth highly doped region 322 that are separated from each other are provided on an upper surface layer of the second well region 320. The first heavily doped region 311, the second heavily doped region 312, the third heavily doped region 321, and the fourth heavily doped region 322 are of a first conductivity type, the first heavily doped region 311 is drawn out as a first electrode J1 and connected to an electrostatic port H, the second heavily doped region 312 is drawn out as a second electrode J2, the third heavily doped region 321 is drawn out as a third electrode J3 and electrically connected to the second electrode J2, and the fourth heavily doped region 322 is drawn out as a fourth electrode J4.

[0029] Here, the electrostatic port H is a port that requires a unidirectional or bidirectional withstand voltage and is used to input an electrostatic voltage, which may be, for example, a high electrostatic voltage. When a unidirectional withstand voltage is required, the electrostatic protection structure of this embodiment can withstand a forward voltage or a reverse voltage, and when a bidirectional withstand voltage is required, the electrostatic protection structure can discharge the connected static electricity by withstanding the forward voltage and the reverse voltage. Here, the fourth electrode J4 functions as the electrostatic port L of the electrostatic protection structure.

[0030] Here, since the first deep well 300 has an opposite conductivity type to the first well region 310 and the second well region 320 and has a different doping concentration gradient from the first well region 310 and the second well region 320, a PN junction can be formed between the first deep well 300 and the first well region 310, and between the first deep well 300 and the second well region 320. As a result, when an electrostatic voltage is input to the electrostatic port H, the area between the first well region 310 and the first highly doped region 311, and the area between the first well region 310 and the second highly doped region 312 can function as one of the potential paths for electrostatic discharge.

[0031] Here, the first well region 310 has an opposite conductivity type to the first heavily doped region 311 and the second heavily doped region 312, and has a different doping concentration gradient from the first heavily doped region 311 and the second heavily doped region 312. Therefore, a PN junction can be formed between the first well region 310 and the first heavily doped region 311, and a PN junction can be formed between the first well region 310 and the second heavily doped region 312. In addition, the PN junction between the first well region 310 and the first heavily doped region 311 and the PN junction formed between the first well region 310 and the second heavily doped region 312 have opposite voltage biases, so that when an electrostatic voltage is input to the electrostatic port H, the area between the first well region 310 and the first heavily doped region 311, and the area between the first well region 310 and the second heavily doped region 312 can function as one of the potential paths for electrostatic discharge.

[0032] Here, the second well region 320 has an opposite conductivity type to the third heavily doped region 321 and the fourth heavily doped region 322 and has a different doping concentration gradient from the third heavily doped region 321 and the fourth heavily doped region 322. Therefore, a PN junction can be formed between the second well region 320 and the third heavily doped region 321, and a PN junction can be formed between the second well region 320 and the fourth heavily doped region 322. In addition, the PN junction between the second well region 320 and the third heavily doped region 321 and the PN junction formed between the second well region 320 and the fourth heavily doped region 322 have opposite voltage biases, so that when an electrostatic voltage is input to the electrostatic port H, the area between the second well region 320 and the third heavily doped region 321 and the area between the second well region 320 and the fourth heavily doped region 322 can function as one of the potential paths for electrostatic discharge.

[0033] Here, the first heavily doped region 311 is drawn out as a first electrode J1 and connected to the electrostatic port H, the second heavily doped region 312 is drawn out as a second electrode J2, the third heavily doped region 321 is drawn out as a third electrode J3 and electrically connected to the second electrode J2, and the fourth heavily doped region 322 is drawn out as a fourth electrode J4. When the PN junction between the first well region 310 and the second heavily doped region 312 breaks down, current is turned on between the third electrode J3 and the second electrode J2, and the first heavily doped region 311, the first well region 310, the second heavily doped region 312, the third heavily doped region 321, the second well region 320, and the fourth heavily doped region 322 form potential paths for electrostatic discharge having different voltage biases.

[0034] In some embodiments, as shown in FIG. 2, the number of the first highly doped region 311, the second highly doped region 312, the third highly doped region 321, and the fourth highly doped region 322 are all at least two (FIG. 2 is an example in which the number is two), and the multiple first highly doped regions 311 are separated from each other, the multiple second highly doped regions 312 are separated from each other, the multiple third highly doped regions 321 are separated from each other, and the multiple fourth highly doped regions 322 are separated from each other. Here, the first highly doped regions 311 are electrically connected to each other and function as a first electrode J1, the second highly doped regions 312 are electrically connected to each other and function as a second electrode J2, the third highly doped regions 321 are electrically connected to each other and function as a third electrode J3, and the fourth highly doped regions 322 are electrically connected to each other and function as a fourth electrode J4. Thus, each electrode corresponds to a plurality of highly doped regions, which is advantageous for improving the electrostatic discharge capability of each electrode during electrostatic protection.

[0035] Here, the numbers of the first highly doped region 311, the second highly doped region 312, the third highly doped region 321, and the fourth highly doped region 322 can be set according to actual requirements, for example, according to the magnitude of the actual electrostatic voltage. If the electrostatic voltage is higher, a larger number can be set within the range that the product size can tolerate, and if the electrostatic voltage is smaller, a smaller number can be set.

[0036] In some embodiments, the first conductivity type is P-type, the second conductivity type is N-type, and when an electrostatic voltage is input to the electrostatic port H, the first highly doped region 311, the first well region 310, and the second highly doped region 312 together constitute a first PNP transistor, the third highly doped region 321, the second well region 320, and the fourth highly doped region 322 together constitute a second PNP transistor, and the first PNP transistor and the second PNP transistor are connected in series with each other. By using the PNP transistor for ESD protection, the sustaining voltage can be made higher.

[0037] Furthermore, when a positive voltage is input to the electrostatic port H, the first electrode J1 is the emitter of the first PNP transistor, the second electrode J2 is the collector of the first PNP transistor, the first well region 310 is the floating base of the first PNP transistor, the third electrode J3 is the emitter of the second PNP transistor, the fourth electrode J4 is the collector of the second PNP transistor, and the second well region 320 is the floating base of the second PNP transistor. Here, when a positive voltage is input to the electrostatic port H, the electrostatic protection structure is in the forward voltage withstand mode, and the forward bias of the emitter and floating base of the first PNP transistor causes the floating base and emitter of the first PNP transistor to break down, and the avalanche current caused by the breakdown passes through the emitter of the second PNP transistor, realizing a series connection between the first PNP transistor and the second PNP transistor, forming the main path of electrostatic discharge for forward electrostatic protection, and achieving the requirement of withstanding high voltage.

[0038] Furthermore, when a negative voltage is input to the electrostatic port H, the first electrode J1 is the collector of the first PNP transistor, the second electrode J2 is the emitter of the first PNP transistor, the third electrode J3 is the collector of the second PNP transistor, and the fourth electrode J4 is the emitter of the second PNP transistor.

[0039] Therefore, when different electrostatic voltages are input, the collectors and emitters of the first PNP transistor and the second PNP transistor can be swapped, making it easier to achieve consistency in the bidirectional withstand voltages.

[0040] It should be noted that other embodiments are not limited to forming a PNP transistor, but may provide other layer structures to form an electrostatic protection structure for other device types, such as PMOS devices, specifically GDPMOS devices.

[0041] In some embodiments, as shown in FIG. 3, at least one fifth well region 330 (FIG. 3 shows an embodiment in which one fifth well region 330 is added to the embodiment shown in FIG. 2) is further provided between the first well region 310 and the second well region 320 in the upper surface layer of the first deep well 300, the fifth well region 330 is separated from the first well region 310 and the second well region 320, the fifth well region 330 is of the second conductivity type, and the upper surface layer of each fifth well region 330 is provided with a first conductive type. A seventh highly doped region 331 and an eighth highly doped region of the same type are provided, and the seventh highly doped region 331 of each fifth well region 330 is electrically connected to the eighth highly doped region 332 in the adjacent fifth well region 330, the seventh highly doped region 331 adjacent to the first well region 310 is electrically connected to the second highly doped region 312, and the eighth highly doped region 332 adjacent to the second well region 320 is electrically connected to the third highly doped region 321. As a result, the first heavily doped region 311, the first well region 310, the second heavily doped region 312, the seventh heavily doped region 331, the fifth well region 330, the eighth heavily doped region 332, the third heavily doped region 321, the second well region 320, and the fourth heavily doped region 322 form potential paths for electrostatic discharge having different voltage biases.

[0042] When the first conductivity type is P type and the second conductivity type is N type, and an electrostatic voltage is input to the electrostatic port H, the first highly-concentrated doped region 311, the first well region 310, and the second highly-concentrated doped region 312 together constitute a first PNP transistor, the third highly-concentrated doped region 321, the second well region 320, and the fourth highly-concentrated doped region 322 together constitute a second PNP transistor, the seventh highly-concentrated doped region 331, the fifth well region 330, and the eighth highly-concentrated doped region 332 together constitute a third PNP transistor, and the first PNP transistor, the multiple third PNP transistors, and the second PNP transistor are connected in series with each other. Here, when a positive voltage is input to the electrostatic port H, the electrostatic protection structure is in a forward withstand voltage mode, and the forward bias of the emitter and floating base of the first PNP transistor causes the floating base and emitter of the first PNP transistor to break down, and an avalanche current caused by the breakdown passes through the emitter of the third PNP transistor; the forward bias of the emitter and floating base of the third PNP transistor causes the floating base and emitter of the second PNP transistor to break down, and an avalanche current caused by the breakdown passes through the emitter of the second PNP transistor, thereby realizing a series connection between the first PNP transistor and the third PNP transistor, and a series connection between the third PNP transistor and the second PNP transistor, which forms a main path of electrostatic discharge for forward electrostatic protection, thereby further improving the electrostatic withstand voltage capability, and at the same time, having a higher electrostatic sustaining voltage and being less susceptible to latch-up effect.

[0043] Here, the number of the third PNP transistors can be set according to different grades of electrostatic voltage, and the higher the grade of electrostatic voltage, the more third PNP transistors can be set to solve the higher grade of electrostatic protection.

[0044] In some embodiments, as shown in FIG. 4, the upper surface layer of the first deep well 300 is further provided with a plurality of sixth well regions 340, which are alternately arranged with the first well regions 310 and the second well regions 320, and the sixth well regions 340 are of the first conductivity type.

[0045] Here, the sixth well region 340 is alternately arranged with the first well region 310 and the second well region 320, and has the opposite conductivity type and the same doping concentration gradient as the first well region 310 and the second well region 320, so that the sixth well region 340 separates the first well region 310 and the second well region 320, and prevents the first well region 310 and the second well region 320 from affecting each other during electrostatic withstand voltage. Furthermore, the sixth well region 340 close to the second deep well 400 is located between the first well region 310 and the third well region. Since the sixth well region 340 has an opposite conductivity type and the same doping concentration gradient as the first well region 310 and the second well region 320, the sixth well region 340 separates the first well region 310 and the third well region, and prevents the first well region 310 and the third well region from affecting each other during electrostatic withstand voltage.

[0046] In this embodiment, the second deep well 400 is located on the upper surface of the buried layer 200, and a portion of the second deep well 400 is in contact with the substrate 100 and is of a second conductivity type. The second deep well 400 is adjacent to the first deep well 300 and is located on the outer periphery of the first deep well 300.

[0047] Here, the second deep well 400 is located on the upper surface of the buried layer 200, and a part of the deep well 400 is in contact with the substrate 100 and adjacent to the first deep well 300. Since the second deep well 400 and the buried layer 200 have the opposite conductivity type and different doping concentration gradient from the first deep well 300 and the substrate 100, a PN junction can be formed between the second deep well 400 and the buried layer 200 and the substrate 100, and a PN junction can be formed between the second deep well 400 and the buried layer 200 and the first deep well 300. When a voltage is input through the electrostatic port H, the area between the second deep well 400 and the buried layer 200 and the substrate 100, and the area between the second deep well 400 and the buried layer 200 and the first deep well 300 can be one of the potential paths for electrostatic discharge. Here, the second deep well 400 is located between the first deep well 300 and the third deep well 500 and has an opposite conductivity type to the first deep well 300 and the third deep well 500, whereby the first deep well 300 and the third deep well 500 are separated by the second deep well 400.

[0048] Here, a third well region 410 of a second conductivity type is provided on an upper surface layer of the second deep well 400, and a floating fifth heavily doped region 411 of the second conductivity type is provided on an upper surface layer of the third well region 410. The fifth heavily doped region 411 is floated and drawn out as an isolation port of the electrostatic protection structure. Exemplarily, the width of a sidewall of the third well region 410 is smaller than the width of a sidewall of the second deep well 400, so that the third well region 410 is isolated from the adjacent first deep well 300 and third deep well 500, respectively.

[0049] In some embodiments, the second deep well 400 is a ring-shaped structure surrounding the outer periphery of the first deep well 300, and the third deep well 500 is a ring-shaped structure surrounding the outer periphery of the second deep well 400, so that the second deep well 400 and the third deep well 500 form a double ring structure, which together with the internal first deep well 300 forms a discharge path for electrostatic discharge, and can also effectively prevent mutual influence between well regions of the same conductivity type, effectively improving electrostatic protection performance.

[0050] In this embodiment, the third deep well 500 is located on the buried layer 200 and in contact with the substrate 100, and is of a first conductivity type. The third deep well 500 is adjacent to the second deep well 400 and is located on the outer periphery of the second deep well 400.

[0051] Here, the third deep well 500 is located on the buried layer 200, is in full contact with the substrate 100, and is adjacent to the second deep well 400. Since the third deep well 500 and the substrate 100 have the opposite conductivity type to the second deep well 400 and the buried layer 200, a PN junction can be formed between the third deep well 500 and the substrate 100 and the second deep well 400 and the buried layer 200, and when a voltage is input through the electrostatic port H, the third deep well 500 and the substrate 100 and the second deep well 400 and the buried layer 200 can be one of the potential paths for electrostatic discharge.

[0052] Here, a fourth well region 510 of a first conductivity type is provided on an upper surface layer of the third deep well 500, and a sixth heavily doped region 511 of a first conductivity type is provided on an upper surface layer of the fourth well region 510, and the sixth heavily doped region 511 is drawn out and grounded together with the fourth electrode J4, i.e., the sixth heavily doped region 511 is drawn out and connected together with the fourth electrode J4 to the substrate. Exemplarily, the width of the sidewall of the fourth well region 510 is smaller than the width of the sidewall of the third deep well 500, so that the fourth well region 510 is separated from the adjacent second deep well 400.

[0053] Here, since the fourth well region 510, the third deep well 500, and the substrate 100 have opposite conductivity types and different doping concentration gradients from the buried layer 200, the second deep well 400, and the third well region 410, a PN junction can be formed between the fourth well region 510, the third deep well 500, and the substrate 100 and the buried layer 200, the second deep well 400, and the third well region 410. Since the buried layer 200, the second deep well 400, and the third well region 410 have opposite conductivity types and different doping concentration gradients from the first deep well 300, a PN junction can be formed between the buried layer 200, the second deep well 400, and the third well region 410 and the first deep well 300.

[0054] Hereinafter, with reference to FIG. 5, a bidirectional electrostatic protection process of the electrostatic protection structure will be described by taking an example in which the electrostatic protection structure includes two PNP transistors.

[0055] When a positive voltage is input to the electrostatic port H, the electrostatic protection structure is in a forward voltage withstand mode, that is, the PN junction (see PN1 in FIG. 5 ) formed between the first highly doped region 311 and the floating first well region 310 is in a forward bias state, the PN junction (see PN2 in FIG. 5 ) formed between the first well region 310 and the second heavily doped well region 310 is in a reverse bias state, the PN junction (see PN3 in FIG. 5 ) formed between the third highly doped region 321 and the floating second well region 320 is in a forward bias state, and the PN junction (see PN4 in FIG. 5 ) formed between the second well region 320 and the fourth heavily doped well region 320 is in a reverse bias state. When the PN junction formed between the first well region 310 and the second heavily doped region 312 breaks down, the first heavily doped region 311, the first well region 310, and the second heavily doped region 312 together constitute a first PNP transistor Q1, and the third heavily doped region 321, the second well region 320, and the fourth heavily doped region 322 together constitute a second PNP transistor Q2. By providing a forward withstand voltage through the first PNP transistor Q1 and the second PNP transistor Q2, the transistor has a higher electrostatic sustaining voltage and is less susceptible to latch-up effects.

[0056] When the electrostatic port H is connected to a negative voltage, the electrostatic protection structure is in a negative voltage withstand mode, i.e., the grounded sixth highly doped region 511 is equivalent to being connected to a positive voltage, so that the PN junctions (see PN5 in FIG. 5 ) formed between the fourth well region 510, the third deep well 500, and the substrate 100 and the buried layer 200, the second deep well 400, and the third well region 410 are in a forward bias state, and the buried layer 200, the second deep well 400, and the third well region 410 are in a forward bias state. The PN junction (see PN6 in FIG. 5) between the third well region 410 and the first deep well 300 is in a reverse bias state, the PN junction (see PN7 in FIG. 5) between the first deep well 300 and the first well region 310 is in a forward bias state, and the withstand voltage of the second deep well 400 and the PN junction between the buried layer 200 and the first deep well 300 is very high, so that it will not become lower than the breakdown voltage of the floating base and emitter of the second PNP transistor Q2. As a result, the buried layer 200, the second deep well 400, and the third well region 410 correspond to a floating base, the fourth well region 510, the third deep well 500, and the substrate 100 correspond to an emitter, the first deep well 300 corresponds to a collector, and the buried layer 200, the second deep well 400, the third well region 410, the fourth well region 510, the third deep well 500, the substrate 100, and the first deep well 300 form a parasitic PNP transistor Q3. The first deep well 300 corresponds to the positive electrode of a diode, and the first well region 310 corresponds to the negative electrode of diode D. The first deep well 300 and the first well region 310 form diode D, thereby enabling a reverse withstand voltage to be realized by the parasitic PNP transistor Q3 and diode D, while at the same time providing the electrostatic protection structure with a higher electrostatic sustaining voltage and making the latch-up effect less likely to occur.

[0057] Therefore, when the electrostatic protection structure is in the forward withstand voltage mode, the series connection capability of the first PNP transistor Q1 and the second PNP transistor Q2 is utilized to provide a forward withstand voltage, thereby providing a higher electrostatic sustain voltage and making the latch-up effect less likely to occur. Even when the electrostatic protection structure is in the negative withstand voltage mode, the series connection capability of the first PNP transistor Q1 and the second PNP transistor Q2 is utilized, and at the same time, the parallel connection of the high-voltage PNP transistor Q3 and the diode D is utilized to provide a higher electrostatic sustain voltage and making the latch-up effect less likely to occur. Therefore, the electrostatic protection structure can achieve consistency in the withstand voltage in both directions.

[0058] The electrostatic protection structure provided by this embodiment includes a substrate 100 of a first conductivity type, a buried layer 200 of a second conductivity type, a first deep well 300 of a first conductivity type, a second deep well 400 of a second conductivity type, and a third deep well 500 of a first conductivity type, in which a well region of an opposite conductivity type and a high-concentration doping region of the same conductivity type are provided in the first deep well 300, and a well region of the same conductivity type and a high-concentration doping region are provided in the second deep well 400 and the third deep well 500, respectively. Here, the first deep well 300, the first well region 310, and the second well region 320 are floating, the first high-concentration doping region 311 is pulled out and connected to an electrostatic voltage, and the sixth high-concentration doping region 511 is grounded. When a positive voltage is input to the electrostatic port H, the electrostatic protection structure is in a forward voltage withstand mode, and the first highly doped region 311, the first well region 310, and the second highly doped region 312 together constitute a first PNP transistor Q1, and the third highly doped region 321, the second well region 320, and the fourth highly doped region 322 together constitute a second PNP transistor Q2. By providing forward voltage withstand capability through the first PNP transistor Q1 and the second PNP transistor Q2, the electrostatic protection structure has a higher electrostatic sustaining voltage and is less susceptible to latch-up effects. When a negative voltage is input to the electrostatic port H, the electrostatic protection structure is in a reverse voltage withstand mode, and the buried layer 200, the second deep well 400, the third well region 410, the fourth well region 510, the third deep well 500, the substrate 100, and the first deep well 300 form a parasitic PNP transistor, and the first deep well 300 and the first well region 310 form a diode, so that the parasitic PNP transistor and the diode can realize a reverse voltage withstand, and at the same time, the electrostatic protection structure can have a higher electrostatic sustaining voltage and be less susceptible to latch-up effects. Therefore, the electrostatic protection structure can realize a consistent bidirectional voltage withstand.

[0059] 6 is a schematic diagram of an electrostatic protection structure according to an embodiment. Based on the electrostatic protection structure according to the above embodiment, the electrostatic protection structure according to this embodiment further includes a first isolation structure, a second isolation structure, a third isolation structure, and a fourth isolation structure.

[0060] In this embodiment, the first isolation structure 600 is located on the upper surface of the first deep well 300 and penetrates from the upper surface of the first deep well 300 to the first well region 310, and the first isolation structure 600 is alternately arranged with the first heavily doped region 311 and the second heavily doped region 312, thereby isolating the first heavily doped region 311 and the second heavily doped region 312 and preventing the first heavily doped region 311 and the second heavily doped region 312 from affecting each other during electrostatic discharge.

[0061] In this embodiment, the second isolation structure 700 is located on the upper surface layer of the first deep well 300 and penetrates from the upper surface of the first deep well 300 to the second well region 320, and the second isolation structure 700 is alternately arranged with the third heavily doped region 321 and the fourth heavily doped region 322, thereby isolating the third heavily doped region 321 and the fourth heavily doped region 322 and preventing the third heavily doped region 321 and the fourth heavily doped region 322 from affecting each other during electrostatic discharge.

[0062] In this embodiment, the third isolation structure 800 is located on the upper surface layer of the second deep well 400 and the third deep well 500, and is located between the fifth heavily doped region 411 and the sixth heavily doped region 511, thereby isolating the fifth heavily doped region 411 and the sixth heavily doped region 511 and preventing the fifth heavily doped region 411 and the sixth heavily doped region 511 from affecting each other during electrostatic discharge.

[0063] In this embodiment, the fourth isolation structure 910 is located in the upper surface layer of the fourth well region 510, and is located between the first heavily doped region 311 and the fifth heavily doped region 411, and between the fourth heavily doped region 322 and the fifth heavily doped region 411, thereby isolating the first heavily doped region 311 and the fifth heavily doped region 411, and isolating the fourth heavily doped region 322 and the fifth heavily doped region 411, and further improving the isolation performance of the electrostatic protection structure.

[0064] In this embodiment, the fifth isolation structure 920 is located on the upper surface layer of the third deep well 500, thereby isolating the electrostatic protection structure from other devices and further improving the isolation performance of the electrostatic protection structure.

[0065] In one embodiment, the first isolation structure 600, the second isolation structure 700, the third isolation structure 800, the fourth isolation structure 910, and the fifth isolation structure 920 may be shallow trench isolation structures.

[0066] According to the electrostatic protection structure in this embodiment, the first isolation structure 600, the second isolation structure 700, the third isolation structure 800, the fourth isolation structure 910, and the fifth isolation structure 920 can effectively improve the isolation performance of the device.

[0067] This embodiment further provides a method for manufacturing the electrostatic protection structure described in the above embodiment. As shown in FIG. 7, the method includes the following steps:

[0068] In step 110, a substrate of a first conductivity type is provided.

[0069] In step 120, a buried layer of a second conductivity type opposite the first conductivity type is formed in the substrate.

[0070] In step 130, a first deep well of a first conductivity type is formed in a floating arrangement on the upper surface of the buried layer.

[0071] In step 140, a second deep well of a second conductivity type is formed in the upper surface of the buried layer, the second deep well having a portion in contact with the substrate and adjacent to and positioned on the periphery of the first deep well.

[0072] In step 150, a third deep well of the first conductivity type is formed on the buried layer, fully contacting the substrate and adjacent to and positioned on the periphery of the second deep well.

[0073] In step 160, a first well region and a second well region of a second conductivity type, which are isolated from each other and arranged floating, are formed in an upper surface layer of the first deep well, a first highly doped region and a second highly doped region, which are isolated from each other, are formed in an upper surface layer of the first well region, and a third highly doped region and a fourth highly doped region, which are isolated from each other, are formed in an upper surface layer of the second well region.

[0074] Here, the first heavily doped region, the second heavily doped region, the third heavily doped region, and the fourth heavily doped region are of a first conductivity type, the first heavily doped region is drawn out as a first electrode and connected to an electrostatic port, the second heavily doped region is drawn out as a second electrode, the third heavily doped region is drawn out as a third electrode and electrically connected to the second electrode, and the fourth heavily doped region is drawn out as a fourth electrode.

[0075] In step 170, a third well region of the second conductivity type is formed in an upper surface of the second deep well, and a floating fifth highly doped region of the second conductivity type is formed in an upper surface of the third well region.

[0076] In step 180, a fourth well region of the first conductivity type is formed in an upper surface layer of the third deep well, a sixth heavily doped region of the first conductivity type is formed in an upper surface layer of the fourth well region, and the sixth heavily doped region is led out and grounded together with the fourth electrode.

[0077] Here, steps 110 to 180 are used to manufacture the electrostatic protection structure described in the embodiment of Figures 1 and 2, and the relevant explanations can be found in the relevant explanations in the embodiment of Figures 1 and 2. Here, the method of "forming" is not limited here because it can adopt a conventional manufacturing method.

[0078] Here, steps 130 to 150 can be executed simultaneously or sequentially, and steps 160 to 180 can be executed simultaneously or sequentially.

[0079] The manufacturing method provided by this embodiment can manufacture an electrostatic protection structure that can withstand voltage in both directions, and at the same time, can provide the electrostatic protection structure with a higher electrostatic sustaining voltage and make the latch-up effect less likely to occur.

[0080] In some embodiments, the method further comprises the steps of:

[0081] In step 190, at least one fifth well region is formed between the first well region and the second well region in an upper surface layer of the first deep well, the fifth well region being separated from the first well region and the second well region respectively and being of a second conductivity type; and a seventh heavily doped region and an eighth heavily doped region of the first conductivity type are formed in an upper surface layer of each fifth well region, the seventh heavily doped region in each fifth well region being electrically connected to the eighth heavily doped region in an adjacent fifth well region, the seventh heavily doped region adjacent to the first well region being electrically connected to the second heavily doped region, and the eighth heavily doped region adjacent to the second well region being electrically connected to the third heavily doped region.

[0082] Here, step 190 is used to manufacture the electrostatic protection structure according to the embodiment of Fig. 3, and the relevant description may refer to the relevant description in the embodiment of Fig. 3. Here, the method of "forming" can adopt a conventional manufacturing method, and is not limited here.

[0083] In some embodiments, the method further comprises the steps of:

[0084] In step 200, a plurality of sixth well regions are formed in an upper surface layer of the first deep well, the plurality of sixth well regions are alternately arranged with the first well regions and the second well regions, and the sixth well regions are of a first conductivity type.

[0085] Here, step 200 is used to manufacture the electrostatic protection structure described in the embodiment of Fig. 4, and the relevant description may be referred to the relevant description in the embodiment of Fig. 4. Step 200 can be performed simultaneously or sequentially with steps 130 to 150 in the above embodiment. Here, the method of "forming" is not limited here because it can adopt a conventional manufacturing method.

[0086] In one embodiment, as shown in FIG. 8, the manufacturing method further includes the following steps.

[0087] In step 210, a first isolation structure is formed on an upper surface layer of the first deep well, the first isolation structure penetrating from an upper surface of the first deep well to the first well region, and the first isolation structure alternating with a first highly doped region and a second highly doped region.

[0088] In step 220, a second isolation structure is formed on an upper surface layer of the second deep well, the second isolation structure penetrating from the upper surface of the first deep well to the second well region, and the second isolation structure alternating with a third highly doped region and a fourth highly doped region.

[0089] In step 230, a third isolation structure is formed on an upper surface layer of the second deep well and the third deep well, the third isolation structure being located between the fifth heavily doped region and the sixth heavily doped region.

[0090] In step 240, a fourth isolation structure is formed in an upper surface layer of the fourth well region, the fourth isolation structure being located between the first highly doped region and the fifth highly doped region and between the fourth highly doped region and the fifth highly doped region.

[0091] In step 250, a fifth isolation structure is formed on the upper surface of the third deep well.

[0092] Here, step 210 is used to manufacture the electrostatic protection structure described in the embodiment of Fig. 6, and the relevant description can be referred to the relevant description in the embodiment of Fig. 6. Steps 210 to 250 can be performed simultaneously or sequentially. Here, the method of "forming" can be any conventional manufacturing method, and is not limited here.

[0093] In the description of this specification, the description of "in some embodiments," "in other embodiments," and the like, is intended to mean that the specific features, structures, materials, or characteristics described in combination with the embodiment or example are included in at least one embodiment or example of the present invention. In the specification, schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0094] The technical features of the embodiments described above can be combined in any manner, and for the sake of brevity, not all possible combinations of the technical features in the embodiments described above have been described; however, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope described in this specification.

[0095] The above examples merely show some embodiments of the present application, and although the description is specific and detailed, it should not be understood as limiting the scope of the present invention. It should be noted that those skilled in the art can make some modifications and improvements that fall within the scope of the present application without departing from the idea of ​​the present application. Therefore, the scope of the patent of the present application shall be subject to the scope of the attached claims.

Claims

1. An electrostatic protection structure, comprising: a substrate of a first conductivity type; a buried layer of a second conductivity type opposite to the first conductivity type located in the substrate; a first deep well of a first conductivity type located on an upper surface of the buried layer and disposed in a floating manner; a second deep well of a second conductivity type located on the upper surface of the buried layer, with a part of a lower surface layer contacting the substrate, adjacent to the first deep well and located on the outer periphery of the first deep well; a third deep well of the first conductivity type located on the buried layer, completely in contact with the substrate, adjacent to the second deep well and located on the periphery of the second deep well; A first well region and a second well region are provided in an upper surface layer of the first deep well, the first well region and the second well region being separated from each other and arranged floating, the first well region and the second well region being both of a second conductivity type, a first highly doped region and a second highly doped region are provided in an upper surface layer of the first well region, the second well region is provided in an upper surface layer of the second well region, the third highly doped region and a fourth highly doped region are provided in an upper surface layer of the second well region, a first heavily doped region, the second heavily doped region, the third heavily doped region, and the fourth heavily doped region are of a first conductivity type, the first heavily doped region is led out as a first electrode and connected to an electrostatic port, the second heavily doped region is led out as a second electrode, the third heavily doped region is led out as a third electrode and electrically connected to the second electrode, and the fourth heavily doped region is led out as a fourth electrode; a third well region of a second conductivity type is provided on an upper surface layer of the second deep well, and a floating fifth highly doped region of the second conductivity type is provided on an upper surface layer of the third well region; A fourth well region of a first conductivity type is provided on an upper surface layer of the third deep well, and a sixth heavily doped region of the first conductivity type is provided on an upper surface layer of the fourth well region, and the sixth heavily doped region is led out and grounded together with the fourth electrode. The electrostatic protection structure is characterized by the above-mentioned.

2. the first conductivity type is P type and the second conductivity type is N type; When an electrostatic voltage is input to the electrostatic port, the first heavily doped region, the first well region, and the second heavily doped region together constitute a first PNP transistor, the third heavily doped region, the second well region, and the fourth heavily doped region together constitute a second PNP transistor, and the first PNP transistor and the second PNP transistor are connected in series with each other.

2. The electrostatic protection structure according to claim 1.

3. When the electrostatic voltage is a positive voltage, the first electrode functions as an emitter of the first PNP transistor, the second electrode functions as a collector of the first PNP transistor, and the first well region functions as a base of the first PNP transistor; The third electrode functions as an emitter of the second PNP transistor, the fourth electrode functions as a collector of the second PNP transistor, and the second well region functions as a base of the second PNP transistor.

3. The electrostatic protection structure according to claim 2.

4. When the electrostatic voltage is a negative voltage, the first electrode functions as a collector of the first PNP transistor, the second electrode functions as an emitter of the first PNP transistor, and the first well region functions as a base of the first PNP transistor; The third electrode functions as a collector of the second PNP transistor, the fourth electrode functions as an emitter of the second PNP transistor, and the second well region functions as a base of the second PNP transistor.

3. The electrostatic protection structure according to claim 2.

5. the number of the first heavily doped region, the second heavily doped region, the third heavily doped region, and the fourth heavily doped region is at least two; The first heavily doped regions are separated from one another, the second heavily doped regions are separated from one another, the third heavily doped regions are separated from one another, and the fourth heavily doped regions are separated from one another.

2. The electrostatic protection structure according to claim 1.

6. The first heavily doped regions are electrically connected to each other and function as the first electrode, the second heavily doped regions are electrically connected to each other and function as the second electrode, the third heavily doped regions are electrically connected to each other and function as the third electrode, and the fourth heavily doped regions are electrically connected to each other and function as the fourth electrode.

6. The electrostatic protection structure according to claim 5.

7. At least one fifth well region is further provided between the first well region and the second well region in an upper surface layer of the first deep well, the fifth well region is separated from the first well region and the second well region, and the fifth well region is of a second conductivity type; A seventh heavily doped region and an eighth heavily doped region of a first conductivity type are provided in an upper surface layer of each of the fifth well regions, the seventh heavily doped region in each of the fifth well regions is electrically connected to the eighth heavily doped region in the adjacent fifth well region, the seventh heavily doped region adjacent to the first well region is electrically connected to the second heavily doped region, and the eighth heavily doped region adjacent to the second well region is electrically connected to the third heavily doped region.

2. The electrostatic protection structure according to claim 1.

8. the first conductivity type is P type and the second conductivity type is N type; When an electrostatic voltage is input to the electrostatic port, the first heavily doped region, the first well region, and the second heavily doped region together constitute a first PNP transistor, the third heavily doped region, the second well region, and the fourth heavily doped region together constitute a second PNP transistor, the seventh heavily doped region, the fifth well region, and the eighth heavily doped region together constitute a third PNP transistor, and the first PNP transistor, the plurality of third PNP transistors, and the second PNP transistor are connected in series with each other.

8. The electrostatic protection structure according to claim 7.

9. A plurality of sixth well regions are further provided in an upper surface layer of the first deep well, the sixth well regions are alternately arranged with the first well region and the second well region, and the sixth well regions are of a first conductivity type.

2. The electrostatic protection structure according to claim 1.

10. The second deep well has an annular structure surrounding the outer periphery of the first deep well, and the third deep well has an annular structure surrounding the outer periphery of the second deep well.

2. The electrostatic protection structure according to claim 1.

11. The width of the sidewall of the third well region is smaller than the width of the sidewall of the second deep well.

2. The electrostatic protection structure according to claim 1.

12. The width of the sidewall of the fourth well region is smaller than the width of the sidewall of the third deep well.

2. The electrostatic protection structure according to claim 1.

13. a first isolation structure located in an upper surface layer of the first deep well, penetrating from an upper surface of the first deep well to the first well region, and alternately arranged with the first heavily doped region and the second heavily doped region; a second isolation structure located in an upper surface layer of the first deep well, penetrating from an upper surface of the first deep well to the second well region, and alternating with the third highly doped region and the fourth highly doped region.

2. The electrostatic protection structure according to claim 1.

14. a third isolation structure located in an upper surface layer of the second deep well and the third deep well and between the fifth heavily doped region and the sixth heavily doped region; a fourth isolation structure located in an upper surface layer of the sixth well region, between the first heavily doped region and the fifth heavily doped region, and between the fourth heavily doped region and the fifth heavily doped region.

10. The electrostatic protection structure according to claim 9.

15. Providing a substrate of a first conductivity type; forming a buried layer in the substrate of a second conductivity type opposite to the first conductivity type; forming a first deep well of a first conductivity type disposed in a floating state on an upper surface of the buried layer; forming a second deep well of a second conductivity type in the upper surface of the buried layer, the second deep well being adjacent to the first deep well and positioned on the outer periphery of the first deep well and having a partial region of a lower surface layer in contact with the substrate; forming a third deep well of a first conductivity type on the buried layer, the third deep well being in complete contact with the substrate and adjacent to and positioned on an outer periphery of the second deep well; forming a first well region and a second well region of a second conductivity type, the first well region and the second well region being separated from each other and arranged floating, in an upper surface layer of the first deep well; forming a first highly doped region and a second highly doped region separated from each other in an upper surface layer of the first well region; forming a third highly doped region and a fourth highly doped region separated from each other in an upper surface layer of the second well region, the first highly doped region, the second highly doped region, the third highly doped region, and the fourth highly doped region being of a first conductivity type; drawing out the first highly doped region as a first electrode and connecting it to an electrostatic port, drawing out the second highly doped region as a second electrode, drawing out the third highly doped region as a third electrode and electrically connecting it to the second electrode, and drawing out the fourth highly doped region as a fourth electrode; forming a third well region of a second conductivity type in an upper surface layer of the second deep well, and forming a floating fifth highly doped region of the second conductivity type in an upper surface layer of the third well region; forming a fourth well region of a first conductivity type on an upper surface layer of the third deep well, forming a sixth heavily doped region of the first conductivity type on an upper surface layer of the fourth well region, and drawing out the sixth heavily doped region and grounding it together with the fourth electrode.

4. A method for manufacturing an electrostatic protection structure comprising:

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