Semiconductor device and etching method

Abstract

Provided is an etching method that can ameliorate defects caused by etching when processing contact holes in a semiconductor device. The etching method comprises: bonding a first polymer film onto an insulation film by using plasma of a first gas, the insulation film being provided on a semiconductor layer that contains silicon; forming an altered layer by oxidizing the upper surface of the insulation film simultaneously with the removal of the first polymer film, using plasma of a second gas; bonding a second polymer film onto the altered layer by using plasma of a third gas; and removing the second polymer film and the altered layer by using plasma of a fourth gas.

Description

[Technical field]

[0001] The technology according to the present disclosure (the present technology) relates to a semiconductor device and an etching method. [Background technology]

[0002] Conventionally, various methods have been considered as etching methods for semiconductor devices. For example, Patent Document 1 discloses an etching method in which a silicon oxide film (SiO2 film) is used as an etching target film, and the etching method removes the film atomic layer by atomic layer by repeating a procedure of generating plasma of a fluorocarbon gas and a procedure of generating plasma of argon (Ar) gas. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2017-183688 A Summary of the Invention [Problem to be solved by the invention]

[0004] A silicon nitride film (SiN film) may be used as an etching stopper when processing contact holes in a semiconductor device, etc. However, over-etching of the SiN film may result in the formation of a recess in the semiconductor layer below the SiN film, and residual defects may occur at the bottom of the recess, resulting in an increase in dark current.

[0005] An object of the present technology is to provide a semiconductor device and an etching method that can improve defects caused by etching during contact hole processing of a semiconductor device. [Means for solving the problem]

[0006] A semiconductor device according to one aspect of the present technology includes a semiconductor layer containing silicon, a first insulating film provided on the semiconductor layer and having an opening, a conductive layer embedded in the opening of the first insulating film and having a lower end in contact with the semiconductor layer, and an altered layer containing oxygen provided between the first insulating film and the conductive layer.

[0007] An etching method according to one aspect of the present technology includes adsorbing a first polymer film onto an insulating film provided on a semiconductor layer containing silicon by using plasma of a first gas, removing the first polymer film by using plasma of a second gas, oxidizing an upper surface of the insulating film exposed after the first polymer film is removed to form an altered layer, adsorbing a second polymer film onto the altered layer by using plasma of a third gas, and removing the second polymer film and the altered layer by using plasma of a fourth gas. [Brief description of the drawings]

[0008] [Figure 1] 1 is a cross-sectional view of a semiconductor device according to a first embodiment. [Diagram 2] 1 is a schematic diagram of a plasma processing apparatus according to a first embodiment. [Diagram 3] 2 is a flowchart of an etching method for a semiconductor device according to the first embodiment. [Figure 4] 1A to 1C are cross-sectional views illustrating steps of an etching method according to a first embodiment. [Diagram 5] 5A to 5C are cross-sectional views illustrating a process subsequent to FIG. 4 in the etching method according to the first embodiment. [Figure 6A] 6A to 6C are cross-sectional views illustrating a process subsequent to FIG. 5 in the etching method according to the first embodiment. [Figure 6B] FIG. 6B is a partially enlarged view of FIG. 6A. [Figure 7A] 6B is a cross-sectional view showing a process subsequent to FIG. 6A in the etching method according to the first embodiment. [Figure 7B] FIG. 7B is a partially enlarged view of FIG. 7A. [Figure 8A] 7B is a cross-sectional view showing a process subsequent to FIG. 7A in the etching method according to the first embodiment. [Figure 8B] FIG. 8B is a partially enlarged view of FIG. 8A. [Figure 9A] 8B is a cross-sectional view showing a process subsequent to FIG. 8A in the etching method according to the first embodiment. [Figure 9B] FIG. 9B is a partially enlarged view of FIG. 9A. [Figure 10] 9B is a cross-sectional view showing a process subsequent to FIG. 9A in the etching method according to the first embodiment. [Figure 11] 13 is a graph showing a simulation result of Ar ion penetration. [Figure 12] 5A to 5C are cross-sectional views illustrating steps of an etching method according to a first comparative example. [Figure 13] 13A to 13C are cross-sectional views illustrating a process subsequent to FIG. 12 in the etching method according to the first comparative example. [Figure 14] 14A to 14C are cross-sectional views illustrating a process subsequent to FIG. 13 in the etching method according to the first comparative example. [Figure 15] 10A to 10C are cross-sectional process diagrams illustrating an etching method according to a second comparative example. [Figure 16] 16A to 16C are cross-sectional views illustrating a process subsequent to FIG. 15 in the etching method according to the second comparative example. [Figure 17] FIG. 11 is a cross-sectional view of a semiconductor device according to a second embodiment. [Figure 18] FIG. 11 is a cross-sectional view of a semiconductor device according to a third embodiment. [Figure 19] 1A to 1C are cross-sectional process diagrams of an etching method according to fourth to sixth embodiments. [Figure 20] FIG. 11 is a cross-sectional view of a semiconductor device according to a fourth embodiment. [Figure 21] FIG. 13 is a cross-sectional view of a semiconductor device according to a fifth embodiment. [Figure 22] FIG. 13 is a cross-sectional view of a semiconductor device according to a sixth embodiment. [Diagram 23] FIG. 13 is a block diagram of a solid-state imaging device according to a seventh embodiment. [Figure 24] FIG. 13 is an equivalent circuit diagram of a pixel according to the seventh embodiment. [Diagram 25] FIG. 13 is a block diagram of an electronic device according to a seventh embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, the first to seventh embodiments of the present technology will be described with reference to the drawings. The following description will refer to the drawings. In the description of the drawings, the same or similar parts are given the same or similar symbols. However, it should be noted that the drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each layer, etc. are different from the actual ones. Therefore, the specific thickness and dimensions should be determined with reference to the following description. In addition, it goes without saying that there are parts with different dimensional relationships and ratios between the drawings. Note that the effects described in this specification are merely examples and are not limited to the above, and other effects may also be present.

[0010] In this specification, the definitions of directions such as "up" and "down" are merely for the convenience of explanation and do not limit the technical idea of ​​the present technology. For example, if an object is rotated 90 degrees and observed, "up" and "down" are converted and read as "left" and "right," and of course, if it is rotated 180 degrees and observed, "up" and "down" are read in reverse.

[0011] (First embodiment) <Structure of Semiconductor Device> As shown in FIG. 1, the semiconductor device according to the first embodiment comprises a semiconductor layer 11 containing silicon (Si), an insulating film (lower-layer insulating film) 12 provided on the semiconductor layer 11, an insulating film (intermediate insulating film) 13 provided on the lower-layer insulating film 12, and an insulating film (upper-layer insulating film) 14 provided on the intermediate insulating film 13.

[0012] The semiconductor layer 11 is made of, for example, silicon (Si). The semiconductor layer 11 may be made of a Si substrate, or may be made of an epitaxially grown layer epitaxially grown on a Si substrate. The semiconductor layer 11 may be made of a compound semiconductor such as silicon carbide (SiC) or silicon germanium (SiGe).

[0013] The lower insulating film 12 is made of a natural oxide film made of, for example, a silicon oxide film (SiO2 film). The thickness of the lower insulating film 12 is, for example, about 1 nm, but is not limited to this. Note that the lower insulating film 12 may not be present, and the semiconductor layer 11 and the intermediate insulating film 13 may be in direct contact with each other.

[0014] The intermediate insulating film 13 is made of, for example, a silicon nitride film (Si3N4 film). The thickness of the intermediate insulating film 13 is, for example, about 30 to 300 nm, but is not limited to this. The upper insulating film 14 is made of, for example, a silicon oxide film (SiO2 film). The thickness of the upper insulating film 14 is, for example, about 30 to 300 nm, but is not limited to this. The upper insulating film 14 may not be provided.

[0015] The lower insulating film 12, the intermediate insulating film 13, and the upper insulating film 14 have openings (contact holes) that expose a part of the upper surface of the semiconductor layer 11. The diameter of the openings of the lower insulating film 12, the intermediate insulating film 13, and the upper insulating film 14 is, for example, about 30 to 100 nm, but is not limited thereto. A conductive layer 18 is embedded in the openings of the lower insulating film 12, the intermediate insulating film 13, and the upper insulating film 14. The lower end of the conductive layer 18 is in contact with the upper surface of the semiconductor layer 11. The conductive layer 18 is made of a metal material such as copper (Cu), aluminum (Al), or tungsten (W). Although not shown in the figure, wiring or the like is connected to the upper end of the conductive layer 18. The conductive layer 18 functions as a contact, a via, or the like that electrically connects the semiconductor layer 11 to wiring or the like. The plane pattern of the conductive layer 18 is, for example, rectangular, but may be circular or groove-shaped.

[0016] Between the intermediate insulating film 13 and the conductive layer 18, an altered layer (modified layer) 15 is formed so as to surround the side of the conductive layer 18. The inner side (inner peripheral surface) of the altered layer 15 is in contact with the side of the conductive layer 18. The thickness T1 of the altered layer 15 in the circumferential direction (left-right direction in FIG. 1) sandwiched between the intermediate insulating film 13 and the conductive layer 18 becomes thinner as it approaches the semiconductor layer 11. The outer side (outer peripheral surface) of the altered layer 15 in contact with the intermediate insulating film 13 has a step shape. FIG. 1 illustrates a case where the step difference T2 of the step shape is approximately uniform. FIG. 1 illustrates a case where the step shape of the altered layer 15 has six steps, but the number of steps is not particularly limited and may be one step, one to five steps, or seven steps or more.

[0017] The altered layer 15 is composed of a region where the intermediate insulating film 13 has been oxidized and altered (modified). The altered layer 15 is a layer containing oxygen, and is made of silicon oxide (SiO), such as silicon monoxide (SiO) or silicon dioxide (SiO2). x For example, the side surface of the altered layer 15 that contacts the conductive layer 18 is made of SiO x The oxygen concentration in the altered layer 15 may be graded from the inside to the outside so that the side of the altered layer 15 in contact with the intermediate insulating film 13 is made of SiON.

[0018] Here, the passivation property of Si3N4 is higher than that of SiON, and the passivation property of SiON is higher than that of SiO x Therefore, the passivation property of the intermediate insulating film 13 made of Si3N4 is higher than that of SiON or SiO x The passivation property of the altered layer 15 is higher than that of the altered layer 15 consisting of

[0019] In addition, the relative dielectric constant of Si3N4 (7.0) is higher than that of SiON or SiO x Therefore, the relative dielectric constant of the intermediate insulating film 13 made of Si3N4 is higher than that of SiON or SiO x The dielectric constant is higher than that of the altered layer 15 consisting of

[0020] In addition, SiO xThe pressure resistance of SiON is higher than that of SiON, which is higher than that of Si3N4. x The breakdown voltage of the altered layer 15 made of Si3N4 is higher than that of the intermediate insulating film 13 made of Si3N4.

[0021] According to the semiconductor device of the first embodiment, since the altered layer 15 containing oxygen is provided between the intermediate insulating film 13 and the conductive layer 18, it is possible to achieve a lower dielectric constant compared to a case where the altered layer 15 is not present. This makes it possible to reduce the capacitance and increase the speed of the device. Furthermore, since the breakdown voltage of the altered layer 15 is higher than that of the intermediate insulating film 13, it is possible to improve the breakdown voltage and reduce the leakage current compared to a case where the altered layer 15 is not present.

[0022] Furthermore, since the circumferential thickness T1 of the altered layer 15 becomes thinner closer to the semiconductor layer 11, it is possible to improve passivation against moisture and gas in the vicinity of the semiconductor layer 11, and to prevent deterioration of the device characteristics. Also, it is possible to suppress oxidation of the semiconductor layer 11 in the portion exposed in the contact hole, and to suppress an increase in contact resistance.

[0023] <Etching equipment> Next, a schematic configuration of an etching apparatus (plasma processing apparatus) according to a first embodiment for carrying out an etching method for a semiconductor device according to a first embodiment will be described. As shown in FIG. 2, the plasma processing apparatus according to the first embodiment includes a processing vessel 21 that accommodates a processing target 100.

[0024] A lower electrode 23 on which the workpiece 100 is placed, and an upper electrode 22 disposed opposite the lower electrode 23 are disposed within the processing vessel 21. High frequency power supplies 27 and 28 are connected to the lower electrode 23 and the upper electrode 22, respectively. The high frequency power supply 27 generates high frequency power (high frequency voltage) for attracting ions into the workpiece 100. The high frequency power supply 28 generates high frequency power for generating plasma.

[0025] A gas supply unit 24 and an exhaust unit 26 are connected to the processing vessel 21. The gas supply unit 24 selectively supplies various gases, such as a processing gas, into the processing vessel 21 while adjusting the flow rate. The exhaust unit 26 is composed of a vacuum pump, such as a turbo molecular pump, and reduces the pressure inside the processing vessel 21.

[0026] A control unit 25 is electrically connected to the gas supply unit 24, the exhaust unit 26, and the high frequency power supplies 27 and 28. The control unit 25 controls the selection and flow rate of gas in the gas supply unit 24, the exhaust amount in the exhaust unit 26, the amount of power supplied from the high frequency power supplies 27 and 28, etc. Note that the plasma processing apparatus according to the first embodiment shown in Fig. 2 is schematic, and in reality, it further includes various components not shown.

[0027] <Etching method> Next, the etching method for a semiconductor device according to the first embodiment will be described with reference to the flow chart in Fig. 3 and the process cross-sectional views in Fig. 4 to Fig. 10. Fig. 6A and Fig. 6B show the same process, and Fig. 6B is an enlarged view of a portion A surrounded by a dashed line in Fig. 6A. Fig. 7A and Fig. 7B, Fig. 8A and Fig. 8B, Fig. 9A and Fig. 9B have the same relationship as Fig. 6A and Fig. 6B.

[0028] In step S1 of Fig. 3, a processing target (semiconductor wafer) to be processed by the etching method for a semiconductor device according to the first embodiment is prepared. As shown in Fig. 4, the semiconductor wafer includes a semiconductor layer 11, a lower insulating film 12 provided on the semiconductor layer 11, an intermediate insulating film (film to be etched) 13 provided on the lower insulating film 12, and an upper insulating film 14 provided on the intermediate insulating film 13. Note that the lower insulating film 12 does not necessarily have to be formed. Then, a part of the upper insulating film 14 is selectively removed using photolithography and etching techniques to form an opening 14a exposing a part of the upper surface of the intermediate insulating film 13.

[0029] 2, the semiconductor wafer shown in Fig. 4 is placed on the lower electrode 23 of the processing vessel 21 as the object to be processed 100. Then, using the upper insulating film 14 as an etching mask, a part of the upper part of the intermediate insulating film 13 is selectively removed by normal dry etching such as reactive ion etching (RIE). As a result, a recess 13a of a predetermined depth is formed in the upper part of the intermediate insulating film 13 as shown in Fig. 5.

[0030] 3, a first gas is supplied into the processing vessel 21 by the gas supply unit 24 shown in FIG. 2, and plasma of the first gas is generated. The first gas is, for example, CH 3 containing carbon (C), fluorine (F), and hydrogen (H). x F y The first gas contains a system gas. Specific examples of the first gas include trifluoromethane (CHF3) gas, difluoromethane (CH2F2) gas, and fluoromethane (CH3F) gas. In addition to the first gas, a rare gas such as argon (Ar) or an inert gas made of nitrogen (N2) may be supplied into the processing vessel 21 to be appropriately diluted.

[0031] The process conditions for generating plasma of the first gas in step S2 are set, for example, as follows: pressure inside the processing vessel 21 is about 20 to 30 mTorr, power of the upper electrode 22 is about 400 to 600 W, high frequency voltage is 0 V, flow rate of the first gas is about 5 to 15 sccm, flow rate of Ar gas is about 400 to 600 sccm, and processing time is about 5 to 20 seconds.

[0032] As shown in Figures 6A and 6B, a first polymer film 16 is deposited on the top surface and side surface of the opening 14a of the upper insulating film 14, and on the side surface and bottom surface of the recess 13a of the intermediate insulating film 13 by ions (shown by straight arrows) and radicals (shown by wavy arrows) contained in the plasma of the first gas. The first polymer film 16 is adsorbed to the surface of the intermediate insulating film 13 located in the recess 13a of the intermediate insulating film 13. The first polymer film 16 is made of a polymer containing, for example, carbon (C), fluorine (F) and hydrogen (H). The first polymer film 16 is made of, for example, a hydrofluorocarbon (HFC).

[0033] 3, the first gas supplied in step S2 is exhausted by purging the processing vessel 21 using the exhaust unit 26 shown in Fig. 2. For example, the processing vessel 21 may be evacuated to a vacuum, or a purge gas such as Ar gas may be supplied into the processing vessel 21.

[0034] In step S4 of Fig. 3, a second gas is supplied into the processing vessel 21 by the gas supply unit 24 shown in Fig. 2, and plasma of the second gas is generated. The second gas is a gas containing oxygen (O). Specific examples of the second gas include oxygen (O2) gas, carbon monoxide (CO) gas, carbon dioxide (CO2) gas, nitric oxide (NO) gas, and nitrogen dioxide (NO2) gas. In addition to the second gas, a rare gas such as argon (Ar) or an inert gas such as nitrogen (N2) may be supplied to appropriately dilute the second gas.

[0035] The process conditions for generating plasma of the second gas in step S4 are set, for example, as follows: pressure inside the processing vessel 21 is about 20 to 30 mTorr, power of the upper electrode 22 is about 300 to 500 W, high frequency voltage is 0 V, flow rate of the second gas is about 400 to 600 sccm, and processing time is about 20 to 40 seconds.

[0036] The first polymer film 16 shown in Figures 6A and 6B is removed by oxygen ions and radicals contained in the plasma of the second gas, as shown in Figures 7A and 7B. At this time, the upper part (surface part) 13b (shown by a dashed line) of the intermediate insulating film 13 to which the first polymer film 16 shown in Figure 6B is adsorbed is detached and removed. Furthermore, as shown in Figures 7A and 7B, the surface of the intermediate insulating film 13 is oxidized and altered (modified), forming an altered layer (modified layer) 15x containing oxygen.

[0037] The thickness T3 of the altered layer 15x is approximately the same on the side and bottom of the recess 13a of the intermediate insulating film 13. The thickness T3 of the altered layer 15x is, for example, approximately 3 nm to 10 nm, and can be appropriately set by adjusting the plasma energy (high frequency power) of the second gas. The higher the plasma energy of the second gas, the thicker the thickness T3 of the altered layer 15x becomes, and the higher the oxygen concentration in the altered layer 15x becomes. On the other hand, the upper insulating film 14 originally contains oxygen, and therefore does not deteriorate like the intermediate insulating film 13.

[0038] 3, the second gas supplied in step S4 is exhausted by purging the processing vessel 21 using the exhaust unit 26 shown in Fig. 2. For example, the processing vessel 21 may be evacuated to a vacuum, or a purge gas such as Ar gas may be supplied into the processing vessel 21.

[0039] In step S6 of FIG. 3, a third gas is supplied into the processing vessel 21 by the gas supply unit 24 shown in FIG. 2, and plasma of the third gas is generated. The third gas is, for example, a fluorocarbon (C x F y )-based gas. Specific examples of the third gas include carbon tetrafluoride (CF4) gas, perfluorocyclobutane (C4F8) gas, hexafluoro-1,3-butadiene (C4F6) gas, and octafluorocyclopentene (C5F8) gas. In addition to the third gas, a rare gas such as argon (Ar) or an inert gas such as nitrogen (N2) may be supplied into the processing vessel 21 for appropriate dilution.

[0040] The process conditions for generating plasma of the third gas in step S6 are set, for example, as follows: pressure inside the processing vessel 21 is about 20 to 30 mTorr, power of the upper electrode 22 is about 400 to 600 W, high frequency voltage is 0 V, flow rate of the CF-based gas which is the third gas is about 5 to 20 sccm, flow rate of the Ar gas is about 400 to 600 sccm, and processing time is about 5 to 15 seconds.

[0041] 8A and 8B, ions and radicals contained in the plasma of the third gas cause a second polymer film 17 to be adsorbed onto the surface of the altered layer 15. The second polymer film 17 is made of a CF-based polymer containing carbon (C) and fluorine (F).

[0042] 3, the third gas supplied in step S6 is exhausted by purging the processing vessel 21 using the exhaust unit 26 shown in Fig. 2. For example, the processing vessel 21 may be evacuated to a vacuum, or a purge gas such as Ar gas may be supplied into the processing vessel 21.

[0043] In step S8 of Fig. 3, a fourth gas is supplied into the processing vessel 21 by the gas supply unit 24 shown in Fig. 2 to generate plasma of the fourth gas. The fourth gas is a gas containing a rare gas. Specific examples of the fourth gas include helium (He), neon (Ne), argon (Ar), krypton (Kr), and xenon (Xe).

[0044] The process conditions for generating plasma of the fourth gas in step S8 are set, for example, as follows: pressure inside the processing vessel 21 is about 20 to 30 mTorr, power of the upper electrode 22 is about 300 to 400 W, high-frequency voltage is 70 V, flow rate of the fourth gas, Ar gas, is about 400 to 500 sccm, and processing time is about 20 to 40 seconds.

[0045] 9A and 9B, the altered layer 15x is detached and removed together with the second polymer film 17 by ions of the rare gas contained in the plasma of the fourth gas. At this time, the altered layer 15x on the bottom surface of the recess 13a of the intermediate insulating film 13 is almost completely removed, and the intermediate insulating film 13 is removed. On the other hand, as shown in FIG. 9A, the side surface of the recess 13a of the intermediate insulating film 13 is thinly removed because the penetration of Ar ions is shallower than that of the bottom surface of the recess 13a. Therefore, the altered layer 15x in the deep portion of the side surface of the recess 13a remains.

[0046] 3, the fourth gas supplied in step S8 is exhausted by purging the processing vessel 21 using the exhaust unit 26 shown in Fig. 2. For example, the processing vessel 21 may be evacuated to a vacuum, or a purge gas such as Ar gas may be supplied into the processing vessel 21.

[0047] In step S10 of FIG. 3, the procedure of steps S2 to S9 is regarded as one cycle, and it is determined whether this cycle has been repeated a predetermined number of times. The predetermined number of times can be set in advance as the number of times to achieve a predetermined etching amount. Note that the predetermined number of times may be one time, and the procedure of steps S2 to S9 may not be repeated. If the cycle has not been repeated the predetermined number of times, the process returns to the procedure of step S2, and the cycle of steps S2 to S9 is repeated. The process conditions may be the same or different in each cycle.

[0048] 3 are repeated multiple times, the depth of the recess 13a in the intermediate insulating film 13 increases. Also, each time plasma of the second gas is generated in step S4 in each cycle, the thickness of the altered layer 15x on the side surface of the recess 13a in the intermediate insulating film 13 increases. Therefore, the altered layer 15x is formed one step at a time in each cycle.

[0049] In step S10 of Fig. 3, when the cycle of steps S2 to S9 is repeated a predetermined number of times, polymers, natural oxide films, etc. are removed using dilute hydrofluoric acid (DHF) or the like, and the etching process is completed. As a result, as shown in Fig. 10, the intermediate insulating film 13 and the lower insulating film 12 are removed, and openings (contact holes) are formed in the intermediate insulating film 13 and the lower insulating film 12, exposing a part of the upper surface of the semiconductor layer 11. In addition, the circumferential thickness T1 of the altered layer 15 becomes thinner closer to the semiconductor layer 11, and the outer peripheral surface of the altered layer 15 has a stepped shape. By making the plasma energy of the second gas in step S4 the same in each cycle of steps S2 to S9 of Fig. 3, the stepped steps T2 of the outer peripheral surface of the altered layer 15 can be formed approximately uniformly.

[0050] Thereafter, a conductive layer 18 is embedded in the openings (contact holes) of the lower insulating film 12, the intermediate insulating film 13, and the upper insulating film 14 by using a chemical vapor deposition (CVD) method or the like, thereby completing the semiconductor device shown in Fig. 1. Alternatively, the conductive layer 18 may be embedded in the openings (contact holes) of the lower insulating film 12 and the intermediate insulating film 13 after the upper insulating film 14 is removed.

[0051] According to the etching method for a semiconductor device of the first embodiment, the intermediate insulating film 13 made of Si3N4 is the etching target, and the intermediate insulating film 13 can be removed atomic layer by atomic layer etching (ALE) in which plasma generation and purging are repeated at least four times in the procedure of steps S2 to S9. This enables a high selectivity with respect to the semiconductor layer 11, and enables low-damage processing.

[0052] The left side of the graph in Fig. 10 shows the results of a simulation of argon (Ar) ion penetration when ALE is used, the power of the upper electrode 22 is 30 W (18 eV), and processing is performed for 60 seconds. The solid line profile in Fig. 10 shows the distribution of Ar ions, and the profile converted into a continuous value is shown by the dashed dotted line. The right side of the graph in Fig. 10 shows the composition in the depth direction from the Si surface measured using an ellipsometer. It can be seen from Fig. 10 that the penetration depth of Ar ions into Si is 5 nm or less, and the amount of recess in Si and the thickness of the altered layer 15 are 5 nm or less.

[0053] <First Comparative Example> Next, an etching method according to a first comparative example will be described. In the etching method according to the first comparative example, as shown in Fig. 12, a semiconductor wafer is prepared that includes a semiconductor layer 11, a lower insulating film 12 provided on the semiconductor layer 11, an intermediate insulating film 13 provided on the lower insulating film 12, and an upper insulating film 14 provided on the intermediate insulating film 13. Then, a part of the upper insulating film 14 is selectively removed using photolithography and etching techniques to form an opening.

[0054] 13, the intermediate insulating film 13 and the lower insulating film 12 are removed by reactive ion etching (RIE) using the upper insulating film 14 as an etching mask. At this time, the upper part of the semiconductor layer 11 is oxidized by overetching, and an oxide layer 11a is formed.

[0055] Next, by performing DHF treatment, the oxide layer 11a on the semiconductor layer 11 is removed to form a recess 11b, and furthermore, residual defects 11c of Si are generated at the bottom of the recess 11b, as shown in Fig. 14. The formation of the recess 11b and the generation of the residual defects 11c increase the dark current. In addition, the lower insulating film 12 is provided with a lateral slit 12a, which may deteriorate the yield and cause a metal filling failure.

[0056] In contrast, according to the etching method for a semiconductor device according to the first embodiment, as shown in Fig. 10, the formation of recesses in the semiconductor layer 11 due to over-etching can be suppressed, or even if recesses are formed, the depth of the recesses in the semiconductor layer 11 can be made shallower (for example, about 5 nm or less) than the recesses 11b in the first comparative example. Furthermore, residual defects at the bottom of the recesses in the semiconductor layer 11 can be suppressed or reduced, so that dark current can be reduced. Furthermore, as shown in Fig. 10, the formation of lateral slits in the lower insulating film 12 can be suppressed, so that the yield can be improved and poor metal filling can be suppressed.

[0057] <Second Comparative Example> Next, an etching method according to the second comparative example will be described. In the etching method according to the second comparative example, as in the first comparative example, a semiconductor wafer is prepared that includes a semiconductor layer 11, a lower insulating film 12 provided on the semiconductor layer 11, an intermediate insulating film 13 provided on the lower insulating film 12, and an upper insulating film 14 provided on the intermediate insulating film 13, as shown in Fig. 12. Then, a part of the upper insulating film 14 is selectively removed using photolithography and etching techniques to form an opening.

[0058] Next, a recess 13a having a predetermined depth is formed in the intermediate insulating film 13. Then, as shown in FIG. x F y A cycle is defined as a procedure of generating plasma of the Ar-based gas to adsorb the first polymer film 16, and a procedure of generating plasma of Ar gas to remove the intermediate insulating film 13 as shown in Fig. 16. In this case, as shown in Fig. 16, a part of the first polymer film 16 may remain when the plasma of Ar gas is generated. Therefore, when the procedures shown in Fig. 15 and Fig. 16 are repeated, the thickness of the first polymer film 16 may increase, and removal of the intermediate insulating film 13 may become difficult.

[0059] In contrast, according to the etching method for a semiconductor device of the first embodiment, by repeating the procedure of steps S2 to S9 shown in FIG. 3, the intermediate insulating film 13 can be easily removed without leaving any first polymer film 16 behind.

[0060] Second embodiment As shown in Fig. 17, the semiconductor device according to the second embodiment differs from the semiconductor device according to the first embodiment shown in Fig. 1 in that the outer peripheral surface of the affected layer 15 is a substantially curved surface (tapered shape). Compared to the semiconductor device according to the first embodiment shown in Fig. 1, the step-like steps of the outer peripheral surface of the affected layer 15 are formed shallow and minute, so that the steps are continuously connected and can be regarded as a substantially curved surface. The circumferential thickness T1 of the affected layer 15 becomes thinner as it approaches the semiconductor layer 11. Other configurations of the semiconductor device according to the second embodiment are similar to those of the semiconductor device according to the first embodiment shown in Fig. 1, so that repeated explanations will be omitted.

[0061] The etching method for the semiconductor device according to the second embodiment is similar to the etching method for the semiconductor device according to the first embodiment, and it is sufficient to reduce the plasma energy of the second gas when generating plasma of the second gas in step S4 shown in FIG.

[0062] Third embodiment As shown in Fig. 18, the semiconductor device according to the third embodiment differs from the semiconductor device according to the first embodiment shown in Fig. 1 in the shape of the affected layer 15. The outer peripheral surface of the upper portion 15a of the affected layer 15 is substantially vertical, and the circumferential thickness T1 of the upper portion 15a of the affected layer 15 is substantially constant. The outer peripheral surface of the lower portion 15b of the affected layer 15 has a stepped shape, and the circumferential thickness T1 of the lower portion 15b of the affected layer 15 becomes thinner as it approaches the semiconductor layer 11. The other configuration of the semiconductor device according to the third embodiment is similar to that of the semiconductor device according to the first embodiment shown in Fig. 1, so a duplicated description will be omitted.

[0063] In the etching method for the semiconductor device according to the third embodiment, after forming the recess 13a in the intermediate insulating film 13 as shown in FIG. 5 and before generating the plasma of the second gas in step S2 shown in FIG. 3, the intermediate insulating film 13 on the bottom surface of the recess 13a is removed to a predetermined depth by dry etching such as RIE. Then, the procedure of steps S2 to S9 shown in FIG. 3 is repeated. As a result, as shown in FIG. 18, the outer peripheral surface of the upper portion 15a of the altered layer 15 corresponding to the position where the intermediate insulating film 13 has been removed by dry etching such as RIE becomes substantially vertical. On the other hand, by repeating the procedure of steps S2 to S9 shown in FIG. 3, the outer peripheral surface of the lower portion 15b of the altered layer 15 corresponding to the position where the intermediate insulating film 13 has been removed becomes stepped.

[0064] According to the etching method for a semiconductor device according to the third embodiment, the number of repetitions of steps S2 to S9 can be reduced by using normal dry etching in the first half of the etching process for the intermediate insulating film 13. On the other hand, by repeating steps S2 to S9 in the second half of the etching process for the intermediate insulating film 13, it is possible to suppress the formation of recesses in the semiconductor layer 11 or reduce the depth of the recesses.

[0065] (Fourth embodiment) In the following fourth to sixth embodiments, compared to the etching method for a semiconductor device according to the first embodiment, a case will be illustrated in which the plasma energy of the second gas is increased when the plasma of the second gas is generated in step S4 shown in Fig. 3. For example, when the plasma energy of the second gas is increased in step S4 shown in Fig. 3, the circumferential thickness T4 of the altered layer 15x becomes thicker as shown in Fig. 19, compared to the circumferential thickness T3 of the altered layer 15x shown in Fig. 7A.

[0066] 20, the semiconductor device according to the fourth embodiment is common to the semiconductor device according to the first embodiment shown in FIG. 1 in that the outer peripheral surface of the affected layer 15 has a stepped shape, and the circumferential thickness T1 of the affected layer 15 becomes thinner the closer it is to the semiconductor layer 11. However, in the semiconductor device according to the fourth embodiment, the step height T5 of the stepped shape of the outer peripheral surface of the affected layer 15 is larger than the step height T2 of the semiconductor device according to the first embodiment shown in FIG. 1. Other configurations of the semiconductor device according to the fourth embodiment are similar to those of the semiconductor device according to the first embodiment shown in FIG. 1, and therefore repeated explanations will be omitted.

[0067] In the etching method for a semiconductor device according to the fourth embodiment, when steps S2 to S9 shown in FIG. 3 are repeated in the etching method for a semiconductor device according to the first embodiment, the plasma energy of the second gas is increased in step S4 as shown in FIG.

[0068] According to the etching method for a semiconductor device of the fourth embodiment, the amount of etching in one cycle of steps S2 to S9 shown in FIG. 3 can be increased, and the number of times steps S2 to S9 shown in FIG. 3 are repeated can be reduced.

[0069] Fifth embodiment As shown in Fig. 21, the semiconductor device according to the fifth embodiment differs from the semiconductor device according to the first embodiment shown in Fig. 1 in the shape of the upper part 15a of the affected layer 15. The outer peripheral surface of the upper part 15a of the affected layer 15 has a stepped shape, and the thickness T5 of the stepped shape is approximately constant. Meanwhile, the outer peripheral surface of the lower part 15b of the affected layer 15 also has a stepped shape, but the thickness T2 of the stepped shape is smaller than the thickness T5 of the stepped part of the upper part 15a of the affected layer 15. The other configuration of the semiconductor device according to the fifth embodiment is similar to that of the semiconductor device according to the first embodiment shown in Fig. 1, so that a duplicated description will be omitted.

[0070] As the etching method for a semiconductor device according to the fifth embodiment, in the etching method for a semiconductor device according to the first embodiment, in the first half of the multiple cycles of the procedure of steps S2 to S9 shown in Fig. 3, the plasma energy of the second gas in step S4 is made relatively large. After that, in the second half of the multiple cycles of the procedure of steps S2 to S9 shown in Fig. 3, the plasma energy of the second gas in step S4 is made relatively small.

[0071] According to the etching method for a semiconductor device according to the fifth embodiment, in the first half of the multiple cycles, the amount of etching in one cycle can be increased, and the number of cycle repetitions can be reduced. On the other hand, in the second half of the multiple cycles, the amount of etching in one cycle can be reduced, and etching accuracy can be improved, thereby suppressing the formation of recesses in the semiconductor layer 11 or reducing the depth of the recesses.

[0072] Sixth embodiment As shown in FIG. 22, the semiconductor device according to the sixth embodiment differs from the semiconductor device according to the first embodiment shown in FIG. 1 in the shapes of the upper portion 15a and the lower portion 15b of the affected layer 15. The outer peripheral surface of the upper portion 15a of the affected layer 15 is substantially vertical, and the circumferential thickness T1 of the upper portion 15a of the affected layer 15 is substantially constant. The outer peripheral surface of the lower portion 15b of the affected layer 15 has a stepped shape. Note that, although the stepped shape of the lower portion 15b of the affected layer 15 has one step in FIG. 22, it may have multiple steps. The other configuration of the semiconductor device according to the sixth embodiment is similar to that of the semiconductor device according to the first embodiment shown in FIG. 1, and therefore a duplicated description will be omitted.

[0073] In the etching method for the semiconductor device according to the sixth embodiment, in the etching method for the semiconductor device according to the first embodiment, a recess 13a is formed in the intermediate insulating film 13 as shown in FIG. 5, and then the intermediate insulating film 13 at the bottom of the recess 13a is removed to a predetermined depth by dry etching such as RIE. Then, the procedure of steps S2 to S9 shown in FIG. 3 is repeated, but the plasma energy of the second gas in step S4 is made larger than that in the etching method for the semiconductor device according to the first embodiment. As a result, as shown in FIG. 22, the outer peripheral surface of the upper portion 15a of the altered layer 15 corresponding to the position where the intermediate insulating film 13 has been removed by dry etching such as RIE becomes approximately vertical. On the other hand, by repeating the procedure of steps S2 to S9 shown in FIG. 3, the outer peripheral surface of the lower portion 15b of the altered layer 15 corresponding to the position where the intermediate insulating film 13 has been removed becomes stepped.

[0074] According to the etching method for a semiconductor device according to the sixth embodiment, the number of repetitions of steps S2 to S9 can be reduced by using normal dry etching in the first half of the etching process for the intermediate insulating film 13. On the other hand, by repeating steps S2 to S9 in the second half of the etching process for the intermediate insulating film 13, the formation of recesses in the semiconductor layer 11 can be suppressed or the depth of the recesses can be reduced.

[0075] Seventh embodiment In the seventh embodiment, a solid-state imaging device and electronic equipment to which the semiconductor device according to the first to sixth embodiments can be applied will be illustrated.

[0076] <Electronic equipment> As the solid-state imaging device according to the seventh embodiment, a CMOS (Complementary Metal Oxide Semiconductor) image sensor will be described as an example. As shown in Fig. 23, the solid-state imaging device according to the seventh embodiment includes a pixel region (imaging region) 3 in which pixels 2 are arranged in a matrix, and a peripheral circuit section (4, 5, 6, 7, 8) that processes pixel signals output from the pixel region 3.

[0077] The pixel 2 generally has a photoelectric conversion region formed of a photodiode that photoelectrically converts incident light, and a plurality of pixel transistors for reading out signal charges generated by the photoelectric conversion of the photoelectric conversion region. The plurality of pixel transistors may be formed of, for example, three transistors, a transfer transistor, a reset transistor, and an amplification transistor. The plurality of pixel transistors may also be formed of four transistors by further adding a selection transistor.

[0078] The peripheral circuit section (4, 5, 6, 7, 8) has a vertical drive circuit 4, a column signal processing circuit 5, a horizontal drive circuit 6, an output circuit 7, and a control circuit 8. The control circuit 8 receives an input clock and data instructing an operation mode, etc., and outputs data such as internal information of the solid-state imaging device. For example, the control circuit 8 generates clock signals and control signals that serve as a reference for the operation of the vertical drive circuit 4, the column signal processing circuit 5, the horizontal drive circuit 6, etc., based on a vertical synchronization signal, a horizontal synchronization signal, and a master clock. The control circuit 8 outputs the generated clock signals and control signals to the vertical drive circuit 4, the column signal processing circuit 5, the horizontal drive circuit 6, etc.

[0079] The vertical drive circuit 4 is formed of, for example, a shift register. The vertical drive circuit 4 selects a pixel drive wiring, supplies a pulse for driving the pixel 2 to the selected pixel drive wiring, and drives the pixel 2 row by row. For example, the vertical drive circuit 4 sequentially selects and scans each pixel 2 in the pixel region 3 row by row in the vertical direction, and supplies a pixel signal based on a signal charge generated in accordance with the amount of light received in, for example, a photodiode serving as a photoelectric conversion region of each pixel 2 to the column signal processing circuit 5 through the vertical signal line 9.

[0080] The column signal processing circuit 5 is disposed, for example, for each column of pixels 2. The column signal processing circuit 5 performs signal processing such as noise removal on signals output from one row of pixels 2 for each pixel column. For example, the column signal processing circuit 5 performs signal processing such as CDS for removing fixed pattern noise specific to the pixels 2, signal amplification, AD conversion, etc. A horizontal selection switch (not shown) is provided at the output stage of the column signal processing circuit 5 and connected between the output stage and the horizontal signal line 10.

[0081] The horizontal drive circuit 6 is configured by, for example, a shift register. The horizontal drive circuit 6 sequentially outputs horizontal scanning pulses to select each of the column signal processing circuits 5 in turn, and causes each of the column signal processing circuits 5 to output a pixel signal to the horizontal signal line 10.

[0082] The output circuit 7 processes and outputs signals sequentially supplied from each of the column signal processing circuits 5 through the horizontal signal line 10. For example, the output circuit 7 may perform only buffering, or may perform black level adjustment, column variation correction, various digital signal processing, etc. The input / output terminal 31 exchanges signals with the outside.

[0083] In Fig. 23, the pixel region 3 and peripheral circuit section (4, 5, 6, 7, 8) of the solid-state imaging device according to the seventh embodiment are formed on one substrate 1, but they may be formed in a laminated structure in which a plurality of substrates are bonded together. For example, the solid-state imaging device according to the seventh embodiment may be configured with first and second substrates, with the photoelectric conversion region and pixel transistors provided on the first substrate, and the peripheral circuits (3, 4, 5, 6, 7) and the like provided on the second substrate. Alternatively, the photoelectric conversion region and a portion of the pixel transistors may be provided on the first substrate, and the remaining portion of the pixel transistors and the peripheral circuits (3, 4, 5, 6, 7) and the like may be provided on the second substrate.

[0084] 24 shows an example of an equivalent circuit of a pixel 2 of a solid-state imaging device according to the seventh embodiment. The anode of a photodiode PD, which is a photoelectric conversion region of the pixel 2, is grounded, and the source of a transfer transistor T1, which is an active element, is connected to the cathode of the photodiode PD. A floating diffusion region FD is connected to the drain of the transfer transistor T1. The floating diffusion region FD is connected to the source of a reset transistor T2, which is an active element, and the gate of an amplification transistor T3, which is an active element. The source of the amplification transistor T3 is connected to the drain of a selection transistor T4, which is an active element, and the drain of the amplification transistor T3 is connected to a power supply Vdd. The source of the selection transistor T4 is connected to a vertical signal line VSL. The drain of the reset transistor T2 is connected to a power supply Vdd.

[0085] During operation of the solid-state imaging device according to the seventh embodiment, a control potential TRG is applied to the transfer transistor T1, and the signal charge generated in the photodiode PD is transferred to the floating diffusion region FD. The signal charge transferred to the floating diffusion region FD is read out and applied to the gate of the amplification transistor T3. A horizontal line selection signal SEL is provided to the gate of the selection transistor T4 from the vertical shift register. By setting the selection signal SEL to a high (H) level, the selection transistor T4 becomes conductive, and a current corresponding to the potential of the floating diffusion region FD amplified by the amplification transistor T3 flows through the vertical signal line VSL. In addition, by setting the reset signal RST applied to the gate of the reset transistor T2 to a high (H) level, the reset transistor T2 becomes conductive, and the signal charge accumulated in the floating diffusion region FD is reset.

[0086] For example, the semiconductor device according to the first to sixth embodiments may be a semiconductor device having a semiconductor layer (diffusion layer) connected to a conductive layer (contact) embedded in a contact hole, such as the photodiode PD, the transfer transistor T1, the reset transistor T2, the amplifying transistor T3, and the selection transistor T4 shown in FIG.

[0087] <Electronic equipment> Fig. 25 is a block diagram showing a configuration example of an embodiment of an imaging device as an electronic device to which the present disclosure is applied. The imaging device 1000 in Fig. 25 is a video camera, a digital still camera, or the like. The imaging device 1000 includes a lens group 1001, a solid-state imaging element 1002, a DSP circuit 1003, a frame memory 1004, a display unit 1005, a recording unit 1006, an operation unit 1007, and a power supply unit 1008. The DSP circuit 1003, the frame memory 1004, the display unit 1005, the recording unit 1006, the operation unit 1007, and the power supply unit 1008 are connected to each other via a bus line 1009.

[0088] The lens group 1001 captures incident light (image light) from a subject and forms an image on the imaging surface of the solid-state imaging element 1002. The solid-state imaging element 1002 corresponds to the solid-state imaging device according to the seventh embodiment of the CMOS image sensor described above. The solid-state imaging element 1002 converts the amount of incident light formed on the imaging surface by the lens group 1001 into an electrical signal on a pixel-by-pixel basis and supplies the electrical signal to the DSP circuit 1003.

[0089] The DSP circuit 1003 performs a predetermined image processing on the pixel signals supplied from the solid-state imaging device 1002, and supplies the processed image signals to a frame memory 1004 on a frame-by-frame basis for temporary storage.

[0090] The display unit 1005 is formed of a panel-type display device such as a liquid crystal panel or an organic EL (Electro Luminescence) panel, and displays an image based on pixel signals temporarily stored in the frame memory 1004 on a frame-by-frame basis.

[0091] The recording unit 1006 is made up of a DVD (Digital Versatile Disk), a flash memory, or the like, and reads out and records the pixel signals in units of frames that are temporarily stored in the frame memory 1004 .

[0092] An operation unit 1007, under the operation of a user, issues operation commands for various functions of the imaging device 1000. A power supply unit 1008 supplies power to the DSP circuit 1003, the frame memory 1004, the display unit 1005, the recording unit 1006, and the operation unit 1007 as appropriate.

[0093] The electronic device to which this technology can be applied may be any device that uses a CMOS image sensor in its image capture section (photoelectric conversion section), and in addition to the imaging device 1000, includes a portable terminal device with imaging function, a copier that uses a CMOS image sensor in its image reading section, and the like.

[0094] (Other embodiments) As described above, the present technology has been described by the first to seventh embodiments, but the descriptions and drawings forming part of this disclosure should not be understood as limiting the present technology. If the gist of the technical content disclosed in the above embodiments is understood, it will be clear to those skilled in the art that various alternative embodiments, examples, and operational techniques can be included in the present technology. In addition, the configurations disclosed in the first to seventh embodiments can be appropriately combined within a range that does not cause contradictions.

[0095] In addition, application examples of the present disclosure include infrared receiving elements, imaging devices using the same, electronic devices, etc., and possible uses include a wide range of imaging and sensing applications other than ordinary cameras and smartphones, such as surveillance cameras, cameras for industrial equipment such as factory inspections, in-vehicle cameras, distance measuring sensors (ToF sensors), infrared sensors, etc. An example is described below.

[0096] The present technology can be configured as follows. (1) A semiconductor layer including silicon; a first insulating film provided on the semiconductor layer and having an opening exposing a portion of the semiconductor layer; a conductive layer embedded in the opening of the first insulating film and having a lower end in contact with the semiconductor layer; an altered layer containing oxygen, the altered layer being provided between the first insulating film and the conductive layer; A semiconductor device comprising: (2) the altered layer has a smaller thickness sandwiched between the first insulating film and the conductive layer as it approaches the semiconductor layer; The semiconductor device according to (1) above. (3) a side surface of the altered layer in contact with the first insulating film has a stepped shape; The semiconductor device according to (2) above. (4) a step height of the step shape in a lower portion of the affected layer is smaller than a step height of the step shape in an upper portion of the semiconductor layer; The semiconductor device according to (3) above. (5) the relative dielectric constant of the altered layer is lower than the relative dielectric constant of the first insulating film; The semiconductor device according to any one of (1) to (4). (6) The first insulating film is made of silicon nitride. The semiconductor device according to any one of (1) to (5). (7) The altered layer contains silicon oxide or silicon oxynitride. The semiconductor device according to any one of (1) to (6). (8) Further comprising a second insulating film provided between the semiconductor layer and the first insulating film. The semiconductor device according to any one of (1) to (7). (9) The second insulating film is made of silicon oxide. The semiconductor device according to (8) above. (10) Further comprising a third insulating film provided on the first insulating film. The semiconductor device according to any one of (1) to (9). (11) the third insulating film is made of a silicon oxide film; The semiconductor device according to (10) above. (12) a first polymer film is adsorbed on an insulating film provided on a semiconductor layer containing silicon by plasma of a first gas; removing the first polymer film by using plasma of a second gas, and oxidizing an upper surface of the insulating film exposed after the first polymer film is removed to form an altered layer; a second polymer film is adsorbed on the altered layer by a plasma of a third gas; removing the second polymer film and the altered layer by plasma of a fourth gas; The etching method includes: (13) The first gas contains carbon, hydrogen and fluorine. The etching method according to (12) above. (14) The second gas contains oxygen. The etching method according to (12) or (13) above. (15) The third gas contains carbon and fluorine. The etching method according to any one of (12) to (14) above. (16) The fourth gas contains a rare gas. The etching method according to any one of (12) to (15) above. (17) Before the first polymer film is adsorbed, Further comprising removing an upper portion of the first insulating film by dry etching. The etching method according to any one of (12) to (16) above. (18) Repeating a cycle including adsorbing the first polymer film, forming the denatured layer, adsorbing the second polymer film, and removing the denatured layer a plurality of times. The etching method according to any one of (12) to (17) above. (19) The plasma energy of the second gas in each of the multiple cycles is made the same. The etching method according to (18) above. (20) a plasma energy of the second gas in the latter half of the multiple cycles is set to be smaller than a plasma energy of the second gas in the first half of the multiple cycles; The etching method according to (18) above. [Explanation of symbols]

[0097] 1...substrate, 2...pixel, 3...pixel region (imaging region), 4...vertical drive circuit, 5...column signal processing circuit, 6...horizontal drive circuit, 7...output circuit, 8...control circuit, 9...vertical signal line, 10...horizontal signal line, 11...semiconductor layer, 11a...oxide layer, 11b...recess, 11c...residual defect, 12...insulating film (lower insulating film), 12a...slit, 13...insulating film (intermediate insulating film), 13a...recess, 13b...upper portion, 14...insulating film (upper insulating film), 14a Opening, 15...degraded layer (modified layer), 15a...upper portion, 15b...lower portion, 18...conductive layer, 21...treatment vessel, 22...upper electrode, 22...electrode, 23...lower electrode, 24...gas supply portion, 25...control portion, 26...exhaust portion, 27, 28...high frequency power supply, 31...input / output terminal, 100...processed object, 1000...imaging device, 1001...lens group, 1002...solid-state imaging element, 1003...DSP circuit, 1004...frame memory, 1005...display portion, 1006...recording portion, 1007...operation portion, 1008...power supply portion, 1009...bus line

Claims

1. A semiconductor layer including silicon; a first insulating film provided on the semiconductor layer and having an opening exposing a portion of the semiconductor layer; a conductive layer embedded in the opening of the first insulating film and having a lower end in contact with the semiconductor layer; an altered layer including oxygen, the altered layer being provided between the first insulating film and the conductive layer; Equipped with the altered layer has a smaller thickness between the first insulating film and the conductive layer as it approaches the semiconductor layer, A semiconductor device, wherein a side surface of the altered layer in contact with the first insulating film has a stepped shape.

2. a step height of the step shape in a lower portion of the affected layer is smaller than a step height of the step shape in an upper portion of the semiconductor layer; The semiconductor device according to claim 1 .

3. the relative dielectric constant of the altered layer is lower than the relative dielectric constant of the first insulating film; The semiconductor device according to claim 1 .

4. The first insulating film is made of silicon nitride. The semiconductor device according to claim 1 .

5. The altered layer contains silicon oxide or silicon oxynitride. The semiconductor device according to claim 1 .

6. Further comprising a second insulating film provided between the semiconductor layer and the first insulating film. The semiconductor device according to claim 1 .

7. The second insulating film is made of silicon oxide. The semiconductor device according to claim 6.

8. Further comprising a third insulating film provided on the first insulating film. The semiconductor device according to claim 1 .

9. the third insulating film is made of a silicon oxide film; The semiconductor device according to claim 8.

10. a first polymer film is adsorbed on an insulating film provided on a semiconductor layer containing silicon by plasma of a first gas; removing the first polymer film by plasma of a second gas, and oxidizing an upper surface of the insulating film exposed by removing the first polymer film to form an altered layer; a second polymer film is adsorbed on the altered layer by a plasma of a third gas; removing the second polymer film and the altered layer by plasma of a fourth gas; The etching method includes:

11. The first gas contains carbon, hydrogen and fluorine. The etching method according to claim 10.

12. The second gas contains oxygen. The etching method according to claim 10.

13. The third gas contains carbon and fluorine. The etching method according to claim 10.

14. The fourth gas contains a rare gas. The etching method according to claim 10.

15. Before the first polymer film is adsorbed, Further comprising removing an upper portion of the insulating film by dry etching. The etching method according to claim 10.

16. Repeating a cycle including adsorbing the first polymer film, forming the denatured layer, adsorbing the second polymer film, and removing the denatured layer a plurality of times. The etching method according to claim 10.

17. The plasma energy of the second gas in each of the multiple cycles is made the same.

17. The etching method according to claim 16.

18. a plasma energy of the second gas in the latter half of the plurality of cycles is set to be smaller than a plasma energy of the second gas in the first half of the plurality of cycles; 17. The etching method according to claim 16.

Images