Semiconductor Device

Abstract

To provide a semiconductor device capable of reducing a loss while suppressing snapback.SOLUTION: A semiconductor device comprises: a first electrode; a first semiconductor layer provided on the first electrode in a diode region; a second semiconductor layer provided on the first electrode in an IGBT region; a semiconductor part provided on the first and second semiconductor layers, and in which the impurity concentration of a first region located in the diode region and adjacent to the IGBT region, among an upper layer part, is lower than that of a second region located in the diode region and separated from the IGBT region; a third semiconductor layer provided on the semiconductor part; a fourth semiconductor layer provided at an upper layer part of the third semiconductor layer, in the IGBT region; a third electrode extending in a direction from the fourth semiconductor layer toward the semiconductor part; and an insulating film provided between the second electrode and each of the third semiconductor layer, the semiconductor part, and the third electrode.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The embodiments relate to a semiconductor device. [Background technology]

[0002] Conventionally, RC-IGBT (Reverse Conducting-IGBT) in which a diode region and an IGBT (Insulated Gate Bipolar Transistor) region are set is known. In the RC-IGBT, a return current from the emitter side to the collector side of the IGBT region can be made to flow in the diode region. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 6589817 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the embodiments is to provide a semiconductor device capable of reducing losses while suppressing snapback. [Means for solving the problem]

[0005] A semiconductor device according to an embodiment is a semiconductor device having a diode region and an IGBT region, the semiconductor device including: a first electrode provided across the diode region and the IGBT region; a first semiconductor layer of a first conductivity type provided on the first electrode in the diode region; a second semiconductor layer of a second conductivity type provided on the first electrode in the IGBT region; a semiconductor portion of the first conductivity type provided on the first semiconductor layer and the second semiconductor layer, the semiconductor portion having an impurity concentration in a first region located in the diode region and adjacent to the IGBT region, the first region being an upper layer portion, the first region being located in the diode region and adjacent to the IGBT region, lower than an impurity concentration in a second region located in the diode region and separated from the IGBT region; the third semiconductor layer of the second conductivity type provided on the semiconductor portion in the IGBT region; a fourth semiconductor layer of the first conductivity type provided on an upper layer of the third semiconductor layer in the IGBT region; a second electrode extending in a direction from the fourth semiconductor layer toward the semiconductor portion in the IGBT region and adjacent to the fourth semiconductor layer, the third semiconductor layer, and the semiconductor portion; a third electrode located on the third semiconductor layer in the diode region and located on the fourth semiconductor layer in the IGBT region; and insulating films provided between the second electrode and the fourth semiconductor layer, between the second electrode and the third semiconductor layer, between the second electrode and the semiconductor portion, and between the second electrode and the third electrode. [Brief description of the drawings]

[0006] [Figure 1] 1 is a top view showing a semiconductor device according to a first embodiment. [Diagram 2] 2 is a cross-sectional view taken along line AA' in FIG. [Diagram 3] FIG. 3(a) is a schematic diagram showing the direction of carrier movement within the semiconductor device of the first embodiment, and FIG. 3(b) is a schematic diagram showing the direction of carrier movement within the semiconductor device of the reference example. [Figure 4]FIG. 4(a) is a graph showing the results of a simulation of the relationship between the voltage Vak applied between the upper electrode and the lower electrode in the diode region of the semiconductor device according to the first embodiment and the semiconductor device according to the reference example, and FIG. 4(b) is a graph showing the results of a simulation of the carrier density of the semiconductor device according to the first embodiment and the semiconductor device according to the reference example. [Diagram 5] FIG. 4 is a cross-sectional view showing a semiconductor device according to a second embodiment. [Figure 6] FIG. 11 is a cross-sectional view showing a semiconductor device according to a third embodiment. [Figure 7] FIG. 7(a) is a cross-sectional view along the top surfaces of the p-type semiconductor layer and the p+ type contact layer in a first region of the diode region, and FIG. 7(b) is a cross-sectional view along the top surfaces of the p-type semiconductor layer and the p+ type contact layer in a second region of the diode region. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Each embodiment will be described below with reference to the drawings. The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between parts, etc. are not necessarily the same as the actual ones. Even when the same part is shown, the dimensions and ratios of each part may be different depending on the drawing. Furthermore, in this specification and each drawing, elements similar to those explained with reference to the previous drawings are given the same reference numerals, and detailed explanations are omitted as appropriate.

[0008] For ease of understanding, the following description will use an XYZ Cartesian coordinate system to explain the arrangement and configuration of each part. The X-axis, Y-axis, and Z-axis are mutually perpendicular. The direction in which the X-axis extends is referred to as the "X-direction," the direction in which the Y-axis extends as the "Y-direction," and the direction in which the Z-axis extends as the "Z-direction." For ease of understanding, the direction of the arrow in the Z-direction is referred to as upward and the opposite direction as downward, but these directions are unrelated to the direction of gravity.

[0009] In the following, the notations + and - indicate the relative level of the impurity concentration in each conductivity type. Specifically, a notation with "+" indicates a higher impurity concentration than a notation with neither "+" nor "-". A notation with "-" indicates a lower impurity concentration than a notation with neither "+" nor "-". Here, "impurity concentration" refers to the net impurity concentration after both donor and acceptor impurities are offset in each region.

[0010] <First embodiment> First, the first embodiment will be described. FIG. 1 is a top view showing a semiconductor device according to the present embodiment. FIG. 2 is a cross-sectional view taken along line AA' in FIG. The semiconductor device 100 according to this embodiment is an RC-IGBT. As shown in Fig. 1, the semiconductor device 100 has a plurality of diode regions S1 and a plurality of IGBT regions S2. The plurality of diode regions S1 and the plurality of IGBT regions S2 are arranged alternately in the X direction.

[0011] As shown in FIG. 2, in this embodiment, the semiconductor device 100 includes a lower electrode 110 and + A cathode layer 121 having a shape of p + A collector layer 122 of n-type, a semiconductor portion 123 of n-type, a p-type semiconductor layer 124 of n-type, + The semiconductor device 100 includes an emitter layer 126 having a rectangular shape, a plurality of internal electrodes 130, a plurality of gate electrodes 140, an upper electrode 150, a plurality of insulating films 161, and a plurality of insulating films 162. Each component of the semiconductor device 100 will be described in detail below.

[0012] The lower electrode 110 is made of a conductive material such as a metal material. The lower electrode 110 is provided over substantially the entire lower surface of the semiconductor device 100. That is, the lower electrode 110 is provided across the diode region S1 and the IGBT region S2. The lower electrode 110 functions as a cathode electrode in the diode region S1, and functions as a collector electrode in the IGBT region S2. The upper and lower surfaces of the lower electrode 110 are substantially parallel to the XY plane.

[0013] n + In this embodiment, the cathode layer 121 having a shape similar to that of the cathode 120 is disposed on a portion of the lower electrode 110 located in the diode region S1.

[0014] p + In this embodiment, the collector layer 122 is disposed on a portion of the lower electrode 110 located in the IGBT region S2. + The collector layer 122 is an n + In the X direction, the cathode layer 121 is adjacent to the cathode layer 121 having the shape of n + A part of the cathode layer having a p-type junction may be located within the IGBT region. + A portion of the collector layer of the semiconductor device may be located within the diode region.

[0015] The n-type semiconductor portion 123 is provided across the diode region S1 and the IGBT region S2. In this embodiment, the n-type semiconductor portion 123 is + In the IGBT region, p + The collector layer 122 is disposed on the collector layer 122 .

[0016] The semiconductor portion 123 is + A buffer layer 123a having a shape of n - The n-type drift layer 123b and the n-type barrier layer 123c.

[0017] n + The n-type buffer layer 123a is provided across the diode region S1 and the IGBT region S2. +The buffer layer 123a has an n-type + In the IGBT region S2, + The collector layer 122 is disposed on the collector layer 122. + The impurity concentration of the buffer layer 123a is n + The impurity concentration of the n-type cathode layer 121 is lower than that of the n-type cathode layer 121. However, the semiconductor device does not necessarily need to have an n-type buffer layer.

[0018] n - The n-type drift layer 123b is disposed in the diode region S1 and the IGBT region S2. + The buffer layer 123a is disposed on the n - The impurity concentration of the drift layer 123b is n + The impurity concentration of the buffer layer 123a is lower than that of the buffer layer 123a.

[0019] 1, the diode region S1 includes a first region S1a adjacent to the IGBT region S2 and a second region S1b separated from the IGBT region S2. In the diode region S1 located between the two IGBT regions S2, one second region S1b is located between the two first regions S1a. Therefore, in the diode region S1 located between the two IGBT regions S2, the first region S1a is a region of the diode region S1 that is close to the IGBT region S2, and the second region S1b is a central region of the diode region S1.

[0020] As shown in FIG. 2, the n-type barrier layer 123c is formed in the second region S1b and the IGBT region S2. - In this embodiment, the n-type barrier layer 123c is disposed in the upper layer of the n-type drift layer 123b. of The impurity concentration of the n-type barrier layer 123c is n - The impurity concentration of the n-type drift layer 123b is higher than that of the n-type barrier layer 123c. + The cathode layer 121 and the n +However, the impurity concentration of the n-type barrier layer is lower than that of the n-type buffer layer 123a. + The cathode layer and n + The magnitude relationship between the impurity concentration of the buffer layer and is not limited to the above.

[0021] In this embodiment, since the n-type barrier layer 123c is provided in the second region S1b, the impurity concentration of the portion of the upper layer of the semiconductor part 123 located in the first region S1a is lower than the impurity concentration of the portion located in the second region S1b. - The difference in impurity concentration between the drift layer 123b and the shaped drift layer 123b is not particularly limited, but may be, for example, 3×10 13 cm -3 More than 1×10 14 cm -3 The following is the result.

[0022] However, the method of making the impurity concentration of the portion of the upper layer of the n-type semiconductor part located in the first region lower than the impurity concentration of the portion located in the second region is not limited to the above. For example, the upper layer of the n-type semiconductor part may be configured so that the impurity concentration increases gradually or stepwise from the boundary between the diode region and the IGBT region toward the center of the diode region.

[0023] In this embodiment, as shown in Fig. 1, the width L1 of the first region S1a in the X direction is shorter than the width L2 of the second region S1b in the X direction. However, the magnitude relationship between the width of the first region and the width of the second region is not limited to the above. For example, the width of the first region and the width of the second region may be approximately the same, or the width of the first region may be longer than the width of the second region.

[0024] 2, the p-type semiconductor layer 124 is provided in the diode region S1 and the IGBT region S2. - The n-type drift layer 123b is disposed on the n-type drift layer 123b. -In the second region S1b and the IGBT region S2, the p-type semiconductor layer 124 is disposed on the n-type barrier layer 123c and in contact with the n-type barrier layer 123c.

[0025] n + The p-type emitter layer 126 is disposed on the upper layer of the p-type semiconductor layer 124 in the IGBT region S2, and is not provided in the diode region S1.

[0026] n + Cathode layer 121, p + A collector layer 122, an n-type semiconductor portion 123, a p-type semiconductor layer 124, and an n + The emitter layers 126 of the semiconductor layer 120 include a semiconductor material, such as silicon, and impurities corresponding to each layer.

[0027] In the diode region S1, the upper layer of the p-type semiconductor layer 124 is provided with a p-type semiconductor layer 124 having an impurity concentration higher than the impurity concentration of the p-type semiconductor layer 124 and in ohmic contact with the upper electrode 150 described later. + A contact layer having a shape similar to that of the first embodiment may be partially provided.

[0028] A plurality of trenches T1 are provided in the diode region S1. The plurality of trenches T1 are arranged in the X direction. Each trench T1 is formed by extending from the upper surface of the p-type semiconductor layer 124 to the n - Each trench T1 extends in the Y direction. The bottom end of each trench T1 is below the bottom surface of the n-type barrier layer 123c. - The drift layer 123b is located above the lower surface of the drift layer 123b.

[0029] An internal electrode 130 is disposed in each trench T1. Each internal electrode 130 is made of a conductive material such as a metal material or polysilicon. - The lower end of each internal electrode 130 extends to the drift layer 123b. Below the lower surface of the n-type barrier layer 123c,- The internal electrodes 130 in the first region S1a are located above the bottom surface of the p-type drift layer 123b. - Each internal electrode 130 in the second region S1b is adjacent to the p-type drift layer 123b in the X direction. - The drift layer 123b is adjacent to the drift layer 123b having a rectangular shape in the X direction.

[0030] A plurality of trenches T2 are provided in the IGBT region S2. The plurality of trenches T2 are arranged in the X direction. Each trench T2 has n + From the top surface of the emitter layer 126, n - The bottom end of each trench T2 extends to the n-type drift layer 123b. - below the top surface of the n-shaped drift layer 123b - The drift layer 123b is located above the lower surface of the drift layer 123b.

[0031] A gate electrode 140 is disposed in each trench T2. Each gate electrode 140 is made of a conductive material such as a metal material or polysilicon. + From the top surface of the emitter layer 126, n - The lower end of each gate electrode 140 extends to the n-type drift layer 123b. - Each gate electrode 140 is located above the bottom surface of the n-type drift layer 123b. + The p-type emitter layer 126, the p-type semiconductor layer 124, the n-type barrier layer 123c, and the n - The drift layer 123b is adjacent to the drift layer 123b having a rectangular shape in the X direction.

[0032] The upper electrode 150 is made of a conductive material such as a metal material. The upper electrode 150 is provided across the diode region S1 and the IGBT region S2. The upper electrode 150 is disposed on the p-type semiconductor layer 124 in the diode region S1. The upper electrode 150 is disposed on the n-type semiconductor layer 124 in the IGBT region S2. +The upper electrode 150 is disposed on the emitter layer 126 having a shape similar to that of the diode region S1. The upper electrode 150 functions as an anode electrode in the diode region S1, and functions as an emitter electrode in the IGBT region S2. The upper electrode 150 is also electrically connected to each of the internal electrodes 130. That is, the potential of the upper electrode 150 and the potential of the internal electrodes 130 are approximately equal.

[0033] In the diode region S1, each insulating film 161 is disposed between each internal electrode 130 and the upper electrode 150, between each internal electrode 130 and the p-type semiconductor layer 124, and between each internal electrode 130 and the n-type semiconductor portion 123.

[0034] In the IGBT region S2, the insulating films 162 are formed between the gate electrodes 140 and the upper electrodes 150, between the gate electrodes 140 and the n + The gate electrodes 140 are disposed between the p-type emitter layer 126 , between the p-type semiconductor layer 124 , and between the n-type semiconductor portion 123 and each gate electrode 140 .

[0035] Each of the insulating films 161 and 162 is made of an insulating material such as silicon oxide or silicon nitride.

[0036] Next, the effects of the semiconductor device 100 according to this embodiment will be described. FIG. 3(a) is a schematic diagram showing the carrier movement direction in the semiconductor device according to this embodiment, and FIG. 3(b) is a schematic diagram showing the carrier movement direction in the semiconductor device according to the reference example. FIG. 4(a) is a graph showing the results of a simulation of the relationship between the voltage Vak applied between the upper electrode and the lower electrode in the diode region of the semiconductor device according to this embodiment and the semiconductor device according to the reference example, and FIG. 4(b) is a graph showing the results of a simulation of the carrier density of the semiconductor device according to this embodiment and the semiconductor device according to the reference example. In Figures 3(a) and 3(b), holes are indicated by circles with h, and electrons are indicated by circles with e. The horizontal axis of Figure 4(a) is the voltage Vak, and the vertical axis is the reflux current Iak. The horizontal axis of Figure 4(b) is the position in the X direction, and the vertical axis is the carrier density.

[0037] In the semiconductor device 100 according to this embodiment, the n-type barrier layer 123c is not provided in the first region S1a of the diode region S1 as shown in Fig. 3(a). In contrast, in the semiconductor device 900 according to the reference example, the n-type barrier layer 123c is provided in the n-type semiconductor portion 923 in the first region S1a of the diode region S1 as shown in Fig. 3(b).

[0038] When the IGBT region S2 is turned off and the diode region S1 is turned on, a return current Iak flows through the diode region S1. As shown in Fig. 4(a) in the semiconductor device 900 according to the reference example, the return current Iak increases as the voltage Vak applied between the lower electrode 110 and the upper electrode 150 increases. After the voltage Vak reaches a peak voltage Vsn2, the return current Iak increases and the voltage Vak drops sharply. This phenomenon is called "snapback."

[0039] Similarly, in the semiconductor device 100 according to this embodiment, as the voltage Vak applied between the lower electrode 110 and the upper electrode 150 increases, the return current Iak increases. After the voltage Vak reaches the peak voltage Vsn1, the return current Iak increases and the voltage Vak decreases. However, the peak voltage Vsn1 in this embodiment is lower than the peak voltage Vsn2 in the reference example. Also, in this embodiment, a return current Iak larger than that in the reference example can be caused to flow at a voltage Vak lower than that in the reference example. That is, in the semiconductor device 100 according to this embodiment, snapback can be suppressed more effectively than in the semiconductor device 900 according to the reference example.

[0040] In the semiconductor device 900 according to the reference example, as shown in FIG. 3B, the n-type barrier layer 123c is provided in the first region S1a, so that the n-type barrier layer 123c in the first region S1a is not - Holes are less likely to be injected into the n-type drift layer 123b, and the amount of holes discharged from the portion of the lower electrode 110 located in the first region S1a is small. - Therefore, electrons are less likely to be injected into the n-type drift layer 123b in the first region S1a. - The carrier density in the drift layer 123b is low. As a result, the n - The effect of conductivity modulation on the drift layer 123b of the n-type in the first region S1a - This reduces the effect of reducing the electrical resistance of the n-type drift layer 123b. This makes it easier for holes to invade from the first region S1a to the IGBT region S2. This further reduces the amount of holes discharged from the lower electrode 110 to the portion located in the first region S1a, and the amount of holes discharged from the lower electrode 110 to the n-type drift layer 123b in the first region S1a. - The amount of electrons injected into the drift layer 123b of this type is further reduced. This is thought to make it difficult for the return current Iak to flow when the voltage Vak is applied between the lower electrode 110 and the upper electrode 150, causing snapback.

[0041] On the other hand, in the semiconductor device 100 according to this embodiment, as shown in FIG. 3A, the n-type barrier layer 123c is not provided in the first region S1a. Therefore, the n-type barrier layer 123c is not provided in the first region S1a. - Holes are easily injected into the n-type drift layer 123b, and a large amount of holes are discharged from the portion of the lower electrode 110 located in the first region S1a. - Therefore, electrons are easily injected into the n-type drift layer 123b in the first region S1a. - As a result, the carrier density in the n-type drift layer 123b in the first region S1a increases. - The effect of conductivity modulation on the drift layer 123b of the n-type -This increases the effect of reducing the electrical resistance of the n-type drift layer 123b. This makes it difficult for holes to invade from the first region S1a to the IGBT region S2 side, and the holes are easily discharged from the portion of the lower electrode 110 located in the first region S1a. - This further increases the amount of electrons injected into the drift layer 123b having the shape of a junction. As a result, it is believed that the reflux current Iak flows more easily when the voltage Vak is applied between the lower electrode 110 and the upper electrode 150, thereby suppressing snapback.

[0042] Therefore, as shown in Fig. 4(b), the carrier density in the IGBT region S2 in this embodiment is lower than that in the IGBT region S2 in the reference example, and the carrier density in the first region S1a in this embodiment is higher than that in the first region S1a in the reference example. And, as shown in Fig. 4(a), in this embodiment, the peak voltage Vsn1 is lower than the peak voltage Vsn2 in the reference example, and it is considered that a larger reflux current Iak can flow at a lower voltage Vak than in the reference example.

[0043] In this embodiment, an n-type barrier layer 123c is provided in the second region S1b of the diode region S1. Therefore, when the diode region S1 is in an on-state, the n-type barrier layer 123c in the second region S1b is - Therefore, holes are hardly injected into the n-type drift layer 123b in the second region S1b from the lower electrode 110. - Therefore, electrons are less likely to be injected into the n-type drift layer 123b in the second region S1b. - Therefore, the carrier density in the drift layer 123b having the diode region S1 becomes OFF, and the loss during recovery can be reduced.

[0044] As described above, by promoting carrier injection in the first region S1a adjacent to the IGBT region S2 and suppressing carrier injection in the second region S1b separated from the IGBT region S2, a semiconductor device 100 can be provided that suppresses snapback and has small recovery loss.

[0045] In this embodiment, the width L1 of the first region S1a is shorter than the width L2 of the second region S1b. In this manner, by limiting the region that promotes carrier injection to the region near the IGBT region S2, it is possible to appropriately reduce recovery loss while suppressing snapback.

[0046] <Second embodiment> Next, a second embodiment will be described. FIG. 5 is a cross-sectional view showing the semiconductor device according to this embodiment. In the semiconductor device 200 according to the present embodiment, in the first region S1a and the second region S1b in the diode region S1, - The method of making a difference in the amount of carriers injected into the drift layer 123b of the semiconductor device 100 according to the first embodiment is different from that of the semiconductor device 100 according to the first embodiment. In the following description, in principle, only the differences from the first embodiment will be described. The matters other than those described below are the same as those in the first embodiment. The same applies to the other embodiments described below.

[0047] In the semiconductor portion 223 of the semiconductor device 200, the n-type barrier layer 123c is not provided in the second region S1b. That is, the impurity concentration of the portion of the upper layer of the semiconductor portion 223 located in the first region S1a is approximately equal to the impurity concentration of the portion of the upper layer of the semiconductor portion 223 located in the second region S1b.

[0048] In the p-type semiconductor layer 224 in the semiconductor device 200, the impurity concentration of the first portion 224a located in the first region S1a of the diode region S1 is higher than the impurity concentration of the second portion 224b located in the second region S1b. In the present embodiment, the impurity concentration of the first portion 224a is lower than the impurity concentration of the third portion 224c located in the IGBT region S2 in the p-type semiconductor layer 224. However, the magnitude relationship between the impurity concentration of the first portion and the impurity concentration of the third portion is not limited to the above. For example, the upper layer portion of the n-type semiconductor portion may be configured so that the impurity concentration gradually increases or increases stepwise from the boundary between the diode region and the IGBT region toward the center of the diode region. Also, for example, the p-type semiconductor layer may be configured so that the impurity concentration gradually decreases or decreases stepwise from the boundary between the diode region and the IGBT region toward the center of the diode region.

[0049] Next, the effects of this embodiment will be described. Since the impurity concentration of the first portion 224a is high, the n - Holes are easily injected into the n-type drift layer 123b. This makes it possible to suppress snapback. On the other hand, since the impurity concentration of the second portion 224b is low, the n-type ... - Holes are less likely to be injected into the drift layer 123b having the axially-oriented structure, which reduces the recovery loss in the diode region S1.

[0050] As described above, by promoting carrier injection in the first region S1a adjacent to the IGBT region S2 and suppressing carrier injection in the second region S1b separated from the IGBT region S2, a semiconductor device 200 can be provided that suppresses snapback and has small recovery loss.

[0051] <Third embodiment> Next, a third embodiment will be described. FIG. 6 is a cross-sectional view showing the semiconductor device according to this embodiment. FIG. 7(a) shows a first region of the diode region, in which a p-type semiconductor layer and a p +FIG. 7(b) is a cross-sectional view of the p-type contact layer in the second region of the diode region. + 1 is a cross-sectional view along the top surface of a contact layer having a shape similar to that of FIG. In the semiconductor device 300 according to the present embodiment, in the first region S1a and the second region S1b in the diode region S1, - The method of making a difference in the amount of carriers injected into the drift layer 123b of the semiconductor device 100 according to the first embodiment is different from that of the semiconductor device 100 according to the first embodiment.

[0052] 6, the semiconductor portion 323 in the semiconductor device 300 does not have an n-type barrier layer 123c in the second region S1b. That is, the impurity concentration of the portion of the upper layer of the semiconductor portion 323 located in the first region S1a is approximately equal to the impurity concentration of the portion of the upper layer of the semiconductor portion 323 located in the second region S1b.

[0053] The semiconductor device 300 includes a p-type semiconductor layer 124 and a p-type + The contact layer 325 has a shape similar to that of the p + As shown in Fig. 7(a) and Fig. 7(b), the contact layer 325 includes a plurality of extensions 325a. Each extension 325a extends in the X direction. The extensions 325a are spaced apart from each other and arranged in the Y direction. + The contact layer is arranged in a stripe pattern. + The configuration of the contact layer is not limited to the above. For example, each extension portion may extend in another direction, such as the Y direction, instead of the X direction, and multiple extension portions may be arranged in another direction, such as the X direction, instead of the Y direction. + The arrangement pattern of the contact layers need not be striped.

[0054] p + The impurity concentration of the contact layer 325 is higher than the impurity concentration of the p-type semiconductor layer 124. The impurity concentration of the p-type semiconductor layer 124 is not particularly limited, but may be, for example, 1×10 17 cm -3 About that level. +The impurity concentration of the contact layer 325 is not particularly limited, but may be, for example, 1×10 18 cm -3 ~1×10 19 cm -3 The p-type semiconductor layer 124 and the upper electrode 150 are in Schottky contact. + The contact layer 325 and the upper electrode 150 are in ohmic contact with each other.

[0055] In this embodiment, the width L3 in the Y direction of each of the extensions 325a provided in the first region S1a is wider than the width L4 in the Y direction of each of the extensions 325a provided in the second region S1b. + The area of ​​the contact layer 325 in the second region S1b is p + The area of ​​the contact layer 325 is larger than that of the contact layer 325 .

[0056] Next, the effects of this embodiment will be described. In the first region S1a, p + The area per unit area of ​​the contact layer 325 having a shape similar to that of the upper electrode 150 in the second region S1b is p + The area per unit area of ​​the contact layer 325 is larger than that of the upper electrode 150. - Holes are easily injected into the n-type drift layer 123b. This makes it possible to suppress snapback. - Holes are less likely to be injected into the drift layer 123b having the axially-oriented structure, which reduces the recovery loss in the diode region S1.

[0057] As described above, by promoting carrier injection in the first region S1a adjacent to the IGBT region S2 and suppressing carrier injection in the second region S1b separated from the IGBT region S2, a semiconductor device 300 can be provided that suppresses snapback and has small recovery loss.

[0058] In addition, p in the first region + The area per unit area of ​​the contact layer in the shape of p + The method of making the area per unit area of ​​the contact layer larger than that of the first region is not limited to the above. For example, the pitch at which the multiple extensions are provided in the first region is made narrower than the pitch at which the multiple extensions are provided in the second region, thereby increasing the p + The area per unit area of ​​the contact layer in the shape of p + The area per unit area of ​​the contact layer may be larger than that of the contact layer of the shape.

[0059] Although a number of embodiments have been described above, these can be combined with one another. For example, the p-type semiconductor layer 224 in the second embodiment may be applied to the semiconductor device 100 according to the first embodiment and the semiconductor device 300 according to the third embodiment. In addition, the p-type semiconductor layer 224 in the third embodiment may be applied to the semiconductor device 100 according to the first embodiment and the semiconductor device 200 according to the second embodiment. + A contact layer 325 of the same shape may be applied.

[0060] The embodiments include the following aspects.

[0061] (Appendix 1) A semiconductor device having a diode region and an IGBT region, a first electrode provided across the diode region and the IGBT region; a first semiconductor layer of a first conductivity type provided on the first electrode in the diode region; a second semiconductor layer of a second conductivity type provided on the first electrode in the IGBT region; a semiconductor portion of the first conductivity type provided on the first semiconductor layer and the second semiconductor layer, the semiconductor portion having an impurity concentration in a first region of an upper layer portion, the first region being located in the diode region and adjacent to the IGBT region, lower than an impurity concentration in a second region being located in the diode region and separated from the IGBT region; a third semiconductor layer of the second conductivity type provided on the semiconductor portion in the diode region and the IGBT region; a fourth semiconductor layer of the first conductivity type provided on an upper layer of the third semiconductor layer in the IGBT region; a second electrode extending in a direction from the fourth semiconductor layer toward the semiconductor portion in the IGBT region and adjacent to the fourth semiconductor layer, the third semiconductor layer, and the semiconductor portion; a third electrode located on the third semiconductor layer in the diode region and on the fourth semiconductor layer in the IGBT region; insulating films provided between the second electrode and the fourth semiconductor layer, between the second electrode and the third semiconductor layer, between the second electrode and the semiconductor portion, and between the second electrode and the third electrode; A semiconductor device comprising:

[0062] (Appendix 2) The semiconductor portion is a fifth semiconductor layer provided across the diode region and the IGBT region, having an impurity concentration lower than an impurity concentration of the first semiconductor layer, and in contact with the third semiconductor layer in the first region of the diode region; a sixth semiconductor layer provided in an upper layer portion of the fifth semiconductor layer in the second region, having an impurity concentration higher than an impurity concentration of the fifth semiconductor layer, and in contact with the third semiconductor layer; 2. The semiconductor device according to claim 1,

[0063] (Appendix 3) A semiconductor device having a diode region and an IGBT region, a first electrode provided across the diode region and the IGBT region; a first semiconductor layer of a first conductivity type provided on the first electrode in the diode region; a second semiconductor layer of a second conductivity type provided on the first electrode in the IGBT region; a semiconductor portion of the first conductivity type provided on the first semiconductor layer and the second semiconductor layer; a third semiconductor layer of the second conductivity type provided on the semiconductor portion in the diode region and the IGBT region, the third semiconductor layer having a first region located in the diode region and adjacent to the IGBT region and having a higher impurity concentration than a second region located in the diode region and separated from the IGBT region; a fourth semiconductor layer of the first conductivity type provided on an upper layer of the third semiconductor layer in the IGBT region; a second electrode extending in a direction from the fourth semiconductor layer toward the semiconductor portion in the IGBT region and adjacent to the fourth semiconductor layer, the third semiconductor layer, and the semiconductor portion; a third electrode located on the third semiconductor layer in the diode region and on the fourth semiconductor layer in the IGBT region; insulating films provided between the second electrode and the fourth semiconductor layer, between the second electrode and the third semiconductor layer, between the second electrode and the semiconductor portion, and between the second electrode and the third electrode; A semiconductor device comprising:

[0064] (Appendix 4) A semiconductor device having a diode region and an IGBT region, a first electrode provided across the diode region and the IGBT region; a first semiconductor layer of a first conductivity type provided on the first electrode in the diode region; a second semiconductor layer of a second conductivity type provided on the first electrode in the IGBT region; a semiconductor portion of the first conductivity type provided on the first semiconductor layer and the second semiconductor layer; a third semiconductor layer of the second conductivity type provided on the semiconductor portion in the diode region and the IGBT region; a fourth semiconductor layer of the first conductivity type provided on an upper layer portion of the third semiconductor layer in the IGBT region; a fifth semiconductor layer of the second conductivity type provided in an upper layer portion of the third semiconductor layer in the diode region, having an impurity concentration higher than an impurity concentration of the third semiconductor layer, and having an area per unit area in a first region located in the diode region and adjacent to the IGBT region when viewed from above larger than an area per unit area in a second region located in the diode region and separated from the IGBT region; a second electrode extending in a direction from the fourth semiconductor layer toward the semiconductor portion in the IGBT region and adjacent to the fourth semiconductor layer, the third semiconductor layer, and the semiconductor portion; a third electrode located on the third semiconductor layer in the diode region and on the fourth semiconductor layer in the IGBT region; insulating films provided between the second electrode and the fourth semiconductor layer, between the second electrode and the third semiconductor layer, between the second electrode and the semiconductor portion, and between the second electrode and the third electrode; A semiconductor device comprising:

[0065] (Appendix 5) the fifth semiconductor layer includes a plurality of extending portions extending in a first direction when viewed from above and aligned in a second direction intersecting the first direction; 5. The semiconductor device according to claim 4, wherein a width in the second direction of the extension portion located in the first region is greater than a width in the second direction of the extension portion located in the second region.

[0066] (Appendix 6) 6. The semiconductor device according to claim 1, wherein a width of the first region in a direction from the diode region toward the IGBT region is shorter than a width of the second region in a direction from the diode region toward the IGBT region.

[0067] Although the embodiments of the present invention have been described above, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0068] 100, 200, 300, 900: Semiconductor device 110: Lower electrode (1st electrode) 121 :n + Shaped cathode layer (first semiconductor layer) 122 :p + Collector layer (second semiconductor layer) 123, 223, 323, 923: Semiconductor Department 123a :n + Shaped buffer layer 123b :n - Drift layer of the shape (the fifth semiconductor layer in Appendix 2) 123c: n-type barrier layer (sixth semiconductor layer in Appendix 2) 124, 224: p-type semiconductor layer (third semiconductor layer) 126 :n + Shaped emitter layer (fourth semiconductor layer) 130: Internal electrode 140: Gate electrode (second electrode) 150: Upper electrode (3rd electrode) 161, 162: insulating film 224a :1st part 224b :Second part 224c: 3rd part 325 :p + Contact layer (5th semiconductor layer in Appendix 4) 325a: Extension part Iak: Return current S1: Diode region S1a: 1st area S1b: 2nd area S2 :IGBT area T1, T2: Trench Vak: Voltage Vsn1, Vsn2: Peak voltage

Claims

1. A semiconductor device having a diode region and an IGBT region, a first electrode provided across the diode region and the IGBT region; a first semiconductor layer of a first conductivity type provided on the first electrode in the diode region; a second semiconductor layer of a second conductivity type provided on the first electrode in the IGBT region; a semiconductor portion of the first conductivity type provided on the first semiconductor layer and the second semiconductor layer, the semiconductor portion having an impurity concentration in a first region of an upper layer portion that is located in the diode region and adjacent to the IGBT region lower than an impurity concentration in a second region of an upper layer portion that is located in the diode region and separated from the IGBT region, and the impurity concentration in the first region lower than an impurity concentration in a third region of the upper layer portion that is located in the IGBT region; a third semiconductor layer of the second conductivity type provided on the semiconductor portion in the diode region and the IGBT region; a fourth semiconductor layer of the first conductivity type provided on an upper layer portion of the third semiconductor layer in the IGBT region; a second electrode extending in a direction from the fourth semiconductor layer toward the semiconductor portion in the IGBT region and adjacent to the fourth semiconductor layer, the third semiconductor layer, and the semiconductor portion; a third electrode located on the third semiconductor layer in the diode region and on the fourth semiconductor layer in the IGBT region; insulating films provided between the second electrode and the fourth semiconductor layer, between the second electrode and the third semiconductor layer, between the second electrode and the semiconductor portion, and between the second electrode and the third electrode; A semiconductor device comprising:

2. The semiconductor portion is a fifth semiconductor layer provided across the diode region and the IGBT region, having an impurity concentration lower than an impurity concentration of the first semiconductor layer, and in contact with the third semiconductor layer in the first region of the diode region; a sixth semiconductor layer provided in an upper layer portion of the fifth semiconductor layer in the second region and the third region, having an impurity concentration higher than an impurity concentration of the fifth semiconductor layer, and in contact with the third semiconductor layer; The semiconductor device according to claim 1 ,

3. A semiconductor device having a diode region and an IGBT region, a first electrode provided across the diode region and the IGBT region; a first semiconductor layer of a first conductivity type provided on the first electrode in the diode region; a second semiconductor layer of a second conductivity type provided on the first electrode in the IGBT region; a semiconductor portion of the first conductivity type provided on the first semiconductor layer and the second semiconductor layer; a third semiconductor layer of the second conductivity type provided on the semiconductor portion in the diode region and the IGBT region, the first region being located in the diode region and adjacent to the IGBT region and having a higher impurity concentration than a second region being located in the diode region and separated from the IGBT region, the first region and the second region being aligned in a first direction, and extending in a second direction intersecting the first direction; a fourth semiconductor layer of the first conductivity type provided on an upper layer portion of the third semiconductor layer in the IGBT region; a second electrode extending in a direction from the fourth semiconductor layer toward the semiconductor portion in the IGBT region and adjacent to the fourth semiconductor layer, the third semiconductor layer, and the semiconductor portion; a third electrode located on the third semiconductor layer in the diode region and on the fourth semiconductor layer in the IGBT region; insulating films provided between the second electrode and the fourth semiconductor layer, between the second electrode and the third semiconductor layer, between the second electrode and the semiconductor portion, and between the second electrode and the third electrode; A semiconductor device comprising:

4. a length in the second direction of a portion of the third semiconductor layer disposed in the first region is greater than a length in the first direction of a portion of the third semiconductor layer disposed in the first region; The semiconductor device according to claim 3 , wherein a length in the second direction of the portion of the third semiconductor layer disposed in the second region is greater than a length in the first direction of the portion of the third semiconductor layer disposed in the second region.

5. A semiconductor device having a diode region and an IGBT region, a first electrode provided across the diode region and the IGBT region; a first semiconductor layer of a first conductivity type provided on the first electrode in the diode region; a second semiconductor layer of a second conductivity type provided on the first electrode in the IGBT region; a semiconductor portion of the first conductivity type provided on the first semiconductor layer and the second semiconductor layer; a third semiconductor layer of the second conductivity type provided on the semiconductor portion in the diode region and the IGBT region; a fourth semiconductor layer of the first conductivity type provided on an upper layer portion of the third semiconductor layer in the IGBT region; a fifth semiconductor layer of the second conductivity type provided in an upper layer portion of the third semiconductor layer in the diode region, having an impurity concentration higher than an impurity concentration of the third semiconductor layer, and having an area per unit area in a first region located in the diode region and adjacent to the IGBT region when viewed from above larger than an area per unit area in a second region located in the diode region and separated from the IGBT region; a second electrode extending in a direction from the fourth semiconductor layer toward the semiconductor portion in the IGBT region and adjacent to the fourth semiconductor layer, the third semiconductor layer, and the semiconductor portion; a third electrode located on the third semiconductor layer in the diode region and on the fourth semiconductor layer in the IGBT region; a plurality of fourth electrodes extending in a direction from the fifth semiconductor layer toward the semiconductor portion in the diode region, arranged in a first direction, extending in a second direction intersecting the first direction, and adjacent to the fifth semiconductor layer, the third semiconductor layer, and the semiconductor portion; a first insulating film provided between the second electrode and the fourth semiconductor layer, between the second electrode and the third semiconductor layer, between the second electrode and the semiconductor portion, and between the second electrode and the third electrode; second insulating films provided between the fourth electrode and the fifth semiconductor layer, between the fourth electrode and the third semiconductor layer, between the fourth electrode and the semiconductor portion, and between the fourth electrode and the third electrode; Equipped with the fifth semiconductor layer is in contact with the second insulating film at both ends in the first direction; the fifth semiconductor layer includes a plurality of extension portions extending in the first direction when viewed from above and arranged in the second direction; A semiconductor device, wherein the width in the second direction of the extension portion located in the first region is greater than the width in the second direction of the extension portion located in the second region.

6. The semiconductor device according to any one of claims 1 to 5, wherein a width of the first region in a direction from the diode region toward the IGBT region is shorter than a width of the second region in a direction from the diode region toward the IGBT region.

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