Semiconductor device and method for manufacturing the same

Abstract

To provide a semiconductor device capable of suppressing degradation of an electro-static discharge (ESD) protection element, easily achieving a desired withstanding voltage and giving a sufficient ESD resistance, and to provide a method of manufacturing the same.SOLUTION: In a semiconductor device, a high-concentration diffusion layer 103 and a low-concentration diffusion layer 102 are arranged around a drain diffusion layer 106B of an ESD protection element. The high-concentration diffusion layer 103 is separated from a gate electrode 105, and an intermediate-concentration LDD diffusion layer 107B is arranged in a gap between the high-concentration diffusion layer 103 and the gate electrode 105. Heat treatment to the high-concentration diffusion layer 103 and the intermediate-concentration diffusion layer 107B is shortened to suppress variation in characteristics.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device, and more particularly to a structure of a semiconductor device having enhanced breakdown voltage and a method for manufacturing the same. [Background technology]

[0002] Semiconductor integrated circuits are provided with ESD protection elements to protect internal elements from various surges such as electrostatic discharge (ESD) and noise caused by fluctuations in power supply voltage. In particular, the operating range of ESD protection elements such as off-transistors, which are arranged so that their gates are always off, must be set higher than the maximum operating voltage of the semiconductor integrated circuit and lower than the withstand voltage of the internal elements used inside the semiconductor integrated circuit. However, due to miniaturization, the operating range required for ESD protection elements is narrowing, making it difficult to achieve the desired characteristics.

[0003] On the other hand, the protective element must also have high ESD resistance, that is, it must have low resistance and not be destroyed even when a large amount of current flows through it. As an improvement measure, the impurity concentration near the P / N junction on the drain side, which determines the breakdown voltage of the transistor, is lowered, and the impurity concentration near the drain diffusion layer, which has a high impurity concentration, is increased by arranging a double diffusion layer around the drain region including the drain diffusion layer, thereby improving the breakdown voltage and achieving a low on-resistance (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2007-266473 A Summary of the Invention [Problem to be solved by the invention]

[0005] Generally, when a dense diffusion layer is placed near the gate electrode, the electric field becomes large and the breakdown voltage decreases, so in order to increase the breakdown voltage, it is necessary to place the dense diffusion layer away from the gate electrode. In addition, when an overvoltage is applied to a protection element, it enters bipolar operation, and thermal destruction is likely to occur due to electric field concentration at the boundary of the drain diffusion layer. In order to suppress this phenomenon, it is necessary to form the region between the gate electrode and the drain diffusion layer as dense.

[0006] That is, in order to secure the drain breakdown voltage and suppress deterioration of the protection element, it is necessary to separate the high concentration drain diffusion layer from the gate electrode and to make the concentration as high as possible in the entire region therebetween.

[0007] On the other hand, in order to ensure the breakdown voltage, in a transistor in which a multiple diffusion structure is formed so that the concentration gradient in the region leading to the drain diffusion layer in the drain region is gentle, it is necessary to adjust the structure of the diffusion layer so that the breakdown voltage falls within the desired range. However, because the breakdown voltage varies with changes in structure and process, it has been difficult to create an element that can protect the internal elements with a margin.

[0008] Therefore, an object of the present invention is to provide a semiconductor device that suppresses deterioration of an ESD protection element, easily achieves a desired withstand voltage, and has sufficient ESD resistance. [Means for solving the problem]

[0009] In order to solve the above problems, the present invention provides a semiconductor device configured as follows. That is, the semiconductor device includes a semiconductor substrate, a low-concentration diffusion layer of a second conductivity type provided in the semiconductor substrate, a gate electrode provided on a surface of the low-concentration diffusion layer of the second conductivity type with a gate oxide film interposed therebetween, a source diffusion layer of a first conductivity type provided on a surface of the semiconductor substrate located on one side of the gate electrode and a drain diffusion layer of a first conductivity type provided on a surface of the semiconductor substrate located on the other side of the gate electrode and spaced apart from the gate electrode, a drain LDD diffusion layer of a first conductivity type provided on the surface of the semiconductor substrate between the drain diffusion layer and immediately below an end of the gate electrode on the drain diffusion layer side, a high-concentration diffusion layer of a first conductivity type provided from a position closer to the drain diffusion layer than the end of the drain LDD diffusion layer on the source diffusion layer side to include the drain diffusion layer, the high-concentration diffusion layer having an impurity concentration higher than that of the drain LDD diffusion layer and a lower impurity concentration than that of the drain diffusion layer, and a low-concentration diffusion layer of a first conductivity type provided from a surface of the semiconductor substrate below the gate electrode to include the drain LDD diffusion layer, the high-concentration diffusion layer, and the drain diffusion layer therein. Effect of the Invention

[0010] By using the above-mentioned means, the electric field in the vicinity of the gate electrode can be relaxed to enhance the breakdown voltage, and the resistance can be reduced by increasing the concentration in the vicinity of the drain diffusion layer, thereby achieving high ESD resistance.

[0011] Furthermore, by separating the high concentration diffusion layer from the gate electrode and providing the drain LDD diffusion layer, it is possible to suppress variations in the high concentration diffusion layer and also to easily adjust the breakdown voltage by the drain LDD diffusion layer. [Brief description of the drawings]

[0012] [Figure 1] 1 is a schematic cross-sectional view showing an N-type MOS transistor according to a first embodiment of a semiconductor device of the present invention. [Diagram 2] 2A to 2C are schematic cross-sectional views showing a manufacturing process of the semiconductor device according to the first embodiment. [Diagram 3] 2A to 2C are schematic cross-sectional views showing a manufacturing process of the semiconductor device according to the first embodiment. [Figure 4] 2A to 2C are schematic cross-sectional views showing a manufacturing process of the semiconductor device according to the first embodiment. [Diagram 5] 2A to 2C are schematic cross-sectional views showing a manufacturing process of the semiconductor device according to the first embodiment. [Figure 6] 2A to 2C are schematic cross-sectional views showing a manufacturing process of the semiconductor device according to the first embodiment. [Figure 7] 2A to 2C are schematic cross-sectional views showing a manufacturing process of the semiconductor device according to the first embodiment. [Figure 8] 1 is a schematic cross-sectional view showing a first modified example of an N-type MOS transistor according to a first embodiment of the semiconductor device of the present invention. [Figure 9] FIG. 4 is a schematic cross-sectional view showing a second modified example of the N-type MOS transistor according to the first embodiment of the semiconductor device of the present invention. [Figure 10] FIG. 4 is a schematic cross-sectional view showing a third modified example of the N-type MOS transistor according to the first embodiment of the semiconductor device of the present invention. [Figure 11] FIG. 4 is a schematic cross-sectional view showing an N-type MOS transistor according to a second embodiment of a semiconductor device of the present invention. [Figure 12] FIG. 11 is a schematic cross-sectional view showing a P-type MOS transistor according to a third embodiment of a semiconductor device of the present invention. [Figure 13] FIG. 11 is a schematic cross-sectional view showing a modified example of a P-type MOS transistor according to the third embodiment of the semiconductor device of the present invention. [Figure 14] FIG. 11 is a schematic cross-sectional view showing an N-type MOS transistor according to a fourth embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] Hereinafter, the embodiment of the present invention will be described with reference to the drawings. In addition, in the following, when simply referred to as a drain, it refers to a structure including a drain diffusion layer and made of an impurity layer of the same conductivity type as the drain diffusion layer, and when simply referred to as a source, it refers to a structure including a source diffusion layer and made of an impurity layer of the same conductivity type as the source diffusion layer. <First embodiment> FIG. 1 is a schematic cross-sectional view showing an N-type MOS transistor 10 according to a first embodiment of a semiconductor device of the present invention.

[0014] The N-type MOS transistor 10 includes a semiconductor substrate 100, a low concentration diffusion layer 101 of a second conductivity type (P type in this embodiment) disposed from the surface of the semiconductor substrate 100 to the inside, a gate electrode 105 disposed on the surface of the semiconductor substrate 100 via a gate oxide film 104, a source diffusion layer 106A of a first conductivity type (N type in this embodiment) disposed on the surface of the semiconductor substrate 100 on one side of the gate electrode 105, a drain diffusion layer 106B of the first conductivity type disposed on the surface of the semiconductor substrate 100 on the other side of the gate electrode 105 at a distance from the gate electrode 105, and a drain diffusion layer 106B of the first conductivity type disposed on the surface of the semiconductor substrate 100 on the other side of the gate electrode 105 at a distance from the gate electrode 105. The drain LDD diffusion layer 107B is a first conductive type drain LDD diffusion layer 107B disposed between the drain LDD diffusion layer 107B and the gate electrode 105, a first conductive type high concentration diffusion layer 103 provided from a position farther toward the drain side than the source side end of the drain LDD diffusion layer 107B with the drain diffusion layer 106B included therein and provided vertically from the surface of the semiconductor substrate 100 to a position deeper than the bottom of the drain diffusion layer 106B, and a first conductive type low concentration diffusion layer 102 provided from the surface of the semiconductor substrate 100 below the gate electrode 105 with the drain LDD diffusion layer 107B, the high concentration diffusion layer 103, and the drain diffusion layer 106B included therein. The impurity concentration of the drain LDD diffusion layer 107B is higher than that of the first conductive type low concentration diffusion layer 102 and lower than that of the first conductive type high concentration diffusion layer 103, so it can also be called a medium concentration.

[0015] Furthermore, in the N-type MOS transistor 10, a source LDD diffusion layer 107A is disposed between the other end of the gate electrode 105, which is the end on the source diffusion layer side, and the source diffusion layer 106A. For this reason, the source diffusion layer 106A is disposed apart from the other end of the gate electrode 105. A channel is induced in a region near the surface of the semiconductor substrate of the second conductive type low concentration diffusion layer 101 below the gate electrode 105, between the source LDD diffusion layer 107A and the drain LDD diffusion layer 107B. It is also possible not to dispose the source LDD diffusion layer 107A in contact with the source diffusion layer 106A, and the case where the source LDD diffusion layer 107A is not disposed will be described later as a modified example.

[0016] When the semiconductor substrate 100 and the low-concentration diffusion layer 101 have the same conductivity type, they can be regarded as the same. In other words, the semiconductor substrate 100 itself can be regarded as the low-concentration diffusion layer 101. This is the case.

[0017] The symbols N--, N-, N+, N++ and P--, P-, P+, P++ used in the figure represent the relative concentrations of impurities diffused in a certain region. That is, the concentration of N-type impurities increases in the order of N--, N-, N+, N++, and the concentration of P-type impurities increases in the order of P--, P-, P+, P++.

[0018] The above structure makes it possible to gradually create a concentration gradient from the channel to the drain diffusion layer, making it possible to make the impurity concentration lower near the channel and higher near the drain diffusion layer than in the conventional technology. This makes it possible to relax the electric field near the channel, strengthen the breakdown voltage, suppress degradation due to hot carriers, and further reduce the resistance near the drain diffusion layer to achieve high ESD resistance.

[0019] Next, a description will be given of a method for manufacturing the N-type MOS transistor 10 shown in Fig. 1. Fig. 2 to Fig. 7 are schematic cross-sectional views showing the manufacturing process of the N-type MOS transistor 10. 2, a P-type region 101 is formed by ion-implanting a P-type impurity into a semiconductor substrate 100. The P-type region 101 can also be formed by epitaxial growth.

[0020] 3, a resist film 109A is applied, and using it as a mask, N-type impurities are ion-implanted. After the resist film 109A is peeled off, the N-type low concentration diffusion layer 102 is formed by thermal diffusion.

[0021] Next, as shown in FIG. 4, a resist film 109B is applied so as to open the region inside the N-type low concentration diffusion layer 102, and using this as a mask, N-type impurity ions are implanted to form the N-type high concentration diffusion layer 103.

[0022] Since the P-type low-concentration diffusion layer 101 and the N-type low-concentration diffusion layer 102 are mainly used as wells, the impurities contained therein are diffused over a wide area and the concentration is low. In contrast, the N-type high-concentration diffusion layer 103 does not require high-temperature and long-term heat treatment for well diffusion, so it is possible to form a uniform diffusion layer with little variation due to heat treatment. As a result, as shown in Figure 1, the withstand voltage of the MOS transistor can be greatly changed by the distance between the N-type high-concentration diffusion layer 103 and the channel and the distance from the end of the N-type high-concentration diffusion layer 103 to the contact in the drain diffusion layer 106B. Therefore, using the N-type high-concentration diffusion layer 103 with little variation in structure is particularly effective when fabricating an off transistor that can be used when there is a small margin of withstand voltage with internal elements.

[0023] Next, after forming a gate oxide film 104 as shown in Fig. 5, a gate electrode 105 is formed as shown in Fig. 6. The gate electrode 105 generally contains polycrystalline silicon as a main component. Subsequently, as shown in FIG. 7, an N-type source diffusion layer 106A and a drain diffusion layer 106B are formed by ion-implanting an N-type impurity using a resist film 109C having openings in necessary portions.

[0024] 1, as shown there, N-type impurities are ion-implanted using the gate electrode 105 as a mask to form the N-type source LDD diffusion layer 107A and drain LDD diffusion layer 107B. The source LDD diffusion layer 107A and drain LDD diffusion layer 107B may be formed continuously from both ends of the gate electrode 105 to the surfaces of the source diffusion layer 106A and drain diffusion layer 106B. This is because the impurity concentrations of the source LDD diffusion layer 107A and drain LDD diffusion layer 107B are higher than the impurity concentration of the N-type low concentration diffusion layer 102, but are higher than the impurity concentration of the N-type high concentration diffusion layer 103 and the N-type source diffusion layer 106A and drain diffusion layer 106B. This is because the impurity concentration of the N-type source LDD diffusion layer 107A and the drain LDD diffusion layer 107B is lower than that of the N-type source LDD diffusion layer 107A and the drain LDD diffusion layer 107B. Since the formation of the N-type source LDD diffusion layer 107A and the drain LDD diffusion layer 107B is performed near the end of the wafer manufacturing process, the heat treatment applied is small, and the variation in characteristics caused by thermal diffusion is small. Therefore, it is possible to easily adjust the element breakdown voltage by the impurity concentration of these two layers.

[0025] Although not shown in the drawings, contacts are formed through the interlayer insulating film provided on the gate electrode 105, the source diffusion layer 106A, and the drain diffusion layer 106B, and metal wiring and a passivation film are formed to complete the semiconductor device.

[0026] 8 is a schematic cross-sectional view showing an N-type MOS transistor 20 which is a first modification of the N-type MOS transistor 10 according to the first embodiment of the semiconductor device of the present invention. The N-type MOS transistor 20 differs from the N-type MOS transistor 10 in that a P-type medium concentration region 108 is provided which covers the source diffusion layer 106A and the source LDD diffusion layer 107A and reaches the channel under the gate electrode 105.

[0027] By providing the P-type medium concentration region 108, the impurity concentration of the P-type region in contact with the source diffusion layer 106A and the source LDD diffusion layer 107A is made higher than that of the P-type low concentration diffusion layer 101, thereby making it possible to reduce the leakage current flowing into the source diffusion layer 106A and the source LDD diffusion layer 107A. Furthermore, since the P-type medium concentration region 108 is provided only on the source side, the impurity distribution on the drain side does not change. Therefore, the N-type MOS transistor 20 can maintain the same ESD resistance as the N-type MOS transistor 10 according to the first embodiment.

[0028] FIG. 9 is a schematic cross-sectional view showing an N-type MOS transistor 30 which is a second modification of the N-type MOS transistor 10 according to the first embodiment of the semiconductor device of the present invention. The source LDD diffusion layer 107A, which is provided in the region from the source diffusion layer 106A to just below the gate electrode 105 in the N-type MOS transistor 10, is not provided in the N-type MOS transistor 30. Furthermore, the source diffusion layer 106A is provided in contact with just below the end of the gate electrode 105. In the case where the electric field strength is not significantly increased in the vicinity of the source diffusion layer 106A, the source LDD diffusion layer 107A can be omitted and the source diffusion layer 106A can be disposed just below the end of the gate electrode 105. This makes it possible to reduce the size of the N-type MOS transistor 30 in the direction along the channel.

[0029] 10 is a schematic cross-sectional view showing an N-type MOS transistor 40 which is a third modification of the N-type MOS transistor 10 according to the first embodiment of the semiconductor device of the present invention. The N-type MOS transistor 40 differs from the N-type MOS transistor 10 in that the source LDD diffusion layer 107A provided in the region extending from the source diffusion layer 106A to directly below the gate electrode 105 is not present, and a P-type medium concentration region 108 is provided covering the source diffusion layer 106A to the channel below the gate electrode 105.

[0030] In the N-type MOS transistor 40, the P-type medium concentration region 108 is provided, so that it is possible to reduce the leakage current flowing into the source diffusion layer 106A, similarly to the N-type MOS transistor 20 of the first modification. Furthermore, since there is no source LDD diffusion layer 107A, the source diffusion layer 106A can be disposed directly under the end of the gate electrode 105, so that the size of the N-type MOS transistor 40 in the direction along the channel can be reduced. <Second embodiment> FIG. 11 is a schematic cross-sectional view showing an N-type MOS transistor 50 according to a second embodiment of the semiconductor device of the present invention.

[0031] The N-type MOS transistor 50 has the same and symmetrical drain and source structures. That is, in the N-type MOS transistor 10 according to the first embodiment, the source and drain structures are not the same and are asymmetric, but the N-type MOS transistor 50 is configured by making the structure of the source surrounding the source diffusion layer 106A equal to the structure of the drain.

[0032] Specifically, the N-type MOS transistor 50 includes a semiconductor substrate 100, a low concentration diffusion layer 101 of a second conductivity type (P type in this embodiment) disposed from the surface to the inside of the semiconductor substrate 100, a gate electrode 105 disposed on the surface of the semiconductor substrate 100 via a gate oxide film 104, a source diffusion layer 106A of a first conductivity type (N type in this embodiment) disposed on the surface of the semiconductor substrate 100 on one side of the gate electrode 105 at a distance from the gate electrode 105, and a source diffusion layer 106B of a first conductivity type (N type in this embodiment) disposed on the surface of the semiconductor substrate 100 on one side of the gate electrode 105 at a distance from the gate electrode 105. A first conductive type drain diffusion layer 106B is disposed on the surface of the gate electrode 100 at a distance from the gate electrode 105, a first conductive type drain LDD diffusion layer 107B is disposed between the drain diffusion layer 106B side, which is one end of the gate electrode 105, and the drain diffusion layer 106B, and a first conductive type source LDD diffusion layer 107A is disposed between the source diffusion layer 106A side, which is the other end of the gate electrode 105, and the source diffusion layer 106A, a first conductive type high concentration diffusion layer 103B provided from a position farther toward the drain side than the diffusion layer 107B to the drain diffusion layer 106B, and vertically provided from the surface of the semiconductor substrate 100 to a position deeper than the bottom of the drain diffusion layer 106B; and a first conductive type high concentration diffusion layer 103B provided from a position farther toward the source side than the source LDD diffusion layer 107A to the source diffusion layer 106A, and vertically provided from the surface of the semiconductor substrate 100 to a position deeper than the bottom of the source diffusion layer 106A, The semiconductor substrate 100 includes a first conductivity type high-concentration diffusion layer 103A, a first conductivity type low-concentration diffusion layer 102B which is disposed from the surface of the semiconductor substrate 100 below the gate electrode 105 and includes therein a drain LDD diffusion layer 107B, a high-concentration diffusion layer 103B, and a drain diffusion layer 106B, and a first conductivity type low-concentration diffusion layer 102A which is disposed from the surface of the semiconductor substrate 100 below the gate electrode 105 and includes therein a source LDD diffusion layer 107A, a high-concentration diffusion layer 103A, and a source diffusion layer 106A.

[0033] Since the N-type MOS transistor 50 has the same drain and source structures and is symmetrical, it can be used even if the source and drain are interchanged. <Third embodiment> 12 is a schematic cross-sectional view showing a P-type MOS transistor 60 according to a third embodiment of the semiconductor device of the present invention. The P-type MOS transistor 60 is obtained by replacing the conductivity type of all regions in the N-type MOS transistor 10 according to the first embodiment with the opposite conductivity type. That is, in the N-type MOS transistor 10, the P-type regions are replaced with N-type regions, and the N-type regions are replaced with P-type regions.

[0034] The P-type MOS transistor 60 includes a semiconductor substrate 100, a low concentration diffusion layer 201 of a second conductivity type (N type in this embodiment) disposed from the surface of the semiconductor substrate 100 to the inside, a gate electrode 105 disposed on the surface of the semiconductor substrate 100 via a gate oxide film 104, a source diffusion layer 206A of a first conductivity type (P type in this embodiment) disposed on the surface of the semiconductor substrate 100 on one side of the gate electrode 105, and a second source diffusion layer 206B of a first conductivity type (P type in this embodiment) disposed on the surface of the semiconductor substrate 100 on the other side of the gate electrode 105 at a distance from the gate electrode 105. a drain diffusion layer 206B of a first conductivity type; a drain LDD diffusion layer 207B of a first conductivity type disposed between an end of the gate electrode 105 on the drain diffusion layer 206B side and the drain diffusion layer 206B; a high-concentration diffusion layer 203 of a first conductivity type disposed from a position farther from the drain LDD diffusion layer 207B toward the source side with respect to the gate electrode 105 to the drain diffusion layer 206B and disposed vertically from the surface of the semiconductor substrate 100 to a position deeper than the bottom of the drain diffusion layer 206B; The gate electrode 105 is configured with a drain LDD diffusion layer 207B, a high concentration diffusion layer 203, and a first conductivity type low concentration diffusion layer 202 including the drain diffusion layer 206B therein, from the surface of the semiconductor substrate 100 below the electrode 105. Furthermore, a source LDD diffusion layer 207A is disposed between the gate electrode 105 and the source diffusion layer 206A, directly below the end on the source diffusion layer side, which is the other end of the gate electrode 105.

[0035] The P-type MOS transistor 60 can be easily used in combination with the N-type MOS transistor 10 or the like, with the higher power supply voltage, such as VDD, being the voltage applied to the source.

[0036] 13 is a schematic cross-sectional view showing a P-type MOS transistor 70 which is a modification of the P-type MOS transistor 60 according to the third embodiment of the semiconductor device of the present invention. The P-type MOS transistor 70 differs from the P-type MOS transistor 60 in that a P-type medium concentration region 208 is further provided to cover the source diffusion layer 206A and the source LDD diffusion layer 207A and reach the channel under the gate electrode 105.

[0037] The features of the P-type MOS transistor 70 compared to the P-type MOS transistor 60 shown in FIG. 12 are similar to the features of the N-type MOS transistor 20 compared to the N-type MOS transistor 10 shown in FIG. 1, and it is possible to reduce leakage current while maintaining ESD resistance. <Fourth embodiment> FIG. 14 is a schematic cross-sectional view showing an N-type MOS transistor 80 according to a fourth embodiment of the semiconductor device of the present invention.

[0038] The N-type MOS transistor 80 differs from the N-type MOS transistor 20 described as the first modification of the first embodiment in that the N-type MOS transistor 80 has a field oxide film 110 thicker than the gate oxide film 104 on the surface of the semiconductor substrate 100 from the middle of the channel to the drain diffusion layer 106B. On the other hand, the first conductivity type source LDD diffusion layer 107A and the second conductivity type (here, P type) medium concentration region 108 provided around the first conductivity type (here, N type) source diffusion layer 106A, the first conductivity type low concentration diffusion layer 102 provided around the drain diffusion layer 106B, the first conductivity type high concentration diffusion layer 103, and the first conductivity type drain LDD diffusion layer 107B are essentially the same.

[0039] The gate electrode 105 is provided not only on the gate oxide film 104 but also extending onto the field oxide film 110. As a result, the end of the gate electrode 105 on the drain diffusion layer side and the end of the drain LDD diffusion layer 107B on the source diffusion layer side do not need to be in contact with each other in a plan view perpendicular to the surface of the semiconductor substrate. In addition, with respect to the first conductivity type low concentration diffusion layer 102, the boundary surface on the source diffusion layer side on the surface of the semiconductor substrate may be located under the field oxide film 110 or may be located under the gate oxide film 104.

[0040] In the structure of the N-type MOS transistor 80, the field oxide film 110 is present between the gate electrode 105 and a plurality of first conductivity type diffusion layers provided around the drain diffusion layer 106B, so that the withstand voltage between the gate and the drain can be improved, and in particular, the withstand voltage when the N-type MOS transistor 80 is off is improved.

[0041] The N-type MOS transistor 80 has a source LDD diffusion layer 107A and a second conductivity type medium concentration region 108, but a structure not having either or both of these can also be easily implemented in the same manner as described in the first embodiment above.

[0042] It is also easy to configure a P-type MOS transistor in which the conductivity types of all of the diffusion layers containing impurities are interchanged with respect to the N-type MOS transistor 80. [Explanation of symbols]

[0043] 100 Semiconductor substrate 101 P-type low concentration diffusion layer 102, 102A, 102B N-type low concentration diffusion layer 103, 103A, 103B N-type high concentration diffusion layer 104 Gate oxide 105 Gate electrode 106A N-type source diffusion layer 106B N-type drain diffusion layer 107A, 107B N-type LDD diffusion layer 108 P-type medium concentration region 109A, 109B, 109C Resist film 201 N-type low concentration diffusion layer 202 P-type low concentration diffusion layer 203 P-type high concentration diffusion layer 206A P-type source diffusion layer 206B P-type drain diffusion layer 207A, 207B P-type LDD diffusion layer 208 N-type medium concentration region

Claims

1. A semiconductor substrate; a second conductivity type lightly doped diffusion layer provided in the semiconductor substrate; a gate electrode provided on a surface of the second conductive type low concentration diffusion layer via a gate oxide film; a first conductive type source diffusion layer provided on a surface of the semiconductor substrate located on one side of the gate electrode, and a first conductive type drain diffusion layer provided on a surface of the semiconductor substrate located on the other side of the gate electrode, the first conductive type being spaced apart from the gate electrode; a drain LDD diffusion layer of a first conductivity type provided on a surface of the semiconductor substrate between the drain diffusion layer and an end of the gate electrode on the drain diffusion layer side; a first conductivity type high concentration diffusion layer that is in contact with only a side surface of the drain LDD diffusion layer, that is provided to include the drain diffusion layer from a position closer to the drain diffusion layer than an end of the drain LDD diffusion layer on the source diffusion layer side, and that has an impurity concentration higher than that of the drain LDD diffusion layer and a lower impurity concentration than that of the drain diffusion layer; a first conductivity type lightly doped diffusion layer having an impurity concentration lower than that of the drain LDD diffusion layer, the lightly doped diffusion layer being provided from a surface of the semiconductor substrate below the gate electrode to include the drain LDD diffusion layer, the heavily doped diffusion layer, and the drain diffusion layer therein; a first conductive type source LDD diffusion layer provided on a surface of the semiconductor substrate from directly under an end of the gate electrode on the source diffusion layer side to the source diffusion layer; A semiconductor device having the above structure.

2. A semiconductor device as described in claim 1, further comprising a medium concentration region of a second conductivity type covering the source diffusion layer and the source LDD diffusion layer and reaching a channel under the gate electrode.

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