Semiconductor device manufacturing method

Abstract

To provide a manufacturing method of a semiconductor device based on a newly discovered gettering phenomenon.SOLUTION: A manufacturing method of a semiconductor device includes a step (S10) of injecting light ions into a semiconductor substrate, and a step (S20) of executing first heat processing (S21) for the semiconductor substrate after ion implantation, and executing second heat processing (S22) for the semiconductor substrate at temperature higher than that of the first heat processing after the first heat processing. The ion implantation, the first heat processing, and the second heat processing are performed before forming the semiconductor device on the semiconductor substrate.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a method for manufacturing a semiconductor device and a semiconductor substrate. [Background technology]

[0002] Conventionally, a method for manufacturing a photoelectric conversion device is known in which a photoelectric conversion section is first formed on the first surface side of a silicon substrate, and then a light element such as helium ions is ion-implanted from the second surface side to form a gettering region for capturing metal impurities that should not be mixed into the photoelectric conversion section. In this method, a heat treatment for capturing the metal impurities in the gettering region by diffusion is performed after the ion implantation (for example, see Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2019-29583 A Summary of the Invention [Problem to be solved by the invention]

[0004] The present inventors have studied the above-mentioned method for manufacturing a photoelectric conversion device and have come to recognize the following problems. The above-mentioned gettering region is formed by ion implantation, and the subsequent heat treatment does not contribute to the formation of the gettering region. The gettering region is formed in the projected range of the implanted ions. Therefore, the gettering region tends to be very thin in the depth direction of the substrate. The thinner the gettering region, the higher the possibility that metal impurities will slip through the gettering region. In addition, in order to prevent deterioration or damage to the photoelectric conversion section or other semiconductor elements or wiring layers already formed on the substrate, the heat treatment conditions are limited to low temperature and short time. If gettering is insufficient, the metal impurities that have entered the semiconductor element region will remain there and may adversely affect the operation of the element. For example, in the photoelectric conversion section, the metal impurities generate a leak current, which may cause white scratches in the photoelectric conversion section. In order to improve the performance of a semiconductor device, it is desirable to improve the gettering ability.

[0005] An exemplary object of an embodiment of the present invention is to provide a method for manufacturing a semiconductor device based on the newly discovered gettering phenomenon. [Means for solving the problem]

[0006] A method for manufacturing a semiconductor device according to an embodiment of the present invention includes the steps of: implanting light ions into a semiconductor substrate; subjecting the semiconductor substrate to a first heat treatment after the ion implantation; and subjecting the semiconductor substrate to a second heat treatment at a temperature higher than that of the first heat treatment after the first heat treatment. The ion implantation, the first heat treatment, and the second heat treatment are performed before forming a semiconductor element on the semiconductor substrate.

[0007] Another aspect of the present invention is a method for manufacturing a semiconductor device. The method includes the steps of implanting light ions into a semiconductor substrate and, after the ion implantation, subjecting the semiconductor substrate to a heat treatment so as to form a defect density distribution in the depth direction of the semiconductor substrate. The defect density distribution has a low defect density layer at or shallower than the projected range of the implanted ions, and has a high defect density layer having a higher lattice defect density than the low defect density layer on the first main surface side, the second main surface side, or both sides of the low defect density layer. The ion implantation and heat treatment are performed before forming semiconductor elements in the semiconductor substrate.

[0008] Yet another embodiment of the present invention is a semiconductor substrate having a defect density distribution in a depth direction, the semiconductor substrate including a low defect density layer, a first high defect density layer including a first main surface of the semiconductor substrate, adjacent to the low defect density layer in the depth direction, and having a higher lattice defect density than the low defect density layer, and a second high defect density layer including a second main surface of the semiconductor substrate, adjacent to the low defect density layer in the depth direction, and having a higher lattice defect density than the low defect density layer.

[0009] Any combination of the above components or mutual substitution of the components or expressions of the present invention between methods, devices, systems, etc. are also valid as aspects of the present invention. Effect of the Invention

[0010] According to the present invention, it is possible to provide a method for manufacturing a semiconductor device based on the newly discovered gettering phenomenon. [Brief description of the drawings]

[0011] [Figure 1] 2 is a flowchart showing a method for manufacturing a semiconductor substrate according to an embodiment. [Diagram 2] 1A to 1C are cross-sectional views each showing a schematic diagram of an ion implantation step into a semiconductor substrate. [Diagram 3] FIG. 3(a) is a cross-sectional view showing a semiconductor substrate subjected to ion implantation and heat treatment according to the embodiment, and FIG. 3(b) is a cross-sectional view showing a semiconductor substrate according to a comparative example. [Figure 4] FIG. 4(a) is a schematic diagram showing processing for observing the defect density distribution in the depth direction formed in a semiconductor substrate, and FIG. 4(b) shows an optical microscope photograph obtained by observing the processed semiconductor substrate. [Diagram 5] 3A to 3C are diagrams illustrating microscopic changes in a semiconductor substrate at each stage of a heat treatment process according to an embodiment. [Figure 6] 1 is a flowchart showing a method for manufacturing a semiconductor device according to an embodiment. [Figure 7] 1 is a cross-sectional view illustrating a semiconductor device according to an embodiment of the present invention. [Figure 8] 4 is a graph showing the analysis results of a semiconductor substrate according to an embodiment, by secondary ion mass spectrometry (SIMS). [Figure 9] 9(a) to 9(c) are schematic diagrams showing a method for manufacturing a semiconductor device according to the embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] Hereinafter, the embodiments for carrying out the present invention will be described in detail. Note that the configurations described below are merely examples and do not limit the scope of the present invention in any way. In addition, in the description of the drawings, the same elements are given the same reference numerals, and duplicated descriptions are omitted as appropriate. In each cross-sectional view referred to in the following description, the thicknesses and sizes of the semiconductor substrate and other layers are for the convenience of explanation, and do not necessarily indicate the actual dimensions or ratios.

[0013] 1 is a flowchart showing a method for manufacturing a semiconductor substrate according to an embodiment. First, a semiconductor substrate is prepared, ions are implanted into the semiconductor substrate (S10), and then the semiconductor substrate is subjected to a heat treatment (S20). The ion implantation and heat treatment are performed before semiconductor elements are formed in the semiconductor substrate.

[0014] As will be described in detail later, a defect density distribution (e.g., a change in density of planar defects such as stacking faults in the depth direction) is formed in the ion-implanted semiconductor substrate through heat treatment. This defect density distribution has a low-defect-density layer in and near the projected range of the implanted ions (or at a depth position shallower than the projected range of the implanted ions), and also has a high-defect-density layer having a higher lattice defect density than the low-defect-density layer on the first main surface side, the second main surface side, or both sides of the low-defect-density layer.

[0015] As is known, a semiconductor substrate immediately after ion implantation has a region near the projected range of the implanted ions that has a higher lattice defect density (i.e., a density of point defects (so-called implanted defects) caused by ion implantation) than other regions (i.e., regions shallower than the projected range and regions deeper than the projected range). In the depth-direction distribution of the lattice defect density, the peak of the lattice defect density is formed at a position slightly shallower than the projected range of the implanted ions (i.e., close to the main surface of the substrate irradiated with ions). For example, the peak of the lattice defect density is located approximately 0.5 μm shallower than the projected range of the implanted ions when the implantation energy is 2 MeV, approximately 1 μm shallower when the implantation energy is 4 MeV, and approximately 3 μm shallower when the implantation energy is 8 MeV.

[0016] However, the inventors have discovered a new phenomenon that was not known until now: by subjecting the semiconductor substrate to a heat treatment, a low defect density layer is formed in the vicinity of the projected range of the implanted ions (or at a depth position shallower than that), while a high defect density layer is formed in other regions. The embodiments described below are based on this groundbreaking discovery.

[0017] The semiconductor substrate prepared initially is, for example, a p-type silicon (Si) wafer produced by the Czochralski (CZ) method. CZ-Si wafers typically contain a trace amount of oxygen (e.g., about 30 ppma).

[0018] The semiconductor element formed on the semiconductor substrate is not particularly limited, but may be, for example, a photoelectric conversion element such as a silicon photodiode. In this case, the semiconductor device finally formed from the semiconductor substrate is, for example, a photoelectric conversion device such as a Si-CMOS image sensor.

[0019] 2 is a cross-sectional view that typically illustrates the step (S10) of implanting ions into the semiconductor substrate 10. In the ion implantation step, light ions including hydrogen ions are implanted into the semiconductor substrate 10. For example, the semiconductor substrate 10 is irradiated with an ion beam B that has been accelerated to high energy by an accelerator such as a cyclotron.

[0020] In this embodiment, the ion beam B is a hydrogen ion beam, and the hydrogen ions are, for example, protons. The light ions implanted into the semiconductor substrate 10 consist only of hydrogen ions. The implantation energy of the hydrogen ions is selected from a range of, for example, more than 0.4 MeV and less than 10.5 MeV. The implantation energy of the hydrogen ions may preferably be, for example, less than 4.6 MeV, and more preferably, less than 2 MeV. The implantation dose may be, for example, 1×10 11 cm -2 More than 1×10 15 cm -2 It is selected from the following range:

[0021] The ion beam B is irradiated from the first main surface 10a of the semiconductor substrate 10, and forms an implanted ion containing region 12 in a projected range of the hydrogen ions according to the implantation energy and in a depth range nearby the projected range. The incident hydrogen ions only pass through a first region 14 extending from the first main surface 10a to the implanted ion containing region 12 in the depth direction, but do not reach a second region 16 extending from the implanted ion containing region 12 to the second main surface 10b in the depth direction. Thus, the first region 14 and the second region 16 do not substantially contain hydrogen ions. The ion beam B may be irradiated to the semiconductor substrate 10 from the second main surface 10b.

[0022] Since lattice defects are formed in the implanted ion containing region 12 , the lattice defect density in the implanted ion containing region 12 becomes higher than that in the first region 14 and the second region 16 .

[0023] In the ion implantation process, lattice defects are formed in the implanted ion containing region 12, and the semiconductor substrate 10 may be heated by the thermal energy imparted to the semiconductor substrate 10 by the beam irradiation. Heating has the effect of repairing lattice defects, leading to a reduction in defect density. Therefore, in order to prevent an excessive increase in temperature of the semiconductor substrate 10, the temperature of the semiconductor substrate 10 may be adjusted (e.g., cooled) in the ion implantation process. The ion implantation process may include irradiating the semiconductor substrate 10 with the ion beam B while cooling the semiconductor substrate 10 so that the temperature of the semiconductor substrate 10 is maintained at, for example, 300° C. or less.

[0024] If necessary, a mask for forming a pattern on the cross section of the ion beam B may be placed above the first main surface 10a of the semiconductor substrate 10, and the implanted ion containing region 12 may be formed in a pattern corresponding to the mask pattern. Also, an absorber (for example, a metal foil such as aluminum foil or a metal plate) for adjusting the implantation energy may be placed above the first main surface 10a of the semiconductor substrate 10.

[0025] In the ion implantation step shown in FIG. 2, the first region 14 and the second region 16 not containing hydrogen ions are formed on both sides of the implanted ion containing region 12, but this is merely an example. Since the depth of the implanted ion containing region 12 is determined according to the implantation energy, the depth of the implanted ion containing region 12 may be controlled by controlling the implantation energy. By reducing the implantation energy, the implanted ion containing region 12 can be brought closer to the first main surface 10a, and the implanted ion containing region 12 can be formed so as to include the first main surface 10a. In this case, the first region 14 is eliminated. Conversely, by increasing the implantation energy, the implanted ion containing region 12 can be formed so as to include the second main surface 10b, and the second region 16 can be eliminated.

[0026] Also, multiple ion implantations with different implantation energies may be performed on the semiconductor substrate 10. For example, ions may be implanted to a first depth in the semiconductor substrate 10 with a first energy, and then to a second depth deeper than the first depth with a second energy higher than the first energy. In this manner, multiple implanted ion containing regions 12 may be formed in the semiconductor substrate 10. The multiple implanted ion containing regions 12 may be separated in the depth direction. Alternatively, the multiple implanted ion containing regions 12 may be continuous in the depth direction to form an implanted ion containing region 12 that is thicker than the implanted ion containing region 12 formed by a single ion implantation.

[0027] 1, the ion implantation process (S10) is followed by a heat treatment process (S20). The ion-implanted semiconductor substrate 10 is subjected to a first heat treatment (S21), a second heat treatment (S22), and a third heat treatment (S23) in this order. The temperature of the semiconductor substrate 10 is gradually or incrementally increased as the ion implantation process (S10), the first heat treatment (S21), the second heat treatment (S22), and the third heat treatment (S23) proceed.

[0028] The first heat treatment (S21) includes heating the semiconductor substrate 10 to a first treatment temperature higher than that of the ion implantation process for a first treatment time. The first treatment temperature is, for example, in the range of 300° C. to 450° C., and preferably, in the range of 400° C. to 450° C. The first treatment time is, for example, in the range of 1 hour to 24 hours.

[0029] The second heat treatment (S22) includes heating the semiconductor substrate 10 to a second treatment temperature higher than that of the first heat treatment for a second treatment time. The second treatment temperature is, for example, in the range of 450° C. to 800° C., and preferably, for example, in the range of 600° C. to 750° C. The second treatment time is, for example, in the range of 1 hour to 24 hours.

[0030] The third heat treatment (S23) includes heating the semiconductor substrate 10 to a third treatment temperature higher than that of the second heat treatment for a third treatment time. The third treatment temperature is, for example, in the range of 800° C. to 1200° C., and preferably, for example, in the range of 950° C. to 1200° C. The third treatment time is, for example, in the range of 1 hour to 24 hours.

[0031] It is efficient to perform the first heat treatment, the second heat treatment, and the third heat treatment consecutively, but an interval for interrupting heating may be set between the first heat treatment and the second heat treatment, or between the second heat treatment and the third heat treatment.

[0032] These heat treatments may be performed on the semiconductor substrate 10 in any atmosphere, such as an air atmosphere, a vacuum atmosphere, or an inert gas atmosphere.

[0033] FIG. 3(a) is a cross-sectional view showing a semiconductor substrate 10 that has been subjected to ion implantation (S10) and heat treatment (S20) according to the embodiment, and FIG. 3(b) is a cross-sectional view showing a semiconductor substrate 50 according to a comparative example.

[0034] As shown in FIG. 3(a), the semiconductor substrate 10 subjected to the ion implantation (S10) and the heat treatment (S20) has a defect density distribution in the depth direction (e.g., a change in density of planar defects such as stacking faults in the depth direction). The semiconductor substrate 10 includes a low defect density layer 22, a first high defect density layer 24, and a second high defect density layer 26. The first high defect density layer 24 includes the first main surface 10a of the semiconductor substrate 10 and is adjacent to the low defect density layer 22 in the depth direction. The second high defect density layer 26 includes the second main surface 10b of the semiconductor substrate 10 and is adjacent to the low defect density layer 22 in the depth direction. The lattice defect densities of the first high defect density layer 24 and the second high defect density layer 26 are both higher than the lattice defect density of the low defect density layer 22. For example, the stacking fault densities of the first high defect density layer 24 and the second high defect density layer 26 are both higher than the stacking fault density of the low defect density layer 22.

[0035] 2, the implanted ion containing region 12, the first region 14, and the second region 16 formed in the semiconductor substrate 10 after ion implantation are transformed into a low defect density layer 22, a first high defect density layer 24, and a second high defect density layer 26, respectively, through heat treatment. Depending on the heat treatment conditions, the position of each layer in the depth direction is generally maintained, and the low defect density layer 22 is located within or near the projected range of the implanted ions, similar to the implanted ion containing region 12.

[0036] Since the depth of the peak of the lattice defect density formed by ion implantation is slightly shallower than the projection range of the implanted ions, the low defect density layer 22 may also be located slightly shallower than the projection range of the implanted ions. Depending on the implantation energy, the low defect density layer 22 may be formed at a position slightly shallower than the projection range of the implanted ions (for example, within about 5 μm, within about 2.5 μm, or within about 0.5 μm of the projection range).

[0037] As described above, the depth and thickness of the implanted ion containing region 12 can be controlled. Therefore, the depth and / or thickness of the low defect density layer 22 may be controlled by controlling the implanted ion containing region 12 in the depth direction. When either the first region 14 or the second region 16 is absent and the implanted ion containing region 12 is exposed to one main surface of the semiconductor substrate 10, a high defect density layer is formed only on one side (the first main surface 10a side or the second main surface 10b side) of the low defect density layer 22, and the low defect density layer 22 is exposed to one main surface of the semiconductor substrate 10.

[0038] The depth and / or thickness of the low defect density layer 22 can be controlled by the conditions of the heat treatment (e.g., the treatment temperature and / or the treatment time of at least one of the first heat treatment, the second heat treatment, and the third heat treatment). For example, by adjusting the conditions of the heat treatment, the low defect density layer 22 can be formed at a depth different from that of the implanted ion containing region 12. The depth position of the low defect density layer 22 may be at least 5 μm or 10 μm shallower than the projected range of the implanted ions, for example.

[0039] On the other hand, for comparison, the semiconductor substrate 50 shown in Fig. 3(b) is subjected to only the heat treatment (S20) without the ion implantation (S10). In contrast to Fig. 3(a), the semiconductor substrate 50 has stacking faults distributed uniformly throughout the entire depth direction.

[0040] FIG. 4(a) is a schematic diagram showing the processing of a semiconductor substrate 10 for observing the defect density distribution in the depth direction formed in the semiconductor substrate 10, and FIG. 4(b) shows an optical microscope photograph obtained by observing the processed semiconductor substrate 10.

[0041] Here, the semiconductor substrate 10 is a p-type silicon wafer (6 inches) produced by the CZ method, which has been subjected to hydrogen ion implantation and heat treatment. The implantation conditions are an implantation energy of 1.9 MeV and an implantation dose of 4×10 14 cm -2 The heat treatment conditions were as follows: first heat treatment at 420°C for 6 hours, second heat treatment at 700°C for 18 hours, and third heat treatment at 1000°C for 10 hours.

[0042] As shown in FIG. 4(a), the semiconductor substrate 10 was polished at an angle using a Secco etchant, and the distribution of defects appearing on the polished surface 28 was observed with an optical microscope.

[0043] 4(b), it was actually confirmed that a defect density distribution having a low defect density layer 22, a first high defect density layer 24, and a second high defect density layer 26 was formed in the semiconductor substrate 10. While a large number of stacking faults (black dots in the figure) were observed in the first high defect density layer 24 and the second high defect density layer 26, almost no stacking faults were observed in the low defect density layer 22.

[0044] This phenomenon was newly discovered by the present inventor and has not been known up to now. Because it is a newly discovered phenomenon, its mechanism has not yet been elucidated, but the present inventor's speculation on it is described below.

[0045] Silicon wafers generally contain a small amount of oxygen. As is known, oxygen precipitates are first formed inside the wafer, and then interstitial silicon generated by the formation of the oxygen precipitates gather on the (111) plane and can change into stacking faults. It is understood that the first high defect density layer 24 and the second high defect density layer 26 are formed by such a known mechanism. Therefore, as shown in FIG. 4(b), a large number of stacking faults are generated in the first high defect density layer 24 and the second high defect density layer 26.

[0046] However, stacking faults are significantly reduced in the low defect density layer 22 compared to the high defect density layer. The main cause of the phenomenon in which stacking faults do not occur is believed to be one or both of the following two factors. (1) Hydrogen ion implantation creates defects with gettering ability inside the wafer, and these defects getter oxygen, preventing the formation of oxygen precipitates. (2) Due to the hydrogen ion implantation, defects that getter interstitial silicon are formed inside the wafer and do not grow into stacking faults.

[0047] The discovery of a clearly observed unknown phenomenon, as shown in Figure 4(b), is groundbreaking for a material such as silicon, whose properties have been thoroughly understood after extensive research. It is expected that this new phenomenon will lead to the establishment of an innovative gettering technology that precisely controls the defect density distribution.

[0048] 5 is a diagram showing a schematic diagram of microscopic changes in the semiconductor substrate 10 at each stage of the heat treatment step (S20) according to the embodiment. Based on the above considerations, FIG. 5 shows changes occurring in the first heat treatment (S21), the second heat treatment (S22), and the third heat treatment (S23) in the implanted ion containing region 12 in comparison with the first region 14 and the second region 16 (i.e., regions where ions are not implanted).

[0049] In the first region 14 and the second region 16, oxygen 30 gathers locally (by oxygen precipitation) during the first heat treatment to form defect nuclei 32. The formed defect nuclei 32 then grow during the second heat treatment. Furthermore, during the third heat treatment, stacking faults 34 and dislocation loops 36 are generated from the grown defect nuclei 32. In this way, in the regions where ions are not implanted, the defect density increases through the heat treatment.

[0050] On the other hand, in the implanted ion containing region 12, lattice defects formed by ion implantation (hereinafter referred to as implantation defects 38) already exist. During the first heat treatment, oxygen 30 gathers at the implantation defects 38 (oxygen 30 is gettered to the implantation defects 38), preventing oxygen precipitation. During the second heat treatment, oxygen 30 also gathers at the implantation defects 38. Furthermore, during the third heat treatment, oxygen 30 also gathers at the implantation defects 38. In this way, in the implanted ion containing region 12, oxygen precipitation is suppressed throughout the first to third heat treatments, making it difficult for stacking faults 34 and dislocation loops 36 to occur.

[0051] It is expected that the processing time of the second heat treatment will affect the growth of defect nuclei in the first region 14 and the second region 16, and oxygen gettering by the implantation defects 38 in the implanted ion containing region 12, as compared with the processing times of the first heat treatment and the third heat treatment. Therefore, the second processing time may be longer than the first processing time. The second processing time may be longer than the third processing time. Thereby, it may be possible to increase the difference in defect density between the first high defect density layer 24 (or the second high defect density layer 26) and the low defect density layer 22.

[0052] The generation of stacking faults 34 and dislocation loops 36 in the first and second regions 14, 16 may be substantially completed during the second heat treatment. Therefore, the third heat treatment may be omitted.

[0053] Fig. 6 is a flowchart showing a method for manufacturing a semiconductor device according to an embodiment. Fig. 7 is a cross-sectional view that typically shows a semiconductor device 40 according to an embodiment.

[0054] First, as shown in Fig. 6, ion implantation (S10) and heat treatment (S20) are performed in the same manner as in the flow of Fig. 1. As a result, a low defect density layer 22, a first high defect density layer 24, and a second high defect density layer 26 are formed in the semiconductor substrate 10, as shown in Fig. 3(a).

[0055] Next, a removal process (S30) is performed. For example, by a physical, chemical, or other removal process such as polishing or etching, the high defect density layer on one side (i.e., either the first high defect density layer 24 or the second high defect density layer 26) is removed from the semiconductor substrate 10, and the low defect density layer 22 is exposed.

[0056] The removal process (S30) may be performed after the ion implantation (S10) rather than after the heat treatment (S20), in which case the removal process removes either the first region 14 or the second region 16 to expose the implanted ion-containing region 12.

[0057] As described above, when the depth and thickness of the implanted ion containing region 12 are controlled so that the implanted ion containing region 12 reaches any of the main surfaces of the semiconductor substrate 10, the low defect density layer 22 is exposed after the heat treatment, and therefore the removal process may be omitted.

[0058] Next, a semiconductor element 42 is formed in the exposed low defect density layer 22 (S41). As shown in Fig. 7, the semiconductor device 40 includes a semiconductor element 42 (e.g., a photoelectric conversion unit) formed in the low defect density layer 22, and a metal gettering layer 46 adjacent to the low defect density layer 22 in the depth direction and including a main surface 44 on the opposite side to the low defect density layer 22. Either the first high defect density layer 24 or the second high defect density layer 26 shown in Fig. 3(a) is used as the metal gettering layer 46, and metal impurities are captured by the metal gettering layer 46.

[0059] Furthermore, a wiring layer is formed on the formed semiconductor element 42 (S42), and a protective film for protecting the element and wiring is formed (S43). The steps S41 to S43 are steps (S40) called "pre-processing" in the semiconductor process. Then, the so-called post-processing (S50) of the semiconductor process is performed, and a semiconductor product is completed. The post-processing (S50) includes, for example, a step of dicing the wafer into individual pieces, a die-bonding step of adhering the individual chips onto a mounting substrate, a step of connecting the mounting substrate and the chips with wire bonds, and a step of sealing the chips with resin.

[0060] Existing CMOS image sensors use a metal gettering layer and an epitaxial layer to counter noise such as white scratches. The metal gettering layer is formed at the projected range of the implanted ions by ion implantation, so it tends to be very thin in the depth direction. The thinner the gettering region, the higher the possibility that metal impurities will slip through the gettering region, and the more limited the gettering effect may be. The epitaxial layer can achieve high crystallinity and is effective in countering noise, but the epitaxial growth process is expensive.

[0061] In contrast, according to the embodiment, a newly discovered gettering phenomenon that occurs under a combination of ion implantation and heat treatment is utilized to form a low defect density layer 22 in the projected range of the implanted ions (and / or at a position shallower than that), and a metal gettering layer 46 is formed in another depth region. Compared to the conventional method, it is easy to make the metal gettering layer 46 considerably thicker, and it is expected to have excellent gettering ability for metal impurities. In addition, by forming the semiconductor element 42 in the low defect density layer 22, it is expected that a high-cost epitaxial growth process will be unnecessary, which may lead to a breakthrough in terms of cost.

[0062] FIG. 8 is a graph showing the analysis results of the semiconductor substrate according to the embodiment by secondary ion mass spectrometry (SIMS). FIG. 8 shows an example together with a comparative example. In the example, a semiconductor substrate that has been subjected to the ion implantation (S10 in FIG. 1) and heat treatment (S20) according to the embodiment is prepared, and a process for intentionally causing copper contamination is performed on the semiconductor substrate. The implanted ions are hydrogen, and the implantation position is 45 μm deep from the main surface, with the main surface of the two main surfaces of the substrate that is irradiated with ions being set to a depth of 0 μm. The contamination process of the semiconductor substrate is performed by immersing the substrate in a copper sulfate solution to diffuse copper into the substrate, thereby simulating metal contamination of the substrate that may actually occur. In the comparative example, a semiconductor substrate 10 that has been subjected to only heat treatment (S20) without ion implantation (S10) is prepared, and a similar copper contamination process is performed. FIG. 8 shows the SIMS analysis results of the contaminated semiconductor substrates of the example and the comparative example, with the copper (Cu) concentration on the vertical axis in logarithm and the depth from the substrate surface on the horizontal axis.

[0063] One noteworthy result of this SIMS analysis is that a high concentration region 52 with a high copper concentration is formed in a depth range shallower than the implantation position, as shown in the embodiment of Figure 8. In this embodiment, the high concentration region 52 is in a depth range of about 21 μm to about 49 μm, and in particular, the peak copper concentration in a depth range of about 28 μm to about 44 μm is 10 18 cm -3 This is understood to be the result of the semiconductor substrate according to the embodiment exhibiting a high gettering ability in the depth range corresponding to the high concentration region 52 and accumulating copper. In contrast, in the comparative example, the copper concentration in the same depth range is 10 15 ~10 16 cm -3 , which is at least two orders of magnitude smaller than that of the embodiment. Thus, the semiconductor substrate according to the embodiment has a metal gettering layer with high gettering ability in a depth range corresponding to the high concentration region 52. In addition, since this metal gettering layer extends to a relatively thick depth range, the possibility that metal impurities will penetrate the gettering layer and reach the element region is reduced.

[0064] In the embodiment, the high concentration region 52 is also provided at a position deeper than the high concentration region 52 by 10 17 cm -3 In contrast, in the comparative example, the copper concentration in the same depth range is one order of magnitude smaller, at 10 16 cm -3 Therefore, the semiconductor substrate according to the embodiment has a metal gettering layer not only in the high concentration region 52 but also in a depth range corresponding to the intermediate concentration region 54 deeper than the high concentration region 52.

[0065] In this embodiment, the implantation position is included in the high concentration region 52, but depending on the conditions for ion implantation into the semiconductor substrate and the heat treatment conditions, it is considered that the implantation position may be located on the boundary between the high concentration region 52 and the medium concentration region 54, or the implantation position may be included in the medium concentration region 54.

[0066] Another noteworthy result is that in the embodiment, the low concentration region 56 is formed in a shallower depth range than the high concentration region 52, that is, in the range from the top surface of the substrate to the high concentration region 52. The copper concentration in the low concentration region 56 is 10 14 cm -3 In the comparative example, the copper concentration in the same depth range is an order of magnitude higher, at 10 15 cm -3 It is not yet confirmed whether this low concentration region 56 is caused by the low defect density layer 22 described above, but it is presumed that this is the result of the low defect density layer 22 being formed at a position shallower than the implantation position through heat treatment. 14 cm -3 This low concentration corresponds to the lower limit of copper concentration detection by the SIMS analysis device used, so the true copper concentration in low-concentration region 56 in the embodiment may be even lower than this measured value. Therefore, the semiconductor substrate according to the embodiment has a layer in which metal is less likely to diffuse (is less likely to be contaminated by metal) in the depth range corresponding to low-concentration region 56. Therefore, this layer can be used as an element formation region for forming semiconductor elements.

[0067] The present invention has been described above based on the embodiments. It will be understood by those skilled in the art that the present invention is not limited to the above embodiments, that various design changes are possible, that various modifications are possible, and that such modifications are also within the scope of the present invention.

[0068] In the above-described embodiment, the hydrogen ions implanted into the semiconductor substrate are protons, but the hydrogen ions may be positive ions such as protons, deuterides, and tritons, or negative ions such as protides, deuterides, and tritides, or a mixture of these ions. In addition, the ion beam B may contain not only hydrogen ions but also ions of other light elements (e.g., helium) or other elements (e.g., carbon). There may be cases where the ion beam B does not contain hydrogen ions.

[0069] The device manufactured by the semiconductor device manufacturing method according to the embodiment is not limited to a photoelectric conversion device such as a CMOS image sensor, etc. The semiconductor device manufacturing method according to the embodiment may be used to manufacture other semiconductor devices such as a lateral power semiconductor.

[0070] In the above-described embodiment, a removal process (S30 in FIG. 6) of the high defect density layer is proposed. Alternatively, the method for manufacturing a semiconductor device may further include a step of performing a defect recovery process on at least a part of the high defect density layer. The defect recovery process may be a surface heat treatment, for example, laser annealing. The method for manufacturing a semiconductor device may further include a step of forming a semiconductor element in the region that has been subjected to the defect recovery process. Such an embodiment will be described below with reference to FIGS. 9(a) to 9(c).

[0071] First, ion implantation (S10) and heat treatment (S20) are performed, and as shown in Fig. 9(a), a low defect density layer 22, a first high defect density layer 24, and a second high defect density layer 26 are formed in the semiconductor substrate 10. In the defect recovery process, as an example, a laser beam 60 for laser annealing is irradiated onto the first high defect density layer 24 on the first main surface 10a (the main surface irradiated with the ion beam) side of the semiconductor substrate 10.

[0072] In the region irradiated with the laser light 60, at least some of the lattice defects (e.g., stacking faults) are repaired (disappeared) as shown in FIG. 9(b). The region thus subjected to the defect recovery process (hereinafter also referred to as the defect recovery layer 62) has fewer lattice defects than before the defect recovery process. In this example, the defect recovery layer 62 is formed on the outermost surface of the semiconductor substrate 10. A part of the first high defect density layer 24 that has not been subjected to the defect recovery process remains between the defect recovery layer 62 and the low defect density layer 22, and the defect recovery layer 62 and the low defect density layer 22 are separated from each other by the first high defect density layer 24. The defect recovery layer 62 has a lower lattice defect density than the first high defect density layer 24. Note that the defect recovery process may be performed on the entire first high defect density layer 24, and the defect recovery layer 62 may be connected to the low defect density layer 22 in the depth direction.

[0073] The wavelength of the laser light 60 used may be selected depending on the depth at which the defect recovery layer 62 is to be formed. For example, a green laser may be used as the laser light 60 to recover defects located at a relatively shallow position, or an infrared laser may be used to recover defects located at a relatively deep position.

[0074] In the case of green laser annealing, the wavelength of the laser light 60 may be in the range of 500 nm to 550 nm, more preferably in the range of 520 nm to 540 nm. As a light source of the laser light 60, a Nd:YAG laser, a Nd:YLF laser, a Nd:YVO4 laser, or the like that outputs a second harmonic may be used.

[0075] In the case of infrared laser annealing, the wavelength of the laser light 60 may be in the range of 690 nm to 950 nm, and more preferably in the range of 800 nm to 830 nm. A semiconductor laser may be used as a light source of the laser light 60.

[0076] The defect recovery process may also include a process of irradiating the high defect density layer with lasers of different wavelengths simultaneously or sequentially. For example, the defect recovery layer 62 can be formed over a wide depth range by irradiating the high defect density layer with a green laser and an infrared laser simultaneously or sequentially.

[0077] 9(c), a semiconductor element 64 (e.g., a photoelectric conversion section) is formed in the defect recovery layer 62. The first high defect density layer 24 and the second high defect density layer 26 can be used as a metal gettering layer 66. In this embodiment, the low defect density layer 22 is not used in the formation of a semiconductor element.

[0078] 6, a wiring layer is formed on the semiconductor element 64, and a protective film is formed to protect the element and wiring. Then, post-processing of the semiconductor is performed, and the semiconductor product is completed.

[0079] Instead of or in addition to irradiating the first main surface 10a of the semiconductor substrate 10 with the laser light 60, the second high defect density layer 26 on the opposite second main surface 10b side may be irradiated with the laser light 60 to repair at least some of the lattice defects in the second high defect density layer 26. A semiconductor element may be formed in the region thus subjected to the defect recovery process. [Explanation of symbols]

[0080] 10 semiconductor substrate, 10a first main surface, 10b second main surface, 12 implanted ion containing region, 14 first region, 16 second region, 22 low defect density layer, 24 first high defect density layer, 26 second high defect density layer, 40 semiconductor device, 42 semiconductor element, 46 metal gettering layer.

Claims

1. A step of implanting light ions into a semiconductor substrate, which is a silicon wafer formed by the CZ method; subjecting the semiconductor substrate to a first heat treatment after the ion implantation, and subjecting the semiconductor substrate to a second heat treatment after the first heat treatment at a temperature higher than that of the first heat treatment; The implantation energy of the light ions in the step of implanting the light ions is greater than 0.4 MeV and less than 10.5 MeV; The processing time of the second heat treatment is longer than the processing time of the first heat treatment, 4. A method for manufacturing a semiconductor device, comprising the steps of: forming a semiconductor element on the semiconductor substrate; forming a first heat treatment on the semiconductor substrate; and forming a second heat treatment on the semiconductor substrate.

2. The method for manufacturing a semiconductor device as described in claim 1, characterized in that the injection energy of the light ions in the step of injecting the light ions is greater than 0.4 MeV and less than 2 MeV.

3. 3. The method for manufacturing a semiconductor device according to claim 1, wherein the light ions include hydrogen ions.

4. 4. The method for manufacturing a semiconductor device according to claim 1, wherein the first heat treatment includes heating the semiconductor substrate to a first treatment temperature of 300° C. or more and 450° C. or less, and the second heat treatment includes heating the semiconductor substrate to a second treatment temperature of 450° C. or more and 800° C. or less.

5. The method further comprises the step of subjecting the semiconductor substrate to a third heat treatment at a temperature higher than that of the second heat treatment after the second heat treatment; 5. The method for manufacturing a semiconductor device according to claim 1, wherein a processing time of the second heat treatment is longer than a processing time of the third heat treatment.

6. 6. The method for manufacturing a semiconductor device according to claim 5, wherein the third heat treatment includes heating the semiconductor substrate to a third treatment temperature of 800.degree. C. or more and 1200.degree. C. or less.

7. a defect density distribution is formed in the semiconductor substrate in a depth direction after the second heat treatment or after the third heat treatment; 7. The method for manufacturing a semiconductor device according to claim 5, wherein the defect density distribution has a low defect density layer at a position equal to or shallower than the projected range of implanted ions, and has a high defect density layer having a higher lattice defect density than the low defect density layer on a first main surface side, a second main surface side, or both sides of the first main surface side and the second main surface side of the semiconductor substrate relative to the low defect density layer.

8. 8. The method for manufacturing a semiconductor device according to claim 7, further comprising the step of forming the semiconductor element in the low defect density layer.

9. 9. The method for manufacturing a semiconductor device according to claim 7, further comprising the step of performing a defect recovery process on at least a part of the high defect density layer.

10. 10. The method for manufacturing a semiconductor device according to claim 9, further comprising the step of forming the semiconductor element in the region where the defect recovery process has been performed.

11. A step of implanting light ions into a semiconductor substrate, which is a silicon wafer formed by the CZ method; and performing a heat treatment on the semiconductor substrate after the ion implantation. The implantation energy of the light ions in the step of implanting the light ions is greater than 0.4 MeV and less than 10.5 MeV; the heat treatment is a stepwise or gradual increase in temperature of the semiconductor substrate so that, after the heat treatment, the semiconductor substrate has a metal gettering layer formed in a depth range including an implantation position of the light ions, and a layer formed at a position shallower than the metal gettering layer and less susceptible to metal contamination than the metal gettering layer; 4. A method for manufacturing a semiconductor device, comprising the steps of: implanting ions and performing a heat treatment on the semiconductor substrate before forming a semiconductor element on the semiconductor substrate.

12. The method for manufacturing a semiconductor device described in Claim 11, characterized in that the semiconductor substrate subjected to the ion implantation and the heat treatment is provided with a further metal gettering layer formed at a deeper position than the metal gettering layer and having a lower gettering ability than the metal gettering layer.

Images