Semiconductor Device

Abstract

To regulate the voltage withstanding property in an active region.SOLUTION: A semiconductor device includes an active region and an edge region. The semiconductor device includes a drift region with a first conductivity type provided to a semiconductor substrate, a base region with a second conductivity type provided above the drift region, a first collector region with the second conductivity type provided below the drift region in the active region, and a second collector region with the second conductivity type provided below the drift region in the edge region. The doping concentration of the first collector region is higher than the doping concentration of the second collector region. In a top view, the area of the first collector region is the same as the area of the second collector region or larger than the area of the second collector region.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] 2. Description of the Related Art Conventionally, semiconductor devices including an active region and an edge region (termination structure portion) in an insulated gate bipolar transistor (IGBT) or the like are known (see, for example, Patent Documents 1 and 2). Patent Document 1: JP 2018-133493 A Patent Document 2: JP 2019-12725 A Summary of the Invention [Problem to be solved by the invention]

[0003] In a semiconductor device, there is a withstand voltage in an active region and a withstand voltage in an edge region, and it is preferable that the withstand voltage during switching operation is higher in the edge region than in the active region. [Means for solving the problem]

[0004] In one aspect of the present invention, there is provided a semiconductor device having an active region and an edge region, the semiconductor device comprising: a drift region of a first conductivity type provided in a semiconductor substrate; a base region of a second conductivity type provided above the drift region; a first collector region of the second conductivity type provided below the drift region in the active region; and a second collector region of the second conductivity type provided below the drift region in the edge region, wherein a doping concentration of the first collector region is greater than a doping concentration of the second collector region, and an area of ​​the first collector region is the same as or greater than an area of ​​the second collector region in a top view.

[0005] The doping concentration of the first collector region is 1E16 cm -3 Above, 5E18cm -3 It may be the following:

[0006] The doping concentration of the second collector region is 1E16 cm -3 Above, 5E18cm -3 It may be the following:

[0007] The semiconductor device may include an intermediate region provided between the active region and the edge region in a top view, and the first collector region may extend from the active region to the intermediate region in a top view.

[0008] The first collector region may be provided inside the active region in a top view.

[0009] The semiconductor device may include an emitter electrode provided above a semiconductor substrate and electrically connected to a front surface of the semiconductor substrate, and a gate metal layer provided above the semiconductor substrate for setting a gate potential. outer edge The width B, which is the distance from the edge of the second collector region to the edge of the semiconductor substrate, is outer edge It may be larger than width A, which is the distance from the gate electrode to the edge of the gate metal layer.

[0010] The doping concentration of the second collector region may be less than or equal to 0.85 times the doping concentration of the first collector region.

[0011] The difference between width B and width A may be greater than 10 μm.

[0012] The doping concentration of the second collector region may be greater than or equal to 0.85 and less than or equal to 0.9 times the doping concentration of the first collector region.

[0013] The thickness T of the semiconductor substrate in the depth direction may satisfy BA<αT when 0.1<α<0.5.

[0014] The semiconductor device includes a guard ring portion of a second conductivity type provided above the drift region in the edge region, and a semiconductor substrate having a lower surface than the guard ring portion above the drift region in the edge region. outer edge and a channel stopper region provided on the side of the first insulating film.

[0015] The above summary of the invention does not list all the features of the present invention. Subcombinations of these features may also be inventions. [Brief description of the drawings]

[0016] [Figure 1A] 1 shows an example of a top view of a semiconductor device 100. FIG. [Figure 1B] 1 shows an example of a top view of a semiconductor device 100. FIG. [Figure 1C] FIG. 2 is a diagram showing an example of aa' cross section in FIG. 1B. [Diagram 2] 1 is a cross-sectional view showing an example of the configuration of a semiconductor device 100. FIG. [Figure 3A] When viewed from above, the semiconductor device 100 shows a region in which the first collector region 61 is formed. [Figure 3B] When viewed from above, the semiconductor device 100 shows a region in which the first collector region 61 is formed. [Figure 3C] When viewed from above, the semiconductor device 100 shows a region in which the first collector region 61 is formed. [Figure 4A] The relationship between the pull-out length (D) and temperature is shown. [Figure 4B] An example of a simulation result of the semiconductor device 100 is shown. [Figure 4C] 13 shows an example of a simulation result of the semiconductor device according to the comparative example. [Figure 5A] An example of the characteristics of the semiconductor device 100 will be shown. [Figure 5B] 4 shows an example of characteristics of a semiconductor device according to a comparative example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0017] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention according to the claims. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0018] In this specification, one side in a direction parallel to the depth direction of a semiconductor substrate is referred to as the "front" or "upper" and the other side as the "rear" or "lower". Of the two main surfaces of a substrate, layer or other member, one surface is referred to as the upper surface and the other surface is referred to as the lower surface. The directions of "front", "upper", "lower" and "lower" are not limited to the direction of gravity or the directions when the semiconductor device is mounted.

[0019] In this specification, technical matters may be explained using orthogonal coordinate axes of X-axis, Y-axis, and Z-axis. The orthogonal coordinate axes merely identify the relative positions of components, and do not limit a specific direction. For example, the Z-axis does not limit the height direction relative to the ground. Note that the +Z-axis direction and the -Z-axis direction are opposite directions. When the Z-axis direction is described without indicating positive or negative, it means a direction parallel to the +Z-axis and -Z-axis. In this specification, the view from the +Z-axis direction may be referred to as a top view.

[0020] In this specification, when the term "same" or "equal" is used, it may include cases where there is an error due to manufacturing variations, etc. The error is, for example, within 10%.

[0021] In this specification, the conductivity type of the doped region doped with impurities is described as P type or N type. However, the conductivity type of each doped region may be the opposite polarity. In addition, in this specification, when P+ type or N+ type is described, it means that the doping concentration is higher than P type or N type, and when P- type or N- type is described, it means that the doping concentration is lower than P type or N type.

[0022] In this specification, the doping concentration refers to the concentration of an impurity activated as a donor or an acceptor. In this specification, the difference in concentration between the donor and the acceptor may be the concentration of the larger one of the donor or the acceptor. The difference in concentration can be measured by a voltage-capacitance measurement method (CV method). The carrier concentration measured by a spreading resistance measurement method (SR) may be the donor or the acceptor concentration. When the donor or the acceptor concentration distribution has a peak, the peak value may be the donor or the acceptor concentration in the region. When the donor or the acceptor concentration in the region where the donor or the acceptor exists is almost uniform, the average value of the donor or the acceptor concentration in the region may be the donor or the acceptor concentration.

[0023] 1A shows an example of a top view of a semiconductor device 100. The semiconductor device 100 is a semiconductor chip including a transistor portion. The semiconductor device 100 includes a semiconductor substrate 10 in which an active region 110 and a non-active region 120 are formed.

[0024] The semiconductor substrate 10 is a substrate formed of a semiconductor material such as silicon, silicon carbide, or gallium nitride. The semiconductor substrate 10 may include a portion formed by epitaxial growth, etc. The semiconductor substrate 10 in this example is a silicon substrate.

[0025] The active region 110 is a region where a main current flows between the front surface 21 and the back surface 23 of the semiconductor substrate 10 when the semiconductor device 100 is controlled to be in the on state. That is, it is a region where a current flows in the depth direction inside the semiconductor substrate 10 from the front surface 21 to the back surface or from the back surface 23 to the front surface 21. An IGBT is formed in the active region 110 of this example.

[0026] The non-active region 120 is a region between the active region 110 and the outer peripheral edge 11 of the semiconductor substrate 10 in a top view. The non-active region 120 includes an edge region 122 and a middle region 124. One or more metal pads may be arranged in the non-active region 120 for connecting the semiconductor device 100 to an external device via a wire or the like.

[0027] The edge region 122 is a region between the active region 110 and the outer circumferential edge 11 of the semiconductor substrate 10. The edge region 122 is provided to surround the active region 110 in a top view. The edge region 122 may have an edge termination structure. The edge termination structure relieves electric field concentration on the top surface side of the semiconductor substrate 10. The specific structure of the edge region 122 will be described later.

[0028] The intermediate region 124 is provided between the active region 110 and the edge region 122 in a top view. intermediate area 124 In top view, the intermediate region 124 surrounds the outer periphery of the active region 110. The intermediate region 124 includes a gate metal layer 50, which will be described later.

[0029] The gate pad 140 is electrically connected to the gate conductive portion of the active region 110 via the gate metal layer 50. The gate pad 140 may be in contact with the gate metal layer 50. The gate pad 140 is set to a gate potential. The gate pad 140 in this example is rectangular in top view.

[0030] Fig. 1B shows an example of a top view of the semiconductor device 100. In this example, a magnified view of region X in Fig. 1A is shown.

[0031] The semiconductor device 100 of this example includes, on the front surface of the semiconductor substrate 10, a gate trench portion 40, a dummy trench portion 30, an emitter region 12, a base region 14, a contact region 15, and a well region 17. The semiconductor device 100 of this example also includes an emitter electrode 52 and a gate metal layer 50 provided above the front surface of the semiconductor substrate 10.

[0032] The emitter electrode 52 is provided above the gate trench portion, the dummy trench portion, the emitter region, the base region, the contact region 15, and the well region 17. The emitter electrode 52 may be connected to an electrode outside the semiconductor device 100 by wire bonding or the like. The electrode outside the semiconductor device 100 may be, for example, an anode electrode of a diode or an electrode of an integrated circuit arranged adjacent to the semiconductor device 100, an electrode provided on a substrate or the like on which the semiconductor device 100 is mounted, or an external terminal or the like provided on a resin case in which a substrate or the like on which the semiconductor device 100 is mounted is incorporated.

[0033] The gate metal layer 50 is provided above the gate trench portion 40 and the well region 17. The gate metal layer 50 is electrically connected to the gate conductive portion of the active region 110 and supplies a gate voltage. The gate metal layer 50 is electrically connected to the gate pad 140. The gate metal layer 50 is provided to surround the outer periphery of the active region 110 in a top view. The gate metal layer 50 may be provided along an intermediate region 124 between the active region 110 and the edge region 122.

[0034] The emitter electrode 52 and the gate metal layer 50 are formed of a material containing a metal. For example, at least a portion of the emitter electrode 52 may be formed of aluminum, an aluminum-silicon alloy, or an aluminum-silicon-copper alloy. At least a portion of the gate metal layer 50 may be formed of aluminum, an aluminum-silicon alloy, or an aluminum-silicon-copper alloy. The emitter electrode 52 and the gate metal layer 50 may have a barrier metal made of titanium, a titanium compound, or the like under the region made of aluminum or the like. The emitter electrode 52 and the gate metal layer 50 are provided separately from each other.

[0035] The emitter electrode 52 and the gate metal layer 50 are provided above the semiconductor substrate 10 with an interlayer insulating film 38 therebetween. The interlayer insulating film 38 is omitted in FIG. 1B. ,Ko A contact hole 55 and a contact hole 56 are provided penetrating therethrough.

[0036] The contact hole 55 connects the gate metal layer 50 and a gate conductive portion in the active region 110. Inside the contact hole 55, a plug 57 made of tungsten or the like, which will be described later, may be formed via a barrier metal layer 53.

[0037] The contact hole 56 connects the emitter electrode 52 and a dummy conductive portion in the dummy trench portion 30. Inside the contact hole 56, a plug 57 made of tungsten or the like may be formed with a barrier metal layer 53 interposed therebetween.

[0038] The connection portion 25 electrically connects a front surface electrode, such as the emitter electrode 52 or the gate metal layer 50, to the semiconductor substrate 10. In one example, the connection portion 25 is provided between the gate metal layer 50 and the gate conductive portion. The connection portion 25 is also provided between the emitter electrode 52 and the dummy conductive portion. The connection portion 25 is a conductive material, such as polysilicon doped with impurities. Here, the connection portion 25 is polysilicon (N+) doped with N-type impurities. The connection portion 25 is provided above the front surface of the semiconductor substrate 10 via an insulating film, such as an oxide film, or the like.

[0039] The gate trench portions 40 are arranged at predetermined intervals along a predetermined arrangement direction (the X-axis direction in this example). The gate trench portions 40 in this example may have two extension portions 41 extending along an extension direction (the Y-axis direction in this example) parallel to the front surface of the semiconductor substrate 10 and perpendicular to the arrangement direction, and a connection portion 43 connecting the two extension portions 41.

[0040] It is preferable that at least a portion of the connection portion 43 is formed in a curved shape. By connecting the ends of the two extension portions 41 of the gate trench portion 40, it is possible to alleviate electric field concentration at the ends of the extension portions 41. At the connection portion 43 of the gate trench portion 40, the gate metal layer 50 may be connected to the gate conductive portion.

[0041] The dummy trench portion 30 is a trench portion electrically connected to the emitter electrode 52. The dummy trench portions 30 are arranged at predetermined intervals along a predetermined arrangement direction (the X-axis direction in this example) similarly to the gate trench portions 40. The dummy trench portions 30 in this example have an extension portion 31 extending along the extension direction. Note that the dummy trench portion 30 may have a U-shape on the front surface of the semiconductor substrate 10 similarly to the gate trench portions 40. That is, the dummy trench portion 30 may have two extension portions 31 extending along the extension direction and a connection portion connecting the two extension portions 31.

[0042] The semiconductor device 100 of this embodiment includes two gate trench portions 40 and 1 The semiconductor device 100 has a structure in which two dummy trench portions 30 are repeatedly arranged. That is, the semiconductor device 100 of this example has the gate trench portions 40 and the dummy trench portions 30 in a ratio of 2:1. For example, the semiconductor device 100 has one extension portion 31 between two extension portions 41.

[0043] However, the ratio of the gate trench portions 40 to the dummy trench portions 30 is not limited to this example. The ratio of the gate trench portions 40 to the dummy trench portions 30 may be 1:1 or 1:2. Also, the semiconductor device 100 may not include the dummy trench portions 30 and may be entirely made up of gate trench portions 40.

[0044] The well region 17 is a second conductive type region provided on the front surface side of the semiconductor substrate 10 relative to the drift region 18 described later. The well region 17 is an example of a well region provided on the inactive region 120 side of the semiconductor device 100. The well region 17 may have a higher doping concentration than the base region 14. The well region 17 is, for example, a P+ type. The well region 17 extends from an end of the active region 110 on the side where the gate metal layer 50 is provided to the inactive region 120 and is formed in a predetermined range. The diffusion depth of the well region 17 may be deeper than the depth of the gate trench portion 40 and the dummy trench portion 30. Part of the regions of the gate trench portion 40 and the dummy trench portion 30 on the gate metal layer 50 side are formed in the well region 17. The bottoms of the ends of the gate trench portion 40 and the dummy trench portion 30 in the extension direction may be covered by the well region 17.

[0045] The contact holes 54 are formed above the emitter region 12 and the contact region 15 in the mesa portion 71. The contact holes 54 are not provided above the well regions 17 provided at both ends in the Y-axis direction. In this manner, one or more contact holes 54 are formed in the interlayer insulating film. The one or more contact holes 54 may be provided extending in the extension direction.

[0046] The mesa portion 71 is a region adjacent to the trench portion in a plane parallel to the front surface of the semiconductor substrate 10. The mesa portion 71 is a portion of the semiconductor substrate 10 sandwiched between two adjacent trench portions, and may be a portion from the front surface of the semiconductor substrate 10 to the depth of the deepest bottom of each trench portion. The extension portion of each trench portion may be one trench portion. In other words, the region sandwiched between the two extension portions may be the mesa portion. The mesa portion 71 has a well region 17, an emitter region 12, a base region 14, and a contact region 15 on the front surface of the semiconductor substrate 10. In the mesa portion 71, the emitter region 12 and the contact region 15 are alternately provided in the extension direction.

[0047] The base region 14 is a second conductivity type region provided on the front surface side of the semiconductor substrate 10. The base region 14 is, for example, a P-type. The base region 14 may be provided on both ends in the Y-axis direction of the mesa portion 71 on the front surface of the semiconductor substrate 10. Note that FIG. 1B shows only one end of the base region 14 in the Y-axis direction.

[0048] The emitter region 12 is a region of a first conductivity type having a higher doping concentration than the drift region 18. In this example, the emitter region 12 is an N+ type, for example. An example of a dopant for the emitter region 12 is arsenic (As). The emitter region 12 is provided on the front surface of the mesa portion 71 in contact with the gate trench portion 40. The emitter region 12 may be provided extending in the X-axis direction from one of the two trench portions sandwiching the mesa portion 71 to the other. The emitter region 12 is also provided below the contact hole 54. In addition, the emitter region 12 may or may not be in contact with the dummy trench portion 30. The emitter region 12 in this example is in contact with the dummy trench portion 30.

[0049] The contact region 15 is a region of a second conductivity type having a higher doping concentration than the base region 14. The contact region 15 in this example is, for example, a P+ type. The contact region 15 in this example is provided on the front surface of the mesa portion 71. The contact region 15 may be provided in the X-axis direction from one of the two trench portions sandwiching the mesa portion 71 to the other. The contact region 15 may or may not be in contact with the gate trench portion 40. The contact region 15 may or may not be in contact with the dummy trench portion 30. In this example, the contact region 15 is in contact with the dummy trench portion 30 and the gate trench portion 40. The contact region 15 is also provided below the contact hole 54.

[0050] The active region 110 includes a region in which the emitter regions 12 and the contact regions 15 are repeatedly arranged. The active region 110 also includes a dummy trench portion 30 and a gate trench portion 40. An end of the active region 110 in the Y-axis direction is an end of a region where the emitter electrode 52 is connected to the semiconductor substrate 10 via a contact hole 54. In this example, an end of the contact hole 54 is located above the contact region 15.

[0051] The edge region 122 is a region closer to the outer circumferential end 11 than the gate metal layer 50 in a top view. In this example, the boundary between the edge region 122 and the intermediate region 124 is an end portion on the negative side in the Y-axis direction of the gate metal layer 50. A more specific structure of the edge region 122 will be described later.

[0052] The intermediate region 124 is a region between the active region 110 and the edge region 122 in a top view. In the intermediate region 124, the emitter electrode 52 does not need to be electrically connected to the semiconductor substrate 10. However, in the intermediate region 124, the emitter electrode 52 may be electrically connected to the dummy conductive portion of the dummy trench portion 30.

[0053] FIG. 1C is a diagram showing an example of the a-a′ cross section in FIG. 1B. The a-a′ cross section shows that, in the mesa portion 71, Contact Area 15 In the a-a' cross section, the semiconductor device 100 of this example has a semiconductor substrate, an interlayer insulating film, an emitter electrode 52, and a collector electrode 24. The emitter electrode 52 is formed above the semiconductor substrate 10 and the interlayer insulating film .

[0054] The drift region 18 is a region of a first conductivity type provided in the semiconductor substrate 10. In this example, the drift region 18 is an N-type, for example. The drift region 18 may be a region remaining in the semiconductor substrate 10 without other doped regions being formed therein. That is, the doping concentration of the drift region 18 may be the doping concentration of the semiconductor substrate 10. The emitter region 12, the contact region 15, and the accumulation region 16 are provided above the drift region 18. The buffer region 20 and the first collector region 61 are provided below the drift region 18.

[0055] The buffer region 20 is a region of a first conductivity type provided below the drift region 18. In this example, the buffer region 20 is, for example, an N-type. The doping concentration of the buffer region 20 is higher than the doping concentration of the drift region 18. The buffer region 20 may function as a field stop layer that prevents a depletion layer spreading from the lower surface side of the base region 14 from reaching the first collector region 61 of the second conductivity type.

[0056] The first collector region 61 is a second conductive type region provided in the active region 110 below the drift region 18. The first collector region 61 is, for example, a P+ type. For example, the doping concentration of the first collector region 61 is 1E16 cm -3 Above, 5E18cm -3 In one example, the doping concentration of the first collector region 61 is 8E17 cm -3 Note that E means a power of 10, for example, 8E17cm -3 is 8 x 10 17 cm -3 The first collector region 61 is provided below the buffer region 20.

[0057] The collector electrode 24 is formed on the rear surface 23 of the semiconductor substrate 10. The collector electrode 24 is made of a conductive material such as a metal. The collector electrode 24 is in contact with the first collector region 61.

[0058] The accumulation region 16 is a region of a first conductivity type provided closer to the front surface 21 of the semiconductor substrate 10 than the drift region 18. The accumulation region 16 in this example is, for example, an N+ type. The accumulation region 16 in this example is provided in contact with the gate trench portion 40. The doping concentration of the accumulation region 16 is higher than the doping concentration of the drift region 18. By providing the accumulation region 16, the carrier injection enhancement effect (IE effect) can be enhanced, and the on-voltage of the active region 110 can be reduced.

[0059] The gate trench portion 40 has a gate trench, a gate insulating film 42, and a gate conductive portion 44 formed on the front surface 21. The gate insulating film 42 is formed to cover the inner wall of the gate trench. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate conductive portion 44 is formed inside the gate insulating film 42 inside the gate trench. The gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon. The gate trench portion 40 is covered on the front surface 21 by an interlayer insulating film 38.

[0060] The gate conductive portion 44 includes a region facing the adjacent base region 14 on the mesa portion 71 side, across the gate insulating film 42, in the depth direction of the semiconductor substrate 10. When a predetermined voltage is applied to the gate conductive portion 44, electrons gather in the surface layer of the interface of the base region 14 that contacts the gate trench, forming a channel due to an N-type inversion layer, and a current flows.

[0061] The dummy trench portion 30 may have the same structure as the gate trench portion 40. The dummy trench portion 30 has a dummy trench, a dummy insulating film 32, and a dummy conductive portion 34 formed on the front surface 21 side. The dummy insulating film 32 is formed to cover the inner wall of the dummy trench. The dummy conductive portion 34 is formed inside the dummy trench and is formed further inward than the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy trench portion 30 is covered on the front surface 21 with an interlayer insulating film 38.

[0062] The interlayer insulating film 38 is provided on the front surface 21. An emitter electrode 52 is provided above the interlayer insulating film 38. The interlayer insulating film 38 is provided with one or more contact holes 54 for electrically connecting the emitter electrode 52 to the semiconductor substrate 10. Contact holes 55 and 56 may also be provided penetrating the interlayer insulating film 38.

[0063] FIG. 2 is a cross-sectional view showing an example of the configuration of the semiconductor device 100. In this example, a plane parallel to the upper surface of the semiconductor substrate 10 is defined as an XY plane, and a depth direction of the semiconductor substrate 10 is defined as a Z axis. FIG. 2 shows a partial cross-sectional view including a part of the active region 110 and an edge region 122 between the part of the active region 110 and the outer peripheral edge 11 of the semiconductor substrate 10. As an example, the active region 110 has a width larger than that of the edge region 122 in the X-axis direction and the Y-axis direction, and is surrounded by the edge region 122 in the XY plane. An end 29 on the outer peripheral edge 11 side of the gate metal layer 50 is provided along the boundary between the edge region 122 and the intermediate region 124.

[0064] A portion of the first collector region 61 may extend from the active region 110 to the intermediate region 124 in a top view. A portion of the first collector region 61 may extend from the active region 110 to the edge region 122 in a top view. In one example, the first collector region 61 may extend from the active region 110 to the non-active region 120 by 10 μm or more, or may extend by 20 μm or more. The distance by which the first collector region 61 extends into the non-active region 120 may be within 40 μm.

[0065] The second collector region 62 is a region of the second conductivity type provided below the drift region 18. The second collector region 62 is provided below the buffer region 20. At least a portion of the second collector region 62 is provided in the edge region 122. The second collector region 62 is provided closer to the outer circumferential end 11 than the first collector region 61 in a top view. For example, the doping concentration of the second collector region 62 is 1E16 cm -3Above, 5E18cm -3 The following is the result.

[0066] The doping concentration of the first collector region 61 is greater than that of the second collector region 62. In one example, the doping concentration of the second collector region 62 is 0.85 times or less the doping concentration of the first collector region 61. The concentration difference between the first collector region 61 and the second collector region 62 is formed by performing ion implantation on the rear surface 23 of the semiconductor substrate 10. As a forming method, ion implantation of a P-type dopant such as boron is performed on the entire surface of the first collector region 61. Thereafter, the second collector region 62 is covered with a resist or the like, and ion implantation of a P-type dopant is performed again. As a result, the doping concentration of the first collector region 61 can be made greater than the doping concentration of the second collector region 62.

[0067] Position X1 is the boundary position in the X-axis direction between active region 110 and non-active region 120. Position X1 is the position of the end portion where emitter electrode 52 is electrically connected to front surface 21 of semiconductor substrate 10. In this example, the boundary position between first collector region 61 and second collector region 62 may be different from position X1.

[0068] Position X2 is the boundary position in the X-axis direction between the edge region 122 and the intermediate region 124. Position X2 is the end position on the negative side in the X-axis direction of the gate metal layer 50. Position X2 is provided closer to the outer circumferential edge 11 of the semiconductor substrate 10 than position X1.

[0069] Position X3 is the boundary position between the first collector region 61 and the second collector region 62 in the X-axis direction. Position X3 is provided between positions X1 and X2 in the X-axis direction. The boundary position between the active region 110 and the inactive region 120 may coincide with the boundary position between the first collector region 61 and the second collector region 62. In this case, position X1 is the same position as position X3.

[0070] The guard ring portion 92 is a second conductive type region provided above the drift region 18 in the edge region 122. In this example, the guard ring portion 92 is formed with the same doping concentration as that of the second collector region 62. The guard ring portion 92 is formed surrounding the intermediate region 124 in top view. The guard ring portion 92 serves to extend the depletion layer from the intermediate region 124 in the X-axis direction. In addition, by arranging a plurality of guard ring portions 92, the depletion layer can be further extended in the X-axis direction. Therefore, by providing a plurality of guard ring portions 92, the breakdown voltage of the edge region 122 can be determined. The plurality of guard ring portions 92 may be provided at a distance from each other. The edge region 122 in this example has four guard ring portions 92-1 to 92-4.

[0071] The field plate electrode 80 may be provided above the guard ring portion 92. A plurality of field plate electrodes 80 and a connection portion 84 may be formed above the semiconductor substrate 10 in the edge region 122. The four field plate electrodes 80-1 to 80-4 and the connection portions 84-1 to 84-4 are provided above the guard ring portions 92-1 to 92-4, respectively. The connection portion 84 may be provided protruding from the corresponding guard ring portion 92 in the X-axis direction, and the connection portion 84 may be provided protruding beyond the field plate electrode 80. The field plate electrode 80 of this example is electrically connected to the guard ring portion 92 via the barrier metal layer 53 and the connection portion 84. The field plate electrode 80 may be formed in the same process as the gate metal layer 50 and the emitter electrode 52. Furthermore, the connection portion 84 may be made of polysilicon and may be formed in the same process as the gate conductive portion 44 of the gate trench portion 40 and the dummy conductive portion 34 of the dummy trench portion 30.

[0072] The connection portion 84 is covered with an insulating film 86. In the insulating film 86, a contact hole for connecting the connection portion 84 to the guard ring portion 92 and a contact hole for connecting the field plate electrode 80 to the connection portion 84 are provided.

[0073] The barrier metal layer 53 electrically connects the field plate electrode 80 and the guard ring portion 92 in the contact hole. The barrier metal layer 53 is made of titanium or a titanium compound. For example, the barrier metal layer 53 is a laminated film of Ti and TiN. A plug 57 of tungsten or the like may be provided in the contact hole via the barrier metal layer 53.

[0074] The channel stopper region 94 is provided above the drift region 18 in the edge region 122, closer to the outer circumferential edge 11 of the semiconductor substrate 10 than the guard ring portion 92. The channel stopper region 94 is an N+ type or P+ type region. A channel stopper electrode 82 may be formed above the channel stopper region 94 with an insulating film 86 interposed therebetween.

[0075] The channel stopper electrode 82 is provided above the channel stopper region 94. The channel stopper electrode 82 is electrically connected to the channel stopper region 94 through a contact hole provided in the insulating film 86. The channel stopper electrode 82 may be electrically connected to the channel stopper region 94 through a barrier metal layer 53. The contact hole may be provided with a plug 57 of tungsten or the like through the barrier metal layer 53 to electrically connect the channel stopper electrode 82 and the channel stopper region 94. The channel stopper electrode 82 may be provided so as to extend in the X-axis direction from the outer circumferential end 11 to a region where the channel stopper region 94 is not provided. The channel stopper electrode 82 may be formed in the same process as the gate metal layer 50 and the emitter electrode 52.

[0076] The protective film 88 covers the field plate electrode, the channel stopper electrode, the insulating film 86, and the emitter electrode 52 above the semiconductor substrate 10. A portion of the emitter electrode 52 may be exposed from the protective film 88 for connection to a bonding wire or the like. In addition, in the upper portion 28 on the outer circumferential edge 11 side of the semiconductor substrate 10, a channel stopper region 94 is exposed from the protective film 88.

[0077] Here, the doping concentration of the first collector region 61 is higher than that of the second collector region 62. When the doping concentration of the second collector region 62 is higher than that of the first collector region 61, the increase in holes amplifies electrons, and the concentration of the drift region 18 increases. Therefore, the withstand voltage is lower than that of the second collector region 62, which has a doping concentration lower than that of the first collector region 61. The withstand voltage in the active region 110 can be relatively lower than that in the edge region 122. Here, the withstand voltage refers to a voltage value calculated from the integral value of the electric field that exceeds the maximum electric field strength of silicon and causes avalanche breakdown when a voltage that is a reverse bias to the pn junction between the base region 14 and the drift region 18 is applied to the semiconductor device when the semiconductor device is in an off state. This allows the active region 110 to undergo avalanche breakdown before the edge region 122.

[0078] When the doping concentration of the first collector region 61 is greater than the doping concentration of the second collector region 62, the electric field at the bottom of the gate trench portion 40 and the dummy trench portion 30 in the active region 110 becomes stronger as shown in FIG. 4B described later, and an avalanche current is generated at the bottom of the gate trench portion 40 and the dummy trench portion 30. When the avalanche current reaches the first collector region 61, holes are generated due to conductivity modulation. The generated holes can be extracted by the extraction region of the front surface 21.

[0079] At this time, avalanche currents at the bottoms of the gate trench portion 40 and the dummy trench portion 30 tend to occur in regions where the widths and depths of the gate trench portion 40 and the dummy trench portion 30 are slightly different locally. The temperature of the region where the avalanche current occurs increases, and the resistance of the drift region 18 increases. This suppresses the avalanche current and increases the breakdown voltage.

[0080] In other regions of the active region 110 where no avalanche current flows, the temperature is low because no avalanche current flows, and the breakdown voltage is low.

[0081] The avalanche current moves to a region with a lower temperature, and the temperature rises in the region to which the avalanche current moves. The movement of the region through which the avalanche current flows is repeated within the active region 110. Therefore, the avalanche current continues to move through the bottoms of the gate trench portion 40 and the dummy trench portion 30, suppressing the rise in temperature of the active region 110 and making it difficult for element destruction due to overvoltage to occur.

[0082] On the other hand, when the doping concentration of the first collector region 61 is smaller than that of the second collector region 62, the avalanche current is generated at the corner of the well region 17 on the guard ring portion 92 side in the edge region 122. When the avalanche current reaches the second collector region 62, holes are generated. These holes can pass through the well region 17 and be extracted from the emitter electrode 52 of the active region 110. Heat is generated due to the distance that the holes pass from the well region 17 to the emitter electrode 52, and the temperature rises. As a result, the element is destroyed before the generation region of the avalanche current moves. As a result, when the doping concentration of the first collector region 61 is larger than that of the second collector region 62, the turn-off resistance (i.e., the breakdown resistance during dynamic avalanche) is improved.

[0083] In particular, when the semiconductor device 100 is miniaturized to reduce the pitch of the trench portion, the breakdown voltage of the active region 110 increases. In this case, when the area of ​​the edge region 122 is reduced to relatively reduce costs, or when the thickness of the semiconductor substrate 10 is reduced to relatively improve characteristics, the breakdown voltage of the edge region 122 becomes relatively low, and avalanche breakdown is likely to occur in the edge region 122. This may result in a decrease in the turn-off breakdown capability of the semiconductor device 100 (i.e., the breakdown capability during dynamic avalanche).

[0084] In the semiconductor device 100 of this example, the first collector region 61 has a higher doping concentration than the second collector region 62. Therefore, even if the area of ​​the edge region 122 is reduced or the thickness of the semiconductor substrate 10 is thinned, the breakdown voltage of the active region 110 is relatively lower than that of the inactive region 120, thereby improving the avalanche resistance.

[0085] By providing the accumulation region 16, the carrier concentration below the accumulation region 16 can be increased, and the on-voltage can be reduced. Furthermore, by providing the accumulation region 16, the breakdown voltage in the active region 110 can be relatively reduced, and the turn-off breakdown capability (i.e., breakdown capability during dynamic avalanche) can be improved, compared to a case where the accumulation region 16 is not provided. However, the semiconductor device 100 does not necessarily have to include the accumulation region 16.

[0086] The width A is the distance from the outer peripheral edge 11 of the semiconductor substrate 10 to the end of the gate metal layer 50. The size of the width A can be increased by increasing the number of guard ring portions 92 to extend the depletion layer in the X direction from the well region 17 of the intermediate region 124. However, if the width A is made too large, the area of ​​the semiconductor device 100 itself becomes large, the number of semiconductor devices 100 provided on one semiconductor wafer decreases, and the cost increases. Therefore, the width A in this example is set to be 120 μm or more and 300 μm or less.

[0087] The width B is the distance from the outer peripheral edge 11 of the semiconductor substrate 10 to the position X3 of the end of the second collector region 62. The width B may be greater than the width A. When the width B is greater than the width A, the difference BA is the distance from the edge region 122 to the position X3. Second collector region 621 indicates the lead-out length of the edge region 122. For example, the lead-out length may be 10 μm or more. The avalanche current of the edge region 122 is generated from the position X1 of the well region 17 of the intermediate region 124. Therefore, when the difference BA becomes smaller (i.e., the position X3 is on the edge region 122 side), the respective withstand voltages of the edge region 122 and the active region 110 are determined by the position X3 of the first collector region 61. As the difference BA becomes smaller (i.e., the position X3 is on the edge region 122 side), the withstand voltage of the edge region 122 becomes higher than the withstand voltage of the active region 110. Therefore, the withstand voltage of the semiconductor device 100 becomes the withstand voltage of the edge region 122, and the turn-off withstand voltage (i.e., the breakdown withstand voltage during dynamic avalanche) becomes lower.

[0088] Width C is the distance from outer peripheral edge 11 of semiconductor substrate 10 to the end of a contact hole for electrically connecting emitter electrode 52 and front surface 21 of semiconductor substrate 10.

[0089] The extension length D is the length by which the first collector region 61 extends beyond the active region 110 toward the non-active region 120. The extension length D is the difference between the width C and the width B. By increasing the extension length D, it becomes easier to relatively lower the breakdown voltage in the active region 110, and the withstand capability can be improved.

[0090] The doping concentration of the second collector region 62 may be 0.85 to 0.9 times the doping concentration of the first collector region 61. In this case, the width B is larger than the width A, and the difference between the widths B and A is larger than 10 μm, so that the withstand voltage of the edge region 122 is less likely to become lower than that of the active region 110.

[0091] Furthermore, the thickness T of the semiconductor substrate 10 in the Z-axis direction (i.e., the depth direction) satisfies BA<αT, where α is 0.1<α<0.5. For example, the thickness T of the semiconductor substrate 10 in the depth direction may be 50 μm or more, or may be 60 μm or more. Furthermore, the thickness T of the semiconductor substrate 10 in the depth direction may be 650 μm or less.

[0092] FIG. 3A shows a region where the first collector region 61 is formed in the top view of the semiconductor device 100. The first collector region 61 in this example is provided in a region inside the gate metal layer 50. The first collector region 61 is provided along the gate metal layer 50. The gate pad 140 is in contact with the gate metal layer 50, and the gate pad 140 is provided from the intermediate region 124 to the active region 110. The first collector region 61 in this example is also provided in a part of the lower part of the gate pad 140. In the top view, the area S1 of the first collector region 61 is equal to or larger than the area S2 of the second collector region 62. This makes it easier to relatively lower the breakdown voltage in the active region 110, and improves the breakdown voltage.

[0093] 3B shows a region in which the first collector region 61 is formed in the semiconductor device 100 as viewed from above. The first collector region 61 in this example is provided inside the active region 110 as viewed from above. The first collector region 61 in this example has a rectangular shape as viewed from above, but is not limited thereto. The first collector region 61 in this example is not provided in the non-active region 120. Even in this case, the area S1 of the first collector region 61 is the same as or larger than the area S2 of the second collector region 62 as viewed from above.

[0094] 3C shows a region where the first collector region 61 is formed in the semiconductor device 100 as viewed from above. The first collector region 61 in this example is provided inside the active region 110 as viewed from above. The first collector region 61 in this example is provided along the active region 110. The first collector region 61 is provided in a region inside the gate metal layer 50 other than the region where the gate pad 140 is provided. Even in this case, the area S1 of the first collector region 61 is the same as or larger than the area S2 of the second collector region 62 as viewed from above.

[0095] 4A shows the relationship between the pull-out length D and the temperature. The vertical axis indicates the maximum temperature inside the semiconductor device 100 when the voltage is clamped, and the horizontal axis indicates the pull-out length D of the first collector region 61. In each graph, the concentration ratio between the first collector region 61 and the second collector region 62 is different.

[0096] The concentration ratio R indicates the ratio of the doping concentration of the second collector region 62 to the doping concentration of the first collector region 61. When R=0.92, the doping concentration of the second collector region 62 is 0.92 times the doping concentration of the first collector region 61. The same is true for R=0.85 and R=0.6.

[0097] Region E1 is a region where the maximum temperature during clamping is low, and is a temperature region where the avalanche current is determined in the active region 110. Region E2 is a region where the maximum temperature during clamping is higher than that in region E1, and is a temperature region where the avalanche current is determined in the edge region 122. Clamping refers to a region where the collector voltage V CE This refers to a state in which the rate has increased and become stable.

[0098] 4B shows an example of a simulation result of the semiconductor device 100. The doping concentration of the first collector region 61 is set to 8E17 cm -3 , the doping concentration of the second collector region 62 is 6E17 cm -3 This shows the internal state when

[0099] By making the doping concentration of the first collector region 61 higher than that of the second collector region 62, an avalanche current is more likely to occur in the active region 110. of The breakdown voltage is the breakdown voltage of the semiconductor device 100. When the avalanche current occurs, the temperature is in region E1 of Fig. 4A, so the temperature does not rise abruptly and element destruction is unlikely to occur. However, the avalanche current eventually moves to the edge portion, and when the temperature rises to region E2, the semiconductor device 100 may be destroyed.

[0100] 4C shows an example of a simulation result of the semiconductor device according to the comparative example. -3 This shows the internal state when

[0101] By making the doping concentrations of the first collector region 61 and the second collector region 62 the same, an avalanche current is more likely to occur in the edge region 122. As a result, the withstand voltage of the edge region 122 becomes the withstand voltage of the semiconductor device of the comparative example. The avalanche current occurs in the corner portion on the guard ring portion 92 side of the well region 17. When the avalanche current occurs, the temperature rises suddenly in region E2 in FIG. 4A. Therefore, when the avalanche current flows, the temperature rises suddenly and the semiconductor device is destroyed.

[0102] 4A are as follows: When R=0.92, the extension length D of the first collector region 61 is set to 10 μm or more. When R=0.85, the extension length D of the first collector region 61 is set to 40 μm or less.

[0103] 5A shows an example of the characteristics of the semiconductor device 100. The graph in this example shows the waveforms of the gate voltage VGE, the collector voltage VCE, and the collector current ICE when a wiring inductance of about 10 to 20 μH is connected. The semiconductor device 100 in this example has a clamping time that is extended when the semiconductor device 100 includes a first collector region 61 having a higher doping concentration than the second collector region 62. This makes it difficult for the element to be destroyed by an overvoltage.

[0104] In the semiconductor device 100 of this embodiment, the doping concentration of the first collector region 61 is made higher than that of the second collector region 62, so that the hole density of the back surface 23 increases and the electron density from the front surface 21 increases. Therefore, in the active region 110, when the waveform of the collector voltage VCE shown in Fig. 5A is clamped to a constant value, the electron density of the drift region 18 increases, suppressing the expansion of the depletion layer and decreasing the breakdown voltage during clamping. Therefore, an avalanche current is more likely to occur in the active region 110, improving the breakdown voltage.

[0105] 5B shows an example of the characteristics of a semiconductor device according to a comparative example. In the semiconductor device of the comparative example, the doping concentration in the collector region is not gradient but is constant. Therefore, in the semiconductor device of the comparative example, when an avalanche current occurs in the edge region, the semiconductor device 100 is destroyed due to a rise in temperature. In FIG. 5B, if the wiring inductance is further increased, the semiconductor device 100 is destroyed.

[0106] Although the present invention has been described above using the embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It is clear to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the description of the claims that such modifications and improvements can also be included in the technical scope of the present invention. [Explanation of symbols]

[0107] 10 semiconductor substrate, 11 outer periphery, 12 emitter region, 14 base region, 15 contact region, 16 accumulation region, 17 well region, 18 drift region, 20 buffer region, 21 front surface, 23 back surface, 24 collector electrode, 25 connection portion, 28 upper portion, 29 end portion, 30 dummy trench portion, 31 extension portion, 32 dummy insulating film, 34 dummy conductive portion, 38 interlayer insulating film, 40 gate trench portion, 41 extension portion, 42 gate insulating film, 43 connection portion, 44 gate conductive portion, 50 Gate metal layer, 52 emitter electrode, 53 barrier metal layer, 54 contact hole, 55 contact hole, 56 contact hole, 57 plug, 61 first collector region, 62 second collector region, 71 mesa portion, 80 field plate electrode, 82 channel stopper electrode, 84 connection portion, 86 insulating film, 88 protective film, 92 guard ring portion, 94 channel stopper region, 100 semiconductor device, 110 active region, 120 non-active region, 122 edge region, 124 middle region, 140 gate pad

Claims

1. 1. A semiconductor device comprising an active region and an edge region, a drift region of a first conductivity type provided in a semiconductor substrate; a second conductivity type base region provided above the drift region; a first collector region of a second conductivity type provided in the active region below the drift region; a second collector region of a second conductivity type provided in the edge region below the drift region; a well region of a second conductivity type provided on the edge region side of the base region; Equipped with a doping concentration of the first collector region is greater than a doping concentration of the second collector region; When viewed from above, an area of ​​the first collector region is equal to or larger than an area of ​​the second collector region; The first collector region extends from the active region toward the edge region in a top view and terminates before an end of the well region on the edge region side. Semiconductor device.

2. 1. A semiconductor device comprising an active region and an edge region, a drift region of a first conductivity type provided in a semiconductor substrate; a second conductivity type base region provided above the drift region; a first collector region of a second conductivity type provided in the active region below the drift region; a second collector region of a second conductivity type provided in the edge region below the drift region; Equipped with a doping concentration of the first collector region is greater than a doping concentration of the second collector region; When viewed from above, an area of ​​the first collector region is equal to or larger than an area of ​​the second collector region; The doping concentration of the second collector region is 1E16 cm －３ Above, 5E18cm －３ is less than or equal to Semiconductor device.

3. 1. A semiconductor device comprising an active region and an edge region, a drift region of a first conductivity type provided in a semiconductor substrate; a second conductivity type base region provided above the drift region; a first collector region of a second conductivity type provided in the active region below the drift region; a second collector region of a second conductivity type provided in the edge region below the drift region; Equipped with a doping concentration of the first collector region is greater than a doping concentration of the second collector region; When viewed from above, an area of ​​the first collector region is equal to or larger than an area of ​​the second collector region; The first collector region is provided inside the active region when viewed from above. Semiconductor device.

4. 1. A semiconductor device comprising an active region and an edge region, a drift region of a first conductivity type provided in a semiconductor substrate; a second conductivity type base region provided above the drift region; a first collector region of a second conductivity type provided in the active region below the drift region; a second collector region of a second conductivity type provided in the edge region below the drift region; an emitter electrode provided above the semiconductor substrate and electrically connected to a front surface of the semiconductor substrate; a gate metal layer provided above the semiconductor substrate for setting a gate potential; Equipped with a doping concentration of the first collector region is greater than a doping concentration of the second collector region; When viewed from above, an area of ​​the first collector region is equal to or larger than an area of ​​the second collector region; A width B, which is a distance from the outer circumferential edge of the semiconductor substrate to an end of the second collector region, is greater than a width A, which is a distance from the outer circumferential edge of the semiconductor substrate to an end of the gate metal layer. Semiconductor device.

5. The doping concentration of the first collector region is 1E16 cm －３ Above, 5E18cm －３ is less than or equal to The semiconductor device according to claim 1 .

6. The doping concentration of the second collector region is 1E16 cm －３ Above, 5E18cm －３ is less than or equal to 5. The semiconductor device according to claim 1, 3 or 4.

7. an intermediate region provided between the active region and the edge region when viewed from above; The first collector region extends from the active region to the intermediate region when viewed from above. The semiconductor device according to claim 1 .

8. The first collector region is provided inside the active region when viewed from above.

5. The semiconductor device according to claim 2.

9. an emitter electrode provided above the semiconductor substrate and electrically connected to a front surface of the semiconductor substrate; a gate metal layer provided above the semiconductor substrate for setting a gate potential; Equipped with A width B, which is a distance from the outer circumferential edge of the semiconductor substrate to an end of the second collector region, is greater than a width A, which is a distance from the outer circumferential edge of the semiconductor substrate to an end of the gate metal layer. The semiconductor device according to claim 1 .

10. The doping concentration of the second collector region is less than or equal to 0.85 times the doping concentration of the first collector region.

10. The semiconductor device according to claim 4 or 9.

11. The difference between the width B and the width A is greater than 10 μm.

10. The semiconductor device according to claim 4 or 9.

12. The doping concentration of the second collector region is 0.85 to 0.9 times the doping concentration of the first collector region. The semiconductor device according to claim 11.

13. The thickness T of the semiconductor substrate in the depth direction satisfies B−A<αT, where 0.1<α<0.

5.

13. The semiconductor device according to claim 4, or any one of claims 9 to 12.

14. a guard ring portion of a second conductivity type provided above the drift region in the edge region; a channel stopper region provided above the drift region in the edge region and closer to the outer periphery of the semiconductor substrate than the guard ring portion; Equipped The semiconductor device according to claim 1 .

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