Silicon carbide semiconductor device and manufacturing method thereof

Abstract

To provide an SiC semiconductor device that suppresses lateral expansion of an impurity layer formed by ion implantation.SOLUTION: A defect introduced portion 21 is formed when an electric field blocking layer 4 is formed in a JFET portion 3 by ion implantation, such that a p-type impurity in a p-type ion implanted portion 20 is trapped in a defect during the activation annealing. As a result, the finally formed electric field blocking layer 4 can be configured with a substantially constant width.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a silicon carbide (hereinafter referred to as SiC) semiconductor device in which a semiconductor element is formed from SiC, and a method for manufacturing the same. [Background technology]

[0002] Conventionally, when forming a semiconductor device, an impurity layer of a desired conductivity type is formed in a silicon substrate by implanting ions into the underlying silicon substrate, but it is desired to form the impurity layer without spreading in the lateral direction. As a method for forming an impurity layer while suppressing such lateral spread, for example, there is an ion implantation method shown in Patent Document 1. In this ion implantation method, a mask with an opening is placed on a silicon substrate, and ions are implanted from above the mask under desired conditions to form an impurity doped region. Specifically, with the silicon substrate cooled to an extremely low temperature, an ion beam is implanted vertically so that most of the ions are channeled. As a result, the ions are introduced into the crystal while maintaining the implanted directionality by the motion forced to fix the traveling direction to the main crystal axis channel in the low-index plane orientation. Therefore, it is possible to form an impurity doped region without wrapping around the lower region of the mask during ion implantation. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 6-252082 Summary of the Invention [Problem to be solved by the invention]

[0004] In recent years, research on semiconductor devices using SiC has been progressing. Since SiC is harder than silicon, high-energy ion implantation is required. Currently, there are facilities capable of accelerating up to 5 MeV, and capable of implanting aluminum (Al) to a depth of about 8 μm. However, the problem occurs that the deeper the dopant spreads laterally as the ions collide with interstitial Si or C during implantation. In the case of SiC, since step-flow growth is performed, an off-substrate having an off-angle is used for crystal growth, and the main surface of the grown SiC also has an off-angle. Therefore, even if ion implantation is performed perpendicular to the main surface of SiC, ions will repeatedly collide with interstitial Si or C during implantation. If the dopant spreads laterally, the range of the impurity layer formed by ion implantation will not be the desired range, which will affect the semiconductor characteristics.

[0005] For example, in the case of a superjunction (hereinafter referred to as SJ) structure, the lower part of the p-type pillar formed by ion implantation expands laterally, narrowing the width of the lower part of the n-type pillar, which serves as a carrier flow path.

[0006] In addition, in order to maintain a low saturation current while achieving a low on-resistance, there is a structure in which JFET sections of different conductivity types and electric field blocking layers are alternately arranged in stripes to form a saturation current suppression layer. In this structure, when ion implantation is performed in the p-type epitaxial layer below the element structure such as a trench gate to form an n-type impurity layer at equal intervals, the lower part of the n-type impurity layer is formed by expanding laterally. As a result, the depletion layer extending from the p-type epitaxial layer to the n-type impurity layer does not extend enough to pinch off, and the saturation current increases.

[0007] In view of the above, an object of the present invention is to provide a SiC semiconductor device that suppresses lateral expansion of an impurity layer formed by ion implantation, and a method for manufacturing the same. [Means for solving the problem]

[0008] In order to achieve the above object, the invention described in claim 1 is a SiC semiconductor device, comprising a SiC substrate (1), a first impurity layer (3) made of an epitaxially grown film formed on the SiC substrate and made of one of a first conductivity type and a second conductivity type, and a second impurity layer (4) formed at a desired position of the first impurity layer and made of an ion-implanted layer and made of the other of the first conductivity type and the second conductivity type. The second impurity layer has a higher impurity concentration of the other of the first conductivity type and the second conductivity type on both sides of the width direction perpendicular to the thickness direction of the SiC substrate than in other regions of the second impurity layer, and the width of the second impurity layer is a predetermined width. The second impurity layer includes defect introduction portions (21) in which defects are formed on both sides in the width direction. .

[0009] In this way, the second impurity layer has a structure in which the impurity concentration is higher on both sides in the width direction than in other regions of the second impurity layer. In other words, when the second impurity layer is formed in the first impurity layer by ion implantation, a defect-introduced portion (21) is formed, and the second impurity layer is formed so that the impurity in the ion-implanted portion is trapped in the defects during activation annealing. This allows the second impurity layer to be finally formed with a predetermined width, for example, a substantially constant width.

[0010] Claim 6The invention described in is a method for manufacturing a SiC semiconductor device, which includes preparing a SiC substrate (1), forming a first impurity layer (3) of one of a first conductivity type and a second conductivity type on the SiC substrate by epitaxial growth, and forming a second impurity layer (4) of the other of the first conductivity type and the second conductivity type by ion implantation at a desired position of the first impurity layer. The formation of the second impurity layer includes forming a defect-introduced portion (21) in which defects are formed on both sides of a region in the width direction in which the second impurity layer is to be formed, with a direction perpendicular to the thickness direction of the SiC substrate as the width direction, forming an impurity ion-implanted portion (20) by implanting impurities into the region in which the second impurity layer is to be formed, and performing activation annealing of the impurities by heat treatment to trap the impurities in the defects in the region in which the defect-introduced portion is formed, thereby forming a second impurity layer of a predetermined width.

[0011] In this way, defect introduction parts are formed on both sides in the width direction of the region where the second impurity layer is to be formed. Therefore, the impurity of the ion implantation part can be trapped in the defects during activation annealing. This makes it possible to suppress the lateral spread of the second impurity layer, and the second impurity layer can be formed with a predetermined width, for example, a substantially constant width.

[0012] The reference symbols in parentheses attached to each component indicate an example of the correspondence between the component and specific components described in the embodiments described below. [Brief description of the drawings]

[0013] [Figure 1] 1 is a diagram showing a cross-sectional configuration of a SiC semiconductor device according to a first embodiment. [Diagram 2] 2 is a perspective cross-sectional view showing a part of the SiC semiconductor device shown in FIG. [Diagram 3] 4 is an enlarged cross-sectional view of a saturation current suppression layer taken along a plane parallel to the XZ plane passing through the electric field blocking layer. FIG. [Figure 4A] 3A to 3C are perspective cross-sectional views showing a manufacturing process of the SiC semiconductor device shown in FIG. 2. [Figure 4B] 4B is a perspective cross-sectional view showing a manufacturing process of the SiC semiconductor device subsequent to FIG. 4A. [Figure 4C] 4C is a perspective cross-sectional view showing a manufacturing process of the SiC semiconductor device subsequent to FIG. 4B. [Figure 4D] 4D is a perspective cross-sectional view showing a manufacturing process of the SiC semiconductor device subsequent to FIG. 4C. [Figure 4E] FIG. 4E is a perspective cross-sectional view showing a manufacturing process of the SiC semiconductor device subsequent to FIG. 4D. [Figure 4F] 4F is a perspective cross-sectional view showing a manufacturing process of the SiC semiconductor device subsequent to FIG. 4E. [Figure 4G] FIG. 4F is a perspective cross-sectional view showing a manufacturing process of the SiC semiconductor device subsequent to FIG. 4F. [Figure 5A] FIG. 4C is a cross-sectional view showing details of the step shown in FIG. 4B. [Figure 5B] FIG. 5B is a cross-sectional view showing a step following FIG. 5A. [Figure 5C] FIG. 5C is a cross-sectional view showing a step following FIG. 5B. [Figure 6A] FIG. 13 is a diagram showing a simulation result of lateral spread in the case where Al ions are implanted with an acceleration energy of 500 eV in a state in which no defect introduction part is formed. [Figure 6B] FIG. 13 is a diagram showing a simulation result of lateral spread in the case where Al ions are implanted with an acceleration energy of 1000 eV in a state in which no defect introduction part is formed. [Figure 6C] FIG. 13 is a diagram showing a simulation result of lateral spread in the case where Al ions are implanted with an acceleration energy of 2000 eV in a state in which no defect introduction part is formed. [Figure 6D] FIG. 13 is a diagram showing a simulation result of lateral spread in the case where Al ions are implanted with an acceleration energy of 3000 eV in a state in which no defect introduction part is formed. [Figure 7] FIG. 13 is a diagram showing changes in p-type impurity concentration after ion implantation and after activation annealing. [Figure 8] FIG. 11 is a perspective cross-sectional view showing a portion of a SiC semiconductor device according to a second embodiment. [Figure 9A] 11A to 11C are cross-sectional views showing a process for forming an electric field blocking layer explained in the third embodiment. [Figure 9B] FIG. 9B is a cross-sectional view showing the step of forming the electric field blocking layer subsequent to FIG. 9A. [Figure 9C] FIG. 9C is a cross-sectional view showing the step of forming the electric field blocking layer subsequent to FIG. 9B. [Figure 9D] FIG. 9B is a cross-sectional view showing the step of forming the electric field blocking layer subsequent to FIG. 9A. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, parts that are the same or equivalent to each other will be denoted by the same reference numerals.

[0015] (First embodiment) A first embodiment will be described. The SiC semiconductor device according to this embodiment is formed with an inversion-type vertical MOSFET having a trench gate structure with a saturation current suppression layer as shown in FIG. 1 and FIG. 2 as a semiconductor element. The vertical MOSFET shown in these figures is formed in a cell region of the SiC semiconductor device, and the SiC semiconductor device is configured by forming a peripheral breakdown voltage structure so as to surround the cell region, but only the vertical MOSFET is illustrated here. In the following, as shown in FIG. 1 and FIG. 2, the depth direction of the vertical MOSFET is the X direction, the width direction of the vertical MOSFET intersecting with the X direction is the Y direction, and the thickness direction or depth direction of the vertical MOSFET, i.e., the normal direction to the XY plane is the Z direction.

[0016] A vertical MOSFET is formed as a semiconductor element in the cell section. Figure 2 is a perspective cross-sectional view of a portion of the cell section, but in order to make the layout of each section easier to see, some of the configuration of the SiC semiconductor device has been omitted.

[0017] As shown in FIG. 1 and FIG. 2, the SiC semiconductor device includes a n-type semiconductor device made of SiC. +A mold substrate 1 is used as a semiconductor substrate. + The mold substrate 1 is, for example, a 4H-SiC substrate whose main surface is tilted at a predetermined off angle with respect to the (0001) plane, and in this embodiment, has an off angle with respect to the [11-20] direction.

[0018] n + On the main surface of the substrate 1, a n-type semiconductor layer constituting a part of the drift layer is formed. - A mold layer 2 is formed. + The substrate 1 has an n-type impurity concentration of, for example, 5.9×10 18 / cm 3 The thickness is set to 100 μm. - The mold layer 2 is n + It is composed of an epitaxially grown film made of SiC with a low impurity concentration on a mold substrate 1. - The dopant layer 2 has an n-type impurity concentration of, for example, 7.0×10 15 ~1.0×10 16 / cm 3 and the thickness is said to be 8.0 μm.

[0019] n - On the mold layer 2, an n-type JFET section 3 constituting a part of a drift layer made of SiC and a p-type electric field blocking layer 4 are formed. - The mold layer 2 is n + It is connected to the JFET section 3 at a position separated from the mold substrate 1 .

[0020] The JFET section 3 and the electric field blocking layer 4 constitute a saturation current suppression layer, and are both extended in the X direction and arranged alternately and repeatedly in the Y direction. + When viewed from the normal direction to the main surface of mold substrate 1, at least a part of JFET section 3 and electric field blocking layer 4 are each formed into a plurality of rectangular strips, in other words, stripes, which are arranged alternately.

[0021] In this embodiment, the JFET section 3 is formed below the electric field blocking layer 4. Therefore, the striped portions of the JFET section 3 are connected below the electric field blocking layer 4, and each striped portion is disposed between a plurality of electric field blocking layers 4.

[0022] Each stripe-shaped portion of the JFET section 3, i.e., each rectangular portion, has a width of, for example, 0.1 to 0.6 μm, preferably 0.1 μm, and the pitch between the portions is, for example, 0.6 to 2.0 μm. The thickness of the JFET section 3 is, for example, 1.5 μm, and the n-type impurity concentration is, for example, 1.5 μm. - It is higher than the mold layer 2, for example, 5.0×10 17 ~2.0×10 18 / cm 3 In the present embodiment, the JFET section 3 has a constant n-type impurity concentration in the depth direction.

[0023] The electric field blocking layer 4 is composed of a p-type impurity layer. As described above, the electric field blocking layer 4 is striped, and each rectangular portion of the striped electric field blocking layer 4 has a width of, for example, 0.15 to 1.4 μm and a thickness of, for example, 1.4 μm. The electric field blocking layer 4 has a p-type impurity concentration of, for example, 3.0×10 17 ~1.0×10 18 / cm 3 In this embodiment, the electric field blocking layer 4 has a constant p-type impurity concentration in the depth direction. As described below, the electric field blocking layer 4 is composed of an ion-implanted layer formed by ion-implanting p-type impurities into the JFET section 3. As shown in FIG. 5A and other figures, the electric field blocking layer 4 has defect-introduced sections 21 formed therein in which defects are introduced to suppress lateral expansion in addition to the p-type impurities. For this reason, the electric field blocking layer 4 has a substantially constant width in the depth direction, and the lower position, that is, the n -The bottom part on the mold layer 2 side has almost the same width as the upper part. However, the defects in the defect-introduced part 21 have been repaired by the activation heat treatment of the p-type ions implanted to form the electric field blocking layer 4, and the SiC semiconductor device is in a state where no or almost no defects remain. The electric field blocking layer 4 is also in a state where the n - The surface opposite to the mold layer 2 is flush with the surface of the JFET section 3 .

[0024] More specifically, the saturation current suppression layer has a detailed structure with a cross section as shown in FIG. 3, and each electric field blocking layer 4 has a substantially rectangular cross section as shown by the bold line in the figure. Each electric field blocking layer 4 is made up of an activation region activated after ion implantation of p-type impurities, and is formed by activating p-type impurities contained in p-type ion implantation section 20 shown in FIG. 5B, which will be described later, by activation annealing. At this time, the activation annealing is performed in a state in which defect introduction section 21 shown in FIG. 5A is formed in addition to p-type ion implantation section 20, so that the activation region has a substantially constant width. The reason why such an effect is obtained will be described later.

[0025] Furthermore, an n-type current spreading layer 6 that constitutes a part of the drift layer made of SiC is formed on the JFET section 3 and the electric field block layer 4. The n-type current spreading layer 6 is a layer that allows the current flowing through the channel to be diffused in the Y direction as described later. - The n-type impurity concentration is higher than that of the type layer 2. In this embodiment, the n-type current spreading layer 6 has an n-type impurity concentration equal to or higher than that of the JFET section 3, and has a thickness of 0.5 μm.

[0026] In this embodiment, n - The drift layer is composed of the n-type layer 2, the JFET section 3, and the n-type current spreading layer 6. However, the configuration of the drift layer is arbitrary. For example, - Type layers 2 and n + A buffer layer may be provided between the mold substrate 1 and the substrate.

[0027] A p-type base region 7 made of SiC is formed on the n-type current spreading layer 6. In addition, a n-type + The n-type source region 8 is formed. + The p-type source region 8 is formed on a portion of the p-type base region 7 corresponding to the n-type current spreading layer 6 .

[0028] The p-type base region 7 is thinner than the electric field blocking layer 4 and has a lower p-type impurity concentration. For example, the p-type impurity concentration is 3×10 17 / cm 3 The thickness is 0.3 μm. + The n-type source region 8 has a higher n-type impurity concentration than the n-type current spreading layer 6, and has a thickness of, for example, 0.5 μm.

[0029] Also, n + A plurality of p-type coupling layers 9 are formed so as to extend from the surface of the source region 8 through the p-type base region 7 and the n-type current spreading layer 6 to reach the electric field blocking layer 4. In this embodiment, the p-type coupling layers 9 are rectangular in shape with their longitudinal direction intersecting the striped portion of the JFET section 3 and the longitudinal direction of the electric field blocking layer 4, in this case the Y direction, and are arranged in a stripe shape by arranging a plurality of layers in the X direction. The p-type base region 7 and the electric field blocking layer 4 are electrically connected through the p-type coupling layers 9. In this embodiment, the n + Deep trenches 9a are formed from the surface of the source region 8 through the p-type base region 7 and the n-type current spreading layer 6 to reach the electric field blocking layer 4, and p-type linking layers 9 are formed so as to be embedded in the deep trenches 9a. The formation pitch of the p-type linking layers 9 is set independently of the cell pitch, which is the formation interval of the trench gate structure described later, but is set so as to suppress a decrease in channel density in the portion where the p-type linking layers 9 are formed. In this embodiment, the distance between the p-type linking layers 9 is, for example, 30 to 100 μm, and the width of each p-type linking layer 9 is, for example, 0.4 to 1.0 μm.

[0030] Furthermore, the p-type base region 7 and the n + The p-type base region 7 and the n-type source region 8 are connected to each other through the n-type current spreading layer 6, for example, with a width of 0.4 μm and a depth of 0.5 μm. + A gate trench 10 is formed to be 0.2 to 0.4 μm deeper than the total film thickness of the n-type source region 8. The p-type base region 7 and the n-type source region 8 are in contact with the side surfaces of the gate trench 10. + 2, the width direction of the gate trench 10 is the Y direction in FIG. 2, the same direction as the longitudinal direction of the JFET section 3 and the electric field blocking layer 4, and here the X direction is the longitudinal direction and the Z direction is the depth direction. As shown in FIG. 1 and FIG. 2, the gate trench 10 is formed in a stripe shape with a plurality of gate trenches 10 arranged at equal intervals in the Y direction, and p-type base region 7 and n-type source region 8 are disposed between each of the gate trenches. + A type source region 8 is arranged.

[0031] For example, the cell pitch, which is the interval between the trench gate structures formed in the gate trenches 10 as described later, that is, the cell pitch, which is the interval between adjacent gate trenches 10, is set to 0.6 to 2.0 μm. The width of the gate trenches 10 is arbitrary, but is set to be smaller than the cell pitch. In addition, the JFET pitch, which is the interval between the JFET sections 3, in other words, the interval between the electric field blocking layers 4, can be set independently of the cell pitch, and may be set under the condition that the JFET section 3 is pinched off as described later. In the present embodiment, the cell pitch and the JFET pitch are different from each other as shown in FIG. 1 and FIG. 2, but they may be equal to each other.

[0032] The portion of the p-type base region 7 located on the side of the gate trench 10 is converted into an n +The inner wall surface of the gate trench 10 including the channel region, which serves as a channel region connecting between the n-type source region 8 and the n-type current spreading layer 6, is covered with a gate insulating film 11. A gate electrode 12 made of doped poly-Si is formed on the surface of the gate insulating film 11, and the inside of the gate trench 10 is filled with the gate insulating film 11 and the gate electrode 12 to form a trench gate structure.

[0033] Also, as shown in Figure 1, + A source electrode 14 and the like are formed on the surface of the n-type source region 8 and the surface of the gate electrode 12 via an interlayer insulating film 13. The source electrode 14 is made of a plurality of metals, for example, Ni / Al. Among the plurality of metals, at least n-type SiC, specifically n + The portion in contact with the n-type source region 8 or the gate electrode 12 in the case of n-type doping is made of a metal capable of making ohmic contact with n-type SiC. At least the portion of the plurality of metals in contact with p-type SiC, specifically the p-type linking layer 9, is made of a metal capable of making ohmic contact with p-type SiC. The source electrode 14 is formed on the interlayer insulating film 13 and is thus electrically insulated from the SiC portion. However, the source electrode 14 can be electrically connected to the n-type SiC through a contact hole formed in the interlayer insulating film 13. + The p-type source region 8 and the p-type junction layer 9 are in electrical contact with each other.

[0034] On the other hand, n + The back side of the mold substrate 1 is + A drain electrode 15 is formed and electrically connected to the substrate 1. With this structure, an n-channel type inversion type vertical MOSFET with a trench gate structure is formed. A cell section is formed by arranging multiple cells of such vertical MOSFETs.

[0035] The SiC semiconductor device having the vertical MOSFET configured in this manner can be operated, for example, by applying a gate voltage Vg of 20 V to the gate electrode 12 with the source voltage Vs set to 0 V and the drain voltage Vd set to 1 to 1.5 V. That is, when the gate voltage Vg is applied, the vertical MOSFET operates in such a way that a channel region is formed in the p-type base region 7 in contact with the gate trench 10, and a current flows between the drain and source.

[0036] At this time, the JFET section 3 and the electric field blocking layer 4 function as a saturation current suppression layer, and by exerting a saturation current suppression effect, it is possible to maintain a low saturation current while achieving a low on-resistance. Specifically, since the striped portions of the JFET section 3 and the electric field blocking layer 4 are repeatedly formed alternately, the operation is as follows.

[0037] First, when the drain voltage Vd is a voltage applied during normal operation, such as 1 to 1.5 V, the depletion layer extending from the electric field blocking layer 4 side to the JFET section 3 extends only to a width smaller than the width of the striped portion of the JFET section 3. Therefore, even if the depletion layer extends into the JFET section 3, a current path is secured. And when the n-type impurity concentration of the JFET section 3 is n - Since the thickness of the insulating layer 1 is higher than that of the mold layer 2 and the current path can be configured to have a low resistance, it is possible to achieve a low on-resistance.

[0038] Also, when the drain voltage Vd becomes higher than the voltage during normal operation due to a load short circuit or the like, the depletion layer extending from the electric field blocking layer 4 side to the JFET section 3 extends beyond the width of the striped portion of the JFET section 3. Then, the JFET section 3 is immediately pinched off before the n-type current spreading layer 6. At this time, the relationship between the drain voltage Vd and the width of the depletion layer is determined based on the width and n-type impurity concentration of the striped portion of the JFET section 3. Therefore, the width and n-type impurity concentration of the striped portion of the JFET section 3 are set so that the JFET section 3 is pinched off when the voltage becomes slightly higher than the drain voltage Vd during normal operation. This makes it possible to pinch off the JFET section 3 even at a low drain voltage Vd. In particular, in this embodiment, the width of each striped JFET section 3 is approximately constant in the thickness direction, and is approximately the same width at the lower position as at the upper position. Therefore, the JFET section 3 can be pinched off accurately throughout the entire thickness direction. In this way, by making the JFET section 3 instantly pinch off when the drain voltage Vd becomes higher than the voltage during normal operation, a low saturation current can be maintained and the resistance of the SiC semiconductor device to load short circuits, etc. can be improved.

[0039] In this way, the JFET section 3 and the electric field blocking layer 4 function as a saturation current suppression layer and exert a saturation current suppression effect, making it possible to obtain a SiC semiconductor device that can achieve both low on-resistance and low saturation current.

[0040] Furthermore, by providing the electric field blocking layers 4 so as to sandwich the JFET section 3, the striped portions of the JFET section 3 and the electric field blocking layers 4 are repeatedly formed in an alternating manner. Therefore, even if the drain voltage Vd becomes high, the n -The extension of the depletion layer into the n-type layer 2 is suppressed by the electric field blocking layer 4, and it is possible to prevent the depletion layer from extending into the trench gate structure. Therefore, an electric field suppression effect that reduces the electric field applied to the gate insulating film 11 is exhibited, and the gate insulating film 11 is prevented from being destroyed, making it possible to obtain a highly reliable element with high withstand voltage. And, since the extension of the depletion layer into the trench gate structure can be prevented in this way, - The n-type impurity concentration in the type layer 2 and the JFET section 3 can be made relatively high, making it possible to achieve a low on-resistance.

[0041] Therefore, it is possible to obtain a SiC semiconductor device having a vertical MOSFET with low on-resistance and high reliability.

[0042] On the other hand, in the SiC semiconductor device of this embodiment, when the gate voltage Vg is not applied, a channel region is not formed, so that the semiconductor element is a normally-off type in which no current flows between the drain and source. Also, the JFET section 3 is a normally-on type because it does not pinch off unless the drain voltage Vd becomes higher than the voltage during normal operation, even when the gate voltage Vg is not applied.

[0043] Although the thickness, depth, and impurity concentration of each component of the vertical MOSFET have been described as an example, these are merely examples, and other thicknesses, depths, and impurity concentrations may be used as long as the above-mentioned operation is performed.

[0044] For example, the width of the JFET section 3, that is, the dimension in the arrangement direction in which a plurality of JFET sections 3 are arranged, may be set so as to obtain a saturation current suppression effect.

[0045] Furthermore, the width of electric field blocking layer 4, that is, the dimension in the arrangement direction of multiple electric field blocking layers 4, may be set taking into consideration low on-resistance and the electric field suppression effect. If the width of electric field blocking layer 4 is made large, the proportion of JFET section 3 formed will relatively decrease, which will increase the JFET resistance, so a smaller width is advantageous, but if it is too small, the electric field suppression effect will be reduced when the depletion layer spreads from the side surfaces of electric field blocking layer 4 during off-state. For this reason, the width of electric field blocking layer 4 may be set taking into consideration the realization of low on-resistance by reducing the JFET resistance, and the electric field suppression effect.

[0046] Next, a method for manufacturing a SiC semiconductor device including a vertical MOSFET with an n-channel type inversion trench gate structure according to this embodiment will be described with reference to cross-sectional views of the manufacturing process shown in FIGS. 4A to 4G.

[0047] [Step shown in FIG. 4A] First, a semiconductor substrate is made of, for example, 4H-SiC, the surface of which is a (0001) Si surface and has an off-angle of 4° with respect to the [11-20] direction. + A mold substrate 1 is prepared. Then, an n-type silicon nitride film is formed by epitaxial growth using a CVD (chemical vapor deposition) apparatus (not shown). + A n-type substrate 1 is formed on the main surface of the n-type substrate 1. - A mold layer 2 is formed. At this time, n + On the main surface of the mold substrate 1, - A so-called epitaxial substrate on which the type layer 2 is grown may be used. - A JFET portion 3 made of SiC is epitaxially grown on the mold layer 2 .

[0048] The epitaxial growth is carried out by introducing an n-type dopant, such as nitrogen (N2), in addition to the SiC source gases silane and propane.

[0049] [Step shown in FIG. 4B] Electric field blocking layer 4 is formed in a predetermined region of JFET section 3. At this time, electric field blocking layer 4 is formed by a method that suppresses lateral expansion of electric field blocking layer 4. This will be described with reference to Figs. 5A to 5C.

[0050] 5A, a step of forming defect introduction portion 21 is performed. After placing mask 16 made of an oxide film or the like, desired positions of mask 16 are opened. Specifically, assuming that the region shown by the thick dashed line in the figure is the target width of the region where electric field blocking layer 4 is to be formed, openings are made on both sides of mask 16 in the region where electric field blocking layer 4 is to be formed.

[0051] Then, a substance for forming defects is irradiated from above the mask 16. For example, electron beam irradiation or ion irradiation (ion implantation) using a cyclotron or the like is performed. This substance implantation forms defect induced portions 21 in which defects are introduced on both sides of the region where the electric field block layer 4 is to be formed, where the mask 16 is open. Defects can be formed at a desired depth by increasing the amount of electron beam irradiation when performing electron beam irradiation, or by increasing the ion dose when performing ion implantation, thereby setting a high dose, and adjusting the acceleration energy. In the case of ion implantation, ions that do not become impurities, such as silicon (Si) or carbon (C), can be used.

[0052] In addition, although the mask 16 is used for material irradiation here, defects can also be formed by applying heat through laser irradiation. In the case of laser irradiation, defects can be formed at the desired depth by scanning the laser over the area to be irradiated and adjusting the irradiation energy and focal position.

[0053] The defect density of the defect induced portion 21 is arbitrary, but is preferably the same as or may be different from the amount of p-type impurities implanted into the p-type ion implantation portion 20. For example, it is desirable that the defect density in the defect induced portion 21 is higher than the amount of p-type impurities when forming the p-type ion implantation portion 20. 5B, mask 16 is removed, and mask 17 is placed again to open an area of ​​mask 17 where electric field blocking layer 4 is to be formed. Then, p-type impurity ions, for example Al, are implanted to form p-type ion implanted portion 20 corresponding to the impurity ion implanted portion. After that, mask 17 is removed, and then, as shown in FIG. 5C, the surface is covered with, for example, carbon film 18, and heat treatment is performed to activate the implanted p-type impurity, thereby forming electric field blocking layer 4.

[0054] At this time, n of the p-type ion implanted portion 20 + Activation annealing is performed in a state where defect induced portions 21 are formed on both sides in the width direction, which is perpendicular to the thickness direction (Z direction) of the substrate 1. Therefore, in the region of the p-type ion implantation portion 20 where the defect induced portions 21 are formed, the lateral spread of the p-type impurity is suppressed. That is, when the p-type impurity is implanted, it repeatedly collides with interstitial Si or C, causing it to spread laterally, and the p-type impurity is concentrated in a particularly deep position, for example, deeper than the center of the thickness of the JFET portion 3. - On the mold layer 2 side, the p-type impurity is distributed outside the target width. However, if activation annealing is performed with defect induced portion 21 formed, the p-type impurity that had spread laterally to the defects contained in defect induced portion 21 is trapped, and the lateral spread of the p-type impurity is suppressed. As a result, electric field block layer 4 formed by the activated portion of p-type ion implantation portion 20 has a substantially constant width and is rectangular in the YZ plane, as shown by the bold line in Fig. 5C.

[0055] A simulation was carried out by simply implanting Al ions into SiC while changing the acceleration energy, and checking the lateral spread without forming defect-introduced portions 21. The results shown in Figs. 6A to 6D were obtained. Figs. 6A to 6D show simulations in which the acceleration energy was changed to 500 eV, 1000 eV, 2000 eV, and 3000 eV, and ions were implanted so that the normal direction of the main surface of the wafer coincided with the ion implantation direction. In the simulation, a mask was placed to limit the implantation position, and then Al ions were implanted into SiC. In all cases shown in Figs. 6A to 6D, the dose was 2.5 × 10 15 cm -2 The vertical axis X of each figure indicates the depth from the surface where ion implantation was performed, and the horizontal axis Y indicates the amount of lateral spread of the ion implantation. The impurity concentration after ion implantation is shown by the shade of hatching on the right side of each figure.

[0056] 6A to 6D, when activation annealing is performed without forming defect introduction portion 21, Al ions spread laterally, and the amount of lateral spread increases as the acceleration energy is increased to implant deeper. This is because the ions collide with interstitial atoms constituting SiC before being implanted deeply, causing the ions to spread laterally.

[0057] On the other hand, the p-type impurity concentration profile before and after activation annealing after ion implantation when the defect-introduced portion 21 is formed was examined by SIMS (secondary ion mass spectrometry). Here, the defect-introduced portion 21 was formed at a depth of about 0.2 μm, and ion implantation was performed with a range from the surface to a depth of 0.2 μm, resulting in a p-type impurity concentration of 1×10 20 cm -3 A simulation was performed assuming the formation of a p-type impurity layer of the above formula. Although the defect introduction part 21 is formed at a position of a predetermined depth, in the sense that the state in which the p-type impurity is trapped in the defect is confirmed, it can be considered to be the same as investigating the lateral spread of the p-type impurity. Figure 7 shows the results.

[0058] As shown by the dashed line in the figure, the impurity concentration of the p-type impurity is higher at a depth of about 0.2 μm after activation annealing compared to before activation annealing after ion implantation. This means that the p-type impurity is trapped in the defects contained in the defect introduction portion 21 and segregated.

[0059] From this result, it is found that by performing activation annealing in a state where defect induced portions 21 are formed on both sides of p-type ion implantation portion 20 as in this embodiment, it is possible to suppress the lateral spread of p-type impurities. From this, it can also be said that if activation annealing is performed in a state where defect induced portions 21 are formed as in this embodiment to form electric field block layer 4, it is possible to form electric field block layer 4 with a substantially constant width. If defect induced portions 21 are formed when electric field block layer 4 is formed as in this embodiment, electric field block layer 4 can be formed with a constant width while having a structure in which the p-type impurity concentration is higher on both sides in the width direction of electric field block layer 4 than in other regions of electric field block layer 4.

[0060] During activation annealing, the defects are repaired and the crystallinity is restored. However, if the defect density is high, the crystallinity is not completely restored and the defect-introduced portions 21 remain partially.

[0061] [Step shown in FIG. 4C] Subsequently, n-type SiC is epitaxially grown on the JFET section 3 and the electric field blocking layer 4 using a CVD apparatus (not shown), thereby forming an n-type current spreading layer 6.

[0062] [Step shown in FIG. 4D] Furthermore, a p-type base region 7 and an n-type current spreading layer 6 are provided on the p-type current spreading layer 6. + The source region 8 is epitaxially grown.

[0063] [Step shown in FIG. 4E] n +A mask (not shown) having an opening at a position corresponding to the p-type connection layer 9 is formed on the p-type source region 8. Then, the mask is used to perform anisotropic etching such as RIE (Reactive Ion Etching), thereby forming an n + The p-type source region 8, the p-type base region 7 and the n-type current spreading layer 6 are removed in that order to form a deep trench 9a that reaches the JFET section 3 and the electric field blocking layer 4. Then, the mask is removed.

[0064] [Step shown in FIG. 4F] Using a CVD apparatus (not shown), p-type SiC is epitaxially grown so as to fill deep trench 9a, and then etched back to leave p-type SiC only in deep trench 9a, thereby forming p-type coupling layer 9.

[0065] [Step shown in FIG. 4G] n + After a mask (not shown) is formed on the source region 8 and the like, an opening is made in the mask in a region where the gate trench 10 is to be formed. Then, the mask is used to perform anisotropic etching such as RIE, thereby forming the gate trench 10.

[0066] Thereafter, the mask is removed and then, for example, thermal oxidation is performed to form a gate insulating film 11. The gate insulating film 11 covers the inner wall surface of the gate trench 10 and the n + The gate electrode 12 is formed by depositing polysilicon doped with p-type or n-type impurities and then etching it back to leave the polysilicon at least in the gate trench 10. This completes the trench gate structure.

[0067] Although the subsequent steps are not shown, the following steps are carried out. That is, an interlayer insulating film 13 made of, for example, an oxide film is formed so as to cover the surfaces of the gate electrode 12 and the gate insulating film 11. In addition, a mask (not shown) is used to apply n-type masking to the interlayer insulating film 13. +Contact holes are formed to expose the n-type source region 8 and the p-type coupling layer 9. Then, an electrode material made of, for example, a laminated structure of multiple metals is formed on the surface of the interlayer insulating film 13, and the electrode material is patterned to form a source electrode 14. + A drain electrode 15 is formed on the back surface side of the mold substrate 1. In this manner, the SiC semiconductor device according to this embodiment is completed.

[0068] As described above, in the SiC semiconductor device of this embodiment, when the electric field blocking layer 4 is formed in the JFET section 3 by ion implantation, the defect introduction section 21 is formed, so that the p-type impurity of the p-type ion implantation section 20 can be trapped in the defects during activation annealing. This makes it possible to configure the electric field blocking layer 4 that is finally formed to have a substantially constant width. Therefore, in a structure including a saturation current suppression layer, it is possible to suppress the reduction in the width of the JFET section 3 caused by the electric field blocking layer 4 expanding laterally. Therefore, it is possible to suppress an increase in the on-resistance caused by the reduction in the width of the JFET section 3.

[0069] (Modification of the first embodiment) (1) In the first embodiment, the electric field blocking layer 4 is formed by an ion implantation layer, that is, the electric field blocking layer 4 is formed by ion implanting p-type impurities after the JFET section 3 is formed. - The JFET section 3 may be formed by epitaxially growing the layer on the mold layer 2 and then ion-implanting n-type impurities.

[0070] In this case, when forming an n-type ion implantation portion in the electric field blocking layer 4, by forming defect introduction portions 21 on both sides of the width of the n-type ion implantation portion, the lateral expansion of the JFET portion 3 can be suppressed, and the JFET portion 3 can be formed with an approximately constant width.

[0071] In this way, it is also possible to form the electric field blocking layer 4 first, and then form the JFET section 3 by ion implantation. In this case, the width of the JFET section 3 can be made almost constant, so it is possible to prevent the width of the electric field blocking layer 4 from being reduced due to the width of the JFET section 3 expanding at the lower position. This makes it possible to prevent an increase in saturation current due to pinch-off caused by insufficient extension of the depletion layer from the electric field blocking layer 4 to the JFET section 3 side.

[0072] (2) In the first embodiment, the longitudinal direction of the JFET section 3 and the electric field blocking layer 4, which have a longitudinal direction in one direction, is the same as the longitudinal direction of the trench gate structure, but these may be in different directions, i.e., they may intersect.

[0073] Second embodiment A second embodiment will be described. This embodiment is different from the first embodiment in that it has an SJ structure, and is otherwise similar to the first embodiment, so only the differences from the first embodiment will be described.

[0074] As shown in Figure 8, n - An n-type pillar 50 and a p-type pillar 51 constituting an SJ structure are formed on the gate layer 2. The n-type pillar 50 and the p-type pillar 51 are both extended in the Y direction and are arranged alternately and repeatedly in the X direction. + When viewed from the normal direction to the main surface of the substrate 1, the n-pillars 50 and the p-pillars 51 are each formed into a plurality of rectangular strips, in other words, stripes, and are arranged alternately. The widths and impurity concentrations of the n-pillars 50 and the p-pillars 51 are set to be charge balanced.

[0075] Then, a saturation current suppression layer made up of a JFET section 3 and an electric field blocking layer 4 is formed on the SJ structure, and further each section constituting the vertical MOSFET described in the first embodiment is formed.

[0076] Thus, in comparison with the first embodiment, n - An SJ structure is provided between the n-type layer 2 and the saturation current suppression layer. By providing such an SJ structure, the depletion layer can be expanded between the n-type pillar 50 and the p-type pillar 51, and the breakdown voltage can be ensured, so that the impurity concentration of the n-type pillar 50 can be increased and the on-resistance can be reduced.

[0077] The SJ structure is, for example, - They can be formed by epitaxially growing either the n-type pillars 50 or the p-type pillars 51 on the dopant layer 2, and then ion-implanting the other. In this case as well, when implanting n-type or p-type impurities into the epitaxially grown impurity layer, defect introduction portions 21 are formed on both sides of the ion-implanted portion in the width direction. This makes it possible to suppress the lateral spread of the n-type pillars 50 and the p-type pillars 51, and allows the n-type pillars 50 and the p-type pillars 51 to be formed with a substantially constant width.

[0078] (Modification of the second embodiment) (1) When an SJ structure is provided as in the second embodiment, the arrangement direction of the n-type pillars 50 and the p-type pillars 51 constituting the SJ structure may be set to the off direction, that is, the direction along which an off angle is provided between the primary surface and the (0001) plane.

[0079] (2) In the second embodiment, the longitudinal direction of the n-type pillars 50 and p-type pillars 51 constituting the SJ structure is not limited to a direction perpendicular to the longitudinal direction of the JFET section 3 and the electric field blocking layer 4 constituting the saturation current suppression layer. In other words, they may be in a different direction, such as a direction intersecting with the perpendicular direction or the same direction. When they are in the same direction, for example, the pitch of the n-type pillars 50 and the JFET section 3 is matched so that the JFET section 3 is disposed above the n-type pillars 50. In addition, the pitch of the p-type pillars 51 and the electric field blocking layer 4 is matched so that the electric field blocking layer 4 is formed above the p-type pillars 51. The widths of the n-type pillars 50 and the p-type pillars 51 are determined in consideration of a charge balance suitable for forming an SJ structure, and the widths of the JFET section 3 and the electric field blocking layer 4 are suitable for forming a saturation current suppression layer.

[0080] In such a configuration, the SJ structure is formed by epitaxially growing either the n-type pillar 50 or the p-type pillar 51, and the other is formed by ion implantation into the epitaxially grown one. Similarly, the saturation current suppression layer is formed by epitaxially growing either the JFET section 3 or the electric field blocking layer 4, and the other is formed by ion implantation into the epitaxially grown one. In this case, the effect of the first embodiment can be obtained by forming the defect introduction section 21 during the ion implantation for forming the SJ structure or the ion implantation for forming the saturation current suppression layer.

[0081] In this embodiment, n-pillars 50 and JFET section 3 are connected, and p-pillars 51 and electric field blocking layer 4 are connected, so the pitch of n-pillars 50 and JFET section 3 are aligned. However, if JFET section 3 is formed below electric field blocking layer 4 and electric field blocking layer 4 and p-pillars 51 are not connected, it is not necessary to match the pitch of n-pillars 50 and JFET section 3.

[0082] (3) In the second embodiment, a structure is provided with both an SJ structure and a saturation current suppression layer. However, a structure may be provided with only an SJ structure without the saturation current suppression layer.

[0083] Third embodiment A third embodiment will be described. This embodiment is the same as the first and second embodiments except for the ion implantation method, and therefore only the differences from the first and second embodiments will be described.

[0084] In this embodiment, when an impurity layer is formed by ion implantation, the relationship between the formation position of defect induced portions 21 formed on both sides of the impurity layer in the width direction and the formation position of the impurity layer is set in a self-aligned manner. Specifically, in the first and second embodiments, ion implantation for forming the impurity layer is performed as shown in Figs. 9A to 9D. Note that, although an example of ion implantation for forming electric field block layer 4 in JFET section 3 will be described here, the same applies to the case of forming impurity layers for JFET section 3, n-type pillar 50, p-type pillar 51, etc. by ion implantation.

[0085] 9A, a mask 40 corresponding to a first mask is placed using an oxide film or the like, and then openings are formed at desired positions in the mask 40. Specifically, openings 40a corresponding to the first openings are formed in the regions of the mask 40 where the p-type ion implantation portions 20 described in the first embodiment are to be formed, and openings 40b corresponding to the second openings are formed in the regions where the defect introduction portions 21 are to be formed. At this time, since the openings are formed in the mask 40 at the same time, it is possible to form the openings 40a and 40b at a constant interval without positional misalignment.

[0086] 9B, resist 41 corresponding to a second mask is applied so as to cover mask 40 and openings 40a and 40b, and then the resist 41 is exposed and developed to leave the portion formed above opening 40a and to expose opening 40b. A defect-forming substance is then irradiated from above mask 40 and resist 41 to form defect introduction portion 21.

[0087] Next, after removing resist 41, resist 42 corresponding to a third mask is applied again as shown in Fig. 9C, and by exposure and development, the portion of resist 42 formed above opening 40b is left and opening 40a is exposed. Then, as shown in Fig. 9D, p-type ion-implanted portion 20 is formed by ion-implanting, for example, Al as a p-type impurity. Thereafter, the implanted ions are activated by heat treatment to form electric field block layer 4.

[0088] In this case as well, activation is performed with defect induced parts 21 formed on both sides of p-type ion implantation part 20 in the width direction, so that the lateral spread of the p-type impurity is suppressed in the vicinity of defect induced parts 21 in p-type ion implantation part 20. As a result, electric field block layer 4 formed by the activated parts of p-type ion implantation part 20 has a substantially constant width, as shown in Fig. 5C described in the first embodiment.

[0089] When the electric field blocking layer 4 is formed in this manner, the openings 40a and 40b are formed without any misalignment, so that the p-type ion implanted portion 20 and the defect induced portion 21 can be formed in an accurate positional relationship without any misalignment. In other words, the p-type ion implanted portion 20 and the defect induced portion 21 can be formed in a self-aligned manner. Therefore, the electric field blocking layer 4 can be formed with higher accuracy.

[0090] (Other embodiments) Although the present disclosure has been described based on the above-described embodiment, it is not limited to the embodiment, and includes various modifications and modifications within the equivalent range. In addition, various combinations and forms, and other combinations and forms including only one element, more than one element, or less than one element, are also within the scope and concept of the present disclosure.

[0091] (1) For example, in each of the above embodiments, the defect introduction portion 21 is formed in the ion implantation for forming a structure having a saturation current suppression layer or an SJ structure, so that the width of the impurity layer formed by ion implantation is made almost constant. However, this is merely an example, and the present invention can be applied to a structure in which a first impurity layer of one conductivity type composed of an epitaxial growth film is formed on a SiC substrate, and a second impurity layer of the other conductivity type is formed of an ion implantation layer with a predetermined width on the first impurity layer. That is, when the second impurity layer is formed on the first impurity layer by ion implantation, the defect introduction portion 21 may be formed on both sides in the width direction of the second impurity layer. In each of the above embodiments, the second impurity layer is configured to have an almost constant width, but when it is desired to control the width of the second impurity layer to a desired predetermined width, the defect introduction portion 21 may be formed.

[0092] Furthermore, by forming the second impurity layer under such conditions, the second impurity layer can be prevented from spreading laterally at a lower position, and the width of the second impurity layer can be made approximately constant, making it possible to stabilize the device characteristics.

[0093] In each of the above embodiments, the defect introduction portion 21 is formed and then the p-type ion implanted portion 20 corresponding to the impurity ion implanted portion is formed, but the order may be reversed.

[0094] (2) Also, in the modified example of the first embodiment and the modified example of the second embodiment, the JFET section 3 may be structured to be deeper than the electric field blocking layer 4. That is, even in a manufacturing method in which the electric field blocking layer 4 is formed first and then the JFET section 3 is formed by ion implantation, the JFET section 3 can be made to be the same depth as the electric field blocking layer 4, or the JFET section 3 can be made to be deeper than the electric field blocking layer 4.

[0095] In this way, when the JFET section 3 is deeper than the electric field blocking layer 4, n - In other words, it is possible to suppress the amount of extension of the two-dimensional depletion layer that extends two-dimensionally toward the n-type layer 2 side. - This further prevents the depletion layer extending into the type layer 2 from penetrating below the JFET section 3. This prevents the narrowing of the current exit in the JFET section 3, making it possible to achieve a low on-resistance.

[0096] (3) In addition, the impurity concentration, thickness, width, and other dimensions of each part constituting the SiC semiconductor device shown in each of the above embodiments are merely examples. Furthermore, although 4H is used as an example of the crystal polytype, a SiC substrate of another crystal polytype, such as 6H, may also be used.

[0097] (4) In addition, in the above embodiments, an n-channel type vertical MOSFET in which the first conductivity type is n-type and the second conductivity type is p-type has been described as an example, but a p-channel type vertical MOSFET in which the conductivity types of each component are inverted may also be used. In the above description, a vertical MOSFET has been described as an example of a semiconductor element, but the present invention can also be applied to an IGBT having a similar structure. In the case of an n-channel type IGBT, the n-channel type IGBT may be replaced with an n-channel type IGBT in the above embodiments. + The only difference is that the conductivity type of the substrate 1 is changed from n-type to p-type, and other structures and manufacturing methods are the same as those of the above-mentioned embodiments. Also, although a trench gate structure is given as an example, a planar type MOSFET or IGBT may be used, or an element other than a MOSFET or IGBT may be used.

[0098] (5) When indicating the crystal orientation, etc., a bar (-) should normally be placed above the desired number. However, due to limitations on expression based on electronic filing, in this specification, a bar will be placed before the desired number. [Explanation of symbols]

[0099] 1n + Mold Board 3 JFET section 4 Electric field blocking layer 20 p-type ion implantation section 21 Defect introduction 40 Mask 40a, 40b opening 41, 42 Resist 50 n-type pillar 51 p-type pillar

Claims

1. 1. A silicon carbide semiconductor device, comprising: A silicon carbide substrate (1); A first impurity layer (3) composed of an epitaxially grown film formed on the silicon carbide substrate and composed of one of a first conductivity type and a second conductivity type; a second impurity layer (4) formed at a desired position of the first impurity layer, the second impurity layer being constituted by an ion implantation layer and being constituted by the other of the first conductivity type and the second conductivity type; In the second impurity layer, a concentration of the other of the first conductivity type and the second conductivity type contained in the second impurity layer is higher than that of another region of the second impurity layer on both sides of a width direction of the second impurity layer that is a direction perpendicular to a thickness direction of the silicon carbide substrate, and the width of the second impurity layer is a predetermined width, the second impurity layer includes a defect introduction portion (21) in which a defect is formed on both sides in the width direction.

2. The silicon carbide semiconductor device according to claim 1 , wherein said second impurity layer has a constant width.

3. It has an inversion type semiconductor element, the silicon carbide substrate having a first or second conductivity type; A first conductivity type layer (2) formed on the silicon carbide substrate and made of first conductivity type silicon carbide having a lower impurity concentration than the silicon carbide substrate; a saturation current suppression layer (3, 4) including an electric field blocking layer (4) made of silicon carbide of a second conductivity type, the electric field blocking layer being arranged in a stripe shape with one direction as a longitudinal direction, and a JFET section (3) made of silicon carbide of the first conductivity type having a portion in which a plurality of electric field blocking layers are arranged in a stripe shape alternately with the electric field blocking layer with the one direction as a longitudinal direction; a current spreading layer (6) formed on the saturation current suppression layer and made of first conductivity type silicon carbide having a first conductivity type impurity concentration higher than that of the first conductivity type layer; a base region (7) made of second conductivity type silicon carbide formed on the current spreading layer; a source region (8) made of first conductivity type silicon carbide formed on the base region and having a first conductivity type impurity concentration higher than that of the first conductivity type layer; a gate insulating film (11) formed on the surface of the base region between the source region and the current spreading layer; A gate electrode (12) is disposed on the gate insulating film and is formed with one direction as a longitudinal direction; an interlayer insulating film (13) covering the gate electrode and the gate insulating film and having a contact hole formed therein; a source electrode (14) electrically connected to the source region through the contact hole; A drain electrode (15) formed on the back surface side of the silicon carbide substrate, 3 . The silicon carbide semiconductor device according to claim 1 , wherein one of said JFET portion and said electric field blocking layer is said first impurity layer, and the other is said second impurity layer.

4. 4. The silicon carbide semiconductor device according to claim 3, further comprising a superjunction structure (50, 51) between the first conductivity type layer and the saturation current suppression layer, the superjunction structure being configured by alternately arranging a plurality of first conductivity type pillars (50) and second conductivity type pillars (51) in a stripe shape, the first conductivity type pillars (50) and second conductivity type pillars (51) extending in one direction as a longitudinal direction.

5. It has an inversion type semiconductor element, the silicon carbide substrate having a first or second conductivity type; A first conductivity type layer (2) formed on the silicon carbide substrate and made of first conductivity type silicon carbide having a lower impurity concentration than the silicon carbide substrate; a superjunction structure (50, 51) formed on the first conductive type layer and configured by alternately arranging a plurality of first conductive type pillars (50) and second conductive type pillars (51) extending in one direction as a longitudinal direction in a stripe shape; a current spreading layer (6) formed on the superjunction structure and made of first conductivity type silicon carbide having a first conductivity type impurity concentration higher than that of the first conductivity type layer; a base region (7) made of second conductivity type silicon carbide formed on the current spreading layer; a source region (8) made of first conductivity type silicon carbide formed on the base region and having a first conductivity type impurity concentration higher than that of the first conductivity type layer; a gate insulating film (11) formed on the surface of the base region between the source region and the current spreading layer; A gate electrode (12) is disposed on the gate insulating film and is formed with one direction as a longitudinal direction; an interlayer insulating film (13) covering the gate electrode and the gate insulating film and having a contact hole formed therein; a source electrode (14) electrically connected to the source region through the contact hole; A drain electrode (15) formed on the back surface side of the silicon carbide substrate, 3 . The silicon carbide semiconductor device according to claim 1 , wherein one of the first conductivity type pillar and the second conductivity type pillar is the first impurity layer, and the other is the second impurity layer.

6. A method for manufacturing a silicon carbide semiconductor device, comprising: Providing a silicon carbide substrate (1); forming a first impurity layer (3) having one of a first conductivity type and a second conductivity type by epitaxial growth on the silicon carbide substrate; forming a second impurity layer (4) composed of the other of the first conductivity type and the second conductivity type by ion implantation at a desired position of the first impurity layer; In forming the second impurity layer, forming a defect introduction portion (21) in which defects are formed on both sides of a region to be formed in the second impurity layer in a width direction perpendicular to a thickness direction of the silicon carbide substrate; forming an impurity ion implanted portion (20) by implanting impurities into a region in which the second impurity layer is to be formed; performing activation annealing of the impurity by heat treatment, and trapping the impurity in the defects in the region where the defect introduction portion is formed, thereby forming the second impurity layer of a predetermined width.

7. In forming the defect introduction portion and the impurity ion implantation portion, forming a first mask (40) on the first impurity layer; forming a first opening (40a) in a region of the first mask where the impurity ion implantation portion is to be formed and forming a second opening (40b) in a region of the first mask where the defect introduction portion is to be formed; disposing a second mask (41) that covers the first opening and exposes the second opening, and irradiating a material from above the first mask and the second mask to form the defect introduction portion; 7. The method for manufacturing a silicon carbide semiconductor device according to claim 6, further comprising: disposing a third mask (42) covering said second opening while exposing said first opening, and performing ion implantation of an impurity from above said first mask and said third mask, thereby forming said impurity ion implanted portion.

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