Semiconductor device manufacturing method

Abstract

To achieve a reduction in area of a semiconductor device.SOLUTION: A semiconductor device has: a first impurity region of a first conductivity type disposed on a semiconductor substrate SB; and a second impurity region of a second conductivity type disposed on the first impurity region. Furthermore, the semiconductor device has a first gate trench GT and a second gate trench GT which are formed from the second impurity region over the first impurity region. A column region CR of the second conductivity type is formed in the first impurity region between the first gate trench GT and the second gate trench GT, a depth of a bottom portion of the column region being deeper than a depth of each of a bottom portion of the first gate trench GT and the second gate trench GT. Furthermore, in the semiconductor device, a third impurity region of the first conductivity type, which is formed in the first impurity region and covers the bottom portion of the first gate trench GT, is formed. The third impurity region is disposed between the first gate trench GT and the column region CR.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to a method for manufacturing a semiconductor device, and can be suitably used, for example, in a method for manufacturing a semiconductor device including a power MOS semiconductor element. [Background technology]

[0002] In semiconductor elements such as power MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), there is a PN junction structure called a super-junction (SJ) to improve the breakdown voltage. For example, in the case of an n-type MOSFET, by alternately arranging p-type column regions CR in an n-type drift region, the periphery of the p-type column regions CR is depleted, thereby improving the breakdown voltage.

[0003] To reduce the on-resistance in such an SJ structure, it is necessary to reduce the pitch of the gate trench GT. Figure 2 is a cross-sectional view showing the problem of the comparative example. By reducing the gate trench GT pitch, the column region CR comes into contact with the gate trench GT and blocks the current path. This increases the on-resistance.

[0004] The column region CR is formed by ion implantation. However, there is a limit to how fine the ion implantation mask can be made, and the implanted impurities are diffused by the subsequent heat treatment, so it is necessary to take measures to prevent the column region CR from coming into contact with the gate trench GT.

[0005] Patent Document 1 describes that in the case of an n-type MOSFET, by two-dimensionally arranging p-type column regions CR in an n-type drift region, the periphery of the p-type column regions CR is depleted, thereby improving the breakdown voltage. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] JP 2010-016309 A Summary of the Invention [Problem to be solved by the invention]

[0007] The problem is that by reducing the pitch of the gate trenches, the lateral expansion of the column region comes into contact with the gate trenches, obstructing the current path. In other words, there is room for improvement in terms of improving the characteristics of the semiconductor device.

[0008] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0009] A semiconductor device according to one embodiment includes a semiconductor substrate, a first impurity region of a first conductivity type formed on the semiconductor substrate, a second impurity region of a second conductivity type formed on the first impurity region, a first gate trench and a second gate trench formed from the second impurity region to the first impurity region, a gate electrode formed in each of the first gate trench and the second gate trench via a gate insulating film, a column region of the second conductivity type formed in the first impurity region between the first gate trench and the second gate trench and having a bottom depth deeper than the bottom depths of the first gate trench and the second gate trench, and a third impurity region of the first conductivity type formed in the first impurity region and covering a bottom of the first gate trench, the third impurity region being formed between the first gate trench and the column region.

[0010] A method for manufacturing a semiconductor device according to an embodiment includes the following steps: A semiconductor substrate is prepared. A first impurity region (drift region) of a first conductivity type is formed on the semiconductor substrate by epitaxial growth. A first gate trench and a second gate trench are formed throughout the first impurity region. Ion implantation is performed to form a third impurity region (column control region) of a first conductivity type in the first impurity region covering the bottom of the first gate trench. A gate insulating film is formed on each of the inner walls of the first gate trench and the second gate trench. A gate electrode is embedded in each of the first gate trench and the second gate trench via a gate insulating film. A second impurity region (base region) of a second conductivity type and a source region of the first conductivity type are formed in this order below the first impurity region, leaving the first impurity region. A column region of a second conductivity type having a bottom depth deeper than the bottom depths of the first gate trench and the second gate trench is formed by ion implantation within the first impurity region between the first gate trench and the second gate trench. Effect of the Invention

[0011] According to the method for manufacturing a semiconductor device according to the embodiment, the characteristics of the semiconductor device can be improved. [Brief description of the drawings]

[0012] [Figure 1] FIG. 1 is a plan view of a semiconductor chip according to a first embodiment. [Diagram 2] FIG. 2 is a partial cross-sectional view for explaining a semiconductor device according to a comparative example. [Diagram 3] FIG. 3 is a partial cross-sectional view of the semiconductor device according to the first embodiment. [Figure 4] FIG. 4 is a partial cross-sectional view showing a step of a method for manufacturing a semiconductor device in the first embodiment. [Diagram 5] FIG. 5 is a partial cross-sectional view showing a step performed after the step shown in FIG. 4 in the first embodiment. [Figure 6]FIG. 6 is a partial cross-sectional view showing a step performed after the step shown in FIG. 5 in the first embodiment. [Figure 7] FIG. 7 is a partial cross-sectional view showing a step performed after the step shown in FIG. 6 in the first embodiment. [Figure 8] FIG. 8 is a partial cross-sectional view showing a step performed after the step shown in FIG. 7 in the first embodiment. [Figure 9] FIG. 9 is a partial cross-sectional view showing a step performed after the step shown in FIG. 8 in the first embodiment. [Figure 10] FIG. 10 is a partial cross-sectional view showing a step performed after the step shown in FIG. 9 in the first embodiment. [Figure 11] FIG. 11 is a partial plan view of the semiconductor device according to the first embodiment. [Figure 12] FIG. 12 is a partial plan view of a modified example of the semiconductor device according to the first embodiment. [Figure 13] FIG. 13 is a partial plan view of a modified example of the semiconductor device according to the first embodiment. [Figure 14] FIG. 14 is a partial cross-sectional view of a semiconductor device according to the second embodiment. [Figure 15] FIG. 15 is a partial cross-sectional view showing a step of a method for manufacturing a semiconductor device in the second embodiment. [Figure 16] FIG. 16 is a partial cross-sectional view showing a step performed after the step shown in FIG. 15 in the second embodiment. [Figure 17] FIG. 17 is a partial cross-sectional view showing a step performed after the step shown in FIG. 16 in the second embodiment. [Figure 18] FIG. 18 is a partial cross-sectional view showing a step performed after the step shown in FIG. 17 in the second embodiment. [Figure 19] FIG. 19 is a partial cross-sectional view showing a step performed after the step shown in FIG. 18 in the second embodiment. [Figure 20] FIG. 20 is a partial cross-sectional view showing a step performed after the step shown in FIG. 19 in the second embodiment. [Figure 21]FIG. 21 is a partial cross-sectional view showing a step performed after the step shown in FIG. 20 in the second embodiment. [Figure 22] FIG. 22 is a partial cross-sectional view showing a step performed after the step shown in FIG. 21 in the second embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] In the following embodiments, when necessary for convenience, the description will be divided into a plurality of sections or embodiments, but unless otherwise specified, they are not unrelated to each other, and one is a partial or complete modification, detail, supplementary explanation, etc. of the other. In addition, in the following embodiments, when the number of elements (including the number, numerical value, amount, range, etc.) is mentioned, it is not limited to the specific number, except when specifically specified or when it is clearly limited to a specific number in principle, and it may be more than or less than the specific number. Furthermore, in the following embodiments, the components (including element steps, etc.) are not necessarily essential, except when specifically specified or when it is clearly considered to be essential in principle. Similarly, in the following embodiments, when the shape, positional relationship, etc. of the components, etc. are mentioned, it is considered to include those that are substantially similar to or similar to the shape, etc., except when specifically specified or when it is clearly considered not to be essential in principle. This also applies to the above numerical values ​​and ranges.

[0014] Hereinafter, the embodiments will be described in detail with reference to the drawings. In all the drawings for explaining the embodiments, the same reference numerals are used for the members having the same functions, and the repeated explanations are omitted. In the following embodiments, the explanations of the same or similar parts will not be repeated as a rule unless it is particularly necessary.

[0015] In the drawings used in the embodiments, hatching may be omitted even in cross-sectional views in order to make the drawings easier to understand, and hatching may be added even in plan views in order to make the drawings easier to understand.

[0016] (Embodiment 1) The semiconductor device according to the first embodiment includes a power MOSFET formed on a semiconductor chip. The power MOSFET has a source, a drain, and a gate.

[0017] <Related Technology> First, a semiconductor device having a power MOSFET according to related technology will be described. Here, the related technology refers to technology that has been investigated by the inventors of the present application, and does not mean publicly known technology.

[0018] FIG. 2 is a partial cross-sectional view of the semiconductor device SDV (see FIG. 1) according to the related art.

[0019] As shown in FIG. 2, by arranging p-type column regions CR two-dimensionally in an n-type drift region DRR, the periphery of the p-type column regions CR is depleted, thereby improving the breakdown voltage.

[0020] A first impurity region (drift region DRR) of a first conductivity type is disposed on the semiconductor substrate SB. A second impurity region (base region BR) of a second conductivity type, and a first gate trench GT and a second gate trench GT formed from the second impurity region (base region BR) to the first impurity region (drift region DRR) are disposed on the first impurity region (drift region DRR). A gate electrode GE formed via a gate insulating film GI is disposed inside each of the first gate trench GT and the second gate trench GT. A column region CR of a second conductivity type is disposed between the first gate trench GT and the second gate trench GT, and is formed inside the first impurity region (drift region DRR) and has a bottom depth deeper than the bottom depths of the plurality of gate trenches GT. Since the plurality of gate trenches GT have the same configuration, only one gate trench GT will be mainly described below.

[0021] One possible way to reduce the on-resistance is to reduce the pitch of the gate trench GT. However, if the pitch of the gate trench GT is reduced, the column region CR comes into contact with the gate trench GT and blocks the current path. This increases the on-resistance.

[0022] According to the study of the present inventors, it has become clear that there is room for improvement in the semiconductor device of the related art. This room for improvement will be described below.

[0023] <Structure of Semiconductor Device> A cross-sectional structure of an example of the semiconductor device according to the first embodiment will be described below. As shown in Fig. 3, in the semiconductor device, a column control region CSR is arranged in the vicinity of a gate trench GT.

[0024] A first impurity region (drift region DRR) of a first conductivity type is disposed on the semiconductor substrate SB. A second impurity region (base region BR) of a second conductivity type, and a first gate trench GT and a second gate trench GT formed from the second impurity region (base region BR) to the first impurity region (drift region DRR) are disposed on the first impurity region (drift region DRR). A gate electrode GE formed via a gate insulating film GI is disposed inside each of the first gate trench GT and the second gate trench GT. A column region CR of a second conductivity type is disposed between the first gate trench GT and the second gate trench GT, and is formed inside the first impurity region (drift region DRR) and has a bottom depth deeper than the bottom depths of the first gate trench GT and the second gate trench GT. A third impurity region (column control region CSR) of a first conductivity type is disposed in the first impurity region (drift region DRR) to cover the bottom of the first gate trench GT. The third impurity region (column control region CSR) is disposed between the first gate trench GT and the column region CR. The third impurity region (column control region CSR) contacts the bottom surfaces of the first gate trench GT and the second gate trench GT and the side surfaces connected to the bottom surfaces. The bottom surface of the third impurity region (column control region CSR) contacts the first impurity region (drift region DRR).

[0025] The impurity concentration of the third impurity region (column control region CSR) is higher than the impurity concentration of the first impurity region (drift region DRR).

[0026] Moreover, the column region CR overlaps with the third impurity region (column control region CSR) in plan view.

[0027] FIG. 1 is a plan view of a semiconductor device SDV according to a first embodiment. As shown in FIG. 1, the semiconductor device SDV has a semiconductor substrate SUB (see FIG. 3) made of single crystal silicon (Si). Furthermore, the semiconductor substrate SUB has an element region SA having a MOSFET, and an outer periphery region OA located outside the element region SA. A source electrode is provided on the upper surface of the element region SA. A gate wiring LG is arranged on the upper surface of part of the outer periphery region OA, and the gate wiring LG is connected to a gate electrode GE arranged on the upper surface of the part of the outer periphery region OA. A drain electrode DE is provided on the rear surface of the semiconductor substrate SUB. FIG. 3 shows the A-A cross section shown in the element region SA in FIG. 1.

[0028] Next, an example of a method for manufacturing the above-mentioned semiconductor device will be described. First, a semiconductor substrate SB made of, for example, single crystal silicon (Si) is prepared. The semiconductor substrate SB is a semiconductor substrate doped with, for example, phosphorus (P) or arsenic (As). The impurity concentration of the semiconductor substrate SB is, for example, 1×10 19 ~1×10 20 / cm 3 4, a first impurity region (drift region DRR) of a first conductivity type is formed on the semiconductor substrate SB by epitaxial growth. The first impurity region (drift region DRR) is formed by epitaxially growing silicon while doping it with, for example, phosphorus (P) or arsenic (As). The impurity concentration of the first impurity region (drift region DRR) is, for example, 1×10 16 ~1×10 17 / cm 3 That's about it.

[0029] Next, as shown in FIG. 5, a plurality of gate trenches GT are formed throughout the inside of the first impurity region (drift region DRR) by photolithography and silicon etching.

[0030] Next, as shown in FIG. 6, a third impurity region (column control region CSR) of the first conductivity type is formed in the first impurity region by ion implantation so as to cover the bottom of the gate trench GT. The third impurity region is formed by, for example, ion implantation of arsenic (As) or phosphorus (P). Here, the angle of ion implantation can be appropriately selected. The angle of ion implantation, that is, the angle from the perpendicular line (Tilt angle), is, for example, 0 to 45 degrees. In particular, when the angle from the perpendicular line is 0 to 23 degrees, the column control region CSR can be efficiently formed in the bottom of the gate trench GT. When the ion species is arsenic, the implantation energy is, for example, 5 to 200 keV. In particular, when the implantation energy is 20 to 60 keV, the column control region CSR can be efficiently formed in the vicinity of the gate trench GT. Furthermore, when the ion species is phosphorus, the implantation energy is 5 to 100 keV. In particular, when the implantation energy of phosphorus is 5 to 30 keV, the column control region CSR can be efficiently formed in the vicinity of the gate trench GT. The impurity concentration of the third impurity region (column control region CSR) is, for example, 1×10 16 ~1×10 17 / cm 3 After the ion implantation, wet etching using hydrofluoric acid or the like is performed to remove the implantation damage layer.

[0031] 7, a gate insulating film GI is formed on each inner wall of the gate trenches GT. The gate insulating film GI is formed by, for example, thermal oxidation. The thermal oxide film formed by this thermal oxidation is also formed on the semiconductor substrate in the upper part of the trench.

[0032] 8, a gate electrode GE is embedded in each of the gate trenches GT via a gate insulating film GI. For example, a polysilicon layer is formed by a CVD (Chemical Vapor Deposition) method, and the polysilicon layer is embedded in the gate trenches GT. Then, the polysilicon layer on the semiconductor substrate SUB is removed by dry etching or the like.

[0033] 9, the first impurity region is left below the first impurity region (drift region DRR), and a second conductivity type second impurity region (base region BR) and a first conductivity type source region SR are formed in this order above the first impurity region (drift region DRR). The second impurity region (base region BR) is formed by photolithography and ion implantation of, for example, boron (B) or arsenic difluoride (BF2). The impurity concentration of the second impurity region (base region BR) is, for example, 1×10 16 ~1×10 17 / cm 3 The source region SR is formed by photolithography and ion implantation of, for example, arsenic (As) or phosphorus (P). The impurity concentration of the source region SR is, for example, 1×10 20 ~1×10 21 / cm 3 That's about it.

[0034] Next, as shown in FIG. 10, a column region CR of a second conductivity type having a bottom depth deeper than the bottom depths of the first gate trench GT and the second gate trench GT is formed by ion implantation inside the first impurity region between the first gate trench GT and the second gate trench GT. The column region CR is formed by photolithography and ion implantation of, for example, boron (B) or arsenic difluoride (BF2). Here, this ion implantation may be performed in multiple steps, with the energy or dose amount being changed for each step. The impurity concentration of the column region CR is, for example, 1×10 16 ~1×10 17 / cm 3 That's about it.

[0035] Next, as shown in FIG. 3, an interlayer insulating film IF is formed. The interlayer insulating film IF is formed by depositing an insulating film such as BPSG (Boron Phosphorous Silicon Glass) or a plasma oxide film by, for example, a CVD method. Next, a source contact SCT is formed. The source contact SCT is formed by performing photolithography and dry etching the interlayer insulating film IF. Next, a contact region BDR is formed. The contact region BDR is formed by ion implantation of, for example, boron (B) or arsenic difluoride (BF2) through the source contact SCT. The impurity concentration of the contact region BDR is, for example, 5×10 18 ~1×10 20 / cm 3 The optimum range of the impurity concentration is, for example, 1×10 19 ~5×10 19 / cm 3 The thickness of the interlayer insulating film IF is about 100 nm. The semiconductor substrate SUB may be dry-etched after the dry etching of the interlayer insulating film IF. In this case, the source contact plug is formed so as to penetrate the source region SR and reach the second impurity region (base region BR). Next, a source contact plug is formed. The source contact plug is formed by forming a titanium (Ti) film and a titanium nitride (TiN) film in the source contact SCT by, for example, a CVD method, embedding a tungsten (W) film, and removing the tungsten film on the interlayer insulating film IF by CMP (Chemical Mechanical Polishing). Next, a source wiring LS is formed. The source wiring LS is formed by, for example, forming an aluminum (Al) film on the interlayer insulating film IF by a sputtering method, and patterning the aluminum film by photolithography and dry etching. After that, a drain electrode DE is formed. The drain electrode DE is formed by grinding the thickness of the semiconductor device SDV to a predetermined thickness, and forming a layer of titanium-nickel-silver (Ti-Ni-Ag) or the like on the back surface by, for example, a sputtering method.

[0036] FIG. 11 shows a partial plan view of the element region SA in FIG. 1. FIG. 11 illustrates the arrangement of the gate trenches GT, the gate insulating film GI, the gate electrode GE, the source contacts SCT, and the column regions CR. The gate trenches GT are formed in a stripe shape in the element region SA. The source contacts SCT are arranged in the center between the gate trenches GT spaced apart from each other, and are formed in a stripe shape. The column regions CR are arranged in the center between the gate trenches GT spaced apart from each other, that is, below the source contacts SCT. The column regions CR have a planar shape of a circular or rectangular dot, and each of the multiple column regions CR is arranged spaced apart from each other. In FIG. 11, the column regions CR are shown as rectangular dots, but they may be arranged in a staggered manner (see FIG. 12). The dots may be arranged not only in a square arrangement, but also in a stripe shape parallel to the gate trenches GT (see FIG. 13).

[0037] The effects of the first embodiment will be described. For comparison, a comparative example will be described. In the semiconductor device SDV according to the comparative example shown in FIG. 2, the gate trench GT pitch is reduced, so that the column region CR comes into contact with the gate trench GT and blocks the current path. Thus, in the comparative example, the current path is blocked due to the reduction in the gate trench GT pitch, and the performance of the semiconductor device is degraded, so there is room for improvement.

[0038] In contrast to the semiconductor device SDV according to the comparative example, in the above-described semiconductor device SDV, a third impurity region (column control region CSR) of the first conductivity type is formed in the first impurity region covering the bottom of the gate trench GT, and in a plan view, the column region CR overlaps with the third impurity region (column control region CSR), so that even if the gate trench GT pitch is reduced, the column region CR does not come into contact with the gate trench GT and does not obstruct the current path. Therefore, the gate trench GT pitch can be reduced, and the chip area can be reduced.

[0039] In addition, a part of the first impurity region (drift region DRR) becomes the third impurity region (column control region CSR) having a higher impurity concentration, which has the effect of lowering the resistance value and also makes it possible to reduce the on-resistance.

[0040] (Embodiment 2) In the first embodiment, the case where the third impurity region (column control region CSR) is formed after the gate trench GT is formed has been described (see FIG. 3). Here, the case where the column control region CSR is formed before the gate trench GT is formed, and the gate trench GT is formed such that the bottom of the gate trench GT reaches the column control region CSR when the gate trench GT is formed will be described (see FIGS. 16 and 17).

[0041] A cross-sectional structure of an example of a semiconductor device SDV according to the second embodiment will be described. As shown in FIG. - A column control region CSR of the mold is disposed between the gate trench GT and the column region CR.

[0042] A first impurity region (drift region DRR) of a first conductivity type is disposed on the semiconductor substrate SB. A second impurity region (base region BR) of a second conductivity type, and a first gate trench GT and a second gate trench GT formed from the second impurity region (base region BR) to the first impurity region (drift region DRR) are disposed on the first impurity region (drift region DRR). A gate electrode GE formed via a gate insulating film GI is disposed inside each of the first gate trench GT and the second gate trench GT. A column region CR of a second conductivity type is disposed between the first gate trench GT and the second gate trench GT and is formed inside the first impurity region (drift region DRR) and has a bottom depth deeper than the bottom depths of the first gate trench GT and the second gate trench GT. A third impurity region (column control region CSR) of the first conductivity type is disposed in the first impurity region (drift region DRR) to cover the bottoms of the first gate trench GT and the second gate trench GT. The third impurity region (column control region CSR) is disposed between the gate trench GT and the column region CR. The third impurity region (column control region CSR) has a multi-stage structure extending toward the semiconductor substrate SB. The third impurity region (column control region CSR) contacts the bottom surfaces of the first gate trench GT and the second gate trench GT and the side surfaces connected to these bottom surfaces. In addition, the bottom surface of the third impurity region (column control region CSR) contacts the first impurity region (drift region DRR).

[0043] The impurity concentration of the third impurity region (column control region CSR) is higher than the impurity concentration of the first impurity region (drift region DRR).

[0044] Moreover, the column region CR overlaps with the third impurity region (column control region CSR) in plan view.

[0045] FIG. 1 is a plan view of a semiconductor device SDV according to a first embodiment. As shown in FIG. 1, the semiconductor device SDV has a semiconductor substrate SUB (see FIG. 14) made of a single crystal such as silicon (Si). Furthermore, the semiconductor substrate SUB has an element region SA having a MOSFET, and an outer periphery region OA located outside the element region SA. A source electrode is provided on the upper surface of the element region SA. A gate wiring LG is arranged on the upper surface of part of the outer periphery region OA, and the gate wiring LG is connected to a gate electrode GE arranged on the upper surface of the part of the outer periphery region OA. A drain electrode DE is provided on the rear surface of the semiconductor substrate SUB. FIG. 14 shows the A-A cross section shown in the element region SA in FIG. 1.

[0046] Next, an example of a method for manufacturing the above-mentioned semiconductor device will be briefly described. First, a semiconductor substrate SB made of a single crystal such as silicon (Si) is prepared. The semiconductor substrate SB is doped with, for example, phosphorus (P) or arsenic (As), and the impurity concentration is, for example, 1×10 19 ~1×10 20 / cm 3 15, a first impurity region (drift region DRR) of a first conductivity type is formed on the semiconductor substrate SB by epitaxial growth. For example, silicon is epitaxially grown while being doped with phosphorus (P) or arsenic (As). The impurity concentration of the first impurity region (drift region DRR) is, for example, 1×10 16 ~1×10 17 / cm 3 That's about it.

[0047] Next, as shown in FIG. 16, a plurality of third impurity regions (column control regions CSR) of the first conductivity type are formed in the first impurity region (drift region DRR) by ion implantation. The third impurity regions (column control regions CSR) are formed by photolithography and ion implantation of, for example, phosphorus (P) or arsenic (As). The ion implantation may be performed in multiple steps, with the energy or dose amount being changed for each step. The angle of the ion implantation, that is, the implantation angle from the perpendicular line (tilt angle), is preferably 0 to 10 degrees. The impurity concentration of the third impurity regions (column control regions CSR) is, for example, 1×10 16 ~1×10 17 / cm 3 That's about it.

[0048] Next, as shown in FIG. 17, a plurality of gate trenches GT reaching a plurality of third impurity regions (column control regions CSR) are formed in the first impurity region (drift region DRR) by photolithography and silicon etching.

[0049] 18, a gate insulating film GI is formed on each inner wall of the gate trenches GT. The gate insulating film GI is formed by, for example, thermal oxidation. The thermal oxide film formed by this thermal oxidation is also formed on the semiconductor substrate in the upper part of the trench.

[0050] 19, a gate electrode GE is embedded in each of the gate trenches GT via a gate insulating film GI. The gate electrode GE is formed by forming a polysilicon layer by a CVD method, for example, and embedding the polysilicon layer in the gate trench GT. Then, the polysilicon layer on the semiconductor substrate SUB is removed by dry etching or the like.

[0051] Next, as shown in FIG. 20, the first impurity region (drift region DRR) is left below the first impurity region, and a second impurity region (base region BR) of a second conductivity type is formed above the first impurity region. The second impurity region (base region BR) is formed by photolithography and ion implantation of, for example, boron (B) or arsenic difluoride (BF2). The impurity concentration of the second impurity region (base region BR) is, for example, 1×10 16 ~1×10 17 / cm 3 That's about it.

[0052] 21, a first conductive type source region SR is formed on the second impurity region (base region BR). The source region SR is formed by photolithography and ion implantation of, for example, arsenic (As) or phosphorus (P). The impurity concentration of the source region SR is, for example, 1×10 20 ~1×10 21 / cm 3 That's about it.

[0053] Thereafter, as shown in FIG. 22, a plurality of column regions CR of the second conductivity type, the bottom of which is deeper than the bottom of the plurality of gate trenches GT, are formed by ion implantation in the first impurity region between each of the plurality of gate trenches GT. The column regions CR are formed by photolithography and ion implantation of, for example, boron (B) or arsenic difluoride (BF2). Here, this ion implantation may be performed in a plurality of times, with the energy or dose amount being changed for each time. The impurity concentration of the column regions CR is, for example, 1×10 16 ~1×10 17 / cm 3 That's about it.

[0054] Next, as shown in FIG. 14, an interlayer insulating film IF is formed. The interlayer insulating film IF is formed by depositing an insulating film of BPSG or a plasma oxide film by, for example, a CVD method. Next, a source contact SCT is formed. The source contact SCT is formed by performing photolithography and dry etching the interlayer insulating film IF. Next, a contact region BDR is formed. The contact region BDR is formed by ion implantation of, for example, boron (B) or arsenic difluoride (BF2) through the source contact SCT. The impurity concentration of the contact region BDR is, for example, 5×10 18 ~1×10 20 / cm 3 The optimum range of the impurity concentration is, for example, 1×10 19 ~5×10 19 / cm 3 The thickness of the interlayer insulating film IF is about 100 nm. The semiconductor substrate SUB may be dry-etched after the dry etching of the interlayer insulating film IF. In this case, the source contact plug is formed so as to penetrate the source region SR and reach the second impurity region (base region BR). Next, a source contact plug is formed. The source contact plug is formed by forming a titanium (Ti) film and a titanium nitride (TiN) film in the source contact SCT by, for example, a CVD method, embedding a tungsten (W) film, and removing the tungsten film on the interlayer insulating film IF by CMP. Next, a source wiring LS is formed. The source wiring LS is formed by, for example, forming an aluminum (Al) film on the interlayer insulating film IF by a sputtering method, and patterning the aluminum film by photolithography and dry etching. After that, a drain electrode DE is formed. The drain electrode DE is formed by grinding the thickness of the semiconductor device SDV to a predetermined thickness, and forming a layer of titanium-nickel-silver (Ti-Ni-Ag) or the like on the back surface by, for example, a sputtering method.

[0055] FIG. 11 shows a partial plan view of the element region SA in FIG. 1. FIG. 11 illustrates the arrangement of the gate trenches GT, the gate insulating film GI, the gate electrode GE, the source contacts SCT, and the column regions CR. The gate trenches GT are formed in a stripe shape in the element region SA. The source contacts SCT are arranged in the center between the gate trenches GT spaced apart from each other, and are formed in a stripe shape. The column regions CR are arranged in the center between the gate trenches GT spaced apart from each other, that is, below the source contacts SCT. The column regions CR have a planar shape of a circular or rectangular dot, and each of the multiple column regions CR is arranged spaced apart from each other. In FIG. 11, the column regions CR are shown as rectangular dots, but they may be arranged in a staggered manner (see FIG. 12). The dots may be arranged not only in a square arrangement, but also in a stripe shape parallel to the gate trenches GT (see FIG. 13).

[0056] The effect of the second embodiment will be described. For comparison, a comparative example will be described. In the semiconductor device SDV according to the comparative example shown in FIG. 2, the pitch of the gate trenches GT is reduced, so that the column region CR comes into contact with the gate trenches GT and blocks the current path.

[0057] In contrast to the semiconductor device SDV according to the comparative example, in the above-described semiconductor device SDV, the third impurity region (column control region CSR) of the first conductivity type is formed in the first impurity region (drift region DRR) covering the bottom of the gate trench GT, so that even if the pitch of the gate trench GT is reduced, the column region CR does not come into contact with the gate trench GT and the current path is not blocked. Therefore, the pitch of the gate trench GT can be reduced, and the chip area can be reduced.

[0058] (Embodiment 3) The third embodiment is a modification of the first and second embodiments. A partial plan view of the semiconductor device of the third embodiment is similar to the structure shown in FIG. 12 used in the description of the first embodiment. The gate trenches GT are striped. The source contacts SCT are disposed at the center between the gate trenches GT spaced apart from each other, and are striped. The column regions CR are disposed at the center between the gate trenches GT spaced apart from each other, that is, below the source contacts SCT, and are striped. The cross-sectional view is the same as that of FIG. 3 or FIG. 14. The gate trenches GT are formed so as to extend from the main surface of the semiconductor substrate SUB toward the back surface thereof, penetrate the source region SR and the base region BR, pass through the column region CR, and reach the drift region DRR. The impurity concentration of the column control region CSR is higher than that of the drift region DRR. The column control region CSR is in contact with the column region CR. Even in the striped column region CR according to the third embodiment, the column control region CSR can prevent contact with the gate trench GT. In addition, a part of the drift region DRR becomes the column control region CSR having a higher impurity concentration, which has the effect of lowering the resistance value and also makes it possible to reduce the on-resistance.

[0059] (Embodiment 4) The fourth embodiment is a modification of the first and second embodiments. A partial plan view of the semiconductor device of the fourth embodiment is similar to the structure shown in FIG. 12 used in the description of the first embodiment. The gate trenches GT are striped. The source contacts SCT are arranged in the center between the gate trenches GT spaced apart from each other, and are striped. The column regions CR are arranged in the center between the gate trenches GT spaced apart from each other, that is, below the source contacts SCT, and are arranged in a staggered arrangement in a circular or rectangular shape. The cross-sectional view is the same as that of FIG. 3 or FIG. 14. The gate trenches GT are formed so as to penetrate the source region SR and the base region BR from the main surface of the semiconductor substrate toward the back surface, pass through the column control region CSR, and reach the drift region DRR. The impurity concentration of the column control region CSR is higher than the impurity concentration of the drift region DRR. The column control region CSR is in contact with the column region CR. Even in the column regions CR spaced apart from each other in a staggered arrangement according to the fourth embodiment, the column control region CSR can prevent contact with the gate trench GT. In addition, a part of the drift region DRR becomes the column control region CSR having a higher impurity concentration, which has the effect of lowering the resistance value and also makes it possible to reduce the on-resistance.

[0060] The semiconductor devices described in each embodiment can be combined in various ways as necessary.

[0061] The present invention has been specifically described above based on the embodiments, but it goes without saying that the present invention is not limited to the above-described embodiments and can be modified in various ways without departing from the spirit of the invention. A part of the contents described in the above-described embodiments is described below.

[0062] [Appendix 1] (a) providing a semiconductor substrate; (b) forming a first impurity region of a first conductivity type on the semiconductor substrate by epitaxial growth; (c) forming a first second impurity region and a second second impurity region of a first conductivity type within the first impurity region by ion implantation; (d) forming a first gate trench in the first impurity region, the first gate trench reaching the first second impurity region, and a second gate trench reaching the second second impurity region; (e) forming a gate insulating film on each of the inner walls of the first gate trench and the second gate trench; (f) embedding a gate electrode into each of the first gate trench and the second gate trench via the gate insulating film; (g) leaving the first impurity region below the first impurity region, and forming a third impurity region of a second conductivity type and a source region of a first conductivity type in this order above the first impurity region; (h) forming, by ion implantation, a column region of a second conductivity type inside the first impurity region between the first gate trench and the second gate trench, the column region having a bottom depth deeper than a bottom depth of each of the first gate trench and the second gate trench.

[0063] [Appendix 2] In the method for manufacturing a semiconductor device according to claim 1, A method for manufacturing a semiconductor device, wherein the second impurity region has an impurity concentration higher than an impurity concentration of the first impurity region.

[0064] [Appendix 3] In the method for manufacturing a semiconductor device according to claim 1, The column region overlaps with the second impurity region in a plan view. [Explanation of symbols]

[0065] SDV Semiconductor Device SA element area OA outer area SUB Semiconductor Substrate SB Semiconductor substrate SR Source Region BDR Contact Area BR Base Region CR Column Area DRR Drift Region CSR column control area DE Drain electrode GE gate electrode GI Gate Insulator LG Gate Wiring LS source wiring SCT Source Contact IF Interlayer Insulating Film GT Gate Trench

Claims

1. A method for manufacturing a semiconductor device, comprising the steps of: (a) providing a semiconductor substrate; (b) after step (a), forming a first impurity region on the semiconductor substrate; (c) after the step (b), forming a first gate trench and a second gate trench in the first impurity region; (d) after the step (c), forming a second impurity region in the first impurity region so as to cover a bottom portion of each of the first gate trench and the second gate trench in a cross-sectional view; (e) after the step (d), forming a gate insulating film on each of the inner walls of the first gate trench and the second gate trench; (f) after the step (e), forming a gate electrode in each of the first gate trench and the second gate trench via the gate insulating film; (g) after the step (f), forming a third impurity region and a source region in a region of the first impurity region located between the first gate trench and the second gate trench; (h) after the step (g), forming the column region in the first impurity region and below each of the third impurity regions such that, in a cross-sectional view, a bottom of the column region is located deeper than the bottoms of the first gate trench and the second gate trench, and the second impurity region is located between each of the first gate trench and the second gate trench and a column region; Where: each of the first impurity region, the second impurity region, and the source region is an impurity region of a first conductivity type; each of the third impurity region and the column region is an impurity region of a second conductivity type different from the first conductivity type; The impurity concentration of the second impurity region is higher than the impurity concentration of the first impurity region, In the step (h), the column region is formed so that, in a cross-sectional view, the column region has a portion that is located directly below each of the first gate trench and the second gate trench, and so that a bottom surface of the second impurity region contacts each of the first impurity region and the column region.

2. 2. The method of manufacturing a semiconductor device according to claim 1, In the step (b), the first impurity region is formed by epitaxial growth.

3. 2. The method of manufacturing a semiconductor device according to claim 1, A method for manufacturing a semiconductor device, wherein in the step (d), the second impurity region is formed so that the second impurity region contacts each of a bottom surface and a side surface connected to the bottom surface of the first gate trench and the second gate trench.

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