NITRIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING NITRIDE SEMICONDUCTOR DEVICE - Patent application

Abstract

To provide a nitride semiconductor device and manufacturing method therefor, achieving a p-type region with high concentration and little concentration variance.SOLUTION: A nitride semiconductor device includes a nitride semiconductor and a p-type region with an acceptor element concentration of 5×1018 cm-3 and more to 2×1020 cm-3 or less, provided on the nitride semiconductor. A density in the p-type region is 1×1014 cm-3 or less with rod-shaped acceptor segregation in which a length in one direction is 30 nm or more and the concentration of an acceptor element is 5×1020 cm-3 or more.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a nitride semiconductor device and a method for manufacturing a nitride semiconductor device. [Background technology]

[0002] A nitride semiconductor device having a vertical MOS (Metal Oxide Semiconductor) structure is known (see, for example, Patent Document 1). In addition, in a nitride semiconductor device, it is possible to control the P-type conductivity by using magnesium (Mg) as a dopant (see, for example, Patent Document 2).

[0003] In order to realize a good ohmic contact in a nitride semiconductor device, it is necessary to selectively form a high-concentration P-type region in the nitride semiconductor. Ion implantation is a desirable method for selectively forming a P-type region in terms of cost, productivity, and reliability. However, when Mg is ion-implanted into a nitride semiconductor at a high concentration and then heat-treated at a high temperature to activate the Mg, the Mg segregates into rod-like structures at a high density. When Mg segregates into rod-like structures at a high density, the Mg concentration decreases in regions other than the region where the segregation occurs. For this reason, it has been difficult to form a high-concentration P-type region with small concentration variation by ion implantation (see, for example, Non-Patent Document 1). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2019-096744 A [Patent Document 2] JP 2014-086698 A [Non-patent literature]

[0005] [Non-Patent Document 1] Kumar et.al.,J.Appl.Phys.126(2019)235704. Summary of the Invention [Problem to be solved by the invention]

[0006] In nitride semiconductor devices, it is desirable to realize a P-type region that is highly doped and has small variations in concentration.

[0007] The present invention has been made in light of the above-mentioned problems, and has an object to provide a nitride semiconductor device that is capable of realizing a P-type region with a high concentration and small variation in concentration, and a method for manufacturing the nitride semiconductor device. [Means for solving the problem]

[0008] In order to achieve the above object, a nitride semiconductor device according to one aspect of the present invention comprises a nitride semiconductor and an acceptor element having a concentration of 5×10 18 cm -3 More than 2×10 20 cm -3 and a P-type region having a length in one direction of 30 nm or more and a concentration of the acceptor element of 5×10 20 cm -3 The density of the rod-shaped acceptor segregation in the P-type region is 1×10 14 cm -3 The following is the result.

[0009] A method for manufacturing a nitride semiconductor device according to one aspect of the present invention includes the steps of ion-implanting an acceptor element into a partial region of a nitride semiconductor, ion-implanting nitrogen into the partial region before or after the step of ion-implanting the acceptor element, and performing a heat treatment on the nitride semiconductor into which the acceptor element and the nitrogen have been ion-implanted to form a P-type region in the partial region. In the step of ion-implanting the acceptor element, the concentration of the acceptor element ion-implanted is 5×10 18 cm -3 More than 2×10 20 cm -3 Set the injection conditions as follows: Effect of the Invention

[0010] According to the present invention, it is possible to provide a nitride semiconductor device capable of realizing a P-type region with a high concentration and small variation in concentration, and a method for manufacturing the nitride semiconductor device. [Brief description of the drawings]

[0011] [Figure 1] FIG. 1 is a plan view showing a configuration example of a gallium nitride semiconductor device (GaN semiconductor device) according to a first embodiment of the present invention. [Diagram 2] FIG. 2 is a cross-sectional view showing an example of the configuration of the vertical MOSFET according to the first embodiment of the present invention. [Figure 3A] FIG. 3A is a cross-sectional view showing a method for manufacturing a vertical MOSFET according to the first embodiment of the present invention in the order of steps. [Figure 3B] 3A to 3B are cross-sectional views showing the process steps of a method for manufacturing the vertical MOSFET according to the first embodiment of the present invention. [Figure 3C] 3A to 3C are cross-sectional views showing the process steps of a method for manufacturing the vertical MOSFET according to the first embodiment of the present invention. [Figure 3D] 3A to 3D are cross-sectional views showing the process steps of a method for manufacturing the vertical MOSFET according to the first embodiment of the present invention. [Figure 3E] 3A to 3E are cross-sectional views showing the process steps of a method for manufacturing the vertical MOSFET according to the first embodiment of the present invention. [Figure 3F] 3A to 3F are cross-sectional views showing the process steps of a method for manufacturing the vertical MOSFET according to the first embodiment of the present invention. [Figure 4A] FIG. 4A is a cross-sectional TEM image showing the analysis results of crystal defects in a GaN substrate according to an embodiment of the present invention. [Figure 4B] FIG. 4B is a 3D-AP diagram showing the analysis results of Mg segregation in a GaN substrate according to an example of the present invention. [Diagram 5] FIG. 5 is a graph showing the Mg concentration in a region (parent phase) where no Mg segregation occurs in a GaN substrate according to an example of the present invention. [Figure 6A]FIG. 6A is a cross-sectional TEM image showing the analysis results of crystal defects in a GaN substrate according to Comparative Example 1 of the present invention. [Figure 6B] FIG. 6B is a 3D-AP diagram showing the analysis results of Mg segregation in the GaN substrate according to Comparative Example 1 of the present invention. [Figure 7] FIG. 7 is a graph showing the results of measuring the composition ratio of elements in rod-shaped Mg segregations and their surrounding regions in the GaN substrate according to Comparative Example 1 of the present invention using 3D-AP. [Figure 8] FIG. 8 is a cross-sectional TEM image showing the measurement range when the data shown in FIG. 7 was obtained. [Figure 9] FIG. 9 is a graph showing the Mg concentration in a region (parent phase) where no Mg segregation occurs in a GaN substrate according to Comparative Example 1 of the present invention. [Figure 10A] FIG. 10A is a cross-sectional TEM image showing the analysis results of crystal defects in a GaN substrate according to Comparative Example 2 of the present invention. [Figure 10B] FIG. 10B is a 3D-AP diagram showing the analysis results of Mg segregation in a GaN substrate according to Comparative Example 2 of the present invention. [Figure 11] FIG. 11 is a cross-sectional view showing the configuration of a vertical MOSFET according to the second embodiment of the present invention. [Figure 12] FIG. 12 is a cross-sectional view showing a configuration example of a vertical MOSFET according to the third embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] An embodiment of the present invention will be described below. In the following description of the drawings, the same or similar parts are given the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each device and each member, etc., differ from the actual ones. Therefore, the specific thickness and dimensions should be determined by taking into consideration the following description. In addition, it goes without saying that the drawings include parts whose dimensional relationships and ratios differ from each other.

[0013] In the following description, directions may be described using the terms X-axis, Y-axis, and Z-axis. For example, the X-axis and Y-axis directions are parallel to the surface 10a of the GaN substrate 10 described below. The X-axis and Y-axis directions are also referred to as horizontal directions. The Z-axis direction is a direction perpendicular to the surface 10a of the GaN substrate 10. The X-axis, Y-axis, and Z-axis directions are mutually orthogonal.

[0014] In the following description, the positive direction of the Z axis may be referred to as "up" and the negative direction of the Z axis may be referred to as "down". "Up" and "down" do not necessarily mean the vertical direction with respect to the ground. In other words, the directions of "up" and "down" are not limited to the direction of gravity. "Up" and "down" are merely convenient expressions for specifying the relative positional relationship in regions, layers, films, substrates, etc., and do not limit the technical idea of ​​the present invention. For example, if the paper is rotated 180 degrees, "up" will of course become "down" and "down" will become "up".

[0015] In the following description, the + or - attached to the P or N indicating the conductivity type means that the semiconductor region has a relatively high or low impurity concentration, respectively, compared to a semiconductor region without the + or - attached. However, even if the same P and P (or N and N) are attached to the semiconductor region, it does not mean that the impurity concentration of each semiconductor region is strictly the same.

[0016] <Embodiment 1> (Example of the configuration of a gallium nitride semiconductor device) FIG. 1 is a plan view showing an example configuration of a gallium nitride semiconductor device 100 according to a first embodiment of the present invention (one example of the "nitride semiconductor device" of the present invention; hereinafter, referred to as a GaN semiconductor device). FIG. 1 is an XY plan view. As shown in FIG. 1, the GaN semiconductor device 100 has an active region 110 and an edge termination region 130. The active region 110 has a gate pad 112 and a source pad 114. The gate pad 112 and the source pad 114 are electrode pads electrically connected to a gate electrode 44 and a source electrode 54, respectively, which will be described later.

[0017] In a plan view from the Z-axis direction, edge termination region 130 surrounds the periphery of active region 110. Edge termination region 130 may have one or more of a guard ring structure, a field plate structure, and a JTE (Junction Termination Extension) structure. Edge termination region 130 may have a function of preventing electric field concentration in active region 110 by expanding a depletion layer generated in active region 110 to edge termination region 130.

[0018] (Example of a vertical MOSFET configuration) Fig. 2 is a cross-sectional view showing a configuration example of a vertical MOSFET 1 according to the first embodiment of the present invention. Fig. 2 shows a cross section of the active region 110 shown in Fig. 1 taken along line II-II', and shows a repeated unit structure of the vertical MOSFET 1. The GaN semiconductor device 100 includes a plurality of vertical MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) 1 shown in Fig. 2. In the GaN semiconductor device 100, the vertical MOSFETs 1 are repeatedly provided in the Y-axis direction.

[0019] As shown in FIG. 2, the vertical MOSFET 1 has a gallium nitride substrate (one example of a "nitride semiconductor" in the present invention; hereinafter, referred to as a GaN substrate) 10, a gate insulating film 42, a gate electrode 44 provided on the gate insulating film 42, a source electrode 54, and a drain electrode 56.

[0020] The GaN substrate 10 (an example of the "nitride semiconductor" of the present invention) is a GaN single crystal substrate. The GaN substrate 10 is, for example, an N-type substrate. The GaN substrate 10 has a front surface 10a and a back surface 10b located on the opposite side to the front surface 10a. For example, the GaN substrate 10 has a threading dislocation density of 1×10 7 cm -2 The low-dislocation free-standing GaN substrate has a dislocation density of less than 100 nm.

[0021] The donor (N-type impurity) contained in the GaN substrate 10 may be one or more of the elements Si (silicon), Ge (germanium), and O (oxygen). The acceptor element (P-type impurity) contained in the GaN substrate 10 may be one or more of the elements Mg (magnesium), Ca (calcium), Be (beryllium), and Zn (zinc).

[0022] Since the GaN substrate 10 is a low-dislocation freestanding GaN substrate, leakage current in the power device can be reduced even when a large-area power device is formed on the GaN substrate 10. This makes it possible to manufacture power devices with a high yield rate. In addition, it is possible to prevent ion-implanted impurities from diffusing deeply along dislocations during heat treatment included in the manufacturing process of the vertical MOSFET 1.

[0023] The GaN substrate 10 may include a GaN single crystal substrate and a single crystal GaN layer epitaxially grown on the GaN single crystal substrate. In this case, the GaN single crystal substrate may be N+ type or N type, and the GaN layer may be N type or N- type.

[0024] In the vertical MOSFET 1, the semiconductor material is GaN, but the semiconductor material may contain one or more elements of aluminum (Al) and indium (In). The semiconductor material may be an alloy semiconductor containing a small amount of Al and In, that is, AlxInyGa1-x-yN (0≦x<1, 0≦y<1). Note that GaN is the case where x=y=0 in AlxInyGa1-x-yN.

[0025] A drift region 22, a well region 23 (an example of a "P-type well region" of the present invention), a contact region 25 (an example of a "P-type region" of the present invention), and a source region 26 (an example of an "N-type source region" of the present invention) are provided in the GaN substrate 10. The well region 23, the contact region 25, and the source region 26 are each a region in which impurities are ion-implanted to a predetermined depth from the surface 10a of the GaN substrate 10 and the impurities are activated by heat treatment.

[0026] For example, the contact region 25 is provided on the surface side of the well region 23. The well region 23 is a P-type region, and the contact region 25 is a P+-type region. The contact region 25 has a higher P-type impurity concentration than the well region 23. The well region 23 and the contact region 25 contain at least one of Mg and Be as an acceptor element (P-type impurity).

[0027] For example, the well region 23 and the contact region 25 contain Mg as an acceptor element. The concentration of Mg in the well region 23 is 1×10 16 cm -3 More than 3×10 18 cm -3 The Mg concentration in the contact region 25 is 5×10 18 cm -3 More than 2×10 20 cm -3 The following is the result.

[0028] The drift region 22 is an N-type region, and the source region 26 is an N+ type region. The source region 26 has a lower N-type impurity concentration than the drift region 22. The drift region 22 and the source region 26 contain, for example, Si as an N-type impurity. For example, the N-type impurity concentration of the drift region 22 is the same as the N-type impurity concentration of the GaN substrate 10. In this case, the drift region 22 does not need to be ion-implanted with N-type impurities. The source region 26 is provided on the surface side of the well region 23. The source region 26 is formed by ion-implanting Si into the surface side of the well region 23 and activating the Si by heat treatment.

[0029] 2, an upper portion of the source region 26 is exposed on the surface 10a of the GaN substrate 10. The bottom and a first side of the source region 26 are in contact with the well region 23, and the second side is in contact with the contact region 25. The first side of the source region 26 is located on the side of a region (hereinafter, channel region) 231 in which the channel of the vertical MOSFET 1 is formed. The second side of the source region 26 is located on the opposite side to the first side in the Y-axis direction.

[0030] An upper portion of the contact region 25 is exposed on the surface 10a of the GaN substrate 10. A side portion of the contact region 25 contacts the source region 26, and a bottom portion of the contact region 25 contacts the well region 23. The well region 23, the contact region 25, and the source region 26 have a stripe shape extending in the X-axis direction.

[0031] An upper portion of the drift region 22 (hereinafter, referred to as the upper region) is exposed on the surface 10a of the GaN substrate 10. The upper region 221 contacts the gate insulating film 42 on the surface 10a. The upper region 221 is located between a pair of well regions 23 facing each other in the Y-axis direction. The upper region 221 may be called a JFET region.

[0032] A lower portion (hereinafter, referred to as lower portion) 222 of the drift region 22 contacts the bottom of the well region 23. The lower portion 222 is located between the upper portion 221 and the drain electrode 56, and between the well region 23 and the drain electrode 56. The lower portion 222 may be provided continuously in the Y-axis direction between a plurality of vertical MOSFETs 1 (i.e., a plurality of unit structures) repeated in the Y-axis direction.

[0033] The drift region 22 functions as a current path between the drain electrode 56 and the channel region 231. The contact region 25 has a function of reducing the contact resistance with the source electrode 54. The contact region 25 also functions as a hole extraction path when the gate is off.

[0034] The gate insulating film 42 is, for example, a silicon oxide film (SiO2 film). The gate insulating film 42 is provided on, for example, the flat surface 10a.

[0035] The gate electrode 44 is provided above the channel region 231 via the gate insulating film 42. For example, the gate electrode 44 is a planar type provided on the flat gate insulating film 42. The gate electrode 44 is made of a material different from that of the gate pad 112. The gate electrode 44 is made of polysilicon doped with impurities, and the gate pad 112 is made of Al or an Al-Si alloy.

[0036] The source electrode 54 is provided on the surface 10a of the GaN substrate 10. The source electrode 54 is in contact with a part of the source region 26 and the contact region 25. The source electrode 54 may also be provided on the gate electrode 44 via an interlayer insulating film (not shown). The interlayer insulating film may cover the top and sides of the gate electrode 44 so that the gate electrode 44 and the source electrode 54 are not electrically connected to each other.

[0037] The source electrode 54 is made of the same material as the source pad 114. For example, the source electrode 54 made of Al or an Al-Si alloy also serves as the source pad 114. The source electrode 54 may have a barrier metal layer between the front surface 10a of the GaN substrate 10 and Al (or Al-Si). Titanium (Ti) may be used as the material of the barrier metal layer. The drain electrode 56 is provided on the rear surface 10b side of the GaN substrate 10 and is in contact with the rear surface 10b. The drain electrode 56 is also made of the same material as the source electrode 54.

[0038] 2, the gate terminal, the source terminal, and the drain terminal are indicated by G, D, and S, respectively. For example, when a potential equal to or higher than the threshold voltage is applied to the gate electrode 44 via the gate terminal G, an inversion layer is formed in the channel region 231. When a predetermined high potential is applied to the drain electrode 56 and a low potential (e.g., ground potential) is applied to the source electrode 54 in a state in which the inversion layer is formed in the channel region 231, a current flows from the drain terminal D to the source terminal S. When a potential lower than the threshold voltage is applied to the gate electrode 44, an inversion layer is not formed in the channel region 231 and the current is blocked. As a result, the vertical MOSFET 1 can switch the current between the source terminal S and the drain terminal D.

[0039] (Manufacturing method for vertical MOSFET) Next, a method for manufacturing the vertical MOSFET 1 according to the first embodiment of the present invention will be described. Figures 3A to 3F are cross-sectional views showing the manufacturing method of the vertical MOSFET 1 according to the first embodiment of the present invention in the order of steps. The vertical MOSFET 1 is manufactured by various manufacturing apparatuses such as a film formation apparatus, an exposure apparatus, and an etching apparatus.

[0040] As shown in FIG. 3A, the manufacturing equipment ion-implants Mg as an acceptor element into a region (hereinafter, well formation region) 23' in the GaN substrate 10 where a well region 23 (see FIG. 2) is formed. For example, the manufacturing equipment forms a mask M1 on the surface 10a of the GaN substrate 10. The mask M1 is a SiO2 film or a photoresist that is selectively removable from the GaN substrate 10. In the active region 110 (see FIG. 1), the mask M1 has a shape that opens above the well formation region 23' and covers above other regions. The manufacturing equipment ion-implants Mg into the GaN substrate 10 on which the mask M1 has been formed. After the ion implantation, the manufacturing equipment removes the mask M1 from above the GaN substrate 10.

[0041] In the Mg ion implantation step shown in FIG. 3A, the Mg ion implantation is performed so that the Mg concentration in the vicinity of the surface 10a of the GaN substrate 10 is 1×10 16 cm -3 More than 3×10 18cm -3 The implantation energy (acceleration voltage) and dose of Mg are set as follows: The vicinity of the surface refers to, for example, a range from the surface 10a to a depth of 50 nm.

[0042] Alternatively, in the Mg ion implantation step shown in FIG. 3A, the Mg concentration in the entire well formation region 23′, not just in the vicinity of the surface 10a of the GaN substrate 10, is set to 1×10 16 cm -3 More than 3×10 18 cm -3 The implantation energy and dose of Mg may be set as follows: The Mg ion implantation step shown in Fig. 3A may be performed as a single-stage ion implantation with one acceleration energy condition, or as a multi-stage ion implantation with multiple acceleration energy conditions.

[0043] Next, as shown in FIG. 3B, the manufacturing equipment ions-implants Si as an N-type impurity into a region 26' in which a source region is to be formed (hereinafter, source formation region) in the GaN substrate 10. For example, the manufacturing equipment forms a mask M2 on the GaN substrate 10. The mask M2 is a SiO2 film or a photoresist. In the active region 110, the mask M2 has a shape that opens above the source formation region 26' and covers above other regions. The manufacturing equipment ions-implants Si into the GaN substrate 10 on which the mask M2 has been formed. After the ion implantation, the manufacturing equipment removes the mask M2 from above the GaN substrate 10.

[0044] Next, as shown in FIG. 3C, the manufacturing equipment ion-implants Mg as a P-type impurity into a region 25' in the GaN substrate 10 where a contact region is to be formed (an example of a "partial region" of the present invention; hereinafter, referred to as a contact formation region). For example, the manufacturing equipment forms a mask M3 on the GaN substrate 10. The mask M3 is a SiO2 film or a photoresist. In the active region 110, the mask M3 has a shape that opens above the contact formation region 25' and covers above the other regions. The manufacturing equipment ion-implants Mg into the GaN substrate 10 on which the mask M3 has been formed.

[0045] 3C, the implantation energy (acceleration voltage) is set so that the depth from the surface 10a of the GaN substrate 10 to the implantation peak position is 200 nm or more and 1500 nm or less, for example, 500 nm. Also, in this step, the Mg ion implantation is performed so that the Mg concentration at the implantation peak position is 5×10 18 cm -3 More than 2×10 20 cm -3 As an example, 19 cm -3 The dose of Mg (acceptor element) is set so that:

[0046] Alternatively, in the Mg ion implantation step shown in FIG. 3C, the Mg concentration not only at the implantation peak position but also in the entire contact formation region 25′ is 5×10 18 cm -3 More than 2×10 20 cm -3 As an example, 19 cm -3 The Mg implantation energy and dose may be set so that the Mg ion implantation step shown in Fig. 3C may be performed as a single-stage ion implantation using a single acceleration energy, or may be performed as a multi-stage ion implantation using different acceleration energies.

[0047] 3D, the manufacturing equipment ions-implants nitrogen (N) into the contact formation region 25' of the GaN substrate 10. For example, the manufacturing equipment ions-implants N into the GaN substrate 10 on which the mask M3 has been formed. After the ion implantation, the manufacturing equipment removes the mask M3 from the GaN substrate 10.

[0048] In the N ion implantation step shown in Fig. 3D, the implantation energy (acceleration voltage) is set so that the depth from the surface 10a of the GaN substrate 10 to the implantation peak position is 200 nm or more and 1500 nm or less, for example, 500 nm. In this step, N ions may be implanted with the same implantation energy as in the Mg ion implantation step shown in Fig. 3C. In this step, the N concentration at the implantation peak position is 0.1 to 10 times the Mg concentration, for example, 1 x 10 19 cm -3 The dose of N is set so that

[0049] Alternatively, in the N ion implantation step shown in FIG. 3D, the N concentration not only at the implantation peak position but also in the entire contact formation region 25′ is 0.1 to 10 times the Mg concentration, for example, 1×10 19 cm -3 The N implantation energy and dose may be set so that the N ion implantation step shown in Fig. 3D may be performed by a single-stage ion implantation using a single acceleration energy, or may be performed by a multi-stage ion implantation using different acceleration energies.

[0050] In the N ion implantation step shown in FIG. 3D, N may be implanted not only into the contact formation region 25' but also into the well formation region 23'.

[0051] In the first embodiment of the present invention, the order of the Mg ion implantation step shown in Fig. 3C and the N ion implantation step shown in Fig. 3D may be interchanged. That is, the Mg ion implantation step shown in Fig. 3C may be performed after the N ion implantation step shown in Fig. 3D.

[0052] Next, as shown in FIG. 3E, the manufacturing equipment forms an insulating protective film 31 on the surface 10a of the GaN substrate 10. The protective film 31 has a function of preventing nitrogen atoms from being released from the GaN substrate 10 during heat treatment. Nitrogen vacancies are formed at positions where the nitrogen atoms are released from the GaN substrate 10. Since the nitrogen vacancies can function as donor-type defects, there is a possibility that the expression of P-type characteristics is inhibited. In order to prevent this, the manufacturing equipment provides the protective film 31 on the GaN substrate 10.

[0053] It is preferable that the protective film 31 has high heat resistance, good adhesion to the GaN substrate 10, does not diffuse impurities from the protective film 31 to the GaN substrate 10, and is selectively removable from the GaN substrate 10. The protective film 31 is an aluminum nitride (AlN) film, a SiO2 film, or a silicon nitride (SiN) film. The protective film 31 may be a laminated film including at least one of an AlN film, a SiO2 film, and a SiN film. An insulating film serving as an underlying layer of the protective film 31 may be provided between the GaN substrate 10 and the protective film 31. An example of the insulating film serving as an underlying layer is a SiO2 film.

[0054] Next, the manufacturing equipment performs a heat treatment at a maximum temperature of 1300° C. or more on the GaN substrate 10 covered with the protective film 31. This heat treatment is, for example, a rapid heating process. This heat treatment activates Mg and Si introduced into the GaN substrate 10. As a result, as shown in FIG. 3F, a P-type well region 23, a P+-type contact region 25, and an N+-type source region 26 are formed in the GaN substrate 10, and the drift region 22 is defined. This heat treatment also allows the GaN substrate 10 to recover to some extent from defects caused by ion implantation. After the heat treatment, the manufacturing equipment removes the protective film 31 from the GaN substrate 10.

[0055] Next, the manufacturing equipment forms a gate insulating film 42 (see FIG. 1) on the GaN substrate 10. Next, the manufacturing equipment forms a gate electrode 44 (see FIG. 1), a source electrode 54 (see FIG. 1), and a drain electrode 56 (see FIG. 1). Next, the manufacturing equipment forms an interlayer insulating film (not shown) on the gate electrode 44. Next, the manufacturing equipment forms a gate pad 112 (see FIG. 1) electrically connected to the gate electrode 44, and a source pad 114 (see FIG. 1) electrically connected to the source electrode 54. This completes the vertical MOSFET 1 shown in FIG. 1.

[0056] (Differences from structures formed by epitaxial growth methods) In the embodiment of the present invention, the P-type contact region 25 is formed by ion implantation of Mg followed by ion implantation of N (or ion implantation of N followed by ion implantation of Mg). Since the contact region 25 is formed by ion implantation, the following points (1) to (3) may be different from the case where a similar structure is formed by epitaxial growth.

[0057] (1) The contact region 25 has the same impurity concentration other than Mg as the surrounding regions (P-type well region 23, N+ type source region 26, etc.). For example, the contact region 25 and the well region 23 have the same impurity concentration other than Mg. Also, the contact region 25 and the source region 26 have the same impurity concentration other than Mg and Si. If a structure similar to the contact region 25 is formed by epitaxial growth, a difference in impurity concentration other than Mg (or other than Mg and Si) will occur between the contact region and the surrounding regions. In the embodiment of the present invention, such a difference does not occur.

[0058] (2) The contact region 25 does not have a Si peak at the interface with the surrounding region (the P-type well region 23, the N+ type source region 26, etc.). When a structure similar to the contact region 25 is formed by epitaxial growth, a Si peak occurs at the interface between the contact region and the surrounding region. This Si peak occurs when Si present in the atmosphere in the chamber is taken into the interface during regrowth. In the embodiment of the present invention, such a Si peak does not occur.

[0059] (3) There is no (or almost no) step between the surface of the contact region 25 and the surfaces of the surrounding regions (e.g., the P-type well region 23, the N+ type source region 26, etc.). If a structure similar to the contact region 25 is formed by epitaxial growth, a step occurs between the surface of the contact region and the surface of the surrounding region due to etching or selective epitaxial growth. In the embodiment of the present invention, such a step does not occur.

[0060] (Experimental Results) Next, experimental results (Example and Comparative Examples 1 and 2) regarding crystal defects and Mg segregation in the GaN layer will be shown.

[0061] (a) Example Fig. 4A is a cross-sectional TEM (Transmission Electron Microscope) image showing the analysis result of crystal defects in a GaN substrate according to an embodiment of the present invention, and Fig. 4B is a 3D-AP (3-Dimensional Atom Probe Microscope) image showing the analysis result of Mg segregation in a GaN substrate according to an embodiment of the present invention.

[0062] The GaN substrate according to the embodiment of the present invention was obtained by ion-implanting Mg into the GaN substrate, then ion-implanting N, and then subjecting the GaN substrate implanted with Mg and N to a heat treatment at 1300° C. for 5 minutes. In the Mg ion implantation, the depth from the surface of the GaN substrate to the implantation peak position was 500 nm, and the Mg concentration at the implantation peak position was 1×10 19 cm -3The implantation conditions (implantation energy and dose) were set so that the implantation conditions for N were set to be the same as those for Mg. That is, in the N ion implantation, the depth from the surface of the GaN substrate to the implantation peak position was 500 nm, and the N concentration at the implantation peak position was 1×10 19 cm -3 In this specification, the ion implantation of N following the ion implantation of Mg is also referred to as successive implantation of N.

[0063] As shown in Fig. 4A, no large crystal defects were observed in the GaN substrate according to the embodiment. For example, if the thickness of the sample is 100 nm, the density of crystal defects when there is one crystal defect such as a dislocation in the observation field of the cross-sectional TEM shown in Fig. 4A is about 6.3 × 10 13 cm -3 Since no crystal defects such as dislocations are observed in the observation field shown in FIG. 4A, the density of crystal defects (defect density) in the GaN substrate according to the example is 1×10 14 cm -3 4B, in the GaN substrate according to the example, non-rod-shaped Mg segregation (an example of the "non-rod-shaped acceptor segregation" of the present invention) was observed, but rod-shaped Mg segregation (an example of the "rod-shaped acceptor segregation" of the present invention) was not observed.

[0064] In this specification, the term "rod-shaped Mg segregation" refers to a structure in which the length in one direction is 30 nm or more and the Mg concentration is 5×10 20 cm -3 The term "one direction" refers to a direction parallel to the m-axis, for example. The m-axis refers to the crystal orientation <1-100> direction. Non-rod-shaped Mg segregation is defined as "a Mg segregation with a length of less than 30 nm in one direction and a Mg concentration of 5×10 or more." 20 cm -3 Mg segregation may also be called Mg segregation defects.

[0065] 5 is a graph showing the Mg concentration in the region (parent phase) where no Mg segregation occurs in the GaN substrate according to the embodiment of the present invention. The horizontal axis of FIG. 5 shows the depth (nm) from the surface of the GaN substrate, and the vertical axis shows the Mg concentration (cm -3 5, in the GaN substrate according to the embodiment, the Mg concentration in the region (parent phase) where no Mg segregation occurs is reduced by 1×10 19 cm -3 Although it has decreased from 5×10 18 cm -3 It was confirmed that the Mg concentration was maintained near the depth, and the variation in Mg concentration in the depth direction was also kept small.

[0066] (b) Comparative example 1 FIG. 6A is a cross-sectional TEM diagram showing the analysis result of crystal defects in the GaN substrate according to Comparative Example 1 of the present invention. FIG. 6B is a 3D-AP diagram showing the analysis result of Mg segregation in the GaN substrate according to Comparative Example 1 of the present invention. The GaN substrate according to Comparative Example 1 of the present invention was obtained by ion-implanting only Mg and subjecting the GaN substrate implanted with only Mg to a heat treatment at 1300° C. for 5 minutes. The ion-implantation conditions for Mg are the same as those in the examples. As shown in FIG. 6A, loop-shaped dislocations were observed in the GaN substrate according to Comparative Example 1. Also, as shown in FIG. 6B, rod-shaped Mg segregation was observed in the GaN substrate according to Comparative Example 1.

[0067] Fig. 7 is a graph showing the results of measuring the composition ratio of elements in rod-shaped Mg segregations and their surrounding regions in a GaN substrate according to Comparative Example 1 of the present invention using 3D-AP. The horizontal axis of Fig. 7 indicates the distance (nm) from the start point of the measurement range, and the vertical axis indicates the composition ratio of elements (at%). Fig. 8 is a cross-sectional TEM image showing the measurement range when the data shown in Fig. 7 was obtained. The left end of the measurement range shown in Fig. 8 corresponds to the position (start point) at a distance of 0 nm in Fig. 7. The right end of the measurement range shown in Fig. 8 corresponds to the position (end point) at a distance of 20 nm in Fig. 7.

[0068] As shown in Fig. 7, in the GaN substrate according to Comparative Example 1, in the region (parent phase) where no Mg segregation occurs, the Mg composition ratio was confirmed to be about 1 at%. Also, in the region where rod-shaped Mg segregation occurs, the Mg composition ratio was confirmed to be a maximum of about 10 at%. The width of the rod-shaped Mg segregation shown in Fig. 8 was confirmed to be 5 nm or less from the measurement results in Fig. 7.

[0069] 9 is a graph showing the Mg concentration in the region (parent phase) where no Mg segregation occurs in the GaN substrate according to Comparative Example 1 of the present invention. The horizontal axis of FIG. 9 shows the depth (nm) from the surface of the GaN substrate, and the vertical axis shows the Mg concentration (cm -3 9 , in the GaN substrate according to Comparative Example 1, the Mg concentration in the region (parent phase) where no Mg segregation occurs is 3×10 18 cm -3 The Mg concentration in the matrix of the GaN substrate according to Comparative Example 1 was also confirmed to vary more than in the Examples. It is believed that the GaN substrate according to Comparative Example 1 has lot-like Mg segregation, which results in a correspondingly lower Mg concentration in the matrix and a larger variation in the Mg concentration in the depth direction.

[0070] (c) Comparative example 2 Fig. 10A is a cross-sectional TEM image showing the analysis results of crystal defects in a GaN substrate according to Comparative Example 2 of the present invention, and Fig. 10B is a 3D-AP image showing the analysis results of Mg segregation in a GaN substrate according to Comparative Example 2 of the present invention.

[0071] The GaN substrate according to Comparative Example 2 of the present invention was obtained by implanting only Mg ions and then subjecting the GaN substrate implanted with only Mg to a heat treatment at 1200°C for 5 minutes. The Mg ion implantation conditions were the same as those in the Example. As shown in FIG. 10A, no crystal defects such as dislocations were observed in the GaN substrate according to Comparative Example 2. Furthermore, as shown in FIG. 10B, no Mg segregation was observed in the GaN substrate according to Comparative Example 2. The density of Mg segregation was 1×10 15 cm -3 is less than.

[0072] From the viewpoint of uniformity of Mg concentration, it is preferable that there is no segregation of Mg. However, when the heat treatment temperature is 1200°C as in Comparative Example 2, recovery of crystal defects caused by ion implantation of Mg and activation of Mg are insufficient, and Mg does not function sufficiently as an acceptor. Therefore, although segregation of Mg occurs, it is preferable that the heat treatment temperature is 1300°C or higher as in the examples.

[0073] (Effects of the First Embodiment) As described above, the GaN semiconductor device 100 according to the first embodiment of the present invention includes the GaN substrate 10 and the vertical MOSFET 1 provided on the GaN substrate 10. The vertical MOSFET 1 is provided on the GaN substrate 10 and has an acceptor element concentration of 5×10 18 cm -3 More than 2×10 20 cm -3 and a P-type contact region 25 having a length of 30 nm or more in one direction (for example, a direction parallel to the m-axis) and an elemental concentration of magnesium (Mg) of 5×10 20 cm -3 The density of the rod-shaped Mg segregation (see FIG. 6B) in the contact region 25 is 1×10 14 cm -3 This suppresses the occurrence of rod-shaped Mg segregation in the contact region 25, thereby suppressing variations in the Mg concentration due to segregation. This makes it possible to realize a contact region 25 with a high concentration and small variations in concentration.

[0074] The contact region 25 has a length of less than 30 nm in one direction (for example, a direction parallel to the m-axis) and a Mg concentration of 5×10 20 cm -3 The density of the non-rod-shaped Mg segregation in the contact region 25 may be 1×10 15 cm -3Even in such a case, the occurrence of rod-shaped Mg segregation is suppressed in the contact region 25, so that it is possible to suppress the variation in Mg concentration due to segregation. This makes it possible to realize the contact region 25 having a high concentration and small variation in concentration.

[0075] The method for manufacturing the GaN semiconductor device 100 according to the first embodiment of the present invention includes the steps of ion-implanting Mg into the contact formation region 25' of the GaN substrate 10, ion-implanting nitrogen (N) into the contact formation region 25' before or after the step of ion-implanting Mg, and performing a heat treatment on the GaN substrate 10 into which Mg and N have been ion-implanted to form a P-type contact region 25 in the contact formation region 25'. In the step of ion-implanting Mg, the concentration of the Mg ions implanted is set to 5×10 18 cm -3 More than 2×10 20 cm -3 The implantation conditions (for example, acceleration energy and dose amount) are set as follows: This makes it possible to manufacture a MOSFET 1 having a contact region 25 with a high concentration and small variation in concentration.

[0076] <Embodiment 2> In the embodiment of the present invention, the drift region 22 may be doped (counter doped) to increase the concentration of N-type impurities.

[0077] Fig. 11 is a cross-sectional view showing a configuration of a vertical MOSFET 1A according to a second embodiment of the present invention. As shown in Fig. 11, the vertical MOSFET 1A according to the second embodiment includes an N-type doped region cd provided in an N-type drift region 22. The doped region cd is a region doped with an N-type impurity (e.g., Si). In the drift region 22, a region other than the doped region cd is an undoped region ucd. The doped region cd has a higher concentration of N-type impurity (e.g., Si) than the undoped region ucd.

[0078] The doped region cd is located closer to the surface 10a of the GaN substrate 10 than the undoped region ucd. For example, the doped region cd is provided continuously over the entire upper region (JFET region) 221 and the end of the lower region 222 that is in contact with the upper region 221.

[0079] Even with this configuration, it is possible to realize the contact region 25 having a high concentration and small variation in concentration. Furthermore, in the vertical MOSFET 1A, the N-type impurity concentration in the region adjacent to the channel region 231 in the drift region 22 can be increased, and therefore the on-resistance can be reduced while suppressing a decrease in the breakdown voltage.

[0080] <Embodiment 3> In the above-described first and second embodiments, the GaN semiconductor device 100 is described as including a vertical MOSFET having a planar structure. However, the vertical MOSFET is not limited to a planar structure. The vertical MOSFET may have a trench gate structure. For example, the GaN semiconductor device 100 may include a vertical MOSFET 1B having a trench gate structure, which will be described below.

[0081] Fig. 12 is a cross-sectional view showing a configuration example of a vertical MOSFET 1B according to embodiment 3 of the present invention. As shown in Fig. 12, the vertical MOSFET 1B has a trench H provided in a GaN substrate 10. The trench H opens on the front surface 10a side of the GaN substrate 10. The trench H is formed deeper than the P-type well region 23, and the bottom of the trench H reaches the N-type region.

[0082] A gate insulating film 42 and a gate electrode 44 are disposed inside the trench H. The inner side surface and bottom surface of the trench H are covered with the gate insulating film 42. The gate electrode 44 is embedded in the trench H via the gate insulating film 42. In the vertical MOSFET 1B, a region facing the gate electrode 44 via the gate insulating film 42 provided on the inner side surface of the trench H becomes a channel region 231.

[0083] Even with this configuration, it is possible to realize a contact region 25 with a high concentration and small variation in concentration. Furthermore, by adopting a trench gate structure, the vertical MOSFET 1B can arrange the channel regions 231 more densely. The vertical MOSFET 1B enables miniaturization of the element size and improvement of the channel density.

[0084] (Other embodiments) As described above, the present invention has been described by the first to third embodiments, but the descriptions and drawings forming a part of this disclosure should not be understood as limiting the present invention. Various alternative embodiments and modifications will become apparent to those skilled in the art from this disclosure.

[0085] For example, the gate insulating film 42 is not limited to a SiO2 film, and may be another insulating film. A silicon oxynitride (SiON) film, a strontium oxide (SrO) film, a silicon nitride (Si3N4) film, or an aluminum oxide (Al2O3) film may also be used for the gate insulating film 42. A composite film in which several single-layer insulating films are stacked may also be used for the gate insulating film 42. A vertical MOSFET using an insulating film other than a SiO2 film as the gate insulating film 42 may be called a vertical MISFET. MISFET refers to a more comprehensive insulated gate transistor that includes a MOSFET.

[0086] In the above embodiment, the contact region 25 is described as being included in a vertical MISFET. However, the embodiment of the present invention is not limited to this. The contact region 25 may be included in a lateral MISFET in which a current flows in the horizontal direction of the GaN substrate, instead of a vertical MISFET in which a current flows in the vertical direction of the GaN substrate.

[0087] In the above embodiment, the electrode in contact with the contact region 25 is described as the source electrode 54. However, the embodiment of the present invention is not limited to this. The contact region 25 may be in contact with an electrode other than the source electrode. The P-type region exemplified by the contact region 25 may be included in an element other than a MOSFET, for example, a bipolar transistor, a diode, a capacitance element, a resistance element, or the like.

[0088] In the above embodiment, as an example of the manufacturing method, in each step of Figures 3A, 3B, 3C, and 3D, ions may be implanted while the surface 10a of the GaN substrate 10 is protected by an insulating film (through film). By having the through film bear part of the damage during ion implantation (i.e., the energy given to the GaN substrate 10 by the ions), defects occurring in the GaN substrate 10 during ion implantation are reduced. This makes it possible to further suppress segregation after heat treatment. For example, a SiO2 film, a SiN film, or an AlN film may be used as the through film.

[0089] In addition, in each step of FIG. 3A, 3B, 3C, and 3D, ion implantation (high-temperature ion implantation) may be performed while the GaN substrate 10 is held at a high temperature. Mg or N, or both Mg and N, may be ion-implanted at high temperature. This allows defects occurring in the GaN substrate 10 during ion implantation to be restored at the high temperature during ion implantation. Ion implantation and defect restoration can be performed simultaneously, and defects occurring during ion implantation can be restored to a certain degree before heat treatment. This makes it possible to further suppress segregation after heat treatment. The above-mentioned high temperature (temperature of high-temperature ion implantation) is, for example, 500°C or higher and 1500°C or lower, more preferably 800°C or higher and 1300°C or lower, and is, for example, about 1000°C.

[0090] In addition, in each of the steps of FIG. 3A, 3B, 3C, and 3D, the ion implantation rate is set to 5×10 10 atoms / (cm 2 s) or more. 10 atoms / (cm 2By implanting ions at a rate of 0.1 s or more, defect recovery due to self-heating can be expected.

[0091] In the embodiment of the present invention, the concentration of carbon (C) in the GaN substrate is 1×10 16 cm -3 Carbon compensates for both the donor and the acceptor, but by defining the concentration of the carbon element as above, unintended compensation by carbon can be reduced.

[0092] Thus, the present technology naturally includes various embodiments not described herein. At least one of various omissions, substitutions, and modifications of components can be made without departing from the spirit of the above-mentioned embodiments and modifications. In addition, the effects described in this specification are merely examples and are not limited to the present invention, and other effects may also be present. [Explanation of symbols]

[0093] 1, 1A, 1B Vertical MOSFET 10 GaN substrate 10a surface 10b back side 22 Drift Region 23 Well Area 23´ Well formation area 25 Contact Area 25´ Contact formation area 26 Source Area 26´ Source formation region 31 Protective film 42 Gate insulating film 44 Gate electrode 54 Source electrode 56 Drain electrode 100 GaN semiconductor device 110 Active area 112 Gate Pad 114 Sauce Pad 130 Edge Termination Area 221 Upper area (JFET area) 222 Lower area 231 Channel Region cd doped region D Drain terminal G Gate terminal H Trench M1, M2, M3 Masks S Source terminal ucd Undoped region

Claims

1. A nitride semiconductor; The nitride semiconductor is provided with an acceptor element having a concentration of 5×10 １８ cm －３ Above 2 x 10 ２０ cm －３ and a P-type region, The length in one direction is 30 nm or more, and the concentration of the acceptor element is 5×10 ２０ cm －３ The density of the rod-shaped acceptor segregation in the P-type region is 1×10 １４ cm －３ is as follows: The one direction is a direction parallel to the m-axis.

2. A nitride semiconductor, a P-type region provided in the nitride semiconductor, the P-type region having an acceptor element concentration of 5×10 18 cm −3 or more and 2×10 20 cm −3 or less; the density of rod-shaped acceptor segregations having a length in one direction of 30 nm or more and a concentration of the acceptor element of 5×10 20 cm −3 or more in the P-type region is 1×10 14 cm −3 or less; The P-type region has a length in one direction of less than 30 nm and a concentration of the acceptor element of 5×10 ２０ cm －３ or more of non-rod-shaped acceptor segregation, The density of the non-rod-shaped acceptor segregation in the P-type region is 1×10 １５ cm －３ This is the nitride semiconductor device.

3. The nitride semiconductor has a threading dislocation density of 1×10 ７ cm －２ 3. The nitride semiconductor device according to claim 1, comprising a low dislocation free-standing gallium nitride (GaN) substrate having less than 1000 nm dislocation density.

4. 4. The nitride semiconductor device according to claim 1, wherein the acceptor element includes at least one of magnesium (Mg) and beryllium (Be).

5. a P-type well region provided in the nitride semiconductor and having a lower concentration of the acceptor element than the P-type region; The nitride semiconductor device according to claim 1 , wherein said P-type region is provided on a surface side of said P-type well region.

6. The concentration of the acceptor element in the P-type well region is 1×10 １６ cm －３ Above 3 x 10 １８ cm －３ The nitride semiconductor device according to claim 5 , wherein:

7. 7. The nitride semiconductor device according to claim 5, wherein said P-type region and said P-type well region have the same impurity concentration other than said acceptor element.

8. an N-type source region provided on a surface side of the P-type well region; a gate insulating film provided on the P-type well region; a gate electrode provided on the gate insulating film; a source electrode provided on the nitride semiconductor and in contact with an N-type source region; The nitride semiconductor device according to claim 5 , further comprising: a drain electrode provided on a surface of the nitride semiconductor opposite to a surface on which the source electrode is provided.

9. The nitride semiconductor device according to claim 8 , wherein said P-type region is in contact with said source electrode.

10. ion-implanting an acceptor element into a partial region of the nitride semiconductor; a step of ion-implanting nitrogen into the partial region before or after the step of ion-implanting the acceptor element; and performing a heat treatment on the nitride semiconductor into which the acceptor element and the nitrogen have been ion-implanted to form a P-type region in the partial region, In the step of ion-implanting the acceptor element, The concentration of the acceptor element to be ion-implanted is 5×10 １８ cm －３ Above 2 x 10 ２０ cm －３ Set the injection conditions as follows: In the step of forming the P-type region, forming the P-type region containing rod-shaped acceptor segregations having a length in one direction of 30 nm or more and a concentration of the acceptor element of 5×10 20 cm −3 or more at a density of 1×10 14 cm −3 or less; The one direction is a direction parallel to the m-axis.

11. In the step of ion-implanting nitrogen, The method for manufacturing a nitride semiconductor device according to claim 10, wherein conditions for ion implantation are set so that the elemental concentration of said nitrogen in said partial region is 0.1 to 10 times the concentration of said acceptor element.

12. The method further includes forming an insulating protective film on the partial region, The method for manufacturing a nitride semiconductor device according to claim 10 , wherein in the step of performing the heat treatment, the heat treatment is performed on the nitride semiconductor in a state where the partial region is covered with the protective film.

13. The method for manufacturing a nitride semiconductor device according to claim 10, wherein the maximum temperature of the heat treatment is 1300° C. or higher.

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