DML Driver

Abstract

This DML driver (11) according to the present invention comprises: a PMOS transistor (M1p); an NMOS transistor (M1n); resistors (R2, R4); a decoupling capacitor (C1) connected between a power supply voltage (V1) and ground; a decoupling capacitor (C2a) connected between a bias voltage (V2) and the power supply voltage (V1); a decoupling capacitor (C2b) connected between a gate of the PMOS transistor (M1p) and the power supply voltage (V1); and a decoupling capacitor (C4b) connected between a bias voltage (V4) and the power supply voltage (V1).

Description

[Technical field]

[0001] The present invention relates to The present invention relates to a technique for driving a directly modulated laser (DML), and more particularly to a DML driver capable of suppressing deterioration of the output waveform of the driver during multi-channel driving. [Background technology]

[0002] In recent years, the remarkable development of SNS (Social Networking Services) has led to an increase in the volume of communication traffic around the world. In the future, the volume of traffic is expected to increase further due to the development of IoT (Internet of Things) and cloud computing technology, and in order to support this huge volume of traffic, there is a demand for increased communication capacity both inside and outside data centers.

[0003] With the increase in capacity, the standardization of 100GbE has been completed for Ethernet (registered trademark), which is a major element of the network standard, and standardization of 400GbE, which aims for an even larger capacity, is currently under discussion. Drivers using DML are attracting attention from the viewpoint of low power consumption for the purpose of application to 400GbE (see Non-Patent Document 1).

[0004] 10 is a circuit diagram showing the configuration of a conventional DML driver. The DML driver includes a PMOS transistor M1 having a source connected to a power supply voltage V1 and a drain connected to the anode of a laser diode (LD) 1. 1p And the gate is modulated by the signal V in The input is an NMOS transistor M 1n and the drain is a PMOS transistor M 1p and the anode of LD1, and the source of the NMOS transistor M 1n NMOS transistor M connected to the drain of 2nOne end is connected to a bias voltage V2, and the other end is connected to a PMOS transistor M 1p A resistor R2 is connected to the gate of the NMOS transistor M 2n A resistor R3 is connected to the gate of the NMOS transistor M 1n the gate of the first transistor, a decoupling capacitor C1 having one end connected to a power supply voltage V1 and the other end connected to ground, a decoupling capacitor C2 having one end connected to a bias voltage V2 and the other end connected to ground, a decoupling capacitor C3 having one end connected to a bias voltage V3 and the other end connected to ground, and a decoupling capacitor C4 having one end connected to a bias voltage V4 and the other end connected to ground.

[0005] NMOS transistor M 1n and M. 2n are connected in cascode, and the NMOS transistor M 1n The frequency characteristics are improved compared to when it is a single transistor. Also, even if the operating voltage of LD1 exceeds the withstand voltage of the NMOS transistor alone, the voltage is divided by the cascode connection, so the NMOS transistor M 1n ,M 2n This can prevent breakdown of the power supply. Decoupling capacitor C1 stabilizes the power supply voltage V1. Resistor R2 and decoupling capacitor C2 stabilize the bias voltage V2. Resistor R3 and decoupling capacitor C3 stabilize the bias voltage V3. Decoupling capacitor C4 stabilizes the bias voltage V4. Resistor R4 is an impedance matching resistor.

[0006] When connecting the power supplies that supply the power supply voltage V1 and the bias voltages V2 to V4 to the driver IC via cables or boards, it is necessary to take into consideration parasitic inductance and parasitic resistance. Figure 11 shows a conventional circuit configuration that includes the parasitic components of each power supply. In the example of Figure 11, the parasitic inductance L w1 and the parasitic resistance R w1are connected in series with the V2 power supply, creating a parasitic inductance L w2 and the parasitic resistance R w2 are connected in series. Also, there is a parasitic inductance L w3 and the parasitic resistance R w3 are connected in series with the V4 power supply, creating a parasitic inductance L w4 and the parasitic resistance R w4 In Figure 11, the parasitic inductance L w1 ~L w4 The parasitic capacitance between the terminal of the DML driver to which the resistor is connected and ground is omitted.

[0007] Here, let us focus on the power supply line V1 through which current flows. 1p The source impedance Z v1 If (s) is expressed using the Laplace function, it becomes as shown in the following equation (1).

[0008]

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[0009] In equation (1), s is the Laplace operator. 1p Since there is no load impedance in series with the source in the circuit, the Z v1 Since (s) directly becomes the load impedance of the V1 power supply, it causes resonance in the power supply line.

[0010] 10 and 11 show the configuration for one channel, but when a multi-channel LD array and a multi-channel DML driver are prepared and the multi-channel DML driver is driven by a multi-stage PRBS (Pseudo Random Bit Sequence) signal, the power supply V1 is shared by the DML driver of each channel. Similarly, the power supplies V2 to V4 are also shared by the DML driver of each channel.

[0011] When driving multiple channels of a DML driver that shares a power supply like this with a multi-stage PRBS signal, crosstalk between channels causes waveform degradation due to an increase in impedance in the V1 power line. If the decoupling capacitor C1 is an extremely large value, waveform degradation can be sufficiently suppressed, but it is difficult to create a capacitor with an extremely large value within an IC, and the decoupling capacitor C1 alone cannot suppress the increase in impedance in the low range, so it is insufficient as a measure against waveform degradation when driving multiple channels with a multi-stage PRBS signal. [Prior art documents] [Non-patent literature]

[0012] [Non-Patent Document 1] T. Kishi et al., “A 137-mW,4 ch x 25-Gbps low-power compact transmitter flip-chip-bonded 1.3-μm LD-array-on-Si”, In Proceedings of the Optical Fiber Communication Conference and Exhibition, 2018, Paper M2D.2. Summary of the Invention [Problem to be solved by the invention]

[0013] The present invention has been made to solve the above-mentioned problems, and has an object to provide a DML driver that can suppress an increase in impedance of a power supply line and suppress deterioration of an output waveform. [Means for solving the problem]

[0014] The DML driver of the present invention includes a first transistor having a source or emitter connected to a first power supply voltage and a drain or collector connected to an anode of a laser diode, a second transistor having a gate or base to which a signal is input, a drain or collector connected to the anode of the laser diode, and a source or emitter connected to a second power supply voltage, a first resistor having one end connected to a first bias voltage and the other end connected to the gate or base of the first transistor, and a second resistor having one end connected to a second bias voltage and the other end connected to the gate or base of the second transistor. a second resistor connected to the gate or base of the first transistor, a first decoupling capacitor having one end connected to the first power supply voltage and the other end connected to the second power supply voltage, a second decoupling capacitor having one end connected to the first bias voltage and the other end connected to the first power supply voltage, a third decoupling capacitor having one end connected to the gate or base of the first transistor and the other end connected to the first power supply voltage, and a fourth decoupling capacitor having one end connected to the second bias voltage and the other end connected to the first power supply voltage.

[0015] Moreover, one configuration example of the DML driver of the present invention further includes a third transistor cascode-connected between the anode of the laser diode and the drain or collector of the second transistor, a third resistor having one end connected to a third bias voltage and the other end connected to the gate or base of the third transistor, a fifth decoupling capacitor having one end connected to the third bias voltage and the other end connected to the first power supply voltage, and a sixth decoupling capacitor having one end connected to the gate or base of the third transistor and the other end connected to the first power supply voltage. Moreover, one configuration example of the DML driver of the present invention further includes a fourth transistor cascode-connected between the drain or collector of the first transistor and the anode of the laser diode, a fourth resistor having one end connected to a fourth bias voltage and the other end connected to the gate or base of the fourth transistor, a seventh decoupling capacitor having one end connected to the fourth bias voltage and the other end connected to the first power supply voltage, and an eighth decoupling capacitor having one end connected to the gate or base of the fourth transistor and the other end connected to the first power supply voltage. Moreover, one configuration example of the DML driver of the present invention further includes a fifth resistor inserted between the first power supply voltage and the source or emitter of the first transistor. Effect of the Invention

[0016] According to the present invention, an increase in the impedance of the power supply line can be suppressed, thereby suppressing crosstalk between channels when multiple channels of DML drivers sharing a common power supply are driven, and resonance of the power supply line at low frequencies can be suppressed, thereby suppressing deterioration of the output waveform. [Brief description of the drawings]

[0017] [Figure 1] FIG. 1 is a circuit diagram showing a configuration of a DML driver according to a first embodiment of the present invention. [Diagram 2] FIG. 2 is a diagram showing parasitic components of each power supply of the DML driver according to the first embodiment of the present invention. [Diagram 3] FIG. 3 is a diagram showing the results of simulating the EO response characteristics of the DML driver and LD for the conventional configuration and the first embodiment of the present invention. [Figure 4] FIG. 4 is a diagram showing the results of simulating the group delay characteristics of the DML driver and LD for the conventional configuration and the first embodiment of the present invention. [Diagram 5]FIG. 5 is a diagram showing the results of simulating the inter-channel crosstalk characteristics of the DML driver for the conventional configuration and this embodiment. [Figure 6] FIG. 6 is a circuit diagram of a DML driver according to a first embodiment of the present invention having a multi-channel configuration. [Figure 7] FIG. 7 is a diagram showing the results of simulating the optical output waveform of the LD for the conventional configuration and this embodiment. [Figure 8] FIG. 8 is a circuit diagram showing a configuration of a DML driver according to the second embodiment of the present invention. [Figure 9] FIG. 9 is a circuit diagram showing a configuration of a DML driver according to a third embodiment of the present invention. [Figure 10] FIG. 10 is a circuit diagram showing the configuration of a conventional DML driver. [Figure 11] FIG. 11 is a diagram showing parasitic components of each power supply of a conventional DML driver. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0018] [Principle of the invention] In the present invention, by changing the connection destination of the decoupling capacitor of each power supply line from ground to the power supply voltage V1, it is possible to suppress the increase in impedance of the power supply line at low frequencies compared to the conventional circuit configuration, and to suppress degradation of the output waveform.

[0019] [First Example] Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram showing the configuration of a DML driver according to a first embodiment of the present invention. A DML driver 11 of this embodiment includes a PMOS transistor M1 having a source connected to a power supply voltage V1 (first power supply voltage) and a drain connected to the anode of LD1. 1p And the gate is modulated by the signal V in is input, and the source is connected to ground (the second power supply voltage). 1n and the drain is a PMOS transistor M 1pand the anode of LD1, and the source of the NMOS transistor M 1n NMOS transistor M connected to the drain of 2n One end is connected to a bias voltage V2 (first bias voltage) and the other end is connected to a PMOS transistor M 1p A resistor R2 is connected to the gate of the NMOS transistor M. One end of the resistor R2 is connected to a bias voltage V3 (third bias voltage) and the other end of the resistor R2 is connected to the gate of the NMOS transistor M. 2n A resistor R3 is connected to the gate of the NMOS transistor M1, one end of which is connected to a bias voltage V4 (second bias voltage) and the other end of which is connected to the gate of the NMOS transistor M2. 1n A resistor R4 is connected to the gate of the MOSFET; a decoupling capacitor C1 is connected to the power supply voltage V1 and the other end is connected to ground; and a decoupling capacitor C1 is connected to the bias voltage V2 and the other end is connected to the power supply voltage V1. 2a One end is a PMOS transistor M 1p The other end of the decoupling capacitor C is connected to the gate of 2b and a decoupling capacitor C whose one end is connected to the bias voltage V3 and whose other end is connected to the power supply voltage V1. 3a One end is an NMOS transistor M 2n The other end of the decoupling capacitor C is connected to the gate of 3b and a decoupling capacitor C whose one end is connected to the bias voltage V4 and whose other end is connected to the power supply voltage V1. 4b It consists of:

[0020] The magnitude relationship of each voltage is V1>V2>V3>V4>GND (ground). In this embodiment, in order to suppress the resonance of the power supply line of V1, the connection destinations of the decoupling capacitors C2, C3, and C4 in FIG. 10 are changed from the ground to the power supply voltage V1. 2b ,C 3b ,C 4b In order to further suppress the resonance, decoupling capacitors C 2a ,C 3a was added and connected to the power supply voltage V1.

[0021] FIG. 2 shows the circuit configuration of this embodiment including the parasitic components of each power supply. As in the case of FIG. 11, attention is focused on the power supply line V1 through which current flows, and the PMOS transistor M 1p The source impedance Z v1 If (s) is expressed using the Laplace function, it becomes as shown in the following equation (2).

[0022]

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[0023] Comparing formula (1) and formula (2), according to this embodiment, the PMOS transistor M 1p The source impedance Z v1 It can be seen that (s) can be reduced.

[0024] The results of simulating the EO (Electrical-to-Optical) response characteristics of the DML driver and LD1 for the conventional configuration and this embodiment are shown in Fig. 3. In Fig. 3, 100 indicates the EO response characteristics of the conventional configuration shown in Fig. 10, 101 indicates the EO response characteristics of this embodiment, and 102 indicates the EO response characteristics in an ideal state in which the parasitic components of each power supply are removed from the configuration of this embodiment. As can be seen from Fig. 3, according to this embodiment, it is possible to suppress resonance of the power supply line at low frequencies and to produce results close to the ideal state.

[0025] Next, the group delay characteristics of the DML driver and LD1 for the conventional configuration and this embodiment are obtained by simulation, and are shown in Fig. 4. In Fig. 4, 103 indicates the group delay characteristics of the conventional configuration, 104 indicates the group delay characteristics of this embodiment, and 105 indicates the group delay characteristics in an ideal state in which the parasitic components of each power supply are removed from the configuration of this embodiment. It can be seen from Fig. 4 that the group delay characteristics in the low range are improved in this embodiment compared to the conventional circuit configuration.

[0026] Next, the results of simulating the inter-channel crosstalk characteristics of the DML driver for the conventional configuration and this embodiment are shown in Fig. 5. In Fig. 5, 106 indicates the inter-channel crosstalk characteristics of the conventional configuration, and 107 indicates the inter-channel crosstalk characteristics of this embodiment. A circuit diagram of the conventional DML driver shown in Fig. 10 with a multi-channel configuration is disclosed in Non-Patent Document 1. Fig. 6 shows a circuit diagram of the DML driver of this embodiment with a multi-channel configuration.

[0027] In the example of FIG. 6 of Non-Patent Document 1, an example of a four-channel configuration is shown. For an LD array 10 having LDs 1 for four channels, DML drivers 11-1 to 11-4 for four channels that drive the respective LDs 1 are provided in a driver IC (Integrated Circuit) 12. Resistors R2 and R3 and decoupling capacitors C1 and C2 are provided in the driver IC 12. 2a ,C 2b ,C 3a ,C 3b ,C 4b are provided in common to each channel. Each DML driver 11-1 to 11-4 is connected to each power supply V1 to V4, resistors R2 and R3, and decoupling capacitors C1 and C 2a ,C 2b ,C 3a ,C 3b ,C 4b Share.

[0028] Fig. 5 shows the results of calculating the loss due to crosstalk between adjacent channels in such a multi-channel configuration. As can be seen from Fig. 5, the loss in the low frequency range is improved in this embodiment compared to the conventional circuit configuration.

[0029] Next, the results of simulating the optical output waveforms of LD1 when multiple channels are simultaneously driven for the conventional configuration and this embodiment are shown in Figures 7(A) to 7(C). The scale of amplitude on the vertical axis is 500 μW / div, and the scale of time on the horizontal axis is 20 ps / div. Figure 7(A) shows the optical output waveform when the conventional configuration is used, Figure 7(B) shows the optical output waveform when the configuration of this embodiment is used, and Figure 7(C) shows the optical output waveform in an ideal state in which the parasitic components of each power supply are removed from the configuration of this embodiment. Comparing Figures 7(A) and 7(B), it can be seen that this embodiment has improved by about 2 ps in the time direction and about 13 μW in the amplitude direction.

[0030] As described above, according to this embodiment, it is possible to suppress an increase in the impedance of the power supply line of V1, thereby suppressing crosstalk between channels when DML drivers sharing a power supply are driven in multi-channel mode with multi-stage PRBS signals, suppressing resonance of the power supply line at low frequencies, and suppressing degradation of the output waveform.

[0031] [Second Example] Next, a second embodiment of the present invention will be described. Fig. 8 is a circuit diagram showing the configuration of a DML driver according to the second embodiment of the present invention. The DML driver 11a of this embodiment includes a PMOS transistor M 1p and NMOS transistor M 1n and PMOS transistor M 1p One or more PMOS transistors M1 and M2 are connected in cascode between the drain of 2p -1~M 2p -x, the anode of LD1 and the NMOS transistor M 1n One or more NMOS transistors M 2n -1~M 2n -y, a resistor R2, one end of which is connected to bias voltages V3-1 to V3-y (third bias voltages) and the other end of which is connected to an NMOS transistor M 2n -1~M 2na resistor R4, one end of which is connected to bias voltages V5-1 to V5-x (fourth bias voltages) and the other end of which is connected to a PMOS transistor M 2p -1~M 2p One or more resistors R5-1 to R5-x connected to the gates of the 2a ,C 2b and one or more decoupling capacitors C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, C11, C12, C13, C14, C15, C16, C17, C18, C21, C22, C31, C32, C43, C54, C65, C76, C87, C98, C10, C11, C12, C1 3a -1~C 3a -y and one end of the NMOS transistor M 2n -1~M 2n One or more decoupling capacitors C connected to the gate of 3b -1~C 3b -y and the decoupling capacitor C 4b and one or more decoupling capacitors C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, C11, C12, C13, C14, C15, C16, C17, C18, C21, C22, C31, C42, C53, C64, C75, C86, C97, C10, C11, C12, C13, C2 5a -1~C 5a -x and one end of a PMOS transistor M 2p -1~M 2p One or more decoupling capacitors C 5b -1~C 5b -x.

[0032] The magnitude relationship of each voltage is V1>V2>V5-1>···>V5-x>V3-y>···>V3-1>V4>GND (ground). To cascode connect PMOS transistors, connect the source to the drain of the upper PMOS transistor, and connect the drain to the source of the lower PMOS transistor or the anode of LD1. To cascode connect NMOS transistors, connect the source to the drain of the lower NMOS transistor, and connect the drain to the source of the upper NMOS transistor or the anode of LD1.

[0033] In this way, a multi-stage circuit configuration can be used to prevent breakdown in both PMOS and NMOS transistors. This is effective because the breakdown voltage per transistor decreases at the most advanced nodes. 1p PMOS transistor M 2p -1~M 2p -x for x stages, NMOS transistor M 1n NMOS transistor M 2n -1~M 2n -y is the yth row. Both x and y are 1 or more.

[0034] In this embodiment, when a multi-channel configuration is used, similarly to FIG. 6, the power supplies V1, V2, V3-1 to V3-y, V4, V5-1 to V5-x, resistors R2, R3-1 to R3-y, R5-1 to R5-x, and decoupling capacitors C1 and C2 are connected. 2a ,C 2b ,C 3b -1~C 3b -y,C 4b ,C 5b -1~C 5b Each of -x is shared by the DML driver of each channel.

[0035] [Third Example] Next, a third embodiment of the present invention will be described. Fig. 9 is a circuit diagram showing the configuration of a DML driver according to the third embodiment of the present invention. A DML driver 11b of this embodiment differs from the DML driver 11 of the first embodiment in that it has a power supply voltage V1 and a PMOS transistor M 1p A resistor R add The PMOS transistor M 1p A resistor R is connected in series with the source of add By connecting this, the effects of power supply resonance can be suppressed.

[0036] In this embodiment, when a multi-channel configuration is used, the power supplies V1 to V4, resistors R2 and R3, and decoupling capacitors C1 and C2 are connected in the same manner as in FIG. 2a ,C 2b ,C3a ,C 3b ,C 4b Each of these is shared by the DML driver of each channel. In addition, the power supply voltage V1 and the PMOS transistor M 1p A resistor R add Insert resistor R add can be shared by the DML drivers of each channel. In FIG. 9, the first embodiment includes a resistor R add is applied, but in the second embodiment, resistor R add may be applied.

[0037] In addition, when there is no problem with the withstand voltage of the NMOS transistor, the NMOS transistor M 2n and the NMOS transistor M 1n The drain of LD1 may be connected to the anode of LD1. In this case, resistor R3 and decoupling capacitor C 3a ,C 3b This eliminates the need for bias voltage V3.

[0038] In the second embodiment, if there is no problem with the withstand voltage of the PMOS transistor, 2p -1~M 2p -x is omitted, and the PMOS transistor is M 1p In this case, only resistors R5-1 to R5-x and decoupling capacitor C 5b -1~C 5b -x and bias voltages V5-1 to V5-x are not required.

[0039] In the first to third embodiments, the transistor M 1p ,M 2p -1~M 2p -x,M 1n ,M 2n -1~M 2n Although an example using a MOS transistor as -y is shown, the transistor M 1p ,M 2p -1~M 2p-x is a PNP bipolar transistor, and the transistor M 1n ,M 2n -1~M 2n An NPN bipolar transistor may be used as -y. When using a bipolar transistor, the gate may be replaced with a base, the drain with a collector, and the source with an emitter in the explanations of the first to third embodiments. [Industrial Applicability]

[0040] The present invention can be applied to a technique for directly modulating the optical output of an LD. [Explanation of symbols]

[0041] 1...LD, 10...LD array, 11, 11-1 to 11-4, 11a, 11b...DML driver, 12...Driver IC, M 1p ,M 2p -1~M 2p -x…PMOS transistor, M 1n ,M 2n -1~M 2n -y...NMOS transistor, R2, R3, R3-1 to R3-y, R4, R5-1 to R5-x...resistors, C1, C 2a ,C 2b ,C 3a ,C 3b ,C 3a -1~C 3a -y,C 3b -1~C 3b -y,C 4b ,C 5a -1~C 5a -x,C 5b -1~C 5b -x...decoupling capacitors.

Claims

1. a first transistor having a source or emitter connected to a first power supply voltage and a drain or collector connected to an anode of the laser diode; a second transistor having a gate or a base to which a signal is input, a drain or a collector connected to the anode of the laser diode, and a source or an emitter connected to a second power supply voltage; a first resistor having one end connected to a first bias voltage and the other end connected to the gate or base of the first transistor; a second resistor having one end connected to a second bias voltage and the other end connected to the gate or base of the second transistor; a first decoupling capacitor having one end connected to the first power supply voltage and the other end connected to the second power supply voltage; a second decoupling capacitor having one end connected to the first bias voltage and the other end connected to the first power supply voltage; a third decoupling capacitor having one end connected to the gate or base of the first transistor and the other end connected to the first power supply voltage; a fourth decoupling capacitor having one end connected to the second bias voltage and the other end connected to the first power supply voltage.

2. 2. The DML driver of claim 1, a third transistor cascoded between the anode of the laser diode and the drain or collector of the second transistor; a third resistor having one end connected to a third bias voltage and the other end connected to the gate or base of the third transistor; a fifth decoupling capacitor, one end of which is connected to the third bias voltage and the other end of which is connected to the first power supply voltage; a sixth decoupling capacitor having one end connected to the gate or base of the third transistor and the other end connected to the first power supply voltage.

3. 3. The DML driver according to claim 1, a fourth transistor cascoded between the drain or collector of the first transistor and the anode of the laser diode; a fourth resistor having one end connected to a fourth bias voltage and the other end connected to the gate or base of the fourth transistor; a seventh decoupling capacitor having one end connected to the fourth bias voltage and the other end connected to the first power supply voltage; an eighth decoupling capacitor having one end connected to the gate or base of the fourth transistor and the other end connected to the first power supply voltage.

4. 4. The DML driver according to claim 1, The DML driver further comprising a fifth resistor inserted between the first power supply voltage and the source or emitter of the first transistor.

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