DML Driver

Abstract

A DML driver (10) comprises: a PMOS transistor (M1p) having a gate connected to a bias voltage (V2), a source connected to a power supply voltage (V1), and a drain connected to an anode of a LD (1); a NMOS transistor (M1n) having a source connected to ground; an inductor (L1) to one end of which a modulation signal (Vin) is inputted and which is connected at the other end to a gate of the NMOS transistor (M1n); and a resistor (Rin) connected, at one end, to a bias voltage (V4) and, at the other end, to one end of the inductor (L1).

Description

[Technical field]

[0001] The present invention relates to a technique for driving a directly modulated laser (DML), and more particularly to a DML driver having a peaking function and an optical waveform shaping function. [Background technology]

[0002] In recent years, the remarkable development of SNS (Social Networking Services) has led to an increase in the volume of communication traffic around the world. In the future, the volume of traffic is expected to increase further due to the development of IoT (Internet of Things) and cloud computing technology, and in order to support this huge volume of traffic, there is a demand for increased communication capacity both inside and outside data centers.

[0003] With the increase in capacity, the standardization of 100GbE has been completed for Ethernet (registered trademark), which is a major element of the network standard, and standardization of 400GbE, which aims for an even larger capacity, is currently under discussion. Drivers using DML are attracting attention from the viewpoint of low power consumption for the purpose of application to 400GbE (see Non-Patent Document 1).

[0004] 10 is a circuit diagram showing the configuration of a conventional DML driver. The DML driver includes a PMOS transistor M1 having a gate connected to a bias voltage V2, a source connected to a power supply voltage V1, and a drain connected to the anode of a laser diode (LD) 1. 1p And the gate is modulated by the signal V in The input is an NMOS transistor M 1n The gate is connected to the bias voltage V3 and the drain is connected to the PMOS transistor M 1p and the anode of LD1, and the source of the NMOS transistor M 1n NMOS transistor M connected to the drain of 2nOne end is connected to a bias voltage V4, and the other end is connected to an NMOS transistor M 1n Resistor R connected to the gate of in It consists of:

[0005] NMOS transistor M 1n and M. 2n are connected in cascode, and the NMOS transistor M 1n The frequency characteristics are improved compared to when it is a single transistor. Also, even if the operating voltage of LD1 exceeds the withstand voltage of the NMOS transistor alone, the voltage is divided by the cascode connection, so the NMOS transistor M 1n ,M 2n Resistance R in is a resistor for impedance matching.

[0006] As shown in Figure 10, in the conventional driver circuit configuration, the driver section did not have the function to compensate for the LD bandwidth, so there was an issue that the bandwidth of the transmission front-end consisting of the DML driver and LD was limited by the LD bandwidth. [Prior art documents] [Non-patent literature]

[0007] [Non-Patent Document 1] T. Kishi et al., “A 137-mW,4 ch x 25-Gbps low-power compact transmitter flip-chip-bonded 1.3-μm LD-array-on-Si”, In Proceedings of the Optical Fiber Communication Conference and Exhibition, 2018, Paper M2D.2. Summary of the Invention [Problem to be solved by the invention]

[0008] The present invention has been made to solve the above problems, and has an object to provide a DML driver capable of compensating for the LD band. [Means for solving the problem]

[0009] The DML driver of the present invention is characterized by comprising a first transistor having a gate or base connected to a first bias voltage, a source or emitter connected to a first power supply voltage, and a drain or collector connected to an anode of a laser diode; a second transistor having a drain or collector connected to the anode of the laser diode and a source or emitter connected to a second power supply voltage; an inductor having one end to which a modulation signal is input and the other end connected to the gate or base of the second transistor; and a first resistor having one end connected to a second bias voltage and the other end connected to one end of the inductor. Furthermore, one configuration example of the DML driver of the present invention is characterized in that it further includes a third transistor whose gate or base is connected to a third bias voltage and cascode-connected between the anode of the laser diode and the drain or collector of the second transistor.

[0010] The DML driver of the present invention is characterized in that it comprises a first transistor having a gate or base connected to a first bias voltage, a source or emitter connected to a first power supply voltage, and a drain or collector connected to an anode of a laser diode; a second transistor having a gate or base connected to a second bias voltage and a source or emitter connected to the second power supply voltage; a third transistor cascode-connected between the anode of the laser diode and the drain or collector of the second transistor; an inductor having one end to which a modulation signal is input and the other end connected to the gate or base of the third transistor; and a first resistor having one end connected to a third bias voltage and the other end connected to one end of the inductor. Moreover, one configuration example of the DML driver of the present invention is characterized in that it further includes a first capacitor having one end connected to the first power supply voltage, and a second resistor having one end connected to the other end of the first capacitor and the other end connected to the drain or collector of the first transistor.

[0011] Moreover, one configuration example of the DML driver of the present invention is characterized in that it further includes a fourth transistor whose gate or base is connected to a fourth bias voltage and which is cascode-connected between the drain or collector of the first transistor and the anode of the laser diode. Moreover, one configuration example of the DML driver of the present invention is characterized in that it further comprises a third resistor inserted between the source or emitter of the second transistor and the second power supply voltage. Moreover, one configuration example of the DML driver of the present invention is characterized in that it further comprises a second capacitor connected in parallel with the third resistor. Effect of the Invention

[0012] According to the present invention, the LD band can be compensated for by the frequency peaking effect of the inductor. [Brief description of the drawings]

[0013] [Figure 1] FIG. 1 is a circuit diagram showing a configuration of a DML driver according to a first embodiment of the present invention. [Diagram 2] FIG. 2 is a diagram showing the resistance component and capacitance component between the gate and source of the NMOS transistor of the DML driver according to the first embodiment of the present invention. [Diagram 3] FIG. 3 is a diagram showing the results of simulating the EO response characteristics of the DML driver and LD for the conventional configuration and the first embodiment of the present invention. [Figure 4A-4C] 4A to 4C are diagrams showing the results of simulating the optical output waveforms of LDs for the conventional configuration and this embodiment. [Diagram 5] FIG. 5 is a circuit diagram showing a configuration of a DML driver according to a second embodiment of the present invention. [Figure 6] FIG. 6 is a circuit diagram showing a configuration of a DML driver according to a third embodiment of the present invention. [Figure 7] FIG. 7 is a circuit diagram showing a configuration of a DML driver according to a fourth embodiment of the present invention. [Figure 8] FIG. 8 is a circuit diagram showing a configuration of a DML driver according to a fifth embodiment of the present invention. [Figure 9] FIG. 9 is a circuit diagram showing a configuration of a DML driver according to a sixth embodiment of the present invention. [Figure 10] FIG. 10 is a circuit diagram showing the configuration of a conventional DML driver. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] [Principle of the invention] In the present invention, the modulating signal V in The transistor to which 1n By connecting an inductor in series to the gate of the LD, the frequency peaking function is activated, making it possible to compensate for the LD band. 1p By connecting a series-connected element of a capacitor and a resistor in parallel to the optical fiber, it is possible to suppress overshoot and undershoot of the optical waveform and shape the optical waveform.

[0015] [First Example] Hereinafter, embodiments of the present invention will be described with reference to the drawings. Fig. 1 is a circuit diagram showing the configuration of a DML driver according to a first embodiment of the present invention. A DML driver 10 of this embodiment includes a PMOS transistor M1 having a gate connected to a bias voltage V2 (first bias voltage), a source connected to a power supply voltage V1 (first power supply voltage), and a drain connected to the anode of LD1. 1p and an NMOS transistor M whose source is connected to ground (the second power supply voltage). 1nThe gate is connected to a bias voltage V3 (third bias voltage) and the drain is connected to a PMOS transistor M 1p and the anode of LD1, and the source of the NMOS transistor M 1n NMOS transistor M connected to the drain of 2n And at one end is the modulated signal V in is input, and the other end is connected to the NMOS transistor M 1n and a resistor R in and a capacitor C whose one end is connected to the power supply voltage V1. f and one end is a capacitor C f The other end is connected to the PMOS transistor M 1p and the anode of LD1. f It consists of:

[0016] The magnitude relationship of each voltage is V1>V2>V3>V4>GND (ground). In this embodiment, the modulation signal V in and NMOS transistor M 1n An inductor L1 is inserted between the gates of the PMOS transistor M 1p In parallel with the capacitor C f and resistor R f A series-connected element was connected.

[0017] Figure 2 shows the NMOS transistor M 1n The circuit configuration of this embodiment includes the resistance component and capacitance component between the gate and source of the NMOS transistor M 1n The gate-source resistance is R1, the gate-source capacitance is C1, and the gate voltage is V G Then, |V G / V in | can be expressed by the following equation (1).

[0018]

number

[0019] In equation (1), ω is the angular frequency. 2 When C1L1=0, |V G / V in If |>1 is satisfied, the frequency peaking effect can be obtained, so the inductance value of L1 must be set so as to satisfy the following equation (2).

[0020]

number

[0021] The results of simulating the EO (Electrical-to-Optical) response characteristics of the DML driver and the LD1 for the conventional configuration and this embodiment are shown in FIG. 3. In FIG. 3, 100 indicates the EO response characteristics of the conventional configuration shown in FIG. 10, 101 indicates the EO response characteristics of this embodiment, and 102 indicates the capacitance C f and resistor R f The figure shows the EO response characteristics when the inductor L1 is removed. As can be seen from Figure 3, the result of the circuit configuration with the inductor L1 added shows that the bandwidth of the EO response characteristics is increased compared to the conventional circuit configuration.

[0022] Next, the results of simulating the optical output waveforms of LD1 for the conventional configuration and this embodiment are shown in Figs. 4A to 4C. The amplitude scale on the vertical axis is 500 μW / div, and the time scale on the horizontal axis is 20 ps / div. Fig. 4A shows the optical output waveform when the conventional configuration is used, Fig. 4B shows the optical output waveform when the configuration of this embodiment is used, and Fig. 4C shows the optical output waveform when the capacitor C is used in the configuration of this embodiment. f and resistor R f 4 shows the optical output waveform with the removal of

[0023] 4A, 4B, and 4C, it can be seen that in this embodiment, the addition of the inductor L1 improves the eye opening in both the horizontal axis (time) direction and the vertical axis (amplitude) direction. Also, in this embodiment, the addition of the capacitor C f and resistor R fIt can be seen that the addition of the filter suppresses overshoot and undershoot in the optical output waveform, improving the eye opening in both the horizontal and vertical directions.

[0024] As shown in the EO response characteristics of FIG. 3, the capacitor C f and resistor R f If the capacitor C is removed, the frequency peaking becomes too strong. f and resistor R f The bandwidth is wider than when the capacitor C is added, but the group delay characteristics of the DML driver and LD1 deteriorate. f and resistor R f It can be seen that adding the filter can suppress overshoot and undershoot of the optical output waveform.

[0025] As described above, in this embodiment, it is possible to compensate for the band of LD1 by the frequency peaking effect of inductor L1. f and resistor R f By using these series-connected elements, it is possible to suppress overshoot and undershoot of the optical output waveform of the LD 1 and shape the optical output waveform.

[0026] [Second Example] Next, a second embodiment of the present invention will be described. Fig. 5 is a circuit diagram showing the configuration of a DML driver according to the second embodiment of the present invention. A DML driver 10a of this embodiment is a DML driver 10a that is connected to a capacitor C f and resistor R f This is the result of removing the above.

[0027] There is variation in the characteristics of commercially available LDs, and some have narrow bandwidths. When using such a narrow bandwidth LD as the LD 1, the capacitor C f and resistor R fThe circuit configuration in which the frequency peaking is strongly activated by removing the capacitor C can compensate for the band of the LD1 without deteriorating the group delay characteristics. f and resistor R f This embodiment, in which the above-mentioned point is removed, can be an effective circuit configuration when the band of the LD 1 is narrow.

[0028] [Third Example] Next, a third embodiment of the present invention will be described. Fig. 6 is a circuit diagram showing the configuration of a DML driver according to the third embodiment of the present invention. A DML driver 10b of this embodiment includes a PMOS transistor M 1p and NMOS transistor M 1n The gates of the PMOS transistors M 1p One or more PMOS transistors M1 and M2 are connected in cascode between the drain of 2p -1~M 2p -x, and the gate is connected to bias voltages V3-1 to V3-y (third bias voltages), and the anode of LD1 and the NMOS transistor M 1n One or more NMOS transistors M 2n -1~M 2n -y, inductor L1, and resistor R in and capacitor C f and resistor R f It consists of:

[0029] The magnitude relationship of each voltage is V1>V2>V5-1>···>V5-x>V3-y>···>V3-1>V4>GND (ground). To cascode connect PMOS transistors, connect the source to the drain of the upper PMOS transistor, and connect the drain to the source of the lower PMOS transistor or the anode of LD1. To cascode connect NMOS transistors, connect the source to the drain of the lower NMOS transistor, and connect the drain to the source of the upper NMOS transistor or the anode of LD1.

[0030] In this way, a multi-stage circuit configuration can be used to prevent breakdown in both PMOS and NMOS transistors. This is effective because the breakdown voltage per transistor decreases at the most advanced nodes. 1p PMOS transistor M 2p -1~M 2p -x for x stages, NMOS transistor M 1n NMOS transistor M 2n -1~M 2n -y is the yth row. Both x and y are 1 or more.

[0031] [Fourth Example] Next, a fourth embodiment of the present invention will be described. Fig. 7 is a circuit diagram showing the configuration of a DML driver according to the fourth embodiment of the present invention. A DML driver 10c of this embodiment includes a PMOS transistor M1 having a gate connected to a bias voltage V2, a source connected to a power supply voltage V1, and a drain connected to the anode of LD1. 1p and an NMOS transistor M whose gate is connected to a bias voltage V4 and whose source is connected to ground. 1n and the drain is a PMOS transistor M 1p and the anode of LD1, and the source of the NMOS transistor M 1n NMOS transistor M connected to the drain of 2n And at one end is the modulated signal V in is input, and the other end is connected to the NMOS transistor M 2n and a resistor R whose one end is connected to the bias voltage V3 and whose other end is connected to one end of the inductor L1. in and capacitor C f and resistor R f It consists of:

[0032] In the first embodiment, an NMOS transistor M 1n The gate of the modulation signal V in In this embodiment, the inductor L1 is connected to the NMOS transistor M 2nThe gate of the modulation signal V in In this embodiment, the NMOS transistor M 1n By adjusting the bias voltage V4 applied to the gate of the PMOS transistor M 1p From NMOS transistor M 2n ,M 1n The current flowing to the side can be adjusted.

[0033] In this embodiment, the NMOS transistor M 1n NMOS transistor M 2n However, as explained in the third embodiment, multiple stages of NMOS transistors M 2n -1~M 2n -y may be connected (y≧2). In this case, multiple stages of NMOS transistors M 2n -1~M 2n Any one of the NMOS transistors M 2n -k (k is 1 to y) gate and modulation signal V in An inductor L1 is connected between the 2n A resistor R is placed between the bias voltage V3-k and the inductor L1 to be applied to the in Just connect the following.

[0034] In this embodiment, the NMOS transistor M 2n ,M 2n If the gate-source resistance of -k is R1 and the gate-source capacitance is C1, then the inductance value of L1 must be set so as to satisfy equation (2) as shown above.

[0035] [Fifth Example] Next, a fifth embodiment of the present invention will be described. Fig. 8 is a circuit diagram showing the configuration of a DML driver according to the fifth embodiment of the present invention. A DML driver 10d of this embodiment differs from the DML driver 10 of the first embodiment in that it has an NMOS transistor M 1n A resistor R is placed between the source and ground. sAs a result, in this embodiment, the modulation signal V in This allows the DML driver to operate more linearly with In FIG. 8, the first embodiment includes a resistor R s is applied, but the resistor R s may be applied.

[0036] [Sixth Example] Next, a sixth embodiment of the present invention will be described. Fig. 9 is a circuit diagram showing the configuration of a DML driver according to the sixth embodiment of the present invention. A DML driver 10e of this embodiment differs from the DML driver 10d of the fifth embodiment in that it has a resistor R s In parallel with the capacitor C s As a result, in this embodiment, the high frequency band of the transmission front end formed by the DML driver 10e and the LD 1 can be improved compared to the fifth embodiment. In FIG. 9, the first embodiment includes a resistor R s and capacitor C s is applied, but the resistor R s and capacitor C s may be applied.

[0037] In addition, when there is no problem with the withstand voltage of the NMOS transistor, the NMOS transistor M 2n ,M 2n -1~M 2n -y is omitted, and the NMOS transistor M 1n The drain of LD1 may be connected to the anode of LD1. In this case, the bias voltages V3, V3-1 to V3-y are not required.

[0038] In the third embodiment, if there is no problem with the withstand voltage of the PMOS transistor, 2p -1~M 2p -x is omitted, and the PMOS transistor is designated as M as in the first, second, fourth to sixth embodiments. 1p In this case, the bias voltages V5-1 to V5-x are not necessary.

[0039] In the first to sixth embodiments, the transistor M 1p ,M 2p -1~M 2p -x,M 1n ,M 2n -1~M 2n Although an example using a MOS transistor as -y is shown, the transistor M 1p ,M 2p -1~M 2p -x is a PNP bipolar transistor, and the transistor M 1n ,M 2n -1~M 2n An NPN bipolar transistor may be used as -y. When using a bipolar transistor, the gate may be replaced with a base, the drain with a collector, and the source with an emitter in the explanations of the first to sixth embodiments. [Industrial Applicability]

[0040] The present invention can be applied to a technique for directly modulating the optical output of an LD. [Explanation of symbols]

[0041] 1...LD, 10,10a~10e...DML driver, M 1p ,M 2p -1~M 2p -x…PMOS transistor, M 1n ,M 2n -1~M 2n -y…NMOS transistor, L1…inductor, R in ,R f ,R s …Resistance, C f ,C s ...Capacitor.

Claims

1. a first transistor having a gate or base connected to a first bias voltage, a source or emitter connected to a first power supply voltage, and a drain or collector connected to an anode of a laser diode; a second transistor having a drain or collector connected to the anode of the laser diode and a source or emitter connected to a second power supply voltage; an inductor having one end to which a modulation signal is input and the other end connected to the gate or base of the second transistor; a first resistor having one end connected to a second bias voltage and the other end connected to one end of the inductor.

2. 2. The DML driver of claim 1, a third transistor having a gate or base connected to a third bias voltage and cascode-connected between the anode of the laser diode and the drain or collector of the second transistor.

3. a first transistor having a gate or base connected to a first bias voltage, a source or emitter connected to a first power supply voltage, and a drain or collector connected to an anode of a laser diode; a second transistor having a gate or base connected to a second bias voltage and a source or emitter connected to a second power supply voltage; a third transistor cascoded between the anode of the laser diode and the drain or collector of the second transistor; an inductor having one end to which a modulation signal is input and the other end connected to the gate or base of the third transistor; a first resistor having one end connected to a third bias voltage and the other end connected to one end of the inductor.

4. 4. The DML driver according to claim 1, a first capacitor having one end connected to the first power supply voltage; a second resistor having one end connected to the other end of the first capacitor and the other end connected to the drain or collector of the first transistor.

5. 5. The DML driver according to claim 1, a fourth transistor having a gate or base connected to a fourth bias voltage and cascode-connected between the drain or collector of the first transistor and the anode of the laser diode.

6. 6. The DML driver according to claim 1, The DML driver further comprising a third resistor inserted between the source or emitter of the second transistor and the second power supply voltage.

7. 7. The DML driver according to claim 6, The DML driver further comprising a second capacitor connected in parallel with the third resistor.

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