Power Conversion Equipment

Abstract

The power conversion device includes a three-phase MMC type power converter of a delta connection cascade system and a control device (3) for controlling the power converter. In the control device (3), a phase voltage balance control unit (30) controls arm current command values ​​(Iuv * ,Ivw * ,Iwu * ) and the circulating current command value (Iz * The negative-sequence current command value calculation unit (40) calculates a negative-sequence current command value (Idn * ,Iqn * The phase voltage balance control unit (30) is configured to limit the magnitude of the arm current command value and the circulating current command value.

Description

[Technical field]

[0001] The present disclosure relates to a power conversion device. [Background technology]

[0002] As a large-capacity power conversion device installed in a power system, a modular multilevel converter (MMC) in which a plurality of unit converters (hereinafter referred to as "converter cells") are connected in cascade is known. The MMC has a plurality of arms in which a plurality of converter cells are cascaded and a reactor is further connected in series. A three-phase delta-connected cascade converter used as a reactive power compensation device has a configuration in which three arms are delta-connected and is connected in parallel to an AC power system via a reactor or a transformer.

[0003] Since MMC has a capacitor in each converter cell, the voltage of the capacitors between phases may become unbalanced due to the voltage variation between the capacitors. If the capacitor voltages between phases become unbalanced, there is a concern that the control characteristics of the MMC may deteriorate due to the generation of unintended circulating currents. Therefore, it is important to control the phase balance of the capacitor voltages to suppress this unbalance.

[0004] A particular problem with the MMC delta-connection reactive power compensator is when an unbalanced voltage occurs in the three-phase power system. For example, if the impedance of the power transmission and distribution network is three-phase unbalanced or if a single-phase load is connected to the load, the three-phase voltage at the interconnection point becomes unbalanced. Furthermore, if a one-phase earth fault, two-phase earth fault, or line-to-line short circuit occurs as a system fault, an even larger unbalanced voltage occurs. The MMC delta-connection reactive power compensator is required to maintain the most basic function of a reactive power compensator, which is to output a positive-sequence reactive current, even when the system voltage becomes unbalanced in this way. For this reason, it is necessary to maintain the capacitor voltage of each converter cell constant in order to continue operation.

[0005] Japanese Patent No. 6147363 (Patent Document 1) discloses a method for suppressing imbalance in capacitor voltages between phases caused by system unbalance by using a circulating current and a negative-phase current. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Patent No. 6147363 Summary of the Invention [Problem to be solved by the invention]

[0007] The problem with the technology disclosed in the above-mentioned Japanese Patent No. 6147363 (Patent Document 1) is that when the circulating current is increased to suppress the imbalance of the capacitor voltages between the phases, the arm current increases, which results in a larger capacity of the power converter.

[0008] The present disclosure has been made in consideration of the above problems, and one of its objectives is to provide a power conversion device with an MMC configuration that can eliminate imbalance in capacitor voltages between phases while suppressing an increase in arm current. [Means for solving the problem]

[0009] A power conversion device according to an embodiment includes a power converter connected to a three-phase AC system and a control device for controlling the power converter. The power converter includes three delta-connected arms each including a plurality of converter cells connected in cascade. Each of the converter cells includes an input / output terminal pair, a bridge circuit including a plurality of semiconductor switching elements, and a storage element connected to the input / output terminal pair via the bridge circuit. The control device includes a phase voltage balance control unit, a negative-phase-sequence current command value calculation unit, an output current control unit, a circulating current control unit, a voltage command value calculation unit, and a gate signal generation unit. The phase voltage balance control unit calculates arm current command values ​​and circulating current command values ​​for each arm so that a difference between a representative value of a voltage of a storage element included in each arm and a representative value of a voltage of storage elements included in all arms is reduced. The negative-phase-sequence current command value calculation unit calculates a negative-phase-sequence current command value based on the arm current command value and the circulating current command value. The output current control unit calculates a voltage command value for controlling an output current of the power converter based on the negative-phase-sequence current command value and the positive-phase-sequence current command value. The circulating current control unit calculates a zero-phase sequence voltage command value for controlling the circulating current based on the detection value of the arm current of each arm, based on the circulating current command value. The voltage command value calculation unit calculates an output voltage command value to be output to each arm, based on the voltage command value and the zero-phase sequence voltage command value. The gate signal generation unit generates a gate signal for controlling on / off of each semiconductor switching element included in each converter cell of each arm, based on the output voltage command value. The phase voltage balance control unit is configured to limit the magnitudes of the arm current command value and the circulating current command value, and the magnitude of the negative sequence current command value calculated by the negative sequence current command value calculation unit increases according to the amount by which the magnitudes of the arm current command value and the circulating current command value of any arm are limited. Effect of the Invention

[0010] According to the above embodiment, while suppressing an increase in the arm current by limiting the magnitudes of the arm current command value and the circulating current command value, the magnitude of the negative-phase current command value increases according to the amount by which the magnitudes of the arm current command value and the circulating current command value are limited, so that the imbalance in the capacitor voltages between the phases can be eliminated. [Brief description of the drawings]

[0011] [Figure 1] 1 is a schematic configuration diagram of a power conversion device according to a first embodiment. [Diagram 2] FIG. 1 is a circuit diagram showing a configuration of a full-bridge type converter cell. [Diagram 3] FIG. 2 is a circuit diagram showing a configuration of a half-bridge type converter cell. [Figure 4] FIG. 2 is a block diagram showing a schematic configuration of a control device shown in FIG. [Diagram 5] 5 is a block diagram showing a configuration example of a phase voltage balance control unit in FIG. 4. [Figure 6] 5 is a block diagram showing an example of the configuration of a negative-phase-sequence current command value calculation unit in FIG. 4. [Figure 7] 5 is a block diagram showing a configuration example of a circulating current control unit in FIG. 4. [Figure 8] 5 is a block diagram showing a configuration example of a DC voltage control unit in FIG. 4. [Figure 9] 5 is a block diagram showing a configuration example of an output current control unit in FIG. 4. [Figure 10] 11 is a block diagram showing a configuration example of a phase voltage balance control unit included in a control device in a power conversion device according to a second embodiment. FIG. [Figure 11] FIG. 11 is a diagram showing an example of arm currents of a power converter under unbalanced system voltage conditions when negative-sequence current control is not performed. [Figure 12] FIG. 11 is a diagram showing an example of a difference in maximum arm current depending on whether or not the negative-phase-sequence current control is performed; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] Hereinafter, each embodiment will be described in detail with reference to the drawings. Note that the same or corresponding parts are designated by the same reference characters and their description will not be repeated.

[0013] Embodiment 1 [Key Points of the First Embodiment] In the control device 3 of the power conversion device 1 of the first embodiment, a limiter 34 is provided at the output of the controller 33 of the phase voltage balance control unit 30. This limits the magnitudes of the arm current command value and the circulating current command value, thereby making it possible to suppress an increase in the arm current. On the other hand, the magnitude of the negative sequence current command value increases according to the amount by which the magnitudes of the arm current command value and the circulating current command value of any arm are limited, so that the phase voltage balance control function can be maintained.

[0014] [Outline of three-phase delta-connected MMC power conversion device] 1 is a schematic configuration diagram of a power conversion device 1 according to a first embodiment. The power conversion device 1 includes a delta-connection cascade type three-phase MMC power converter 2 and a control device 3 for the power converter 2. The power converter 2 is also called a STATCOM (Static Synchronous Compensator).

[0015] The power converter 2 includes a transformer 4 and three-phase AC lines UL, VL, and WL. A primary winding of the transformer 4 is connected to U-phase, V-phase, and W-phase transmission lines of an AC power system 9. A secondary winding of the transformer 4 is connected to first terminals of the AC lines UL, VL, and WL, respectively.

[0016] The power converter 2 functions as a reactive power compensator that injects or absorbs reactive power into the AC power system 9 via the transformer 4. Specifically, when the three-phase AC voltage (hereinafter also referred to as "system voltage") of the AC power system 9 decreases, the power converter 2 injects reactive power into the AC power system 9 so as to increase the system voltage. On the other hand, when the system voltage increases, the power converter 2 absorbs reactive power from the AC power system 9 so as to decrease the system voltage. That is, the power converter 2 can compensate for reactive power by injecting or absorbing a current that is orthogonal to the system voltage into the AC power system 9.

[0017] The power converter 2 further includes arms A1 to A3. The arm A1 is connected between a second terminal of the U-phase AC line UL and a second terminal of the V-phase AC line VL. The arm A2 is connected between a second terminal of the V-phase AC line VL and a second terminal of the W-phase AC line WL. The arm A3 is connected between a second terminal of the W-phase AC line WL and a second terminal of the U-phase AC line UL. That is, the arms A1 to A3 are connected in a delta connection.

[0018] The arms A1 to A3 may be connected in a star connection. In this case, the arm A1 is connected between a second terminal of the U-phase AC line UL and the common neutral point. The arm A2 is connected between a second terminal of the V-phase AC line VL and the common neutral point. The arm A3 is connected between a second terminal of the W-phase AC line WL and the common neutral point.

[0019] Each of the arms A1 to A3 has a reactor L (L1 to L3) and n (n is an integer of 2 or more) converter cells 5. Therefore, the power converter 2 has a total of 3n converter cells 5. The n converter cells 5 are connected in series with each other. The reactor L is connected in series with the n converter cells 5 in each arm (A1 to A3) to suppress the circulating current flowing in the delta connection.

[0020] Each of the multiple converter cells 5 performs bidirectional power conversion in accordance with a control signal from the control device 3. An example of the configuration of the converter cells 5 will be described later with reference to Figs.

[0021] The power conversion device 1 further includes an arm current detection unit 10 arranged in each arm (A1 to A3), and an AC current detection unit 11 and an AC voltage detection unit 12 arranged in the AC power system 9.

[0022] The arm current detection unit 10a detects the arm current Iuv flowing in the arm A1, the arm current detection unit 10b detects the arm current Ivw flowing in the arm A2, and the arm current detection unit 10c detects the arm current Iwu flowing in the arm A3. The AC current detection unit 11 detects the U-phase AC current Iu, the V-phase AC current Iv, and the W-phase AC current Iw of the AC power system 9. That is, the AC current detection unit 11 detects the output current from the power converter 2 to the power conversion device 1. The AC voltage detection unit 12 detects the U-phase AC voltage Vu, the V-phase AC voltage Vv, and the W-phase AC voltage Vw of the AC power system 9. Signals representing these detected currents and voltages are input to the control device 3.

[0023] In FIG. 1, the UV phase voltage applied to arm A1 is denoted as Vuv, the VW phase voltage applied to arm A2 is denoted as Vvw, and the WU phase voltage applied to arm A3 is denoted as Vwu.

[0024] [Example of converter cell 5 configuration] Hereinafter, a configuration example of the converter cell 5 will be described with reference to Fig. 2 and Fig. 3. Fig. 2 shows a full-bridge type configuration example, and Fig. 3 shows a half-bridge type configuration example. The converter cell 5 may have a configuration other than that shown in Figs. 2 and 3.

[0025] Fig. 2 is a circuit diagram showing the configuration of a full-bridge type converter cell 5. The converter cell 5 in Fig. 2 includes a first series body formed by connecting two semiconductor switching elements Q1 and Q2 in series, a second series body formed by connecting two semiconductor switching elements Q3 and Q4 in series, rectifier elements D1, D2, D3, and D4 (typically diodes), a storage element 17 (typically a capacitor), a voltage detector 18, input / output terminals 16a and 16b, and a driver 19.

[0026] The first series body, the second series body, and the storage element 17 are connected in parallel between the positive electrode line PL and the negative electrode line NL. The rectifier elements D1 and D2 are connected in anti-parallel to the semiconductor switching elements Q1 and Q2, respectively (i.e., in parallel and in the reverse bias direction). The rectifier elements D3 and D4 are connected in anti-parallel to the semiconductor switching elements Q3 and Q4, respectively. The semiconductor switching elements Q1, Q2, Q3, and Q4 and the rectifier elements D1, D2, D3, and D4 form a full bridge circuit 15F. The voltage detector 18 detects the voltage Vdccell (also referred to as the capacitor voltage Vdccell) across the storage element 17.

[0027] The midpoint of the semiconductor switching element Q1 and the semiconductor switching element Q2 is connected to the input / output terminal 16a. Similarly, the midpoint of the semiconductor switching element Q3 and the semiconductor switching element Q4 is connected to the input / output terminal 16b. Therefore, the storage element 17 is connected to the input / output terminals 16a and 16b via the full bridge circuit 15F. The converter cell 5 outputs the voltage Vdccell or -Vdccell or zero voltage of the storage element 17 as the output voltage Vcell between the input / output terminals 16a and 16b by the switching operation of the semiconductor switching elements Q1, Q2, Q3, and Q4.

[0028] Driver 19 is connected to positive electrode line PL and negative electrode line NL, and operates by the voltage of storage element 17. Driver 19 controls the switching of semiconductor switching elements Q1, Q2, Q3, and Q4 by outputting a gate signal Ga to each control electrode G of semiconductor switching elements Q1, Q2, Q3, and Q4.

[0029] Fig. 3 is a circuit diagram showing the configuration of a half-bridge type converter cell 5. The converter cell 5 in Fig. 3 includes a series body formed by connecting two semiconductor switching elements Q1 and Q2 in series, rectifier elements D1 and D2, a storage element 17, a voltage detector 18, and input / output terminals 16a and 16b.

[0030] Rectifier elements D1 and D2 are connected in anti-parallel to semiconductor switching elements Q1 and Q2. A series connection of semiconductor switching elements Q1 and Q2 and storage element 17 are connected in parallel between positive electrode line PL and negative electrode line NL. Voltage detector 18 detects voltage Vdccell across storage element 17.

[0031] A half-bridge circuit 15H is formed by a series circuit of semiconductor switching elements Q1 and Q2 and rectifier elements D1 and D2. Both terminals of semiconductor switching element Q2 are connected to input / output terminals 16a and 16b, respectively. Therefore, the storage element 17 is connected to the input / output terminals 16a and 16b via the half-bridge circuit 15H.

[0032] The converter cell 5 outputs the voltage Vdccell of the storage element 17 or zero voltage between the input / output terminals 16a and 16b by the switching operation of the semiconductor switching elements Q1 and Q2. When the semiconductor switching element Q1 is on and the semiconductor switching element Q2 is off, the converter cell 5 outputs the voltage Vdccell of the storage element 17. When the semiconductor switching element Q1 is off and the semiconductor switching element Q2 is on, the converter cell 5 outputs zero voltage.

[0033] Both terminals of the semiconductor switching element Q1 may be connected to the input / output terminals 16a and 16b, respectively. In this case, too, the converter cell 5 outputs the voltage Vdccell of the storage element 17 and zero voltage as the output voltage Vcell from the input / output terminals 16a and 16b by the on / off operation of the semiconductor switching elements Q1 and Q2.

[0034] Driver 19 is connected to positive electrode line PL and negative electrode line NL, and operates by the voltage of storage element 17. Driver 19 controls the switching of semiconductor switching elements Q1, Q2 by outputting a gate signal Ga to each control electrode G of semiconductor switching elements Q1, Q2.

[0035] 2 and 3, semiconductor switching elements Q1, Q2, Q3, and Q4 are configured by self-extinguishing semiconductor switching elements such as IGBTs (Insulated Gate Bipolar Transistors) and GCT (Gate Commutated Turn-off) thyristors.

[0036] In the following description, when the semiconductor switching elements are referred to collectively or any one of them is indicated, they will be referred to as a semiconductor switching element Q. When the rectifying elements are referred to collectively or any one of them is indicated, they will be referred to as a rectifying element D.

[0037] As shown in Fig. 1, the converter cells 5 are cascaded. Therefore, in each of Fig. 2 and Fig. 3, the input / output terminal 16a is connected to the input / output terminal 16b of one adjacent converter cell 5 or the second terminal of one corresponding AC line. The input / output terminal 16b is connected to the input / output terminal 16a of the other adjacent converter cell 5 or the second terminal of the other corresponding AC line.

[0038] [Outline of control device configuration] Fig. 4 is a block diagram showing a schematic configuration of the control device 3 in Fig. 1. As shown in Fig. 4, the control device 3 includes a DC voltage control unit 20, a phase voltage balance control unit 30, a negative-phase-sequence current command value calculation unit 40, an output current control unit 50, a circulating current control unit 60, a voltage command value calculation unit 70, and a gate signal generation unit 80. The configurations and operations of these components will be described in more detail below.

[0039] The control device 3 can be configured based on at least one computer including at least one CPU (Central Processing Unit) that operates according to a program and at least one memory. Alternatively, at least a part of the control device 3 can be configured using a PLD (Programmable Logic Device) such as an FPGA (Field Programmable Gate Array) and / or a dedicated circuit such as an ASIC (Application Specific Integrated Circuit).

[0040] [Phase voltage balance control unit 30] The phasors of the arm currents Iuv, Ivw, Iwu flowing through arms A1, A2, A3 of a three-phase delta-connection MMC type power converter can be expressed by the positive-sequence component Ip of the output current, the negative-sequence component In of the output current, and the circulating current I0 as shown in the following equation (1): In the following equation (1), j represents the imaginary unit, e represents the base of the natural logarithm, and θ0 represents the phase of the circulating current.

[0041]

number

[0042] As shown in FIG. 4, the phase voltage balance control unit 30 controls the arm current command value Iuv * ,Ivw * ,Iwu * and the circulating current command value Iz * The negative sequence current command value calculation unit 40 calculates the arm current command value Iuv calculated by the phase voltage balance control unit 30. * ,Ivw * ,Iwu * and the circulating current command value Iz * Using the negative-phase current command value Idn * ,Iqn * Calculate the following.

[0043] Fig. 5 is a block diagram showing a configuration example of the phase voltage balance control unit 30 in Fig. 4. The phase voltage balance control unit 30 receives an input of the value of the capacitor voltage Vdccell detected by the voltage detector 18 of each converter cell 5, and outputs arm current command values ​​Iuv * ,Ivw * ,Iwu * and the circulating current command value Iz * Output.

[0044] 5, the phase voltage balance control unit 30 includes a voltage representative value calculation unit 31, a subtractor 32, a controller 33, a limiter 34, a multiplier 35, an adder 36, a constant multiplier 37, and a filter 38. Among these components, the subtractor 32, the controller 33, the limiter 34, the multiplier 35, and the filter 38 are provided corresponding to the voltage or current of each arm. When distinguishing between the arms, a, b, and c are added to the end of the reference numerals to correspond to the arms A1, A2, and A3, respectively.

[0045] The voltage representative value calculation unit 31 receives an input of the value of the capacitor voltage Vdccell detected in each converter cell 5. The voltage representative value calculation unit 31 calculates a representative value Vph of the capacitor voltages Vdccell of all converter cells 5 based on the detected values ​​of these capacitor voltages Vdccell. * , a representative value Vdcuv of the capacitor voltage Vdccell of the converter cells 5 constituting arm A1, a representative value Vdcvw of the capacitor voltage Vdccell of the converter cells 5 constituting arm A2, and a representative value Vdcwu of the capacitor voltage Vdccell of the converter cells 5 constituting arm A3 are calculated. As the representative value of the capacitor voltage Vdccell, an average value, a median value, a maximum value, a minimum value, or the like may be used, and there is no particular limitation as long as it reflects the magnitude of the capacitor voltage Vdccell of the corresponding converter cell 5.

[0046] The representative values ​​Vdcuv, Vdcvw, and Vdcwu of the capacitor voltages of the above-mentioned arms oscillate at a frequency of 2f, where f is the fundamental frequency of the power system. Each of the filters 38a, 38b, and 38c outputs only the DC component by removing the 2f AC component from the representative value Vdcuv, Vdcvw, or Vdcwu of the capacitor voltage of the corresponding arm.

[0047] Each of the subtractors 32a, 32b, and 32c calculates a representative value Vph of the total capacitor voltage Vdccell. * The error ΔVuv, ΔVvw, or ΔVwu is calculated by subtracting the representative value Vdcuv, Vdcvw, or Vdcwu of the capacitor voltage of the corresponding arm from the error ΔVuv, ΔVvw, or ΔVwu.

[0048] Each of the controllers 33a, 33b, and 33c executes a feedback calculation to bring the corresponding error ΔVuv, ΔVvw, or ΔVwu closer to 0. Specifically, the controller 33 may be configured as a proportional controller, or may be configured as a PI (proportional-integral) controller that adds the results of executing a proportional calculation (P) and an integral calculation (I), or may be configured as another controller.

[0049] Each of the limiters 34a, 34b, and 34c limits the output of the corresponding controller 33a, 33b, or 33c to within a range between an upper limit value and a lower limit value. That is, when the output of the corresponding controller 33 exceeds the upper limit value, each limiter 34 changes the output value to the upper limit value and outputs it, when the output of the corresponding controller 33 exceeds the lower limit value, changes the output value to the lower limit value and outputs it, and when the output of the corresponding controller 33 is between the upper limit value and the lower limit value, outputs the output value as is. When the system voltage is unbalanced, the circulating current command value Iz * Since the magnitude of the circulating current command value Iz * A limiter 34 is provided to reduce the magnitude of

[0050] The upper and lower limit values ​​of the limiter 34 may be determined, for example, according to the rated value of the arm current so that the arm current flowing through the converter cell 5 does not become an overcurrent. Alternatively, the upper and lower limit values ​​may be set in advance in the form of a table according to the values ​​of the positive and negative sequence voltages of the power system (i.e., the degree of voltage imbalance) so that the output current of the power converter does not exceed the current capacity.

[0051] The multiplier 35a multiplies the output of the corresponding limiter 34a by the voltage Vuv of the arm A1 to obtain a UV-phase arm current command value Iuv * Similarly, the multiplier 35b multiplies the output of the corresponding limiter 34b by the voltage Vvw of the arm A2 to calculate a VW-phase arm current command value Ivw * The multiplier 35c multiplies the output of the corresponding limiter 34c by the voltage Vwu of the arm A3 to calculate a WU-phase arm current command value Iwu * Calculate the following.

[0052] The adder 36 calculates the arm current command value Iuv * ,Ivw * ,Iwu * The constant multiplier 37 multiplies the sum of the adder 36 by 1 / 3 to obtain the circulating current command value Iz * The arm current command value Iuv is calculated by the limiter 34. * ,Ivw * ,Iwu * When any of the values ​​is limited, the circulating current command value Iz * The value of is also restricted.

[0053] When the limiter 34 is not provided at the output of the controller 33 of the phase voltage balance control unit 30, the circulating current command value Iz is set to 0 in order to compensate for the phase voltage balance, particularly when the system voltage is unbalanced. * This causes a problem that the arm current increases. By limiting the output of the controller 33 of the phase voltage balance control unit 30 by the limiter 34, the circulating current command value Iz *The compensation for the phase voltage balance control limited by the limiter 34 is the negative-sequence current command value In * That is, the circulating current command value Iz * and the negative-phase current command value In * (i.e., Iz * and In * The proportion of

[0054] [Negative-phase current command value calculation unit 40] 6 is a block diagram showing an example of the configuration of the negative-phase-sequence current command value calculation unit 40 shown in FIG. * ,Ivw * ,Iwu * and the circulating current command value Iz * Then, the negative-phase current command value In * Calculate the negative-phase current command value In * is the negative-phase reactive current command value Idn * and the negative-phase active current command value Iqn * It is composed of:

[0055] As shown in FIG. 6, the negative-phase-sequence current command value calculation unit 40 includes subtractors 41a, 41b, 41c, 41d, and 41e, a three-phase / two-phase coordinate conversion unit 42, and filters 43a and 43b.

[0056] The subtractor 41a subtracts the UV phase arm current command value Iuv output from the phase voltage balance control unit 30. * from the circulating current command value Iz * The difference value ΔIuv is obtained by subtracting * By calculating the UV phase arm current command value Iuv * Similarly, the subtractor 41b extracts the positive and negative sequence components included in the VW phase arm current command value Ivw * from the circulating current command value Iz * The difference value ΔIvw is calculated by subtracting * By calculating the VW phase arm current command value Ivw* The subtractor 41c extracts the positive and negative sequence components contained in the WU phase arm current command value Iwu * from the circulating current command value Iz * Subtract the difference value ΔIwu * By calculating the WU phase arm current command value Iwu * The positive and negative phase components contained in the signal are extracted.

[0057] The three-phase / two-phase coordinate conversion unit 42 converts the extracted positive and negative phase components (i.e., the difference value ΔIuv * ,ΔIvw * ,ΔIwu * That is, the three-phase / two-phase coordinate converter 42 converts the difference value ΔIuv * ,ΔIvw * ,ΔIwu * Then, a three-phase / two-phase transformation is performed from the UVW coordinates to the αβ coordinates, and a rotational coordinate transformation is performed from the αβ coordinates to the positive phase dq coordinates using the reference phase θ.

[0058] Here, the reference phase θ is a phase θ synchronized with the system voltage, and is extracted from the detection values ​​of the system voltages Vu, Vv, and Vw by a PLL circuit (phase-locked loop circuit) (not shown). The transformation matrices of the above three-phase / two-phase transformation and rotational coordinate transformation are the same as the transformation matrices of equations (3A) and (3B) described later.

[0059] The filter 43a extracts a positive-sequence component from the output (q-axis component) of the three-phase / two-phase coordinate conversion unit 42. The filter 43b extracts a positive-sequence component from the output (d-axis component) of the three-phase / two-phase coordinate conversion unit 42. Specifically, each of the filters 43a and 43b is configured to remove a negative-sequence component from the input value to the filter itself and extract a positive-sequence component. In the positive-sequence coordinate system, the positive-sequence component is a DC component, and the negative-sequence component is a frequency component (2f) twice the fundamental frequency (f) of the power system. Therefore, a first-order lag, a 2f moving average, a 2f notch filter, or the like is used for the filters 43a and 43b.

[0060] The subtractor 41d subtracts the output (positive sequence component) of the filter 43a from the q-axis components (positive sequence component and negative sequence component) output from the three-phase / two-phase coordinate conversion unit 42 to obtain the negative sequence active current command value Iqn * Similarly, the subtractor 41e subtracts the output (positive sequence component) of the filter 43a from the d-axis components (positive sequence component and negative sequence component) output from the three-phase / two-phase coordinate conversion unit 42 to generate the negative sequence reactive current command value Idn * Generate.

[0061] When the output of any one of the controllers 33a, 33b, and 33c of the phase voltage balance control unit 30 is limited by the corresponding limiter 34, the arm current command value and the circulating current command value Iz * In this case, the difference values ​​ΔIuv output from the subtractors 41a, 41b, and 41c of the negative-phase-sequence current command value calculation unit 40 are * ,ΔIvw * ,ΔIwu * Since the difference value of the phase that is not limited in output becomes large, the negative-sequence current command value In * (Idn * ,Iqn * In other words, the circulating current command value Iz becomes larger depending on the upper and lower limit values ​​of the limiter 34. * and the negative-phase current command value In * (i.e., Iz * and In * The proportion of

[0062] [Circulating current control unit 60] Fig. 7 is a block diagram showing an example of the configuration of circulating current control unit 60 of Fig. 4. Referring to Fig. 7, circulating current control unit 60 includes an adder 63, a constant multiplier 64, a subtractor 62, and a controller 61.

[0063] The adder 63 adds up the valve branch currents Iuv, Ivw, and Iwu detected by the valve branch current detection unit 10. The constant multiplier 64 multiplies the sum of the adder 63 by one-third to calculate the circulating current Iz flowing through the power converter 2.

[0064] The subtractor 62 calculates the circulating current command value Iz * The controller 61 calculates the deviation ΔIz between the circulating current Iz and the circulating current command value Iz. * The zero-phase voltage command value vz is calculated by performing a feedback control calculation to make it follow the zero-phase voltage command value vz * The controller 84 may be a PI controller or some other controller.

[0065] [DC voltage control unit 20] Fig. 8 is a block diagram showing a configuration example of the DC voltage control unit 20 of Fig. 4. Referring to Fig. 8, the DC voltage control unit 20 includes a DC voltage representative value calculation unit 21, a subtractor 22, and a controller 23. The DC voltage control unit 20 calculates the capacitor voltages Vdccell of all (3n in this case) converter cells 5 detected by a voltage detector 18 for each converter cell 5, and the DC total voltage command value vdc * is entered.

[0066] The DC voltage representative value calculation unit 21 calculates a voltage representative value vdc representing all the capacitor voltages Vdccell from the capacitor voltages Vdccell of all the converter cells 5. The voltage representative value vdc may be the average value, median value, maximum value, or minimum value of at least some of the capacitor voltages Vdccell, and is not particularly limited as long as it reflects the magnitude of the capacitor voltages Vdccell of all the converter cells 5.

[0067] The subtractor 22 subtracts the DC total voltage command value vdc * The deviation Δvdc between the DC total voltage command value vdc and the representative voltage value vdc is calculated. * is set to 1 [pu]. In order to make this deviation Δvdc zero, that is, to set the voltage representative value vdc to the DC total voltage command value vdc * The feedback control calculation is performed to make the positive-phase active current command value Iq * The controller 23 may be a PI controller or another controller.

[0068] [Output current control unit 50] Fig. 9 is a block diagram showing an example of the configuration of output current control unit 50 in Fig. 4. Referring to Fig. 9, output current control unit 50 includes a reference voltage calculation unit 51, a three-phase / two-phase coordinate conversion unit 55b, and adders 53c and 53d.

[0069] The reference voltage calculation unit 51 includes a three-phase / two-phase coordinate conversion unit 55a, adders 53a and 53b, subtractors 54a and 54b, and a controller 52. As shown in FIG. 9, the reference voltage calculation unit 51 includes a positive-phase reactive current command value Id * and the positive-phase active current command value Iq calculated by the DC voltage control unit 20. * and the negative-phase-sequence reactive current command value Idn calculated by the negative-phase-sequence current command value calculation unit 40. * and the negative-phase active current command value Iqn * and a U-phase AC current Iu, a V-phase AC current Iv, and a W-phase AC current Iw, which are output currents of the power converter 2 detected by the AC current detection unit 11, are input.

[0070] The adder 53a calculates the positive-phase reactive current command value Id as shown in the following equation (2A). * and the negative-phase reactive current command value Idn * The reactive current command value Id2 is obtained by adding * The adder 53b calculates the positive-phase active current command value Iq as shown in the following equation (2B). * and the negative-phase active current command value Iqn * The active current command value Iq2 is obtained by adding * Calculate the following.

[0071]

number

[0072] The three-phase / two-phase coordinate conversion unit 55a calculates a positive-phase reactive current Id and a positive-phase active current Iq obtained by three-phase / two-phase conversion of the output currents Iu, Iv, Iw detected by the AC current detection unit 11 in the positive-phase coordinate system. More specifically, the three-phase / two-phase coordinate conversion unit 55a performs three-phase / two-phase conversion on the output currents Iu, Iv, Iw from the UVW coordinates to the output currents Iα, Iβ on the αβ coordinates according to the following equation (3A). The three-phase / two-phase coordinate conversion unit 55a further performs rotational coordinate conversion from the output currents Iα, Iβ on the αβ coordinates to the positive-phase currents Id, Iq on the positive-phase dq coordinates according to the following equation (3B) using a reference phase θ. Here, the reference phase θ is a phase θ synchronized with the system voltage.

[0073]

number

[0074] The subtractor 54a subtracts the reactive current command value Id2 output from the adder 53a. * The subtractor 54b calculates the deviation ΔId between the active current command value Iq2 output from the adder 53b and the positive-sequence reactive current Id output from the three-phase / two-phase coordinate conversion unit 55a. * and the positive-sequence active current Iq output from the three-phase / two-phase coordinate conversion unit 55a.

[0075] In order to make the deviations ΔId and ΔIq zero, that is, to set the positive-phase reactive current Id and the positive-phase active current Iq to the reactive current command value Id2 * and the active current command value Iq2 * The feedback control calculation is performed to make the DC total voltage command value vdc * The controller 52 performs a feedback control calculation to make the positive and negative phase reference voltages vdref and vqref follow the input voltages vdref and vqref, where vdref is a reactive component of the positive and negative phase reference voltages, and vqref is an active component of the positive and negative phase reference voltages. The controller 52 may be a PI controller or another controller.

[0076] On the other hand, the three-phase / two-phase coordinate conversion unit 55b generates positive-phase voltages (positive-phase reactive voltage Vdff, positive-phase effective voltage Vqff) by performing three-phase / two-phase conversion on the U-phase AC voltage Vu, V-phase AC voltage Vv, and W-phase AC voltage Vw of the power system in the positive-phase coordinate system. More specifically, the three-phase / two-phase coordinate conversion unit 55b performs three-phase / two-phase conversion on the system voltages U-phase AC voltage Vu, V-phase AC voltage Vv, and W-phase AC voltage Vw from the UVW coordinate to the system voltages Vα and Vβ on the αβ coordinate. The three-phase / two-phase coordinate conversion unit 55b further performs rotational coordinate conversion from the system voltages Vα and Vβ on the αβ coordinate to the positive-phase voltages Vdff and Vqff on the positive-phase dq coordinate using a reference phase θ. Here, the reference phase θ is a phase θ synchronized with the system voltage.

[0077] The adder 53c adds the positive-phase reactive voltage Vdff calculated by the three-phase / two-phase coordinate conversion unit 55b in a feedforward manner to the positive-phase / negative-phase reference voltage vdref on the d axis, which is the output of the controller 52, to obtain a reactive voltage command value vd * The adder 53c adds the positive-phase effective voltage Vqff calculated by the three-phase / two-phase coordinate conversion unit 55b in a feedforward manner to the positive-phase / negative-phase reference voltage vqref on the q axis, which is the output of the controller 52, to calculate the effective voltage command value vq * Here, the voltage command value vd on the d axis is calculated. * and the voltage command value vq on the q axis * Each of the signals includes both positive and negative sequence components.

[0078] [Voltage command value calculation unit 70] Referring again to FIG. 4, the voltage command value calculation unit 70 calculates the voltage command value vd * and the voltage command value vq on the q axis * By performing two-phase / three-phase conversion on the U-phase, V-phase, and W-phase AC voltage command values ​​vu * ,vv * ,vw * The two-phase / three-phase conversion can be configured as an inverse conversion of the three-phase / two-phase conversion. That is, the voltage command value calculation unit 70 converts the dq coordinates into the αβ coordinates, and then converts the αβ coordinates into the three-phase coordinates.

[0079] Furthermore, the voltage command value calculation unit 70 calculates the AC voltage command value vu * ,vv * ,vw * The zero-phase voltage command value vz * By adding these, the output voltage command value Vuo of the U phase, V phase, and W phase is * ,Vvo * ,Vwo * Calculate the following.

[0080] [Gate signal generating unit 80] 4, the gate signal generating unit 80 receives the output voltage command values ​​Vuo of the U-phase, V-phase, and W-phase output from the voltage command value calculating unit 70. * ,Vvo * ,Vwo * A gate signal Ga for controlling the on / off of the semiconductor switching elements Q1 to Q4 of each converter cell 5 of each arm is generated by PWM (Pulse Width Modulation) control according to the above. The gate signal Ga is input to the control electrode G of the semiconductor switching elements Q1 to Q4 of each converter cell 5 via the driver 19 of each converter cell 5. This determines whether the semiconductor switching elements Q1 to Q4 of each converter cell 5 are on or off.

[0081] [Advantages of the first embodiment] As described above, according to the power conversion device 1 of the first embodiment, it is possible to appropriately determine the sharing ratio of the circulating current and the negative-phase current contributing to the phase voltage balance control while suppressing an increase in the arm current by limiting the magnitudes of the arm current command value and the circulating current command value output from the phase voltage balance control unit 30. It is possible to reduce the converter capacity and improve the operational continuity of the power conversion device during a grid accident.

[0082] Embodiment 2 [Key Points of the Second Embodiment] In the power conversion device of the second embodiment, the controller 33 included in the phase voltage balance control unit 30 is configured by a proportional-integral (PI) controller, and a limiter 34 is provided at the output of an integrator of the PI controller. This makes it possible to adjust the magnitudes of the valve branch current command value and the circulating current command value output from the phase voltage balance control unit 30, as in the case of the first embodiment. Furthermore, the magnitudes of the valve branch current command value and the circulating current command value can also be adjusted by the input / output characteristics (specifically, the proportional gain and the integral gain) of the PI controller.

[0083] [Configuration of phase voltage balance control unit] In the power conversion device 1 of the second embodiment, the configuration of the phase voltage balance control unit 30 included in the control device 3 of Fig. 4 is different from that of the first embodiment. The other components included in the control device 3 are similar to those in Fig. 4, and therefore description thereof will not be repeated.

[0084] FIG. 10 is a block diagram showing an example of the configuration of a phase voltage balance control unit 30 included in the control device 3 in the power conversion device 1 according to the second embodiment.

[0085] The phase voltage balance control unit 30 in Fig. 10 differs from the phase voltage balance control unit 30 in Fig. 5 in the configurations of the controllers 33a, 33b, and 33c and the limiters 34a, 34b, and 34c. In the phase voltage balance control unit 30 in Fig. 10, each controller 33 is formed of a PI controller and includes a corresponding limiter 34 therein.

[0086] Specifically, the controller 33a receives an input of the UV-phase error ΔVuv from the corresponding subtractor 32a. The controller 33a includes a proportional unit 39a having a proportional gain Kp, an integrator 390a having an integral gain Ki, a limiter 34a, and an adder 36a.

[0087] The proportional unit 39a multiplies the error ΔVuv by Kp and outputs the result. The integrator 390a multiplies the error ΔVuv by Ki and integrates it. The limiter 34a limits the calculation result of the integrator 390a to a range between an upper limit value and a lower limit value. That is, when the output of the integrator 390a exceeds the upper limit value, the limiter 34a changes the output value of the integrator 390a to the upper limit value and outputs it, when the output of the integrator 390a exceeds the lower limit value, the limiter 34a changes the output value of the integrator 390a to the lower limit value and outputs it, and when the output of the integrator 390a is between the upper limit value and the lower limit value, the limiter 34a outputs the output value as it is. The adder 36a adds the calculation result of the proportional unit 39a and the output of the limiter 34a. The multiplier 35a receives the addition result of the adder 36a as the output of the controller 33a and multiplies the output of the controller 33a by the voltage Vuv of the arm A1.

[0088] Similarly, the controller 33b to which the VW-phase error ΔVvw is input from the corresponding subtractor 32b includes a proportional unit 39b having a proportional gain Kp, an integrator 390b having an integral gain Ki, a limiter 34b, and an adder 36b. The proportional unit 39b multiplies the error ΔVvw by Kp and outputs the result. The integrator 390b integrates the error ΔVvw by Ki. The limiter 34b limits the calculation result of the integrator 390b within a range between an upper limit value and a lower limit value. The adder 36b adds the calculation result of the proportional unit 39b and the output of the limiter 34b, and outputs the addition result to the corresponding multiplier 35b as the output of the controller 33b. The multiplier 35b multiplies the output of the controller 33b by the voltage Vvw of the arm A2.

[0089] Similarly, the controller 33c to which the error ΔVwu of the WU phase is input from the corresponding subtractor 32c includes a proportional unit 39c having a proportional gain Kp, an integrator 390c having an integral gain Ki, a limiter 34c, and an adder 36c. The proportional unit 39c multiplies the error ΔVwu by Kp and outputs the multiplied value. The integrator 390c integrates the error ΔVwu by Ki. The limiter 34c limits the calculation result of the integrator 390c within the range of an upper limit value and a lower limit value. The adder 36c adds the calculation result of the proportional unit 39c and the output of the limiter 34c, and outputs the sum to the corresponding multiplier 35c as the output of the controller 33c. The multiplier 35c multiplies the output of the controller 33c by the voltage Vwu of the arm A3.

[0090] Other points in FIG. 10 are the same as those in FIG. 5, so the same or corresponding parts are given the same reference characters and the description will not be repeated.

[0091] [Effects of the second embodiment] According to the power conversion device 1 of the second embodiment, each controller 33 of the phase voltage balance control unit 30 is configured as a PI controller, and a limiter 34 is arranged to limit the output of the integrator 390. As a result, the arm current command value and the circulating current command value Iz of any phase are controlled according to the degree of unbalance of the system voltage. * The compensation amount of the phase voltage balance control unit 30 limited by the limiter 34 is limited to the negative sequence current command value In * (That is, the negative-phase active current command value Iqn * and the negative-phase reactive current command value Idn * ) and its magnitude increases. That is, the circulating current command value Iz * and the negative-phase current command value In * (i.e., the circulating current command value Iz * and the negative-phase current command value In * This makes it possible to limit the arm current flowing through the power converter 2, thereby making it possible to reduce the converter capacity of the power converter 2. In addition, the operation continuity of the power converter 2 in the event of a fault in the power grid can be improved.

[0092] The magnitudes of the arm current command value and the circulating current command value may be adjusted according to the input / output characteristics of the controller 33. For example, the input / output characteristics of the PI controller relate to the proportional gain, the integral gain, and the upper and lower limit values ​​of the limiter 34 that limits the output of the integrator 390.

[0093] Embodiment 3 [Key Points of the Third Embodiment] In the power conversion device 1 of the third embodiment, the upper and lower limit values ​​of the limiter 34 described in the first and second embodiments are adjusted to become the minimum circulating current value determined according to the detected value of the system voltage and the detected value of the output current of the power converter 2. The minimum circulating current value can be determined under the condition that the DC component of the voltage of the storage element 17 of each converter cell 5 does not fluctuate.

[0094] [Difference in arm current with and without negative-sequence current control] When the system voltage becomes unbalanced due to a fault in the power system, the arm current of the power conversion device increases. In order to suppress the arm current, negative-sequence current control is required. Below, we will explain the calculation results of the difference in the magnitude of the arm current with and without negative-sequence current control.

[0095] FIG. 11 is a diagram illustrating an example of arm currents of a power converter under unbalanced system voltage conditions when negative-sequence current control is not performed.

[0096] Specifically, the graph in Fig. 11 shows the amplitude [pu] of theoretical arm currents of each phase (UV, VW, WU) relative to the phase of the negative sequence voltage during steady operation when the positive sequence voltage is 2 / 3 [pu] and the negative sequence voltage is 1 / 3 [pu]. The phase of the negative sequence voltage on the horizontal axis indicates the value when the phase of the positive sequence voltage is taken as the reference (0°). The positive sequence reactive current of the output current is set to 1 [pu], and the negative sequence current In shown in equation (1) of the first embodiment is set to 0 [pu] (i.e., no negative sequence current control).

[0097] As shown in Fig. 11, the amplitude of the arm current varies depending on the phase of the negative-sequence current. When the phase of the negative-sequence voltage is in the range of 0° to 120°, the WU-phase arm current has the maximum amplitude, when the phase of the negative-sequence voltage is in the range of 120° to 240°, the UV-phase arm current has the maximum amplitude, and when the phase of the negative-sequence voltage is in the range of 240° to 360°, the VW-phase arm current has the maximum amplitude.

[0098] Fig. 12 is a diagram showing an example of the difference in maximum arm current depending on whether or not negative-sequence current control is performed. In Fig. 12, the dashed line graph shows the maximum arm current versus the phase of the negative-sequence voltage when there is no negative-sequence current control. Specifically, as in Fig. 11, the positive-sequence voltage is set to 2 / 3 [pu], the negative-sequence voltage to 1 / 3 [pu], the positive-sequence reactive current to 1 [pu], and the negative-sequence current In to 0 [pu]. Therefore, the maximum amplitude indicated by the dashed line in Fig. 12 is the same as in Fig. 11.

[0099] On the other hand, the solid line graph in Fig. 12 shows the maximum arm current versus the phase of the negative-sequence voltage when negative-sequence current control is applied. Specifically, the negative-sequence current In is set to 0.2 [pu], and the phase of the negative-sequence current In is controlled to have a 90-degree difference from the phase of the negative-sequence voltage. As shown in Fig. 12, the maximum value of the arm current when negative-sequence current control is applied is smaller than the maximum value of the arm current when negative-sequence current control is not applied, confirming that the arm current can be suppressed by the negative-sequence current control.

[0100] Here, the conditions under which the arm current decreases are shown based on the relational expression between the capacitor voltage and the arm current of each converter cell of the MMC.

[0101] In the MMC type power converter 2, the instantaneous value v of the capacitor voltage of each converter cell 5 dc and the instantaneous value of the capacitor current i dc The differential equation that expresses the relationship between the capacitance of the capacitor, C SM and differential operator p, it is expressed as the following equation (4).

[0102]

number

[0103] The instantaneous value of the AC output voltage of arm A1 of the UV phase is v uv The instantaneous value of the AC output current is i uv Let the number of converter cells 5 be N SMConsidering the voltage balance between the series-connected converter cells 5 and assuming that there is no loss in conversion in the voltage source converter, the DC input power of each converter cell 5 and the AC output power of arm A1 must be balanced as shown in the following equation (5).

[0104]

number

[0105] Each converter cell 5 of the UV phase arm A1 is connected to the voltage source converter modulation index k uv By introducing the above, the AC voltage of each converter cell 5 of the UV phase arm A1 can be expressed by the following equation (6).

[0106]

number

[0107] Substituting equations (5) and (6) into equation (4), the arm current i uv and modulation index k uv The differential equation for the capacitor is derived as shown in the following equation (7).

[0108]

number

[0109] Equivalent time constant of a capacitor, T dc [s], the normalized U-V phase capacitor voltage v cUV [pu], modulation index m of UV phase UV [pu / peak], UV phase arm current i UV [pu / peak], system frequency ω sys [rad / s], DC capacitor voltage V cap [V], rated capacity of power converter 2 (STATCOM) S rate By using the line-to-line secondary voltage Vu [V], the differential equation (7) above can be converted to a differential equation for the system per unit as shown in the following equation (8A). In addition, the equivalent time constant Tdc [s] is given by the following equation (8B):

[0110]

number

[0111] Here, the normalized UV phase capacitor voltage v cUV [pu], UV phase arm current i UV [pu / peak], modulation index m of UV phase UV [pu / peak] is defined by the following equations (9A) to (9C), respectively.

[0112]

number

[0113] Differential equations can be obtained similarly for the VW phase and WU phase. Considering the fundamental wave components of the line voltages and arm currents, the above equation (8A) holds for the average value of the DC capacitor voltage of the converter cell 5 in each arm. Therefore, the three-phase differential equation for the average value of the DC capacitor voltage in the arm is given by the following equation (10).

[0114]

number

[0115] Since the transformer 4 is Y-Δ connected, the UV phase of the power converter 2 corresponds to the U phase (also referred to as the A phase) of the AC power system 9, the VW phase of the power converter 2 corresponds to the V phase (also referred to as the B phase) of the AC power system 9, and the WU phase of the power converter 2 corresponds to the W phase (also referred to as the C phase) of the AC power system 9.

[0116]

number

[0117] When formula (10) is converted by the conversion formula of formula (11) (x represents v and i), the following formula (12) is obtained. In the following formula (12), v c0 represents the voltage of the zero-phase component and corresponds to the three-phase average voltage of the capacitor voltage. cα , v cβ corresponds to the imbalance of the capacitor voltages between the phases (i.e., the fluctuation component with respect to the three-phase average voltage).

[0118]

number

[0119] Here, to make it easier to handle the unbalanced components (i.e., positive and negative phases), the signals on the orthogonal stationary coordinates are expressed as complex signals. In the orthogonal stationary coordinates, the positive frequency components represent the positive phase components, and the negative frequency components represent the negative phase components, so by handling them as complex signals, both components can be included in a single variable. Specifically, the unbalanced component of the capacitor voltage can be expressed by the following equation (13A), the unbalanced component of the arm current can be expressed by the following equation (13B), and the unbalanced component of the modulation index can be expressed by the following equation (13C).

[0120]

number

[0121] The discharge current associated with the unbalanced component of the DC voltage is given by v cα and v cβ v in equation (12) cα and v cβ By substituting the above and transforming the equation using equations (13B) and (13C), the following equation (14) can be obtained. In the following equation (14), the complex conjugate is represented by a bar.

[0122]

number

[0123] [Circulating current conditions required for phase voltage balancing] Below, we derive the minimum value of the circulating current required for balancing the phase voltages from the steady-state equation of the delta-connected STATCOM. The positive-sequence instantaneous voltage v p (t) and the negative-phase instantaneous voltage v n (t) is the voltage phasor V p ,V n Using these equations, we obtain the following equations (15A) and (15B). In the following equations, the angular frequency of the power system is expressed as ω sys Let us assume that.

[0124]

number

[0125] Similarly, the positive-sequence instantaneous current i in the steady state of the power system p (t) and the negative-phase instantaneous current i n (t) is the current phasor I p ,I n Using this, we obtain the following equations (16A) and (16B).

[0126]

number

[0127] In the phasor representation, the voltage v(t) and current i(t) in the Cartesian stationary coordinate system are expressed as the sum of the complex conjugates of the positive and negative sequence components, so the following equations (17A) and (17B) hold, where the complex conjugates are represented by bars.

[0128]

number

[0129] Since the circulating current i0(t) is a single-phase component and a real number, it is expressed by the following equation (18). In the following equation, the amplitude of the circulating current is I0, and the phase of the circulating current is θ0.

[0130]

number

[0131] The rated value of the capacitor voltage of each converter cell is V c0 Let us assume that V c0 corresponds to the zero-phase component voltage. Also, the fundamental component of the modulation index m of each converter cell is m1, and the reactance of the transformer X t and the unit reactance of the arm reactor, X arm The sum of and X s Let v(t) be [pu] and the differential operator be p. The differential equation shown below, equation (19A), holds for the output voltage v(t) and output current i(t). Furthermore, equation (19B) can be obtained from equation (19A) and equations (17A) and (17B). If the modulation index of the circulating current is m0, then m0 can be expressed by equation (19C).

[0132]

number

[0133] The first term in the brackets on the right side of equation (19B) above corresponds to the positive-sequence voltage output by the MMC-STATCOM power converter 2, and the second term in the brackets on the right side corresponds to the negative-sequence voltage output by the MMC-STATCOM power converter 2. The result of dividing these voltages by the three-phase average voltage of the capacitor becomes the modulation signal.

[0134] Here, the condition for the capacitor voltage of each converter cell not to fluctuate at least with respect to the DC component is when the discharge current related to the unbalanced component of the DC voltage becomes 0, and the above-mentioned formula (14) becomes 0, that is, the following formula (20A) is satisfied. Note that the left side of the following formula (20A) is formula (14) multiplied by -1. Here, the modulation index m includes a fundamental wave component and a harmonic component, but since the fundamental wave component m1 expressed by formula (19B) is large and dominant, the modulation index m in the following formula (20A) is replaced by m1 in the above formula (19B). Furthermore, in the following formula (20A), formula (19C) is substituted for m0, formula (18) is substituted for i0, and formula (17B) is substituted for i. Since the modulation signals m1 and m0 and the currents i and i0 include fundamental wave components, the multiplication of the modulation signal and the current includes a DC component and positive and negative double frequency components. Therefore, by extracting only the DC component and rearranging it, the following equation (20B) is obtained. In the derivation of the following equation (20B), X s =X arm +X t The relationship was used.

[0135]

number

[0136] The first term in the curly brackets in the above equation (20B) corresponds to the power when a circulating current flows when a positive-sequence voltage and a negative-sequence voltage exist, and the second term in the curly brackets in the above equation (20B) corresponds to the power when an unbalanced voltage and an unbalanced current exist. Therefore, by balancing the power due to the negative-sequence component and the power due to the circulating current, the imbalance of the DC capacitor voltage can be suppressed.

[0137] From the above equation (20B), the condition for the circulating current to make the fluctuation component of the capacitor voltage constant is derived, and the phase θ0 of the circulating current is given by the following equation (21A), and the magnitude I0 of the circulating current is given by the following equation (21B). In other words, the circulating current required for phase balance control (equation (18)) can be found from the following equations (21A) and (21B). Note that the following equation (21B) can be found by solving the above equation (20B) with I0. The following equation (21A) can be found as the phase θ0 when the imaginary part of the following equation (21B) becomes 0.

[0138]

number

[0139] The positive-sequence voltage phasor Vp and the negative-sequence voltage phasor Vn in the above equations (21A) and (21B) are the voltage phasors V of the U-phase, V-phase, and W-phase of the three-phase AC voltage based on the detection values ​​of the AC voltage detection unit 12 in FIG. u ,V v ,V w The positive-sequence current phasor I p The negative-phase current phasor In is the current phasor I of the output current of the U phase, V phase, and W phase based on the detection value of the AC current detection unit 11 in FIG. u ,I v ,I w The operator a in the following equations (22A) and (22B) can be expressed by the following equation (22C).

[0140]

number

[0141] A phasor includes a magnitude and a phase. If the phase of the positive-sequence voltage phasor is set as a reference (0°), in equations (21A) and (21B), the phase and magnitude of the circulating current are determined by inputting the magnitude of the positive-sequence voltage, the magnitude of the negative-sequence voltage, and the phase of the negative-sequence voltage of the power system, and the magnitude of the positive-sequence current, the phase of the positive-sequence current, the magnitude of the negative-sequence current, and the phase of the negative-sequence current for the output current of power conversion device 1.

[0142] According to the above-mentioned formula (1), when the magnitude of the circulating current is reduced, the magnitude of the arm current is reduced, so that the upper and lower limit values ​​of the limiter 34 are determined so as to obtain the minimum value of the arm current given by the formulas (21A) and (21B). * The upper and lower limit values ​​of each limiter 34 are determined so that the magnitude of is equal to the magnitude of the circulating current I0 calculated by equation (21B).

[0143] The phase voltage balance control unit 30 may calculate the minimum value of the circulating current that satisfies (21A) and (21B) by sequentially performing calculation processing based on the system voltage detected by the AC voltage detection unit 12 and the output current of the power converter 2 detected by the AC current detection unit 11, and determine the upper and lower limit values ​​of the limiter 34 based on the minimum value of the circulating current. However, this method requires a considerable amount of time for the calculation processing.

[0144] Therefore, the upper and lower limit values ​​of the limiter 34 that provide the minimum circulating current value may be determined in advance according to various values ​​of the system voltage and the output current of the power converter 2, and may be stored in memory as a table showing the relationship between the values ​​of the system voltage and the output current and the upper and lower limit values ​​of the limiter 34. In this case, the phase voltage balance control unit 30 refers to this table to determine the upper and lower limit values ​​of the limiter 34 that correspond to the detected values ​​of the system voltage and the output power.

[0145] [Effects of the third embodiment] According to the power conversion device 1 of the third embodiment, the upper and lower limit values ​​of the limiter 34 described in the first and second embodiments are made variable, and the upper and lower limit values ​​of the limiter 34 are adjusted so that the circulating current command value is equal to the minimum circulating current value determined according to the detected value of the grid voltage and the detected value of the output current of the power converter 2. This makes it possible to reduce the magnitude of the arm current as much as possible while maintaining the balance control function of the phase voltages, thereby making it possible to reduce the capacity of the power converter 2 as much as possible and improve the continuity of operation during a grid accident.

[0146] The embodiments disclosed herein should be considered to be illustrative and not restrictive in all respects. The scope of this application is defined by the claims, not the above description, and is intended to include all modifications within the meaning and scope of the claims. [Explanation of symbols]

[0147] 1 power conversion device, 2 power converter, 3 control device, 4 transformer, 5 converter cell, 9 AC power system, 10 arm current detection section, 11 AC current detection section, 12 AC voltage detection section, 15F full bridge circuit, 15H half bridge circuit, 16a, 16b input / output terminals, 17 storage element, 18 voltage detector, 19 driver, 20 DC voltage control section, 21 DC voltage representative value calculation section, 22, 32, 41, 54, 62 subtractor, 23, 33, 52, 61, 84 controller, 30 voltage balance control section, 31 voltage representative value calculation section, 34 limiter, 35 multiplier, 36, 53, 63 adder, 37, 64 constant multiplier, 38, 43 filter, 39 proportional section, 40 negative-phase current command value calculation section, 42, 55 Three-phase / two-phase coordinate conversion unit, 50 output current control unit, 51 reference voltage calculation unit, 60 circulating current control unit, 70 voltage command value calculation unit, 80 gate signal generation unit, 390 integrator, A1, A2, A3 arms, D rectifier element, G control electrode, L reactor, NL negative pole line, PL positive pole line, Q semiconductor switching element, UL, VL, WL AC lines.

Claims

1. A power converter connected to a three-phase AC system; a control device for controlling the power converter, The power converter comprises three delta-connected arms, each of which includes a plurality of cascaded converter cells; Each of the plurality of transducer cells comprises: An input / output terminal pair; a bridge circuit including a plurality of semiconductor switching elements; a storage element connected to the input / output terminal pair via the bridge circuit, The control device includes: a phase voltage balance control unit that calculates an arm current command value and a circulating current command value of each arm so that a difference between a representative value of the voltage of the storage element included in each arm and a representative value of the voltage of the storage elements included in all of the arms becomes small; a negative-sequence current command value calculation unit that calculates a negative-sequence current command value based on the arm current command value and the circulating current command value; an output current control unit that calculates a voltage command value to control an output current of the power converter based on the negative sequence current command value and the positive sequence current command value; a circulating current control unit that calculates a zero-phase sequence voltage command value for controlling a circulating current based on a detection value of an arm current of each arm, based on the circulating current command value; a voltage command value calculation unit that calculates an output voltage command value to be output to each arm based on the voltage command value and the zero-phase voltage command value; a gate signal generating unit that generates a gate signal for controlling on / off of each semiconductor switching element included in each converter cell of each arm based on the output voltage command value, the phase voltage balance control unit is configured to limit magnitudes of the arm current command value and the circulating current command value, and a magnitude of the negative-sequence current command value calculated by the negative-sequence current command value calculation unit increases according to an amount by which the magnitudes of the arm current command value and the circulating current command value of any one of the arms are limited.

2. The phase voltage balance control unit includes: a feedback controller to which a difference between a representative value of the voltage of the storage element included in each arm and a representative value of the voltage of the storage elements included in all arms is input; 2. The power conversion device according to claim 1, further comprising: a limiter that limits an output of the controller within a range between an upper limit value and a lower limit value.

3. the phase voltage balance control unit includes a feedback controller to which a difference between a representative value of a voltage of the storage element included in each arm and a representative value of a voltage of the storage elements included in all of the arms is input, The power conversion device according to claim 1 , wherein the magnitudes of the valve branch current command value and the circulating current command value are limited in accordance with an input / output characteristic of the controller.

4. The power converter according to claim 3 , wherein the controller includes a limiter that limits the internal signal within a range of upper and lower limits.

5. the controller is a proportional-integral controller including a proportional unit and an integrator; The power conversion device according to claim 4 , wherein the limiter limits an output of the integrator.

6. a minimum circulating current value is determined under a condition that a DC component of a voltage of the storage element of each converter cell does not fluctuate, according to a detection value of a system voltage of the three-phase AC system and a detection value of an output current of the power converter; 6. The power conversion device according to claim 2, wherein the phase voltage balance control unit adjusts the upper limit value and the lower limit value of the limiter in accordance with a detection value of a system voltage of the three-phase AC system and a detection value of an output current of the power converter, so that the circulating current command value is equal to a value of the minimum circulating current.

7. A positive-sequence voltage phasor V based on the detection value of the system voltage of the three-phase AC system ｐ and the negative-phase voltage phasor V ｎ , a positive-sequence current phasor I based on the detection value of the output current of the power converter ｐ and the negative sequence current phasor I ｎ , and a reactance X of a transformer provided between the three-phase AC system and the power converter. ｔ Using the above, the phase of the circulating current θ ０ and the minimum value I of the circulating current ０ is given by the following formula: [0010] The power converter according to claim 6.

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