Method for manufacturing wiring board

Abstract

To provide a wiring board capable of suppressing migration between wirings, and a method for manufacturing the wiring board.SOLUTION: The method for manufacturing a wiring board including a first wiring board in which a first wiring layer is formed and a second wiring board in which a second wiring layer finer than the first wiring layer is formed forms the second wiring layer by performing the steps of: forming a first insulation resin layer including a wiring pattern and an opening; forming a first inorganic insulation film on the first insulation resin layer; forming a first conductor layer according to the wiring pattern and the opening on the inorganic insulation film; and forming a second inorganic film on the first conductor layer.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to wiring The present invention relates to a method for manufacturing a substrate. [Background technology]

[0002] In recent years, as semiconductor devices become faster and more highly integrated, there is a demand for narrower pitches for connection terminals with semiconductor elements and finer wiring within the board for FC-BGA (Flip Chip-Ball Grid Array) wiring boards on which semiconductor elements are mounted. On the other hand, there is a demand for connection between FC-BGA wiring boards and motherboards using connection terminals with almost the same pitch as before.

[0003] In order to accommodate the narrower pitch of connection terminals with semiconductor elements and the accompanying finer wiring within FC-BGA wiring boards, a technology has been adopted in which a multilayer wiring board containing fine wiring, also known as an interposer, is provided between the FC-BGA wiring board and the semiconductor elements.

[0004] One of them is silicon interposer technology, in which an interposer is formed on a silicon wafer using semiconductor circuit manufacturing technology.

[0005] Also, a method has been developed in which an interposer is directly fabricated on a wiring board for FC-BGA, rather than being formed on a silicon wafer. This is a method in which the surface of the wiring board for FC-BGA is flattened by CMP (Chemical Mechanical Polishing) or the like, and a multilayer wiring board that will become the interposer is directly formed on the wiring board for FC-BGA. This is disclosed in Patent Document 1.

[0006] Furthermore, there is a method in which an interposer (multilayer wiring board) is formed on a support such as a glass substrate, and then this is mounted on an FC-BGA substrate, and the support is then peeled off to form a narrow-pitch multilayer wiring board on the FC-BGA wiring board. This method is disclosed in Patent Document 2. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] JP 2014-225671 A [Patent Document 2] International Publication No. 2018 / 047861 Summary of the Invention [Problem to be solved by the invention]

[0008] Silicon interposers are made from silicon wafers using equipment for front-end semiconductor manufacturing, making them suitable for forming fine wiring layers. However, silicon wafers are limited in shape and size, and only a small number of interposers can be made from a single wafer. In addition, the manufacturing equipment is expensive, making the interposers expensive. In addition, because silicon wafers are semiconductors, there is also the problem of degradation of transmission characteristics.

[0009] In addition, in the method of flattening the surface of the FC-BGA wiring board and forming multiple wiring layers on it to serve as the interposer, the deterioration of transmission characteristics seen in silicon interposers is small, but there are issues with the overall low manufacturing yield due to problems with the manufacturing yield of the FC-BGA wiring board itself and the high difficulty of forming fine wiring on the FC-BGA wiring board. Furthermore, there are also issues in mounting semiconductor elements due to warping and distortion of the FC-BGA wiring board.

[0010] Furthermore, in a method in which a multilayer wiring board is formed on a support such as a glass substrate, and then the support is peeled off after the multilayer wiring board is placed on a wiring board for FC-BGA, a semi-additive method is often used when forming a fine wiring layer on the support. Here, the photosensitive resin layer used in the fine wiring layer and the wiring layer are formed adjacent to each other, so there is a problem that copper, which is a material of the wiring layer, diffuses into the photosensitive resin layer during high temperature and high humidity environmental testing, causing electrical conduction between nearby wirings, which is called migration (also called electromigration).

[0011] The present invention has been made in consideration of the above problems, and provides a wiring capable of suppressing migration between wirings. Board The object is to provide a manufacturing method. [Means for solving the problem]

[0013] In order to solve the above problems, A representative method for manufacturing a wiring board of the present invention includes a first wiring board having a first wiring layer formed thereon, and a second wiring board having two or more second wiring layers formed thereon that are finer than the first wiring layer, the first wiring board being bonded to one surface of the second wiring board, and a semiconductor element being mountable on the other surface of the second wiring board, The step of manufacturing the second wiring substrate includes: forming a first insulating resin layer having a wiring pattern and an opening corresponding to the second wiring layer; forming a first inorganic insulating film on the first insulating resin layer; forming a first conductor layer on the first inorganic insulating film in accordance with the wiring pattern and the opening; and forming a second inorganic insulating film on the first conductor layer. Effect of the Invention

[0014] According to the present invention, a wiring capable of suppressing migration between wirings is provided. Board A method of manufacture may be provided. Problems, configurations and effects other than those described above will become apparent from the following description of the embodiments. [Brief description of the drawings]

[0015] [Figure 1] FIG. 1 is a cross-sectional view of a semiconductor device using a wiring board shown in a state in which a semiconductor element is mounted. [Diagram 2] FIG. 2 is a cross-sectional view showing a state in which a release layer, a photosensitive resin layer, a seed adhesion layer, a seed layer, and a conductor layer are formed on a support. [Diagram 3] FIG. 3 is a cross-sectional view showing a state in which the conductor layer and the seed layer have been polished by surface polishing. [Figure 4] FIG. 4 is a cross-sectional view showing a state in which the seed adhesion layer and the photosensitive resin layer have been polished by surface polishing to form an electrode for bonding with a semiconductor element. [Diagram 5] FIG. 5 is a cross-sectional view showing a state in which the inorganic insulating film has been formed. [Figure 6] FIG. 6 is a cross-sectional view showing a state in which a photosensitive resin layer is formed in the via portion. [Figure 7] FIG. 7 is a cross-sectional view showing a state in which a photosensitive resin layer is formed in the via portion and the wiring portion. [Figure 8] FIG. 8 is a cross-sectional view showing a state in which an inorganic insulating film is formed on a via portion and a wiring portion. [Figure 9] FIG. 9 is a cross-sectional view showing a state in which the inorganic insulating film in the via portion has been removed. [Figure 10] FIG. 10 is a cross-sectional view showing a state in which a seed adhesion layer, a seed layer, and a conductor layer are formed in the same manner as above. [Figure 11] FIG. 11 is a cross-sectional view showing a state in which a via portion and a wiring portion have been formed by surface polishing. [Figure 12] FIG. 12 is a cross-sectional view showing a state in which the seed adhesion layer and the photosensitive resin layer have been polished by surface polishing, and an interlayer connection conductor has been formed. [Figure 13] FIG. 13 is a cross-sectional view showing a state in which the inorganic insulating film has been formed. [Figure 14] FIG. 14 is a cross-sectional view showing a state in which a multilayer wiring is formed by repeating the steps shown in FIGS. [Figure 15]FIG. 15 is a cross-sectional view showing a state after the photosensitive resin layer is formed. [Figure 16] FIG. 16 is a cross-sectional view showing a state in which the inorganic insulating film in the via portion has been removed and a seed adhesion layer, a seed layer, and a resist pattern have been formed in the same manner as the lower layer. [Figure 17] FIG. 17 is a cross-sectional view showing a state after the conductor layer is formed and the resist pattern is removed. [Figure 18] FIG. 18 is a cross-sectional view showing a state in which the unnecessary seed adhesion layer and seed layer have been removed by etching. [Figure 19] FIG. 19 is a cross-sectional view showing a state after the solder resist layer and the surface treatment layer are formed. [Figure 20] FIG. 20 is a cross-sectional view showing a state in which the solder joints are formed and the wiring board on the support body is completed. [Figure 21] FIG. 21 is a cross-sectional view showing a state in which the wiring board on the support body and the FC-BGA substrate are joined and sealed with an underfill layer. [Figure 22] FIG. 22 is a cross-sectional view showing a state in which the peeling layer is irradiated with laser light. [Figure 23] FIG. 23 is a cross-sectional view showing a state where the support has been removed. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0016] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each layer, etc., differ from the actual ones. Therefore, the specific thickness and dimensions should be determined with reference to the following description. In addition, it goes without saying that the drawings include parts with different dimensional relationships and ratios.

[0017] In addition, the embodiments shown below are merely examples of devices and methods for embodying the technical idea of ​​the present invention, and the technical idea of ​​the present invention does not specify the materials, shapes, structures, arrangements, etc. of the components to those described below. The technical idea of ​​the present invention can be modified in various ways within the technical scope defined by the claims.

[0018] In this disclosure, the term "surface" may refer not only to the surface of a plate-shaped member, but also to the interface of a layer contained in the plate-shaped member that is approximately parallel to the surface of the plate-shaped member. Additionally, the terms "upper surface" and "lower surface" refer to the surface shown at the top or bottom of a drawing of a plate-shaped member or a layer contained in the plate-shaped member. The term "side surface" refers to a surface of a plate-like member or a layer included in a plate-like member, or a portion of the thickness of a layer. Furthermore, a part of a surface and a side surface may be collectively referred to as an "end portion." In addition, "upper" refers to the vertically upward direction when a plate-like member or layer is placed horizontally. Furthermore, "upper" and its opposite, "lower", are sometimes referred to as the "Z-axis direction", and the horizontal direction is sometimes referred to as the "X-axis direction" or the "Y-axis direction". Additionally, the terms "planar shape" and "plan view" refer to the shape of a surface or layer when viewed from above. Furthermore, the terms "cross-sectional shape" and "cross-sectional view" refer to the shape of a plate-like member or layer when cut in a specific direction and viewed from the horizontal direction. Furthermore, the term "central portion" refers to the central portion other than the peripheral portion of the surface or layer, and the term "toward the center" refers to the direction from the peripheral portion of the surface or layer toward the center of the planar shape of the surface or layer.

[0019] (Configuration of wiring board) Wiring board 16 of the present embodiment is formed by joining second wiring board (interposer) 13 and FC-BGA board (also referred to as first wiring board) 14. First, as shown in FIG. 1, a semiconductor device 18 manufactured using wiring board 16 of the present embodiment will be described in its entirety. 1, second wiring board 13 can be connected to semiconductor element 17 on a first surface (upper surface) and is joined to FC-BGA substrate 14 on a second surface (lower surface), which together form semiconductor device 18. The two or more wiring layers (also called second wiring layers) of second wiring board 13 are finer than the wiring layer (also called first wiring layer) of FC-BGA substrate 14, and the spacing between adjacent wirings is, for example, 0.5 to 5.0 μm. For this reason, it is necessary to suppress migration, as will be described in detail later.

[0020] The second wiring board 13 is connected to the semiconductor element 17 via the chip connection terminals 19, and then sealed and fixed with a sealing resin 26. The second wiring board 13 is connected to the FC-BGA substrate 14 via the connection terminals 20 and the solder joints 12, and then sealed and fixed with a sealing resin 23. As described later, the second wiring board 13 is formed above a support (carrier substrate) 1 with a release layer 2 interposed therebetween, and after being bonded to the FC-BGA substrate 14 together with the support 1, the support 1 is peeled off and removed at the release layer 2.

[0021] Semiconductor element 17 may be bonded to second wiring board 13 after it has been bonded to FC-BGA substrate 14, or may be bonded to second wiring board 13 before it is bonded to FC-BGA substrate 14. In the following description of the embodiment, a mode in which semiconductor element 17 is bonded to wiring board 16 after second wiring board 13 is bonded to FC-BGA substrate 14 will be described.

[0022] (Method of Manufacturing Wiring Board) An example of a manufacturing process for a wiring board using a support according to this embodiment will be described with reference to FIGS.

[0023] (1) Formation of a release layer on a support First, referring to FIG. 2, a release layer 2 necessary for peeling off the support 1 in a later step is formed on one surface of the support 1.

[0024] The release layer 2 may be formed of a resin that becomes peelable by absorbing light such as UV light and generating heat or by being altered, or may be formed of a resin that becomes peelable by foaming due to heat. When a resin that becomes peelable by light such as UV light, for example laser light, is used, the support 1 can be removed from the bonded body of the second wiring board 13 and the FC-BGA board 14 on the support 1 by irradiating the support 1 with light from the side opposite to the side where the release layer 2 is provided.

[0025] The material of the peeling layer 2 can be selected from organic resins such as epoxy resin, polyimide resin, polyurethane resin, silicone resin, polyester resin, oxetane resin, maleimide resin, and acrylic resin, and inorganic layers such as amorphous silicon, gallium nitride, and metal oxide layers. The material of the peeling layer 2 may further contain additives such as a photodecomposition promoter, a light absorber, a sensitizer, and a filler. The peeling layer 2 may be composed of multiple layers, and for example, a protective layer may be further provided on the peeling layer 2 for the purpose of protecting the multilayer wiring layer formed on the support 1, or a layer for improving adhesion with the support 1 may be provided under the peeling layer 2. Furthermore, a laser light reflective layer or a metal layer may be provided between the peeling layer 2 and the multilayer wiring layer, and the configuration is not limited by this embodiment.

[0026] Since light may be irradiated onto the peeling layer 2 through the support 1, the support 1 is preferably transparent, and glass, for example, may be used. Glass has excellent flatness and high rigidity, and is therefore suitable for forming a fine pattern on a wiring board on the support. In addition, glass has a small CTE (coefficient of thermal expansion) and is resistant to distortion, and is therefore excellent in ensuring pattern placement accuracy and flatness.

[0027] When glass is used as the support 1, the thickness of the glass is preferably thicker in order to suppress the occurrence of warping in the manufacturing process, and is set to, for example, 0.5 mm or more, preferably 1.2 mm or more. The CTE of the glass is preferably 3 ppm or more and 16 ppm or less, and more preferably about 10 ppm in terms of the CTE of the FC-BGA wiring board 14 and the semiconductor element 17.

[0028] Examples of glass that can be used include quartz glass, borosilicate glass, alkali-free glass, soda glass, and sapphire glass. On the other hand, in cases where the support 1 does not need to be transparent when peeling off the support 1, such as when a resin that foams when heated is used for the peeling layer 2, a material with less distortion, such as metal or ceramics, can be used for the support 1. In this embodiment, a resin that absorbs UV light and becomes peelable is used for the peeling layer 2, and glass is used for the support 1.

[0029] (2) Formation of a photosensitive resin layer on the top surface of the release layer Next, a photosensitive resin layer 3, which is an insulating resin layer, is formed on the release layer 2. In this embodiment, for example, a photosensitive epoxy resin is formed by spin coating as the photosensitive resin layer 3. Photosensitive epoxy resin can be cured at a relatively low temperature and shrinks little due to curing after formation, which makes it excellent for subsequent fine pattern formation.

[0030] When a liquid photosensitive resin is used, the method of forming the photosensitive resin can be selected from slit coating, curtain coating, die coating, spray coating, electrostatic coating, inkjet coating, gravure coating, screen printing, gravure offset printing, spin coating, and doctor coating. When a film-like photosensitive resin is used, lamination, vacuum lamination, vacuum pressing, and the like can be applied.

[0031] The photosensitive resin layer 3 may be made of, for example, a photosensitive polyimide resin, a photosensitive benzocyclobutene resin, a photosensitive epoxy resin, or a modified product thereof, as an insulating resin. Next, a large-diameter opening is provided in the photosensitive resin layer 3 by photolithography. The large-diameter opening may be subjected to plasma treatment for the purpose of removing residues from development. The thickness of the photosensitive resin layer 3 is set according to the thickness of the conductor layer to be formed in the large-diameter opening, and is set to, for example, 8 μm in this embodiment. The shape of the large-diameter opening in plan view is set according to the pitch and shape of the bonding electrodes of the semiconductor element, and is formed to, for example, φ25 μm and a pitch of 55 μm in this embodiment.

[0032] (3) Formation of seed adhesion layer and seed layer Next, a seed adhesion layer 4 and a seed layer 5 are formed in a vacuum. The seed adhesion layer 4 is a layer that improves the adhesion of the seed layer 5 to the photosensitive resin layer 3 and prevents peeling of the seed layer 5. The seed layer 5 acts as a power supply layer for electrolytic plating in forming wiring.

[0033] The seed adhesion layer 4 and the seed layer 5 are formed by, for example, a sputtering method or a vapor deposition method, and may be made of, for example, Cu, Ni, Al, Ti, Cr, Mo, W, Ta, Au, Ir, Ru, Pd, Pt, AlSi, AlSiCu, AlCu, NiFe, ITO, IZO, AZO, ZnO, PZT, TiN, Cu3N4, Cu alloy, or a combination of a plurality of these. In this embodiment, in consideration of electrical characteristics, ease of manufacture, and cost, a titanium layer is formed on the seed adhesion layer 4, and then a copper layer of the seed layer 5 is formed in sequence by a sputtering method. The total thickness of the titanium and copper layers is preferably 1 μm or less as a power supply layer for electrolytic plating. In this embodiment, Ti: 50 nm, Cu: 300 nm are formed.

[0034] (4) Formation of the conductor layer Next, the conductor layer 6 is formed by electrolytic plating. The conductor layer 6 becomes an electrode for bonding with the semiconductor element 17. Examples of electrolytic plating include electrolytic nickel plating, electrolytic copper plating, electrolytic chromium plating, electrolytic Pd plating, electrolytic gold plating, electrolytic rhodium plating, and electrolytic iridium plating. However, electrolytic copper plating is preferable because it is simple, inexpensive, and has good electrical conductivity. The thickness of the electrolytic copper plating becomes an electrode for bonding with the semiconductor element 17, and is preferably 1 μm or more from the viewpoint of solder bonding and 30 μm or less from the viewpoint of productivity. In this embodiment, Cu: 10 μm is formed in the opening of the photosensitive resin layer 3, and Cu: 2 μm is formed on the upper part of the photosensitive resin layer 3.

[0035] By the above steps, it is possible to obtain the configuration shown in Fig. 2. Furthermore, the following steps are carried out.

[0036] (5) Polishing the conductor layer 3, the copper layer is polished by CMP (chemical mechanical polishing) or the like to remove unnecessary conductor layer 6 and seed layer 5. This allows polishing to be performed so that the seed adhesion layer 4 and conductor layer 6 become the surface. In this embodiment, Cu: 2 μm of the conductor layer 6 of the photosensitive resin layer 3 and Cu: 300 nm of the seed layer 5 are removed by polishing.

[0037] (6) Removal of the seed adhesion layer and photosensitive resin layer Next, as shown in FIG. 4, polishing such as CMP processing is performed again to remove unnecessary seed adhesion layer 4 and photosensitive resin layer 3. Since the seed adhesion layer 4 and the photosensitive resin layer 3 are different materials, chemical polishing is less effective, and physical polishing using an abrasive is more effective. However, for the purpose of simplifying the process, a method similar to the polishing described above with reference to FIG. 3 may be used, and for the purpose of improving the efficiency of polishing, the polishing method may be changed depending on the material type of the seed adhesion layer 4 and the photosensitive resin layer 3. The conductor layer 6 remaining after polishing becomes an electrode for bonding with the semiconductor element 17.

[0038] (7) Formation of inorganic insulating film 5, an inorganic insulating film 7 is formed on the upper surfaces of the conductor layer 6 and the photosensitive resin layer 3, etc. The inorganic insulating film 7 may be made of a silicon oxide film (SiOx), a silicon nitride film (SiNx), SiC, SiOF, SiOC, etc. The thickness of the inorganic insulating film 7 is preferably 20 nm to 200 nm. In this embodiment, SiNx (thickness 50 nm) is used as the inorganic insulating film 7, and is formed by a plasma CVD method that can form a dense film at a relatively low temperature.

[0039] However, the inorganic insulating film 7 does not have to be an insulating film formed by plasma CVD such as the silicon oxide film (SiOx) or silicon nitride film (SiNx), and the type and manufacturing method are not limited as long as it is an inorganic insulating film.

[0040] (8) Formation of photosensitive resin layer Next, as shown in Fig. 6, a photosensitive resin layer 3 having a small diameter opening on its upper surface is formed by the same method as above. The thickness of the photosensitive resin layer 3 is set according to the thickness of the conductor layer to be formed in the small diameter opening, and in this embodiment, it is formed to be, for example, 2 µm. The shape of the small diameter opening in plan view is set from the viewpoint of connection with the conductor layer 6, and in this embodiment, an opening shape of, for example, φ11 µm is formed. This small diameter opening has the shape of a via portion connecting upper and lower layers of the multilayer wiring.

[0041] 6, by interposing the inorganic insulating film 7 at the interface between the photosensitive resin layers 3, 3, adhesion is improved compared to the case where the photosensitive resin layer 3 is directly formed on the photosensitive resin layer 3. Furthermore, by interposing the inorganic insulating film 7 between the photosensitive resin layer 3 and the conductor layer 6, adhesion is improved compared to the case where the conductor layer 6 is in direct contact with the photosensitive resin layer 3.

[0042] Further, as shown in FIG. 7, a photosensitive resin layer 3 having a large diameter opening overlapping the small diameter opening of the lower layer and a wiring pattern on the upper surface is formed by the same method as above. The thickness of the photosensitive resin layer 3 is set according to the thickness of the conductor layer to be formed in the large diameter opening, and is formed to be, for example, 2 μm in this embodiment. The shape of the large diameter opening in plan view is set from the viewpoint of the connectivity of the laminate, and is formed surrounding the outside of the small diameter opening of the lower layer. In this embodiment, the shape of the large diameter opening is, for example, φ25 μm. This large diameter opening becomes the wiring part of the multilayer wiring, and when multilayered, it becomes a receiving pad of the via, so-called a land part. In this embodiment, the via part for connecting between layers is formed together with the land part at the same time. As shown in the figure, the wiring part constituting the wiring pattern of the photosensitive resin layer 3 has an isosceles trapezoid shape with the lower base smaller than the upper base.

[0043] (9) Formation of inorganic insulating film 8, an inorganic insulating film 7' is formed on the photosensitive resin layer 3 and in the openings of the photosensitive resin layer 3. As with the inorganic insulating film 7, the inorganic insulating film 7' may be a silicon oxide film (SiOx), a silicon nitride film (SiNx), SiC, SiOF, SiOC, or the like. The thickness of the inorganic insulating film 7' is preferably 20 nm to 200 nm. In this embodiment, SiNx (thickness 50 nm) is used as the inorganic insulating film 7', and is formed by a plasma CVD method that can form a dense film at a relatively low temperature.

[0044] (10) Formation of openings in inorganic insulating film 9, the inorganic insulating film 7' covering the conductor layer 6 in the small opening of the photosensitive resin layer 3 is removed by, for example, a dry etching method in a vacuum. That is, an opening is formed in the inorganic insulating film 7' so as to open the bottom of the small opening of the photosensitive resin layer 3, and a via portion is formed by the conductor layer 6 formed inside the opening in a process described later.

[0045] (11) Formation of seed adhesion layer and seed layer Next, a seed adhesion layer 4 and a seed layer 5 are formed in a vacuum by the same method as above, and further, a conductor layer 6 is formed by electrolytic plating by the same method as in Fig. 2. In this embodiment, the seed adhesion layer 4 is formed of Ti: 50 nm, the seed layer 5 is formed of Cu: 300 nm, and the conductor layer 6 is formed of Cu: 6 µm. This state is shown in Fig. 10, but since the seed layer 5 and the conductor layer 6 are made of the same material, the seed layer 5 is omitted from the figure. The conductor layer 6 becomes the via portion and the wiring portion.

[0046] (12) Removal of the conductor layer and seed layer 11, unnecessary conductor layer 6 and seed layer 5 are removed by polishing using CMP (chemical mechanical polishing) or the like. At this time, a seed adhesion layer 4 is formed on the side wall of the photosensitive resin layer 3 coated with the inorganic insulating film 7. By forming the seed adhesion layer 4 as a continuous film on the side wall of the photosensitive resin layer 3 with the inorganic insulating film 7 interposed therebetween, the risk of disconnection between the via portion and the land portion due to thermal warping can be reduced.

[0047] (13) Removal of the seed adhesion layer and photosensitive resin layer 12, polishing is performed again by CMP (chemical mechanical polishing) or the like to remove unnecessary seed adhesion layer 4 and photosensitive resin layer 3 while leaving inorganic insulating film 7'. Then, the conductor layer 6 remaining after CMP or the like becomes the conductor portion of the via portion and wiring portion. In this embodiment, Cu: 2 μm of the conductor layer 6 of the photosensitive resin layer 3 and Cu: 300 nm of the seed layer 5 are removed by polishing. In this manner, an interlayer connection conductor layer in which the via portion and the land portion are integrated can be formed.

[0048] (14) Formation of inorganic insulating film Next, as shown in FIG. 13, an inorganic insulating film 7 is formed on the remaining inorganic insulating film 7'. The inorganic insulating film 7 can be a silicon oxide film (SiOx), a silicon nitride film (SiNx), SiC, SiOF, SiOC, or the like. The thickness of the inorganic insulating film 7 is preferably 20 nm to 200 nm. In this embodiment, SiNx (thickness 50 nm) is used as the inorganic insulating film 7, and it is formed by a plasma CVD method that can perform dense film formation at a relatively low temperature. As a result, the periphery of the conductor layer 6 is surrounded by the photosensitive resin layer 3, and further, the inorganic insulating film 7' is interposed between the photosensitive resin layer 3 below and to the sides of the conductor layer 6 and the conductor layer 6, and the inorganic insulating films 7, 7' are interposed between the photosensitive resin layer 3 above the conductor layer 6 and the conductor layer 6. Therefore, the second wiring layer made of the conductor layer 6 is covered with the inorganic insulating films 7, 7' from all directions, up, down, left, and right, and migration during a high-temperature and high-humidity test or the like is prevented.

[0049] (15) Formation of multi-layer wiring 6 to 13 are repeated to form a multilayer wiring in which two or more conductor layers 6 are laminated. That is, a first photosensitive resin layer 3 having a wiring pattern and an opening corresponding to a second wiring layer is formed. -1 (referred to as a first insulating resin layer) (FIGS. 6 and 7), a process of forming an inorganic insulating film 7' (referred to as a first inorganic insulating film) on the first insulating resin layer (FIG. 8), and a process of forming a first conductor layer 6 on the first inorganic insulating film according to the wiring pattern and the opening. -1 10 and 11), and a step of forming an inorganic insulating film 7 (referred to as a second inorganic insulating film) on the first conductive layer (FIG. 13).

[0050] Further, a second photosensitive resin layer 3 having a wiring pattern and an opening is formed on the second inorganic insulating film by the same method as described above. -2 (referred to as a second insulating resin layer), a process of forming an opening in the second inorganic insulating film by, for example, a dry etching method in a vacuum in accordance with the opening of the second insulating resin layer (FIG. 9), and a process of forming a second conductor layer 6 that is electrically connected to the first conductor layer through the opening of the second inorganic insulating film. -2(hereinafter referred to as a second conductor layer) is formed. This results in the configuration shown in FIG.

[0051] In this embodiment, as shown in Fig. 14, a second wiring layer is formed by stacking two conductor layers 6 each having an isosceles trapezoid shape with a lower base smaller than an upper base. To electrically connect the stacked second wiring layers, a via portion 3a is formed using an opening in the photosensitive resin layer 3 adjacent to the conductor layer 6, and an interlayer connection conductor layer is formed in the via portion 3a. By forming an opening in the inorganic insulating films 7, 7' in the via portion 3a, the second wiring layers can be electrically connected to each other. Furthermore, as shown in FIG. 14, the upper and lower surfaces of each photosensitive resin layer 3 are covered with inorganic insulating films 7, 7'.

[0052] (16) Formation of photosensitive resin layer Next, as shown in FIG. 15, a photosensitive resin layer 3 is formed on the upper surface.

[0053] (17) Removal of inorganic insulating film and formation of resist pattern 16, the inorganic insulating film 7 in the openings of the photosensitive resin layer 3 is removed by dry etching in the same manner as in Fig. 9. Thereafter, a seed adhesion layer 4 and a seed layer 5 are formed in a vacuum in the same manner as above, and a resist pattern 8 is further formed.

[0054] (18) Formation of electrodes Next, as shown in FIG. 17, a conductor layer (for solder connection) 9 is formed by electrolytic plating. The conductor layer (for solder connection) 9 becomes an electrode for bonding to the FC-BGA substrate 14. It is desirable that the thickness of the electrolytic copper plating is 1 μm or more from the viewpoint of solder bonding, and 30 μm or less from the viewpoint of productivity. In this embodiment, Cu: 10 μm is formed in the openings of the photosensitive resin layer 3, and Cu: 8 μm is formed on the upper part of the photosensitive resin layer 3. Thereafter, the resist pattern 8 is removed.

[0055] (19) Removal of seed adhesion layer and seed layer Next, as shown in FIG. 18, unnecessary seed adhesion layer 4 and seed layer 5 are removed by etching.

[0056] (20) Formation of solder resist layer Next, as shown in Fig. 19, a solder resist layer 10 is formed. The solder resist layer 10 is exposed to light and developed so as to cover the photosensitive resin layer 3, and is formed so as to have an opening through which the conductor layer (for solder connection) 9 is exposed. Note that, as the material for the solder resist layer 10, for example, an insulating resin such as an epoxy resin or an acrylic resin can be used. In this embodiment, the solder resist layer 10 is formed using a photosensitive epoxy resin containing a filler.

[0057] Furthermore, a surface treatment layer 11 is provided to prevent oxidation of the surface of the conductor layer (for solder connection) 9 and to improve the wettability of the solder bump. In the embodiment of the present invention, an electroless Ni / Pd / Au plating film is formed as the surface treatment layer 11. Note that an OSP (Organic Solderability Preservative, surface treatment with a water-soluble preflux) film may be formed on the surface treatment layer 11. Alternatively, electroless tin plating, electroless Ni / Au plating, etc. may be appropriately selected depending on the application.

[0058] (21) Formation of solder joints 20, a solder material is placed on the surface treatment layer 11, and then melted, cooled, and fixed to form a solder joint 12 on the conductor layer 9 via the surface treatment layer 11. This completes the second wiring board 13 on the support body formed on the support body 1.

[0059] (22) Bonding of wiring board and FC-BGA board 21, after bonding the second wiring board 13 on the support and the FC-BGA board 14, the bonded portion is sealed with an underfill layer (sealing resin 23). For example, the underfill layer is made of a resin containing one or more of epoxy resin, urethane resin, silicone resin, polyester resin, oxetane resin, and maleimide resin, and a filler such as silica, titanium oxide, aluminum oxide, magnesium oxide, or zinc oxide. The underfill layer is formed by filling with liquid resin.

[0060] (23) Peeling of support 22, laser light 15 is applied to the peeling layer 2 to make it peelable, and then the support 1 is peeled off. That is, the peeling layer 2 formed at the interface with the support 1 is irradiated with laser light 15 from the rear surface of the support 1, that is, from the surface of the support 1 opposite to the FC-BGA substrate 14, to make it peelable, which makes it possible to remove the support 1.

[0061] (24) Completion of the wiring board Next, as shown in FIG. 23, after removing the support 1, the release layer 2, the seed adhesion layer 4 and the seed layer 5 are removed to obtain the wiring board 16.

[0062] (25) Mounting of semiconductor elements Thereafter, a semiconductor element 17 is mounted to complete the semiconductor device 18 shown in Fig. 1. At this time, prior to mounting the semiconductor element 17, a surface treatment such as electroless Ni / Pd / Au plating, OSP, electroless tin plating, or electroless Ni / Au plating may be performed on the conductor layer 6 exposed on the surface to prevent oxidation and improve the wettability of the solder bumps. In this manner, the semiconductor device 18 is completed.

[0063] <Confirmation of action and effect> Next, the wiring board 16 manufactured as described above will be compared with a comparative example to explain the comparative effect.

[0064] The inventors subjected wiring board 16 to a high-temperature, high-humidity bias test for 96 hours at a temperature of 130°C, a humidity of 85%, and an applied voltage of 3.3V as an example and a comparative example, in which silicon nitride was used as inorganic insulating films 7 and 7' in the configuration of wiring board 16, and a wiring board having the same configuration as wiring board 16 except that inorganic insulating films 7 and 7' were not provided. As a result, migration occurred in all of the comparative examples, but migration did not occur in all of the examples, and no conduction failure occurred. This confirmed the effect of migration suppression by inorganic insulating films 7 and 7'.

[0065] According to this embodiment, in a second wiring board in which a fine wiring layer is formed on a support substrate and mounted on an FC-BGA substrate, even if the substrate warps when heated, by surrounding the wiring portion with a seed adhesion layer or an inorganic insulating film, cracks in the photosensitive resin layer can be suppressed and wiring breaks can be suppressed. Furthermore, peeling of the photosensitive resin can be suppressed, thereby improving the reliability of the second wiring board. Furthermore, by covering the entire periphery of the wiring with an inorganic insulating film, it is possible to suppress the diffusion of the wiring material into the insulating resin, which contributes to further improving the reliability of the wiring board.

[0066] The present invention can be used in a semiconductor device having a wiring board equipped with an interposer or the like interposed between a main board and an IC chip. [Explanation of symbols]

[0067] 1 Support 2. Peel layer 3 Photosensitive resin layer (insulating resin layer) 4 Seed adhesion layer 5 Seed layer 6 Conductor Layer 7, 7´ Inorganic insulating film 8. Resist Pattern 9 Conductor layer (solder joint) 10 Solder resist layer 11 Surface treatment layer 12 Solder joints 13 Wiring board on support 14 FC-BGA board 15 Laser light 16 Wiring board 17 Semiconductor elements 18 Semiconductor Devices 19 Chip connection terminal

Claims

1. A method for manufacturing a wiring board comprising: a first wiring board on which a first wiring layer is formed; and a second wiring board on which two or more second wiring layers finer than the first wiring layer are formed, the first wiring board being bonded to one surface of the second wiring board, and a semiconductor element being mountable on the other surface of the second wiring board, the method comprising the steps of: The step of manufacturing the second wiring substrate includes: forming a first insulating resin layer having a wiring pattern and an opening corresponding to the second wiring layer; forming a first inorganic insulating film on the first insulating resin layer; forming a first conductor layer on the first inorganic insulating film in accordance with the wiring pattern and the opening; forming a second inorganic insulating film on the first conductor layer; 4. A method for manufacturing a wiring board comprising the steps of:

2. forming a second insulating resin layer having a wiring pattern and an opening on the second inorganic insulating film; forming an opening in the second inorganic insulating film in accordance with the opening of the second insulating resin layer; forming a second conductor layer that is electrically connected to the first conductor layer through the opening in the second inorganic insulating film; 2. The method for manufacturing a wiring board according to claim 1.

3. At least one of the first inorganic insulating film and the second inorganic insulating film is formed by a plasma CVD method using silicon nitride as a material.

3. The method for manufacturing a wiring board according to claim 2.

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