Product-sum calculation circuit, control method for product-sum calculation circuit, and calculation system

Abstract

A product-sum operation circuit capable of making product-sum operations more efficient is provided. [Solution] A multiply-and-accumulate circuit includes a plurality of multiplier circuits and an adder circuit that adds up the multiplication results of each of the plurality of multiplier circuits and outputs the addition result, each of the plurality of multiplier circuits includes a capacitance array including a plurality of capacitive elements, and an inverting amplifier connected to the capacitance array in a switchable manner, when multiplication is performed in the multiplier circuit, a first side of the capacitance array is connected to the inverting input terminal of the inverting amplifier, and a second side opposite the first side of the capacitance array is connected to the output terminal of the inverting amplifier, and a predetermined ground voltage is supplied to the non-inverting input terminal of the inverting amplifier, and when charge transfer of the multiplication result of the multiplication circuit is performed to the adder circuit, the first side of the capacitance array is connected to the non-inverting input terminal of the inverting amplifier, and the second side is connected to the inverting input terminal and the output terminal.

Description

[Technical field]

[0001] The present embodiment relates to a product-sum calculation circuit, a control method for the product-sum calculation circuit, and a calculation system. [Background technology]

[0002] A semiconductor integrated circuit may execute a product-sum operation in which a plurality of results obtained by multiplying a plurality of input values ​​by a weight are added together, and a technology for performing the product-sum operation has been developed (see Patent Document 1). The product-sum operation is an operation in which a weight is multiplied by each of a plurality of input values, and the multiplication results are added together. For example, the product-sum operation is used in recognition processing of images, voices, etc. using neural networks, etc., and there is a demand for improving the efficiency of the product-sum operation. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2020-160887 A Summary of the Invention [Problem to be solved by the invention]

[0004] An object of one embodiment is to provide a product-sum operation circuit capable of improving the efficiency of product-sum operation. [Means for solving the problem]

[0005] One aspect of the present invention for solving the above problem is a multiply-accumulate circuit, a plurality of multiplication circuits; and an addition circuit that adds up the multiplication results of the plurality of multiplication circuits and outputs the addition result; Each of the plurality of multiplication circuits comprises: a capacitance array including a plurality of capacitance elements; an inverting amplifier connected to the capacitance array in a switchable manner; Including, When multiplication is performed in the multiplication circuit, a first side of the capacitance array is connected to an inverting input terminal of the inverting amplifier, and a second side of the capacitance array opposite to the first side is connected to an output terminal of the inverting amplifier; A predetermined ground voltage is supplied to the non-inverting input terminal of the inverting amplifier, When the multiplication result of the multiplication circuit is transferred to the addition circuit, The first side of the capacitance array is connected to the non-inverting input terminal of the inverting amplifier, and the second side is connected to the inverting input terminal and the output terminal. Effect of the Invention

[0006] According to the present invention, it is possible to provide a product-sum operation circuit capable of improving the efficiency of product-sum operation. [Brief description of the drawings]

[0007] [Figure 1A] FIG. 2 is a diagram showing an example of the configuration of a product-sum calculation circuit 10 according to the embodiment. [Figure 1B] 1 is a diagram showing an example of the configuration of a calculation system including a plurality of product-sum calculation circuits 10 according to an embodiment. [Diagram 2] FIG. 2 is a diagram showing an example of a schematic configuration of a multiplication circuit 101 according to the embodiment. [Diagram 3] 4 is a diagram for explaining an example of multiplication processing in a multiplication circuit 101 according to the embodiment. [Figure 4] 5 is a diagram for explaining another example of the multiplication process in the multiplication circuit 101 according to the embodiment. FIG. [Figure 5A] 4 is a diagram for explaining a charge transfer process from a multiplication circuit 101A to an addition circuit 102 according to the embodiment. [Figure 5B] 5A and 5B are diagrams for explaining switching of a connection method of an amplifier according to the embodiment. [Figure 6] FIG. 2 is a diagram showing an example of a differentiating configuration of a product-sum operation circuit according to the embodiment. [Figure 7] 1 is a circuit diagram for explaining a method of controlling a differentiation configuration of a product-sum operation circuit according to an embodiment. [Figure 8]5A to 5C are diagrams for explaining an example of a method for generating a differential capacitance according to the embodiment. [Figure 9] FIG. 4 is a diagram showing an example of a timing chart for controlling the operation of a product-sum calculation circuit according to the embodiment. [Figure 10] FIG. 13 is a diagram showing another example of a timing chart for controlling the operation of the product-sum calculation circuit according to the embodiment. [Figure 11] 6 is a flowchart showing an example of operation control of a product-sum calculation circuit according to the embodiment. [Figure 12] FIG. 13 is a diagram showing an example of a schematic configuration of a multiplication circuit 101 according to a modified example of the embodiment. [Figure 13] 10 is a flowchart showing an example of operation control of a product-sum calculation circuit according to a modified example of the embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Hereinafter, the embodiments will be described in detail with reference to the accompanying drawings. Note that the following embodiments do not limit the invention according to the claims, and not all combinations of features described in the embodiments are essential to the invention. Two or more features among the multiple features described in the embodiments may be arbitrarily combined. In addition, the same reference numbers are used for the same or similar configurations, and duplicated descriptions are omitted.

[0009] Hereinafter, a computing system according to an embodiment will be described in detail with reference to the accompanying drawings. Note that the present invention is not limited to these embodiments.

[0010] The computing system according to the present embodiment can be used to execute a part of the processing of a neural network, such as an AI (artificial intelligence) accelerator. In order to learn a task or perform inference, the AI ​​accelerator executes a multiply-and-accumulate operation in which a multi-bit input is multiplied by a multi-bit weight and the result of the multiplication is added. The computing system is required to perform this operation in parallel, quickly and efficiently. For example, the computing system performs a multiply-and-accumulate operation in parallel for multiple neurons in a certain layer in the neural network (parallel operation). The parallel operation includes an operation in which an input including multiple bits is multiplied by a weight including multiple bits with any bit precision.

[0011] This parallel operation can be implemented in hardware by an in-memory semiconductor integrated circuit, which is characterized by integrating memory circuits and arithmetic circuits or arranging them physically close to each other. In an in-memory semiconductor integrated circuit, the weights for multiplication are set fixedly, not dynamically. In-memory configurations include a digital configuration, an analog-current configuration, and an analog-charge configuration.

[0012] The digital configuration performs calculations in memory by performing operations on input bits according to weight bits using bit-wise logic circuits arranged in memory, while the analog current configuration applies voltages to each row of an array of weight-programmed resistive change elements and adds up the currents using Kirchhoff's law.

[0013] On the other hand, the analog charge method performs logical AND operations on multiple input bits and multiple weight bits in parallel on a bit-by-bit basis, and stores a voltage corresponding to the result of the operation on multiple bits in multiple capacitive elements of the capacitance array.Then, the charges of the multiple capacitive elements in the capacitance array are sequentially read out and converted to analog to generate a digital signal, while the digital signal is bit-shifted and added repeatedly, thereby performing addition of the digital signal.

[0014] The analog-charge type configuration is superior to the digital type configuration in that it has a faster calculation speed when calculating with a medium bit accuracy.The analog-charge type configuration is superior to the analog-current type configuration in that it is easier to reduce the effects of variations between elements.

[0015] However, in the analog-charge method, the number of bit shift operations proportional to the number of bits of at least one of the input and weights is required to add signals, so the efficiency of parallel operations tends to decrease as the number of bits of at least one of the input and weights increases, and the processing time of parallel operations tends to increase depending on the bit precision of at least one of the input and weights.

[0016] In this embodiment, a more efficient analog charge type circuit configuration is proposed. FIG. 1A shows an example of a product-sum operation circuit corresponding to this embodiment. The product-sum operation circuit 10 shown in FIG. 1 is configured by connecting an adder circuit 102 to multiplier circuits 101A and 101B. The operation of the product-sum operation circuit 10 is controlled by a control circuit 103. The multiplier circuit 101A receives inputs A and B in serial order, performs a multiplication operation of A×B, and outputs a multiplication result A*B to the adder circuit 102. The multiplier circuit 101B also receives inputs C and D in serial order, performs a multiplication operation of C×D, and outputs a multiplication result C*D to the adder circuit 102. The adder circuit 102 adds the inputs A*B and C*D, and outputs the addition result A*B+C*D. Although FIG. 1 shows only two multiplier circuits 101, 101A and 101B, more multiplier circuits 101 can be connected in parallel. The control circuit 103 provides signals for controlling the switches of the multiplication circuit 101 and the addition circuit 102, signals and charges representing the multiplication value, control voltages, and the like, and controls the operations of the multiplication circuit 101 and the addition circuit 102. An arithmetic system can be constructed by arranging a plurality of product-sum calculation circuits 10 shown in FIG. 1A.

[0017] Fig. 1B is a diagram showing an example of the configuration of a calculation system 1 configured by arranging a plurality of product-sum calculation circuits 10. In Fig. 1B, the calculation system 1 includes a multiplication circuit 101, an addition circuit 102, a control circuit 103, a memory 104, and a processing circuit 105. The multiplication circuit 101, the addition circuit 102, and the control circuit 103 are the same as those described in Fig. 1A. In Fig. 1B, the solid lines connecting each circuit block represent data signals, and the dotted lines supplied from the control circuit 103 to each circuit block represent control signals. The memory 104 is a storage circuit that holds various data for arithmetic processing. The held data may be digital data or analog data. The output from the adder circuit 102 may be stored in the memory 104 before being provided to the next stage, or may be directly input to the product-sum calculation circuit 10 of the next stage.

[0018] The processing circuit 105 is a circuit that executes a predetermined process based on the results of the calculations executed in the upstream calculation circuit. Examples of the processes that can be executed here include nonlinear processes such as processes using a ReLU (Rectified Linear Unit) function, a Softmax function, a Sigmoid function, and a Tanh function, which are used in deep learning. In addition to nonlinear processes, processes such as maxpooling and average-pooling can be executed. The output from the processing circuit 105 may be digital or analog, but among the above, the ReLU function, maxpooling, and averagepooling can be output in analog form.

[0019] 1B does not show an example in which the processing result in the processing circuit 105 is input to the product-sum calculation circuit 10, but the embodiment of the invention is not limited to this, and the processing result in the processing circuit 105 can be input to the product-sum calculation circuit 10 to perform calculation. Also, although data is input to the processing circuit 105 from a memory, the addition result in the adder circuit 102 may be directly input thereto. Also, the processing in the processing circuit 105 is executed in response to a control signal supplied from the control circuit 103.

[0020] In FIG. 1B, 10A and 10B surrounded by dotted lines and 10C surrounded by a dashed line correspond to the sum-of-products circuit 10 described in FIG. 1A. The sum-of-products circuits 10A and 10C are circuits that add the multiplication results of two-stage multiplication circuits 101 in an adder circuit 102, and the sum-of-products circuit 10B is a circuit that adds the multiplication results of three-stage multiplication circuits 101 in an adder circuit 102. Here, the multiplication process in the multiplication circuits 101 in the sum-of-products circuits 10A and 10B can be executed as a multiplication process of a digital value supplied from a memory 104. On the other hand, an analog value supplied from the adder circuit 102 of the sum-of-products circuit 10C is input to a part of the multiplication circuit in the sum-of-products circuit 10B, and a multiplication process using an analog value can be executed. In addition to a direct input from the adder circuit 102, a digital value acquired from the memory 104 can be converted into an analog charge and then input. An analog output from a processing circuit 105 may also be input. In FIG. 1B, the number of stages in the multiplication circuit 101 is limited to three, but it may be four or more.

[0021] FIG. 2 is a diagram showing an example of a schematic configuration of the multiplication circuit 101. FIG. 2 shows a case where the multiplication circuit 101 is configured as a 3-bit capacitance array. The configuration in FIG. 2 is merely an example, and the multiplication circuit 101 may be configured as a 4-bit, 5-bit, or n-bit capacitance array. In that case, the capacitance of the capacitance element (capacitor) is set to be a power of 2. For example, in the case of 4 (n=4) bits, a capacitor with a capacitance of 8C is further added, and capacitance elements corresponding to 1 bit, 2 bits, 3 bits, and 4 bits are given capacitances of 1C, 2C, 4C, and 8C, respectively. In the case of 5 (n=5) bits, a capacitor with a capacitance of 16C is further added, and capacitance elements corresponding to 1 bit to 5 bits are given capacitances of 1C, 2C, 4C, 8C, and 16C, respectively.

[0022] When the multiplication circuit is configured as a 3-bit capacitance array, the capacitance array 201 is composed of four capacitance elements (capacitors) with capacitances of 4C, 2C, 1C, and 1C. Here, C is a reference capacitance (unit: F). C may be the smallest unit capacitance in the capacitance array, or any other capacitance. The bottommost 1C is a dummy capacitance, which is short-circuited in the multiplication process. Even if the number of bits of the capacitance array 201 changes, the bottommost dummy capacitance is always provided. An input is given to the capacitance array 201 as a charge Q. Also, Cst1 and Cst2 represent the parasitic capacitances at both ends of the capacitance array 201. In this embodiment, the side of the capacitance array 201 to which the parasitic capacitance Cst1 is connected may be referred to as the input side or the first side, and the side to which the parasitic capacitance Cst2 is connected may be referred to as the output side or the second side. The parasitic capacitance is set in consideration of, for example, wiring and switch capacitance. However, the effect of this parasitic capacitance can be eliminated by using the inverting amplifier 202.

[0023] An electric charge Q1 is input to the inverting input terminal (-) of the inverting amplifier 202. The inverting input terminal is connected in parallel to the input side of the capacitance array 201 and the parasitic capacitance Cst1. The non-inverting input terminal (+) of the inverting amplifier 202 is grounded to a predetermined ground voltage. In this embodiment, the ground voltage is exemplarily set to 0.6 V, so that 0.6 V is input to the non-inverting input terminal. The output side of the inverting amplifier 202 is connected in parallel to the output side of the capacitance array 201 and the parasitic capacitance Cst2.

[0024] The gain of the inverting amplifier 202 can be secured to be sufficiently large, for example, 1000 times. When the potential difference between the potential of the inverting input terminal and the potential of the non-inverting input terminal (ground potential) disappears, a virtual short-circuit state is established between the inverting input terminal and the non-inverting input terminal. In the virtual short-circuit state, the terminal voltage of the parasitic capacitance Cst1 is also defined as the potential difference between the potential of the inverting input terminal of the inverting amplifier 202 and the ground potential, so it is also 0, and the parasitic capacitance Cst1 can be ignored regardless of its magnitude. Therefore, the input charge Q1 does not flow into Cst1, but is supplied to the capacitance array 201. In addition, the parasitic capacitance Cst2 on the output side is connected to the output of the inverting amplifier 202, and the charge flowing into the parasitic capacitance Cst2 is provided from the output of the inverting amplifier 202. Therefore, the charge flowing into the parasitic capacitance Cst2 does not affect the amount of charge stored in the capacitance array 201.

[0025] Next, referring to FIG. 3, the multiplication process performed in the multiplication circuit 101 of this embodiment will be described. FIG. 3 is a conceptual diagram for explaining the multiplication process in the multiplication circuit in a simplified manner, and mainly shows the operation on the capacitance array 201. FIG. 3(A) shows a state in which an electric charge Q is given to the capacitance array 201 as the input A or input C. The input here is an analog signal. Note that the capacitance array 201 is reset before the electric charge Q is input. The reset can be realized by setting both ends of each capacitor to 0.6V. When the electric charge Q is input, each capacitor of the capacitance array 201 holds a charge according to its respective capacitance. That is, a capacitor with a capacitance of 4C holds 4Q / 8, a capacitor with a capacitance of 2C holds 2Q / 8, and a capacitor with a capacitance of 1C holds 1Q / 8. The potential difference V of the capacitance array 201 at this time is Q / 8C.

[0026] Next, input B is input to the multiplication circuit 101A. Input B is a 3-bit digital signal. Input B has seven values, for example, 000, 001, 010, 011, 100, 101, and 111. The respective values ​​mean 0, 1 / 8, 2 / 8, 3 / 8, 4 / 8, 5 / 8, 6 / 8, and 7 / 8. For 8 / 8 (=1), the multiplication result is the same value as input A, so this multiplication process can be skipped. Each bit corresponds to capacitances 4C, 2C, and 1C from the most significant bit, respectively. In the multiplication process, the dummy capacitance is short-circuited as described above. Similarly, input D of the multiplication circuit 101B can take one of seven values. The calculation using input B will be described below.

[0027] In the multiplication process of this embodiment, bit positions having 0 in input B are shorted. For example, if input B is 101, the capacitor of capacitance 2C is shorted. This causes the charge held in the capacitor of capacitance 2C to be discharged. Meanwhile, the charges held in 4C and 1C are maintained as they are. The dummy capacitance is also shorted. FIG. 3(B) shows the state after multiplication by B. The total charge remaining in the capacitance array 201 becomes 5 / 8Q, and the multiplication result A*B is obtained. At this point, the charge may be immediately discharged and the multiplication result may be transferred to another capacitance array.

[0028] Fig. 3(C) shows a state in which, in the state of Fig. 3(B), all the capacitors in the capacitance array are reconnected and set to the same potential, thereby redistributing the charge to each element in a ratio of a power of 2. As a result, the capacitor with capacitance 2C and the dummy capacitance capacitors again hold charge, and each capacitor holds charges of 5Q / 16, 5Q / 32, 5Q / 64, and 5Q / 64. The potential difference V across the capacitance array 201 at this time is 5Q / 64C. This allows subsequent multiplication (for example, A x B x E based on a new input E) to be performed.

[0029] In Fig. 3, we have explained the case where analog signals are input as input A and input C. In contrast, Fig. 4 explains the operation when input A and input C are input as digital signals. In Fig. 4(A), the capacitor corresponding to the digit with a value of 1 among the three bits for input A or input C is charged to a specified value, and the capacitor corresponding to the digit with a value of 0 is shorted and discharged. In Fig. 4, the input voltage is V i , ground voltage V g The dummy capacitance is also shorted. In Figure 4(A), the input value is set to 011, so the capacitors with capacitances of 2C and 1C are set to the specified value V1 (=V i -V g ), and 4C and the dummy capacitance of 1C capacitor are short-circuited. As a result, the total charge stored in the capacitance array 201 is 2C×V1+1C×V1=3CV1. In this embodiment, as an example, V i to 0.9V, V g can be set to 0.6V, in which case V1 will be 0.3V.

[0030] Next, in Fig. 4(B), all the capacitors in the capacitance array 201 are reconnected and set to the same potential. As a result, the charge held in Fig. 4(A) is redistributed to each capacitor in a ratio of powers of 2. In the case of digital signals, charge redistribution must always be performed before multiplication processing. As a result, when 3CV1 is distributed to the capacitors with capacitances 4C, 2C, C, and C, the respective charges become 12CV1 / 8, 6CV1 / 8, 3CV1 / 8, and 3CV1 / 8.

[0031] Next, FIG. 4(C) shows the state after input B has been multiplied to FIG. 4(B). Here, input B is 101. The dummy capacitance is shorted as before, so the capacitor with capacitance 2C is shorted, the total charge remaining in capacitance array 201 becomes 15CV1 / 8, and the multiplication result A*B is obtained. At this point, the charge can be immediately discharged and the multiplication result can be transferred to another capacitance array. The charge can also be redistributed to perform additional multiplications. A similar multiplication can be performed on input D.

[0032] Next, referring to FIG. 5A, the charge transfer process from the multiplication circuit 101A to the addition circuit 102 will be described. The multiplication circuit 101A is the same as the multiplication circuit shown in FIG. 2. The addition circuit 102 can be configured in the same manner as the multiplication circuit shown in FIG. 2. Appropriate switches can be arranged in the charge transfer path, but they are omitted in FIG. 5A for simplicity of explanation. It is not necessary to adopt the configuration of a multiplication circuit as the addition circuit 102, but by using a multiplication circuit, it is possible to deal with cases where further multiplication is performed. When transferring charges from the multiplication circuit 101A to the addition circuit 102, the inverting amplifier 202 of the capacitance array 201 of the multiplication circuit 101A is replaced by an equal-times amplifier with a gain of 1 by switching the connection from a state in which the gain is sufficiently large. As a result, the transfer of charges from the multiplication circuit 101A to the addition circuit 102 is performed from the input side of the capacitance array 201. Since the potential difference of the capacitance array 201 connected to the inverting amplifier 202 is forcibly set to 0, the charge held in the capacitance array 201 is discharged to the addition circuit 102 side. At this time, the parasitic capacitance Cst1 of the sending multiplication circuit 101A is incorporated into the parasitic capacitance of the adder circuit 102, but the influence of this, including the parasitic capacitance Cst3 of the adder circuit 102 itself, can be eliminated by virtually short-circuiting the inverting amplifier 502 connected to the input side of the capacitance array 501 of the receiving adder circuit 102.

[0033] 5A, only one multiplication circuit 101A is shown on the input side of the addition circuit 102, but by connecting multiple multiplication circuits 101 in parallel, it is possible to add up the transferred charges from each multiplication circuit 101. In this case, the charge transfer timing from each multiplication circuit 101 may be simultaneous or different.

[0034] The charge Q2 transferred to the adder circuit 102 is held in the capacitance array 501 of the adder circuit 102. The capacitance array 501 can hold the charges transferred from a plurality of multiplication circuits 101. Furthermore, the charges held in the capacitance array 501 can be further subjected to multiplication processing in the same manner as the above-mentioned multiplication circuit 101. Furthermore, if multiplication processing is not performed, at least one predetermined capacitive element may be disposed in place of the capacitance array 501.

[0035] Also, instead of transferring the charge of the multiplication result in the multiplication circuit 101, multiplication and charge transfer may be performed simultaneously. For example, in the example shown in Fig. 4 above, the state of Fig. 4(B) is further multiplied by a value of 101 to form the state of Fig. 4(C). Here, instead of multiplying by the value of 101, the charges held in the 4C capacitor of the 3rd bit and the 1C capacitor of the 1st bit are transferred, thereby obtaining the same effect as performing multiplication simultaneously with transfer.

[0036] 5A, in order to change the inverting amplifier 202 to a unity amplifier, the inverting input terminal (-) and the output side of the inverting amplifier 202 are connected to apply 100% feedback, and the non-inverting input terminal (+) is connected to the capacitance array 201. The connection switching of the inverting amplifier 202 will be specifically described with reference to FIG. 5B. The connection switching of the inverting amplifier 202 is executed by a control signal from the control circuit 103.

[0037] Fig. 5B(A) shows an example of a switch configuration around the inverting amplifier 202. In Fig. 5B(A), all the switches are open. For the sake of explanation, in Fig. 5B, a parasitic capacitance Cst1 is placed on the input side of the inverting amplifier 202, and a parasitic capacitance Cst2 is placed on the output side, so that the positional relationship with the capacitance array can be understood.

[0038] In the configuration of Fig. 5B(A), by turning on / off the switch with a control signal from the control circuit 103, it is possible to switch between a connection configuration in which the input side is virtually short-circuited as shown in Fig. 2 and a connection configuration for operating as a 1x amplifier as shown in Fig. 5B. Fig. 5B(B) shows a connection configuration with a virtual short circuit.

[0039] 5B(B), the part that is enabled as a connection by switching on is indicated by a solid line, and the part that is disabled as a connection is indicated by a dotted line. In this connection example, the input side of the capacitance array 201 in which the parasitic capacitance Cst1 is arranged is connected to the inverting input terminal of the inverting amplifier 202, and the non-inverting input terminal is grounded. The output side of the capacitance array 201 in which the parasitic capacitance Cst2 is arranged is connected to the output terminal of the inverting amplifier 202, and the connection between the output terminal and the inverting output terminal of the inverting amplifier 202 is cut off by the switch.

[0040] 5B(C), a part that is enabled as a connection by switching on is indicated by a solid line, and a part that is disabled as a connection is indicated by a dotted line. In this connection example, the output side of the capacitance array 201 in which the parasitic capacitance Cst2 is arranged is connected to the inverting input terminal of the inverting amplifier 202, and is further connected to the output terminal of the inverting amplifier 202. The input side of the capacitance array 201 in which the parasitic capacitance Cst1 is arranged is connected to the non-inverting input terminal of the inverting amplifier 202.

[0041] By using the inverting amplifier 202 in the above manner, the connection relationship between the inverting amplifier 202 and the capacitor array 201 can be switched depending on the processing status in the multiplication circuit 101 .

[0042] The product-sum calculation circuit of this embodiment can also be configured by differentiating the circuit as shown in FIG. 6. In the differential configuration, a first product-sum calculation circuit for positive phase and a second product-sum calculation circuit for negative phase are combined. FIG. 6 shows an example of a differential configuration of a product-sum calculation circuit. The multiplication circuit 101A is configured with a positive phase circuit 101A+ and a negative phase circuit 101A-, and the addition circuit 102 is configured with a positive phase circuit 102+ and a negative phase circuit 102-. The first product-sum calculation circuit is configured with a positive phase multiplication circuit 101A+ and a positive phase addition circuit 102+, and the second product-sum calculation circuit is configured with a negative phase multiplication circuit 101A- and a negative phase addition circuit 102-.

[0043] The parasitic capacitances Cst1 and Cst2 of the positive-phase multiplier circuit 101A+ and Cst5 and Cst6 of the negative-phase multiplier circuit 101A- should ideally match, but may differ. Similarly, the parasitic capacitances Cst3 and Cst4 of the positive-phase adder circuit 102+ and Cst7 and Cst8 of the negative-phase adder circuit 102- should ideally match, but may differ. Even if the parasitic capacitance values ​​do not match, there is no problem because each parasitic capacitance can be ignored by virtual shorting of the inverting amplifiers 202+, 202-, 502+, and 502-. Q2-(-Q2)=2Q2 is obtained as the output, and the in-phase component is canceled at this time, so the effects of disturbance noise and DC offset can be reduced.

[0044] Next, a method for controlling the multiplication circuit 101 will be described with reference to FIG. 7. FIG. 7 shows a circuit configuration in which the multiplication circuit is configured as a 3-bit capacitance array. In FIG. 7, the capacitance array 201 has a capacitance array 201+ for a positive-phase circuit and a capacitance array 201- for a negative-phase circuit. In addition, a configuration is shown in which two capacitors with a capacitance of 1C are generated as differential capacitance. Here, the differential capacitance refers to a combination of a capacitor with a small capacitance and a capacitor with a large capacitance. When configuring a product-sum operation circuit corresponding to this embodiment, since the minimum capacitance of the capacitor is determined by the circuit specifications, it is effective to configure a capacitance element as a differential capacitance when a capacitance element with a capacitance below the minimum capacitance cannot be created by itself.

[0045] In Fig. 7, for example, a capacitor with a differential capacitance of 1C can be created by arranging two capacitors with capacitances of 3C and 2C in parallel. Here, the differential capacitance is generated by combining capacitors with capacitances of 3C and 2C, but the ratio of the combined capacitances varies depending on the size of the smallest unit capacitance.

[0046] In Figure 7, the capacitor C1a+ and dummy capacitance Cda+ on the positive phase circuit side have a capacitance of 3C, and the capacitor C1b+ and dummy capacitance Cdb+ have a capacitance of 2C. One end of the capacitor C1b+ and the dummy capacitance Cdb+ is connected to COMP on the negative phase circuit side. Similarly, on the negative phase circuit side, the capacitor C1a- and dummy capacitance Cda- have a capacitance of 3C, and the capacitor C1b- and dummy capacitance Cdb- have a capacitance of 2C. One end of the capacitor C1b- and dummy capacitance Cdb- are connected to COMP on the positive phase circuit side.

[0047] By using such a differential capacitance, not only can the capacitance of the first bit capacitive element and the dummy capacitance be made smaller, but also the total capacitance and the capacitance of the capacitive element with the maximum capacitance can be made smaller. For example, consider the case where a 4-bit capacitive array is configured with a capacitance of 1C due to the differential capacitance between 2C and 3C (case 1) and a capacitance of 2C (case 2). The capacitance of the first bit capacitive element is 5C and 2C, which is smaller in case 2, but from the second bit to the fourth bit, the difference is widening, such as 2C and 4C, 4C and 8C, and 8C and 16C. In case 1, even for a 4-bit capacitive array, the total capacitance is 24C including the dummy capacitance, but in case 2, the total capacitance is 32C, so it is inevitable that the capacitance will be larger than when a differential capacitance is used. Furthermore, if the number of bits in the capacitive array is further increased, this difference will be further increased. By using a differential capacitance in this way, the mounting area of ​​the capacitive array can be reduced.

[0048] In FIG. 7, the capacitors C4+, C2+, C1a+, C1b+, Cda+, and Cdb+ constituting the capacitance array 201+ are supplied with electric charges via INP on the input side. The capacitors C4-, C2-, C1a-, C1b-, Cda-, and Cdb- constituting the capacitance array 201- are supplied with electric charges via INN on the input side. INP and INN are in a positive phase while INN is in a reverse phase. In addition, the input terminal is configured so that a VRC input for resetting is input when the switch is ON. In this embodiment, VRC can be set to 0.6V, which allows each capacitor of the capacitance array 201 to be reset. VRP (0.9V), VRC (0.6V), and VRN (0.3V) can be input to the terminals of the capacitance array 201+ and the capacitance array 201- opposite to the input side by switching with a switch. COMP is a wiring that is connected to each capacitor element by switching ON during charge redistribution. These switches can hold charge in the capacitors, create differential capacitance, reset, and redistribute charge.

[0049] In the configuration shown in FIG. 7, a control circuit 103 supplies the voltages at VRP, VRC, and VRN, the voltage supply and charge supply to INP and INN, and control signals for switching each switch on / off.

[0050] The capacitance array 201 and capacitance array 501 corresponding to this embodiment are configured by connecting multiple capacitance elements in parallel. The minimum capacitance of the multiple capacitance elements is determined, for example, by the design rules of a semiconductor circuit, but there is a method of realizing the minimum capacitance as a differential capacitance by combining multiple capacitance elements rather than by using a single capacitance element. In other words, the multiple capacitance elements constituting the capacitance arrays 201 and 501 in this embodiment can include a first type capacitance element that realizes a predetermined capacitance using a single capacitance element and a second type capacitance element that realizes a predetermined capacitance using a combination of multiple capacitance elements.

[0051] FIG. 8 is a diagram for explaining an example of a method for generating a differential capacitance. Here, a case where a capacitor with a capacitance of 1C is generated will be explained. To this end, capacitors with capacitances of 3C and 2C are connected in parallel, VRP (0.9V) is applied to the capacitor C1 with a capacitance of 3C, and VRN (0.3V) is applied to the capacitor C2 with a capacitance of 2C. At this time, since the voltage of the input INP is 0.6V, 0.3V is applied to C1, and -0.3V is applied to C2. Therefore, the charge Q1 stored in C1 is 3C*0.3=0.9C, and the charge Q1 stored in C2 is 2C*(-0.3)=-0.6C. The sum of Q1 and Q2 is 0.3C, and when converted into a potential difference of 0.3V on the positive phase side applied to the capacitor C1, the capacitance is 1C. In this way, the 1C in the multiplication circuit 101 of FIG. 7 can be realized by the differential capacitance.

[0052] In the circuit of Fig. 7, the operation when transferring charges after multiplying the first input value (input A) and the second input value (input B) will be described with reference to the timing chart of Fig. 9. Fig. 9 shows the control operation of the positive phase side of the differential circuit of Fig. 7. The negative phase side can be controlled in the same way as Fig. 9.

[0053] In the timing chart shown in FIG. 9, the control of the capacitance array 201+ is divided into five periods: a reset period, an input period 1, an input period 2, a charge redistribution period, and a charge transfer period. The process corresponding to the timing chart is shown as a flowchart in FIG. 11. The flowchart shows the flow of the process executed by the control circuit 103. FIG. 9 shows the state of the control signal controlled by the switch SW in each period supplied from the control circuit 103. In the reset period, all the capacitors of the capacitance array 201+ are reset. In this embodiment, the ground voltage is 0.6 V, so only the switch VRC is set to High, and the switches VRP, VRN, and COMP are set to Low. In addition, by setting the switch INP to High and inputting a voltage of 0.6 V, the potential difference across each capacitor becomes 0, and the capacitors are reset. The above operation in the reset period corresponds to the reset operation of S1101.

[0054] In the following input period 1, an input charge is input from INP. At this time, the VRP, VRC, and VRN switches are set to Low, and only the COMP switch is set to High. In addition, the INP switch is set to Low, and the inverting input terminal of the capacitor is set to floating. This causes charge to be supplied to each capacitor, and charge according to the capacitance of each capacitor is accumulated. At this time, the COMP voltage is 0.7875V. Since the inverting input terminal voltage of the capacitor is 0.6V, the potential difference of each capacitor is 0.1875V. Note that in input period 1, the transfer path from the transmission side capacitance array to INP is in a floating state (a state in which the voltage is not controlled from the outside), and charge is transferred based on the 0.6V standard, so the voltage of INP is 0.6V. When injecting charge in input period 1, if the VRC switch of the INP node is turned on, charge transfer will not be established, so the INP switch is turned off.

[0055] The first total charge Qt held during input period 1 is expressed by the following formula: This value is based on the charge amount equivalent to 101 in digital signal representation. Qt=(4C+2C+C+C)*0.1875=1.5C...(Formula 1) The above operation in the input period 1 corresponds to the process of causing the capacitor array 201 to hold the first input value in S1102.

[0056] Next, in the input period 2, a digital signal to be multiplied with the analog signal input in the input period 1 is input. Here, it is assumed that "010" is input. Therefore, for C4+, C1a+, C1b+, C1da+, and C1db+, VRC becomes High for resetting, and the other switches become Low. In addition, by inputting VRC (0.6V) with the INP switch set to High, the potential difference applied to C4+, C1a+, C1b+, C1da+, and C1db+ becomes 0V, and the held charge is discharged. On the other hand, all switches of C2+ become Low, and the held charge is maintained. At this time, COMP is maintained at 0.6V. As a result, the charges of the capacitors C4, C1a, and C1b are erased, and only the charge of C2 remains. At this time, the inverting amplifier 202+ is in a virtual short-circuit state because the voltages input to the inverting input terminal and the non-inverting input terminal match at 0.6V, and the parasitic capacitance around the capacitance array can be ignored when performing multiplication in the input period 2.

[0057] At this time, the second total charge Qt′ held during the input period 2 is expressed by the following formula. Qt'=2C*0.1875=0.375C...(Formula 2) The above operation in the input period 2 corresponds to the process of causing the capacitor array 201 to hold the second input value in S1104.

[0058] In the subsequent charge reallocation period, the COM switch is set to High and all other switches are set to Low. INP is also set to Low. As a result, all capacitors are connected in parallel and the charge held in C2 is distributed to each capacitor. At this time, the voltage of COMP is 0.375C / 8C+0.6=0.6469V. The above operation during the charge reallocation period corresponds to the charge reallocation process in S1105.

[0059] In the subsequent charge transfer period, as in the charge redistribution period, the COM switch is set to High and all other switches are set to Low. INP is also set to Low. At this time, the inverting input terminal voltage of the capacitor is 0.6 V, so the potential difference of each capacitor is 0.0469 V. Furthermore, in the charge transfer period, the connection relationship between the inverting amplifier 202 and the capacitance array 201 is switched to the state shown in FIG. 5. The above operation in the charge transfer period corresponds to the process of S1106 of transferring the charges held by the capacitance array 201 to the adder circuit 102. Note that the capacitance array 501 of the adder circuit 102 is reset in advance before the first charge transfer is performed.

[0060] In the flowchart of Fig. 11, the charge reallocation process in S1103 is omitted because the first input value in S1102 is an analog input value. Also, in Fig. 11, charge reallocation is performed in S1105, but this charge reallocation may also be omitted and charge transfer may be performed in S1106. Also, in the process of holding the second input value in S1103, the charge held in the capacitive element corresponding to the significant bit in the second input value may be transferred to the adder circuit 102, thereby integrating S1103 and S1106.

[0061] 11 is executed in parallel for the multiple multiplication circuits 101, the charges transferred to the addition circuit 102 are added in the capacitance array 501 to obtain an addition result of the multiplication results in each multiplication circuit, and the addition result is output in S1107. The timing of execution of the process in FIG. 11 may be simultaneous or may be shifted in time.

[0062] While Fig. 9 shows a timing chart for multiplying an analog input by a digital input, Fig. 10 shows a timing chart for multiplying a digital input by a digital input. Fig. 10 shows the control operation of the positive phase side of the differential circuit in Fig. 7. The negative phase side can be controlled in the same way as Fig. 10. The flowchart in Fig. 11 also corresponds to the processing of the timing chart in Fig. 10.

[0063] In the timing chart shown in FIG. 10, the control of the capacitance array 201+ is divided into six periods: a reset period, an input period 1, a charge reallocation period, an input period 2, a charge reallocation period, and a charge transfer period. FIG. 10 shows the control operation of the switch SW in each period. In the reset period, the capacitance of all the capacitors in the capacitance array 201+ is reset. In this embodiment, the ground voltage is set to 0.6 V, so that only the switch VRC is set to High, and the switches VRP, VRN, and COMP are set to Low. In addition, by setting the switch INP to High and inputting 0.6 V, the potential difference across each capacitor becomes 0, and the capacitors are reset. The above operation in the reset period corresponds to the reset operation of S1101.

[0064] In the following input period 1, a digital signal is input. At this time, the input signal has a value of 101, so C4+ has a High VRP, C2+ is all Low, C1a+ has a High VRP, C1b+ has a High VRN, and Cda+ and Cdb+ are all Low. In addition, the INP switch is set to High, and the inverting input terminal of the capacitor is fixed to 0.6V. This causes charge to be supplied to each capacitor, and charge according to the capacitance of each capacitor is accumulated. At this time, the COMP voltage becomes 0.6V. As a result, the inverting amplifier 202+ is in a virtual short-circuit state because the voltages input to the inverting input terminal and the non-inverting input terminal match at 0.6V, and the parasitic capacitance around the capacitance array can be ignored in input period 1.

[0065] The first total charge Qtd held in the input period 1 is expressed by the following formula: This value is the same as the total charge Qt calculated by formula 1, which is the charge amount equivalent to 101 in digital signal representation. Qtd=4C*0.3+C*0.3=1.5C...(Formula 3) The above operation in the input period 1 corresponds to the process of causing the capacitor array 201 to hold the first input value in S1102.

[0066] In the following charge reallocation period 1, the COM switch is set to High and all other switches are set to Low. INP is also set to Low. As a result, all capacitors are connected in parallel, and the charges held in C4+ and C1a+ are distributed to each capacitor according to its capacitance. At this time, the voltage of COMP is 1.5C / 8C+0.6=0.7875V. The above operations in charge reallocation period 1 correspond to the charge reallocation process in S1103.

[0067] Next, in the input period 2, a digital signal is input to each capacitor that holds the charge reallocated in the charge reallocation period 1. Here, it is assumed that "010" is input. Therefore, for C4+, C1a+, C1b+, C1da+, and C1db+, VRC becomes High for resetting, and the other switches become Low. Also, by setting the INP switch to High and inputting VRC (0.6V), the potential difference applied to C4+, C1a+, C1b+, C1da+, and C1db+ becomes 0V, and the held charge is discharged. On the other hand, all switches of C2+ become Low, and the held charge is maintained. At this time, COMP is maintained at 0.6V. As a result, the charges of the capacitors C4, C1a, and C1b are erased, and only the charge of C2 remains. Here again, the inverting amplifier 202+ is in a virtual short-circuit state because the voltages input to the inverting input terminal and the non-inverting input terminal match at 0.6V, and the parasitic capacitance around the capacitance array can be ignored when performing multiplication in the input period 2.

[0068] At this time, the second total charge Qtd′ held in the input period 2 is expressed by the following equation, which has the same result as equation 2. Qtd'=2C*0.1875=0.375C...(Formula 4) The above operation in the input period 2 corresponds to the process of causing the capacitor array 201 to hold the second input value in S1104.

[0069] In the following charge reallocation period 2, the COM switch is set to High and all other switches are set to Low. INP is also set to Low. As a result, all capacitors are connected in parallel and the charge held in C2 is distributed to each capacitor. At this time, the voltage of COMP is 0.375C / 8C+0.6=0.6469V. The above operation in charge reallocation period 2 corresponds to the charge reallocation process in S1105.

[0070] In the subsequent charge transfer period, as in the charge redistribution period, the COM switch is set to High and all other switches are set to Low. INP is also set to Low. At this time, the inverting input terminal voltage of the capacitor is 0.6 V, so the potential difference of each capacitor is 0.0469 V. At this time, the control circuit 103 switches the connection relationship between the inverting amplifier 202 and the capacitance array 201 to the state shown in FIG. 5. The above operation in the charge transfer period corresponds to the process of S1106 of transferring the charge held by the capacitance array 201 to the adder circuit 102. Note that the capacitance array 501 of the adder circuit 102 is reset in advance before the first charge transfer is performed.

[0071] 11 corresponding to the timing chart of Fig. 10, charge reallocation is performed in S1105, but this charge reallocation may also be omitted and charge transfer may be performed in S1106. Also, in the process of holding the second input value in S1103, the charge held in the capacitance element corresponding to the significant bit in the second input value may be transferred to the adder circuit 102, thereby integrating S1103 and S1106.

[0072] 11 is executed in parallel for the multiple multiplication circuits 101, the charges transferred to the addition circuit 102 are added in the capacitance array 501 to obtain an addition result of the multiplication results in each multiplication circuit, and the addition result is output in S1107. The timing of execution of the process in FIG. 11 may be simultaneous or may be shifted in time.

[0073] An example of the embodiment has been described above. According to the multiplication and accumulation calculator corresponding to this embodiment, the multiplication and accumulation operation can be performed as an analog process rather than a digital process, and the calculation speed can be increased compared to the conventional multiplication and accumulation operation. Specifically, in the case of digital, only one value can be added together, but in the case of analog, by using a circuit as shown in FIG. 5 and providing multiple multiplication circuits 101 on the input side in multiple stages, it is possible to add multiple values ​​simultaneously. Since the operation of the multiplication circuits 101 can be performed synchronously in parallel and the input to the addition circuit 102 can be performed almost simultaneously, the number of processing steps can be minimized and the speed can be increased compared to a digital circuit. From the viewpoint of power consumption, an analog circuit that operates at an intermediate amplitude according to the charge consumes less power than a digital circuit that operates at a fixed amplitude. In addition, since the charge addition process can be realized asynchronously, there is no need to route a clock, which is also advantageous in terms of circuit layout.

[0074] In addition, when implementing with an FPGA, the clock frequency tends to be low due to the influence of wiring capacitance, and power consumption tends to be high, but in the circuit configuration corresponding to this embodiment, the influence of parasitic capacitance can be reduced, so that high speed can be realized while suppressing power consumption. Also, since the number of processing steps can be reduced as described above, power consumption is improved from that viewpoint as well.

[0075] [Variations] In the above embodiment, the case has been described where each multiplier circuit 101 is configured as a circuit using a one-stage capacitance array, but each multiplier circuit 101 can also be configured using a multi-stage capacitance array.

[0076] 12 shows an example of a multiplication circuit 101 configured using a two-stage capacitance array. The multiplication circuit 101 is configured such that a first partial circuit 1201 and a second partial circuit 1202 are connected to form a loop. A switch 1203 controls charge transfer from the first partial circuit 1201 to the second partial circuit 1202. The switch 1204 is used to switch on and off the charge transfer path when transferring charges from the second partial circuit 1202 to the first partial circuit 1201. As shown in FIG. 12, in this modification, a charge transfer path from the second partial circuit 1202 to the first partial circuit 1201 is also secured. The first partial circuit 1201 includes a first stage first capacitance array 201A and a first inverting amplifier 202A, and the second partial circuit 1202 includes a second stage second capacitance array 201B and a second inverting amplifier 202B. In FIG. 12, the multiplication circuit 101 is shown as a configuration using a two-stage capacitance array, but it may be configured to further include three or more stages of capacitance arrays, i.e., a third partial circuit, a fourth partial circuit, etc.

[0077] In FIG. 12, (A) shows a circuit connection state when electric charge is stored in the first-stage capacitor array 201A, and (B) shows a circuit connection state when electric charge held in the first-stage capacitor array 201A is transferred to the second-stage capacitor array 201B. (C) shows a circuit connection state when electric charge held in the second-stage capacitor array 201B is transferred to the first-stage capacitor array 201A. In FIG. 12(C), the positional relationship between the first partial circuit 1201 and the second partial circuit 1202 is reversed from that in FIG. 12(A) and (B), but this is for illustration purposes only and does not change the actual circuit arrangement. In FIG. 12(A), (B), and (C), the capacitor arrays 201A and 201B, the inverting amplifiers 202A and 202B, and the parasitic capacitances Cst1 and Cst2 are the same as those shown in FIG. 2. Moreover, the parasitic capacitances Cst5 and Cst6 indicate parasitic capacitances related to the second-stage capacitor array 201B, and their properties are similar to those of the parasitic capacitances Cst1 and Cst2. Therefore, the description of these elements shall be the same as that of FIG. 2, and the description here will be omitted.

[0078] The operation of the multiplication circuit 101A shown in Fig. 12 will be described below with reference to the flowchart in Fig. 13. This flowchart shows the flow of processing executed by the control circuit 103. When a multi-stage capacitance array 201 is used, multiplication can be performed during charge transfer. First, the processing will be described when the first input value A is an analog value, and the second input value B and the third input value C are digital values.

[0079] Before inputting the first input value A, the multiplication circuit 101A is reset in S1301. In particular, the capacitance arrays 201A and 201B are reset. In FIG. 12(A), the inverting amplifier 202A connected to the capacitance array 201A is in a virtual short-circuit state between the inverting input terminal and the non-inverting input terminal, and the parasitic capacitance Cst1 is in a negligible state. In the following S1302, the first input value A is held in the first capacitance array 201A. Here, a description will be given assuming that the first total charge Qt in FIG. 9 is held as an analog value as the first input value A. The charge Qt corresponding to the first input value A is distributed and held in each capacitance element of the capacitance array 201A according to the magnitude of the electrostatic capacitance. Note that a switch 1201 is disposed between the first-stage capacitance array 201A and the second-stage capacitance array 201B, and at this point, the switch 1201 is turned off so that the capacitance array 201A is separated from the capacitance array 201B.

[0080] Next, in S1303, charge transfer is performed from the first capacitance array 201A to the second capacitance array 201B. When transferring charges, only the charges held in the capacitance elements whose bit is 1 (having a significant value) in the second input value B are transferred as shown in FIG. 12(B). For example, the charges in the capacitance elements corresponding to the significant value may be maintained as they are, and the charges held in the capacitance elements whose bit is 0 may be reset and then transferred. Here, as in the example described in FIG. 9, it is assumed that "010" is given as the digital value of the input B. Therefore, only the charge in the capacitance element of the electrostatic capacitance 2C is maintained, and the rest are reset. Then, the switch 1201 is turned on to connect the first capacitance array 201A to the second capacitance array 201B, and the connection is switched so that the first inverting amplifier 202A operates as an equal-power amplifier. As a result, only the charges held in the capacitance elements whose bit is 1 in the first capacitance array 201A are transferred and input to the second capacitance array 201B. On the second capacitance array 201B side, the second inverting amplifier 202B is in a virtual short-circuit state between the inverting input terminal and the non-inverting input terminal, and the parasitic capacitance Cst5 is in a negligible state. Therefore, the input charge is distributed and held by each capacitance element of the second capacitance array 201B according to the magnitude of the electrostatic capacitance. At this point, the multiplication of the first input value A and the second input value B is completed, and further, the charge reallocation is completed. At this time, the total charge held by the second capacitance array 201B corresponds to the second total charge Qt'.

[0081] Next, in S1304, charge transfer is performed from the second capacitance array 201B to the first capacitance array 201A. When transferring charges, only the charges held in the capacitance elements whose bit is 1 (having a significant value) in the third input value C are transferred as shown in FIG. 12(C). As in S1303, the charges in the capacitance elements corresponding to the significant value may be maintained as they are, and the charges held in the capacitance elements whose bit is 0 may be reset and then transferred. Here, for example, a case is assumed in which "110" is given as the digital value of the third input value C. Therefore, only the charges in the capacitance elements of the electrostatic capacitances 4C and 2C are maintained, and the rest are reset. Then, the switch 1204 is turned on to connect the second capacitance array 201B to the first capacitance array 201A, and the connection is switched so that the inverting amplifier 202B operates as an equal-power amplifier. As a result, only the charges held in the capacitance elements whose bit is 1 in the second capacitance array B are transferred and re-input to the first capacitance array 201A. On the first capacitance array 201A side, the inverting amplifier 202A is in a virtual short-circuit state between the inverting input terminal and the non-inverting input terminal, and the parasitic capacitance Cst1 is in a negligible state. Therefore, the input charge is distributed and held by each capacitance element of the first capacitance array 201A according to the magnitude of the electrostatic capacitance. At this point, the multiplication of the third input value C with the multiplication result of the first input value A and the second input value B is completed, and further the charge reallocation is completed.

[0082] After the process of S1304, the process may proceed to S1305 to transfer the charge held in the first capacitance array 201A to the adder circuit 102, or may return to S1303. When returning to S1303, the charge held in the first capacitance array 201A is multiplied by the fourth input value D and transferred to the second capacitance array 201B. Thereafter, the process may proceed to S1305 to transfer the charge held in the second capacitance array 201B to the adder circuit 102, or may proceed to S1304. These multiplication processes are executed until a desired number of multiplications is reached, and when the desired number of multiplications is reached, in S1305, the charge corresponding to the multiplication result is transferred from the first capacitance array 201A or the second capacitance array 201B to the adder circuit 102. Then, in S1306, the charge transferred to the adder circuit 102 is added in the capacitance array 501, and the sum of the multiplication results in each multiplication circuit is output.

[0083] Next, a process will be described in the case where the first input value A, the second input value B, and the third input value C are digital values. Before inputting the first input value A, the multiplication circuit 101A is reset in S1301. In particular, the capacitance arrays 201A and 201B are reset. In the following S1302, the first input value A is held in the first capacitance array 201A. Since the first input value A is given a digital value of "101", charges are held only in the capacitance elements with capacitances of 4C and 1C, and the capacitance element with capacitance of 2C and the dummy element are reset. At this point, the switch 1201 is turned off so that the first capacitance array 201A is separated from the second capacitance array 201B. Next, charge redistribution is performed in the first capacitance array 201A, and charges according to the magnitude of the capacitance are held in each capacitance element of the capacitance array 201A. The following process from S1303 onwards is the same as that described in the case where the first input value A is an analog value.

[0084] In the above description, the charge is transferred from the first capacitance array 201A or the second capacitance array B to the next stage by multiplying the charge by a predetermined input value, but it is also possible to transfer the charge to the next-stage capacitance array 201 without multiplication, and then multiply the charge by the next input value in the capacitance array 201. In this case, only some of the capacitance elements in the capacitance array 201 from which the charge is transferred will hold charge, but when the charge is transferred, whether the charge destination is the adder circuit 102 or the capacitance array 201, charge reallocation will be performed there, so multiplication can be performed immediately.

[0085] In this manner, the multiplication circuit 101 can be configured by connecting partial circuits each having a capacitance array 201 and an inverting amplifier 202 in a plurality of stages. In this configuration, charge transfer can be performed from the partial circuits to the adder circuit 102 according to the number of multiplications. For example, when two multiplications are performed, the charge held in the second capacitance array 201B is transferred to the adder circuit 102 in the above configuration. When three multiplications are performed, the charge held in the first capacitance array 201A is transferred to the adder circuit 102. In this embodiment, a desired number of multiplications can be realized by configuring a loop with the output of the partial circuit in the previous stage as the input of the partial circuit in the next stage. The above-described modified example also provides the same effects as the embodiment. In particular, in this modified example, by using a plurality of partial circuits in a loop, an arbitrary number of multiplication processes can be realized in a common circuit. In addition, since charge redistribution can be performed during charge transfer, the processing steps can be reduced, further speeding up the process, and power consumption is further improved.

[0086] <Summary of the embodiment> The above-described embodiments disclose at least the following product-sum calculation circuit, a control method for the product-sum calculation circuit, and a calculation system. (1) A multiply-and-accumulate circuit a plurality of multiplication circuits; and an addition circuit that adds up the multiplication results of the plurality of multiplication circuits and outputs the addition result; Each of the plurality of multiplication circuits a capacitance array including a plurality of capacitance elements; an inverting amplifier connected to the capacitance array in a switchable manner; Including, When multiplication is performed in the multiplication circuit, a first side of the capacitance array is connected to an inverting input terminal of the inverting amplifier, and a second side of the capacitance array opposite to the first side is connected to an output terminal of the inverting amplifier; A predetermined ground voltage is supplied to the non-inverting input terminal of the inverting amplifier, When the multiplication result of the multiplication circuit is transferred to the addition circuit, a multiply-accumulate circuit, the first side of the capacitance array being connected to a non-inverting input terminal of the inverting amplifier, and the second side being connected to the inverting input terminal and the output terminal; (2) the capacitance array is configured by connecting a plurality of capacitance elements in parallel; The multiply-and-accumulate circuit according to claim 1, wherein the capacitances of the plurality of capacitive elements are set to have a power-of-two relationship. (3) The multiply-accumulate circuit according to (1) or (2), wherein the capacitance array includes a dummy capacitance, and the capacitance of the dummy capacitance is equal to the smallest capacitance among the capacitances of the plurality of capacitance elements constituting the capacitance array. (4) The multiply-accumulate circuit according to any one of (1) to (3), wherein, when multiplication is performed in the multiplication circuit, a voltage is supplied to the inverting input terminal and the non-inverting input terminal so that the inverting amplifier is in a virtual short-circuit state. (5) The plurality of capacitance elements constituting the capacitance array are composed of either a first type capacitance element composed of a single capacitance element or a second type capacitance element composed of a combination of a plurality of capacitance elements having different capacitances; The multiply-accumulate circuit according to any one of (1) to (4), wherein the second type capacitive element is a combination of a capacitive element having a first capacitance that is the smallest in the multiply-accumulate circuit, and a capacitive element having a second capacitance that is larger than the first capacitance. (6) The product-sum calculation circuit is configured by differentiating a first product-sum calculation circuit of a positive phase and a second product-sum calculation circuit of a negative phase, and when multiplication is performed in the multiplication circuit, Among the second type capacitive elements in the first product-sum operation circuit, a terminal on the second side of the capacitive element having the second capacitance is connected to an output terminal of an inverting amplifier of the first product-sum operation circuit; a terminal on the second side of the capacitive element having the first capacitance is connected to an output terminal of an inverting amplifier of the second product-sum operation circuit; Among the second type capacitive elements in the second product-sum operation circuit, a terminal on the second side of a capacitive element having the second capacitance is connected to the output terminal of the inverting amplifier of the second product-sum operation circuit; The product-sum operation circuit according to (5), wherein a terminal on the second side of a capacitive element having the first capacitance is connected to the output terminal of the inverting amplifier of the first product-sum operation circuit. (7) The multiply-accumulate circuit according to any one of (1) to (6), wherein the adder circuit is configured to include a capacitance array including a plurality of capacitance elements and an inverting amplifier connected to the capacitance array in a switchable manner, or is configured from at least one capacitance element. (8) The multiply-add circuit according to any one of (1) to (7), wherein the multiplier circuit is configured by arranging a plurality of partial circuits, each partial circuit including a capacitance array including a plurality of capacitance elements and an inverting amplifier connected to the capacitance array in a switchable manner. (9) When multiplication is performed in a first partial circuit among the plurality of arranged partial circuits, the first side of the first capacitance array of the first partial circuit is connected to an inverting input terminal of a first inverting amplifier, and the second side of the first capacitance array is connected to an output terminal of the first inverting amplifier; the predetermined ground voltage is supplied to a non-inverting input terminal of the first inverting amplifier; When a charge transfer of a multiplication result in the first partial circuit is performed from the first partial circuit to a second partial circuit different from the first partial circuit, The multiply-accumulate circuit according to (8), wherein the first side of the first capacitance array is connected to the non-inverting input terminal of the first inverting amplifier, and the second side of the first capacitance array is connected to the inverting input terminal and the output terminal of the first inverting amplifier. (10) The multiply-add circuit according to (9), wherein the multiplier circuit is configured to be able to repeatedly execute multiplication a predetermined number of times by supplying an output of the second partial circuit as an input of the first partial circuit. (11) An arithmetic system including a plurality of multiply-accumulate circuits according to any one of (1) to (10). (12) A method for controlling the multiply-accumulate circuit according to any one of (1) to (6), comprising: a first step of resetting the multiplication circuit; a second step of supplying a first amount of charge to the capacitance array of the reset multiplication circuit; a third step of resetting charges of at least a part of capacitance elements corresponding to a predetermined digital value in the capacitance array that holds the first amount of charges, thereby performing a multiplication process of the predetermined digital value; a fourth step of transferring a second amount of charge held by the capacitance array after the charge of at least some of the capacitance elements has been reset to the adder circuit; a fifth step of executing the first step to the fourth step for each of the plurality of multiplier circuits included in the product-sum calculation circuit, and outputting a sum of the charges transferred from each of the plurality of multiplier circuits; A method for controlling a multiply-accumulate circuit, comprising: (13) In the third step, the same voltage is supplied to an inverting input terminal and a non-inverting input terminal of the inverting amplifier connected in parallel with the capacitance array in the multiplication circuit so that the inverting amplifier is in a virtual short-circuit state; The method for controlling a multiply-accumulate circuit according to (12), wherein in the fourth step, the inverting amplifier operates as a unitary amplifier, thereby transferring the charge held in the capacitance array to the adder circuit. (14) The method for controlling a multiply-accumulate circuit according to (12) or (13), wherein in the fourth step, the second amount of charge is redistributed in the capacitance array, and the redistributed charge is transferred to the adder circuit. (15) The second step comprises: a sixth step of supplying charge to at least some of the plurality of capacitance elements constituting the capacitance array to cause them to hold the first amount of charge, and resetting capacitance elements to which no charge is supplied; a seventh step of redistributing the first amount of charge in the capacitance array that holds the first amount of charge; Including, The method for operating a product-sum calculation circuit according to any one of (12) to (14), wherein in the sixth step, an identical voltage is supplied to an inverting input terminal and a non-inverting input terminal of the inverting amplifier connected in parallel to the capacitance array in the multiplication circuit so that the inverting amplifier is in a virtual short-circuit state. (16) A method for controlling the multiply-accumulate circuit according to any one of (1) to (6), comprising the steps of: a first step of resetting the multiplication circuit; a second step of supplying a first amount of charge to the capacitance array of the reset multiplication circuit; a third step of transferring, to the adder circuit, only charges of at least some of the capacitance elements in the capacitance array that hold the first amount of charges, the charges corresponding to a predetermined digital value, thereby performing a multiplication process of the predetermined digital value; a fourth step of executing the first step to the third step for each of the plurality of multiplier circuits included in the product-sum calculation circuit, and outputting a sum of the charges transferred from each of the plurality of multiplier circuits; A method for controlling a multiply-accumulate circuit, comprising: (17) A method for controlling the multiply-accumulate circuit according to (9) or (10), comprising the steps of: a first step of resetting the multiplication circuit; a second step of supplying an amount of charge corresponding to a first input value to the first capacitor array of the first partial circuit of the reset multiplication circuit; a second step of transferring charges of at least a part of capacitance elements of the first capacitance array corresponding to a second input value to a second capacitance array of the second partial circuit; a third step of transferring charges of at least a part of capacitance elements of the second capacitance array corresponding to a third input value to the first capacitance array of the first partial circuit; a fourth step of repeating the second step and the third step according to a desired number of multiplications after the third step; a fifth step of transferring the charges held in the first capacitance array or the second capacitance array to the adder circuit after the third step or the fourth step; a sixth step of executing the first step to the fifth step for each of the plurality of multiplier circuits included in the multiply-accumulate circuit, and outputting a sum of the charges transferred from each of the plurality of multiplier circuits; A method for controlling a multiply-accumulate circuit, comprising: (18) In the second step, When the first input value is an analog value, the first amount of charge is distributed in accordance with the capacitance of each capacitive element of the first capacitive array, and the charge is held in each capacitive element, thereby causing the first capacitive array to hold an amount of charge corresponding to the first input value; or 18. A method for controlling a multiply-accumulate circuit according to claim 17, further comprising the steps of: when the first input value is a digital value, causing charge to be held only in a capacitive element of the first capacitance array that corresponds to a significant value in the first input value; and then redistributing the held charge to each capacitive element of the first capacitance array, thereby causing the first charge amount to be held in the first capacitance. (19) A method for controlling the multiply-accumulate circuit according to (9) or (10), comprising the steps of: a first step of resetting the multiplication circuit; a second step of supplying an amount of charge corresponding to a first input value to the first capacitor array of the first partial circuit of the reset multiplication circuit; a third step of transferring the charges held in the first capacitance array to a second capacitance array of the second partial circuit; a fourth step of resetting charges of at least some of the capacitance elements corresponding to a second input value in the second capacitance array, thereby multiplying the charges held in the second capacitance array by the second input value; a fifth step of transferring the charge held in the second capacitance array after the multiplication process of the second input value to the first capacitance array of the first partial circuit; a sixth step of resetting charges of at least some of the capacitance elements in the first capacitance array, the charges corresponding to a third input value, thereby multiplying the charges held in the first capacitance array by the third input value; a seventh step of repeating the third step, the fourth step, the fifth step, and the sixth step according to a desired number of multiplications, after the sixth step; an eighth step, after the sixth step or the seventh step, of transferring the charges held in the first capacitance array or the second capacitance array to the adder circuit; a ninth step of executing the first step to the eighth step for each of the plurality of multiplying circuits included in the product-sum calculation circuit, and outputting a sum of the charges transferred from each of the plurality of multiplying circuits; A method for controlling a multiply-accumulate circuit, comprising: (20) In the second step, When the first input value is an analog value, the first amount of charge is distributed in accordance with the capacitance of each capacitive element of the first capacitive array, and the charge is held in each capacitive element, thereby causing the first capacitive array to hold an amount of charge corresponding to the first input value; or 20. The control method for a multiply-accumulate circuit according to claim 19, wherein, when the first input value is a digital value, a charge of the first amount of charge is held in the first capacitance by causing only a capacitive element, among the capacitive elements constituting the first capacitance array, that corresponds to a significant value in the first input value to hold a charge. (21) The method for operating the product-sum calculation circuit according to (19) or (20), wherein in the third step, the fifth step, and the eighth step, the same voltage is supplied to the inverting input terminal and the non-inverting input terminal of each of the first inverting amplifier and the second inverting amplifier so that the first inverting amplifier and the second inverting amplifier are in a virtual short-circuit state.

[0087] [Other embodiments] The present invention is not limited to the above-described embodiment, and various modifications and variations are possible within the scope of the present invention. Therefore, in order to clarify the scope of the present invention, the following claims are appended. [Explanation of symbols]

[0088] 10: product-sum calculation circuit, 101: multiplication circuit, 102: addition circuit, 103: control circuit

Claims

1. A multiply-and-accumulate circuit a plurality of multiplication circuits; and an addition circuit that adds up the multiplication results of the plurality of multiplication circuits and outputs the addition result; Each of the plurality of multiplication circuits comprises: a capacitance array including a plurality of capacitance elements; an inverting amplifier connected to the capacitance array in a switchable manner; Including, When multiplication is performed in the multiplication circuit, a first side of the capacitance array is connected to an inverting input terminal of the inverting amplifier, and a second side of the capacitance array opposite to the first side is connected to an output terminal of the inverting amplifier; A predetermined ground voltage is supplied to the non-inverting input terminal of the inverting amplifier, When the multiplication result of the multiplication circuit is transferred to the addition circuit, a first side of the capacitance array connected to a non-inverting input terminal of the inverting amplifier, and a second side of the capacitance array connected to the inverting input terminal and the output terminal of the inverting amplifier;

2. The capacitance array is configured by connecting a plurality of capacitance elements in parallel, 2. The multiply-add circuit according to claim 1, wherein the capacitances of the plurality of capacitive elements are set to have a power-of-two relationship.

3. 3. The multiply-accumulate circuit according to claim 2, wherein the capacitance array includes a dummy capacitance, and the capacitance of the dummy capacitance is equal to a minimum capacitance among capacitances of the plurality of capacitive elements constituting the capacitance array.

4. 4. The multiply-accumulate circuit according to claim 3, wherein when said multiplication circuit performs multiplication, a voltage is supplied to said inverting input terminal and said non-inverting input terminal such that said inverting amplifier is in a virtual short-circuit state.

5. the plurality of capacitance elements constituting the capacitance array are composed of either a first type capacitance element composed of a single capacitance element or a second type capacitance element composed of a combination of a plurality of capacitance elements having different capacitances; 2. The multiply-accumulate circuit according to claim 1, wherein the second type capacitive element is a combination of a capacitive element having a first capacitance that is the smallest in the multiply-accumulate circuit and a capacitive element having a second capacitance that is larger than the first capacitance.

6. The sum-of-products circuit is configured by differentiating a first sum-of-products circuit of a positive phase and a second sum-of-products circuit of a negative phase, and when multiplication is performed in the multiplication circuit, Among the second type capacitive elements in the first product-sum operation circuit, a terminal on the second side of the capacitive element having the second capacitance is connected to an output terminal of an inverting amplifier of the first product-sum operation circuit; a terminal on the second side of the capacitive element having the first capacitance is connected to an output terminal of an inverting amplifier of the second product-sum operation circuit; Among the second type capacitive elements in the second product-sum operation circuit, a terminal on the second side of a capacitive element having the second capacitance is connected to the output terminal of the inverting amplifier of the second product-sum operation circuit; 6. The product-sum operation circuit according to claim 5, wherein the second terminal of the capacitive element having the first capacitance is connected to the output terminal of the inverting amplifier of the first product-sum operation circuit.

7. The adding circuit includes:

2. The product-sum operation circuit according to claim 1, comprising: a capacitance array including a plurality of capacitance elements; and an inverting amplifier connected to said capacitance array in a switchable manner, or comprising at least one capacitance element.

8. 2. The multiply-add circuit according to claim 1, wherein the multiplier circuit is configured by arranging a plurality of partial circuits, each partial circuit including a capacitance array including a plurality of capacitance elements and an inverting amplifier connected to the capacitance array in a switchable manner.

9. When multiplication is performed in a first partial circuit among the plurality of arranged partial circuits, the first side of the first capacitance array of the first partial circuit is connected to an inverting input terminal of a first inverting amplifier, and the second side of the first capacitance array is connected to an output terminal of the first inverting amplifier; the predetermined ground voltage is supplied to a non-inverting input terminal of the first inverting amplifier; When a charge transfer of a multiplication result in the first partial circuit is performed from the first partial circuit to a second partial circuit different from the first partial circuit, 9. The multiply-accumulate circuit according to claim 8, wherein the first side of the first capacitance array is connected to the non-inverting input terminal of the first inverting amplifier, and the second side of the first capacitance array is connected to the inverting input terminal and the output terminal of the first inverting amplifier.

10. 10. The multiply-add circuit according to claim 9, wherein the multiplier circuit is configured to be capable of repeatedly executing multiplication a predetermined number of times by supplying an output of the second partial circuit as an input of the first partial circuit.

11. An arithmetic system comprising a plurality of multiply-accumulate circuits according to any one of claims 1 to 10.

12. A method for controlling the product-sum calculation circuit according to any one of claims 1 to 6, comprising the steps of: a first step of resetting the multiplication circuit; a second step of supplying a first amount of charge to the capacitance array of the reset multiplication circuit; a third step of resetting charges of at least a part of capacitance elements corresponding to a predetermined digital value in the capacitance array that holds the first amount of charges, thereby performing a multiplication process of the predetermined digital value; a fourth step of transferring a second amount of charge held by the capacitance array after the charge of at least some of the capacitance elements has been reset to the adder circuit; a fifth step of executing the first step to the fourth step for each of the plurality of multiplying circuits included in the multiply-accumulate circuit and outputting a sum of the charges transferred from each of the plurality of multiplying circuits; A method for controlling a multiply-accumulate circuit, comprising:

13. In the third step, the same voltage is supplied to an inverting input terminal and a non-inverting input terminal of the inverting amplifier connected in parallel with the capacitance array in the multiplication circuit so that the inverting amplifier is in a virtual short-circuit state; 13. The method of claim 12, wherein in the fourth step, the inverting amplifier operates as a unitary amplifier to transfer the charges held in the capacitance array to the adder circuit.

14. 14. The method for controlling a multiply-accumulate circuit according to claim 13, wherein in the fourth step, the second amount of charge is redistributed in the capacitance array, and the redistributed charge is transferred to the adder circuit.

15. The second step includes: a sixth step of supplying charge to at least some of the plurality of capacitance elements constituting the capacitance array to hold the first amount of charge, and resetting capacitance elements to which no charge is supplied; a seventh step of redistributing the first amount of charge in the capacitance array that holds the first amount of charge; Including, 13. The control method for a product-sum operation circuit according to claim 12, wherein in the sixth step, an identical voltage is supplied to an inverting input terminal and a non-inverting input terminal of the inverting amplifier connected in parallel to the capacitance array in the multiplication circuit so that the inverting amplifier is brought into a virtual short-circuit state.

16. A method for controlling the product-sum calculation circuit according to any one of claims 1 to 6, comprising the steps of: a first step of resetting the multiplication circuit; a second step of supplying a first amount of charge to the capacitance array of the reset multiplication circuit; a third step of performing a multiplication process of the predetermined digital value by transferring only charges of at least a part of capacitance elements corresponding to a predetermined digital value in the capacitance array that holds the first amount of charges, to the adder circuit; a fourth step of executing the first step to the third step for each of the plurality of multiplying circuits included in the multiply-accumulate circuit, and outputting a sum of the charges transferred from each of the plurality of multiplying circuits; A method for controlling a multiply-accumulate circuit, comprising:

17. A method for controlling the product-sum calculation circuit according to claim 9 or 10, comprising the steps of: a first step of resetting the multiplication circuit; a second step of supplying an amount of charge corresponding to a first input value to the first capacitor array of the first partial circuit of the reset multiplication circuit; a second step of transferring charges of at least a portion of capacitance elements of the first capacitance array corresponding to a second input value to a second capacitance array of the second partial circuit; a third step of transferring charges of at least a part of capacitance elements of the second capacitance array corresponding to a third input value to the first capacitance array of the first partial circuit; a fourth step of repeating the second step and the third step according to a desired number of multiplications after the third step; a fifth step of transferring the charges held in the first capacitance array or the second capacitance array to the adder circuit after the third step or the fourth step; a sixth step of executing the first step to the fifth step for each of the plurality of multiplier circuits included in the multiply-accumulate circuit and outputting a sum of the charges transferred from each of the plurality of multiplier circuits; A method for controlling a multiply-accumulate circuit, comprising:

18. In the second step, When the first input value is an analog value, a first amount of charge is distributed in accordance with the capacitance of each capacitive element of the first capacitance array, and the charge is held in each capacitive element, thereby causing a charge amount corresponding to the first input value to be held in the first capacitance array; or 18. The control method for a product-sum calculation circuit according to claim 17, further comprising the steps of: when the first input value is a digital value, among the capacitance elements constituting the first capacitance array, causing charge to be held only in capacitance elements corresponding to a significant value in the first input value; and then redistributing the held charge to each capacitance element of the first capacitance array, thereby causing charge of the first charge amount to be held in the first capacitance array.

19. A method for controlling the product-sum calculation circuit according to claim 9 or 10, comprising: a first step of resetting the multiplication circuit; a second step of supplying an amount of charge corresponding to a first input value to the first capacitor array of the first partial circuit of the reset multiplication circuit; a third step of transferring the charges held in the first capacitance array to a second capacitance array of the second partial circuit; a fourth step of resetting charges of at least some of the capacitance elements corresponding to a second input value in the second capacitance array, thereby multiplying the charges held in the second capacitance array by the second input value; a fifth step of transferring the charges held in the second capacitance array after the multiplication process of the second input value to the first capacitance array of the first partial circuit; a sixth step of resetting charges of at least some of the capacitance elements in the first capacitance array, the charges corresponding to a third input value, thereby executing a multiplication process of the charges held in the first capacitance array by the third input value; a seventh step of repeating the third step, the fourth step, the fifth step, and the sixth step according to a desired number of multiplications, after the sixth step; an eighth step of transferring the charges held in the first capacitance array or the second capacitance array to the adder circuit after the sixth step or the seventh step; a ninth step of executing the first step to the eighth step for each of the plurality of multiplying circuits included in the multiply-accumulate circuit, and outputting a sum of the charges transferred from each of the plurality of multiplying circuits; A method for controlling a multiply-accumulate circuit, comprising:

20. In the second step, When the first input value is an analog value, a first amount of charge is distributed in accordance with the capacitance of each capacitive element of the first capacitance array, and the charge is held in each capacitive element, thereby causing a charge amount corresponding to the first input value to be held in the first capacitance array; or 20. The control method for a product-sum calculation circuit according to claim 19, further comprising the steps of: when the first input value is a digital value, causing only a capacitance element corresponding to a significant value in the first input value, among capacitance elements constituting the first capacitance array, to hold a charge, thereby causing the first amount of charge to be held in the first capacitance array.

21. 21. The control method for a product-sum operation circuit according to claim 20, wherein in the third step, the fifth step, and the eighth step, the same voltage is supplied to an inverting input terminal and a non-inverting input terminal of each of the first inverting amplifier and the second inverting amplifier so that the first inverting amplifier and the second inverting amplifier are in a virtual short-circuit state.

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