Majority logic gate based sequential circuits

Abstract

The low power sequential circuit (e.g., a latch) uses nonlinear polarized capacitors to hold charge with fewer transistors than conventional CMOS sequential circuits. The sequential circuit includes a three-input majority gate having first, second and third inputs and a first output. The sequential circuit includes a driver coupled to the first output, the driver generating a second output. The sequential circuit further includes an exclusive-or (XOR) gate for receiving a clock and the second output, the XOR gate generating a third output coupled to the second input, the first input receiving the data and the third input receiving the second output.

Description

[Technical field]

[0001] Claiming priority This PCT application claims priority to U.S. Patent Application No. 17 / 129,842, filed December 21, 2020, which is incorporated by reference in its entirety for all purposes. [Background technology]

[0002] A sequential circuit is a logic circuit whose output is sampled by a clock. The output depends not only on the current value of the input (e.g., data) but also on the order of past inputs. Thus, the input history plays a role in the output value. This is in contrast to combinational logic, where the output is a function of only the current input. A typical sequential circuit, such as a flip-flop, may consist of several gates and transistors to form master and slave stages, and many interconnects to connect the various gates and transistors. These transistors and gates toggle regularly, increasing the dynamic power consumption of sequential circuits. As processors push down the power envelope to conserve battery power, existing architectures of sequential circuits present a challenge to the goal of lower power consumption.

[0003] The background discussion provided herein is for the purpose of generally presenting the context of the present disclosure. Unless otherwise indicated herein, the material described in this section is not prior art to the claims of this application and is not admitted to be prior art by inclusion in this section. [Brief description of the drawings]

[0004] Embodiments of the present disclosure will be more fully understood from the detailed description given below and the accompanying drawings of various embodiments of the present disclosure, which should not be construed as limiting the disclosure to the specific embodiments, but are for illustration and understanding only.

[0005] [Figure 1A]FIG. 2 illustrates a logic gate having a 3-input majority gate, according to some embodiments.

[0006] [Figure 1B] FIG. 2 illustrates a logic gate having a 5-input majority gate in accordance with some embodiments.

[0007] [Figure 1C] 1 is a plot showing characteristics of a ferroelectric capacitor.

[0008] [Figure 1D] FIG. 2 illustrates a plot showing the output of a three-input majority gate, according to some embodiments.

[0009] [Figure 1E] FIG. 2 is a timing diagram for resetting the ferroelectric capacitor of the majority gate of FIGS. 1A-1B, according to some embodiments.

[0010] [Figure 1F] FIG. 2 illustrates a logic gate having a 3-input majority gate with a passgate-based reset mechanism in accordance with some embodiments.

[0011] [Figure 1G] FIG. 1C is a timing diagram for resetting the ferroelectric capacitor of the majority gate of FIG. 1F according to some embodiments.

[0012] [Figure 1H] FIG. 1 illustrates a logic gate having a 3-input majority gate with an input reset mechanism in accordance with some embodiments.

[0013] [Figure 1I] FIG. 1C is a timing diagram for resetting the ferroelectric capacitor of the majority gate of FIG. 1H according to some embodiments.

[0014] [Figure 1J] FIG. 2 illustrates a plot showing the voltage at node Vout_int2 related to the behavior of a ferroelectric capacitor in accordance with some embodiments.

[0015] [Figure 2A] FIG. 2 illustrates a logic gate having a three-input threshold gate that can operate as an AND gate or an OR gate, according to some embodiments.

[0016] [Figure 2B] FIG. 2 illustrates a logic gate having a three-input threshold gate with a passgate-based reset mechanism, according to some embodiments, where the three-input threshold gate can operate as an AND or OR gate.

[0017] [Figure 2C] FIG. 1 illustrates a logic gate having a three-input threshold gate with an input reset mechanism, according to some embodiments, where the three-input threshold gate can operate as an AND or OR gate.

[0018] [Figure 2D] FIG. 2 illustrates a logic gate having a 5-input threshold gate that can operate as an AND or OR gate, according to some embodiments.

[0019] [Figure 3A] FIG. 1C is a diagram showing waveforms illustrating the operation of the three-input majority gate of FIG. 1B.

[0020] [Figure 3B] FIG. 11 illustrates waveforms illustrating the operation of a five-input threshold gate, each with a different Vbias value, in accordance with some embodiments. [Figure 3C] FIG. 11 illustrates waveforms illustrating the operation of a five-input threshold gate, each with a different Vbias value, in accordance with some embodiments. [Figure 3D]FIG. 11 illustrates waveforms illustrating the operation of a five-input threshold gate, each with a different Vbias value, in accordance with some embodiments. [Figure 3E] FIG. 11 illustrates waveforms illustrating the operation of a five-input threshold gate, each with a different Vbias value, in accordance with some embodiments.

[0021] [Figure 4] FIG. 1B illustrates combinational logic including the logic gate of FIG. 1A with a 3D (three-dimensional) view of a 3-input majority gate coupled to an inverter or buffer in accordance with some embodiments.

[0022] [Diagram 5] FIG. 1C illustrates combinational logic including the logic gate of FIG. 1B with a 3D view of a three-input threshold gate coupled to an inverter or buffer in accordance with some embodiments.

[0023] [Figure 6] FIG. 2 illustrates a low-power sequential circuit (eg, a latch) including a non-linear polar capacitor, according to some embodiments.

[0024] [Figure 7] 7 is a table illustrating a truth table for the low power sequential circuit of FIG. 6 in accordance with some embodiments.

[0025] [Figure 8A] FIG. 2 illustrates a low-power majority-gate based sequential circuit (e.g., a latch) including a nonlinear polarized capacitor, according to some embodiments.

[0026] [Figure 8B] FIG. 2 illustrates a low-power majority gate-based flip-flop circuit including a nonlinear polarized capacitor, according to some embodiments.

[0027] [Figure 9] FIG. 8B is a schematic diagram of the sequential circuit of FIG. 8A in accordance with some embodiments.

[0028] [Figure 10] FIG. 1 illustrates a system-on-chip (SOC) using low-voltage sequential circuits, according to some embodiments. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0029] Some embodiments describe sequential circuits that use nonlinear polar capacitors to hold charge. Unlike standard CMOS (Complementary Metal Oxide Semiconductor) based transistors, where each transistor must be directly connected to a source or drain, in some embodiments the transistors are connected to a charged ferroelectric capacitor. In some embodiments, the sequential circuit includes a three-input majority gate having first, second and third inputs and a first output. The majority gate uses nonlinear polar materials, forming a new class of logic gate. In some embodiments, a threshold gate can be used instead of the majority gate.

[0030] An input signal in the form of analog, digital or a combination thereof is driven into a first terminal of a non-ferroelectric capacitor of a majority gate. A second terminal of the non-ferroelectric capacitor is coupled to form a majority node. A majority function of the input signal occurs at this node. The majority node is then coupled to a first terminal of a capacitor comprising a non-linear polar material. A second terminal of the capacitor provides the output of the logic gate.

[0031] In some embodiments, the sequential circuit further includes a driver coupled to the first output (e.g., the output of the three-input majority gate). The driver generates a second output. The driver may be any suitable logic gate, such as a buffer, an inverter, a NAND gate, a NOR gate, etc. Any suitable logic or analog circuit may drive the output and input of the majority logic gate. Thus, the majority gates of various embodiments may be combined with existing transistor technologies, such as complementary metal-oxide semiconductor (CMOS), tunnel field effect transistors (TFETs), GaAs-based transistors, bipolar junction transistors (BJTs), Bi-CMOS transistors, etc.

[0032] In some embodiments, the sequential circuit includes an exclusive-or (XOR) gate for receiving the clock and the second output, the XOR gate generating a third output coupled to a second input (of a three-input majority gate), where a first input of the three-input majority gate receives data (e.g., the input data to be sampled) and a third input (of the three-input majority gate) receives the second output (e.g., the output of the driver).

[0033] In some embodiments, the majority gate of the sequential circuit is replaced with a threshold gate. In the threshold gate, an additional fixed or programmable input is coupled to the majority node through another capacitor. This additional fixed or programmable input can be a positive or negative bias. The bias acts as a threshold or offset that is added to or subtracted from the voltage (or current) at the majority node to determine the final logic value of the logic gate. According to various embodiments, depending on the polarity or voltage value of the bias, an AND gate or an OR logic gate function is realized.

[0034] In some embodiments, an apparatus is provided that includes a three-input majority logic gate and a driver coupled to an output of the three-input majority logic gate. In some embodiments, the three-input majority logic gate includes first, second and third non-ferroelectric capacitors for receiving the first input, the second input and the third input, respectively. In some embodiments, the three-input majority logic gate includes a non-linear polarized capacitor for storing a majority function output of the first, second and third inputs, one terminal of the non-linear polarized capacitor providing an output of the three-input majority logic gate. In some embodiments, the driver generates an amplified output of the three-input majority logic gate, where the amplified output is coupled to the third input. In some embodiments, the apparatus includes comparison logic for receiving a clock and the amplified output, where an output of the comparison logic gate is the second input.

[0035] In some embodiments, the first input is a data input. In some embodiments, the driver comprises one of a buffer, an amplifier, a NAND, an AND, an OR, a multiplexer, or a NOR logic gate, and the comparison logic comprises an exclusive OR (XOR) gate. In some embodiments, the apparatus comprises a first transistor coupled to a first terminal of the nonlinear polar capacitor, the first transistor controllable by a first clock, a second transistor coupled to a second terminal of the nonlinear polar capacitor, the second transistor controllable by a second clock, and a third transistor coupled to the second terminal of the nonlinear polar capacitor, the third transistor controllable by a third clock.

[0036] In some embodiments, the first clock has a pulse width greater than a pulse width of the second clock and a pulse width of the third clock. In some embodiments, the third clock de-asserts prior to assertion of the second clock. In some embodiments, the first transistor is a first n-type transistor, the second transistor is a second n-type transistor, and the third transistor is a p-type transistor. In some embodiments, the first transistor, the second transistor, and the third transistor are disabled in an evaluation phase and enabled in a reset phase, where the reset phase is before the evaluation phase. In some embodiments, the first and second signals are the same, where the first and second signals are reset signals. In some embodiments, the first and second signals are different signals. In some embodiments, the apparatus includes a first driver for generating the first input and a second driver for generating the clock. In some embodiments, the first and second drivers include CMOS transistors. In some embodiments, the first, second and third non-ferroelectric capacitors of the three-input majority logic gate comprise one of a metal-insulator-metal (MIM) capacitor, a transistor gate capacitor, a hybrid metal-transistor capacitor, or a capacitor comprising a para-electric material.

[0037] In some embodiments, the nonlinear polar capacitor comprises one of a ferroelectric material, a paraelectric material, or a nonlinear dielectric material. In some embodiments, the ferroelectric material includes one of the following: bismuth ferrite (BFO), BFO with a doping material, where the doping material includes lanthanum or one of the elements of the lanthanide series of the periodic table; lead zirconate titanate (PZT), or PZT with a doping material, where the doping material includes one of La or Nb; the relaxor ferroelectric includes one of lead magnesium niobate (PMN), lead magnesium niobate-lead titanate (PMN-PT), lead lanthanum zirconate titanate (PLZT), lead scandium niobate (PSN), Barium Titanium-Zinc Niobium Tantalum (BT-BZNT), or Barium Titanium-Barium Strontium Titanium (BT-BST). In some embodiments, the perovskite ferroelectric comprises one of BaTiO3, PbTiO3, KNbO3, or NaTaO3. In some embodiments, the hexagonal ferroelectric comprises one of YMnO3 or LuFeO3.In some embodiments, the hexagonal ferroelectric material is of type h-RMnO3, where R is a rare earth element comprising one of cerium (Ce), dysprosium (Dy), erbium (Er), europium (Eu), gadolinium (Gd), holmium (Ho), lanthanum (La), lutetium (Lu), neodymium (Nd), praseodymium (Pr), promethium (Pm), samarium (Sm), scandium (Sc), terbium (Tb), thulium (Tm), ytterbium (Yb), or yttrium (Y); hafnium (Hf), zirconium (Zr), aluminum (Al), silicon (Si), oxides thereof, or alloy oxides thereof; hafnium oxide of the form Hf1-x Ex Oy. oxides), where E can be Al, Ca, Ce, Dy, Er, Gd, Ge, La, Sc, Si, Sr, Sn, or Y; Al(1-x)Sc(x)N, Ga(1-x)Sc(x)N, Al(1-x)Y(x)N, or Al(1-xy)Mg(x)Nb(y)N, y doped HfO2, where y contains one of Al, Ca, Ce, Dy, Er, Gd, Ge, La, Sc, Si, Sr, Sn or Y, and 'x' is fraction a fraction of the ferroelectric material; a niobate type compound LiNbO3, LiTaO3, lithium iron tantalum oxyfluoride, barium strontium niobate, sodium barium niobate, or potassium strontium niobate; or an improper ferroelectric comprising one of [PTO / STO]n or [LAO / STO]n, where 'n' is between 1 and 100. In some embodiments, the nonlinear polar capacitor is located at the back end of the die, while the driver and comparison logic transistors are located at the front end of the die.

[0038] Various embodiments have many technical effects. For example, highly compact sequential circuits are formed using non-ferroelectric capacitors and capacitors with nonlinear polar materials. The nonlinear polar materials can be ferroelectric, paraelectric, or nonlinear dielectric materials. The majority and / or threshold gates of various embodiments lower the power consumption of sequential circuits because the majority and / or threshold gates do not use switching transistors and the interconnect routing is much less than that used in transition CMOS logic gates. For example, for the same functionality and performance, the majority and threshold gates of various embodiments use 10 times less interconnect length than conventional CMOS circuits. Capacitors with nonlinear polar materials provide non-volatility, which allows for intermittent operation and zero power drain when not in use.

[0039] For example, a processor having such sequential logic gates can enter and exit various types of low power states without having to worry about losing data. Because the capacitors having the nonlinear polar material can store charge from low energy devices, the entire processor can operate at very low voltage levels from the power supply, reducing the overall power of the processor. Furthermore, the very low voltage switching (e.g., 100 mV) of the nonlinear polar material allows for low swing signal switching, resulting in low power.

[0040] Capacitors using nonlinear polar materials can be used with any type of transistor. For example, capacitors using nonlinear polar materials of various embodiments can be used with planar or non-planar transistors. Transistors can be formed on the front end or back end of a die. Capacitors using nonlinear polar materials can be formed on the front end or back end of a die. Thus, logic gates can be packed more densely compared to conventional logic gates. Other technical advantages will be apparent from the various embodiments and drawings.

[0041] In the following description, numerous details are discussed to provide a more thorough explanation of the embodiments of the present disclosure. However, it will be apparent to those skilled in the art that the embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring the embodiments of the present disclosure.

[0042] It should be noted that in the corresponding drawings of the embodiments, signals are represented using lines. Some lines may be thickened to indicate more component signal paths and / or may have arrows at one or more ends to indicate the primary information flow direction. Such indications are not intended to be limiting. Rather, the lines are used in connection with one or more exemplary embodiments to facilitate easier understanding of a circuit or logic unit. Any represented signal includes one or more signals that may actually travel in either direction and may be implemented in any suitable type of signaling scheme, as determined by design needs or preferences.

[0043] The term "device" may generally refer to an apparatus depending on the context of use of the term. For example, a device may refer to a stack of layers or structures, a single structure or layer, a connection of various structures with active and / or passive elements, etc. In general, a device is a three-dimensional structure having a plane along the xy direction and a height along the z direction of an xyz Cartesian coordinate system. The plane of a device may also be the plane of an apparatus that contains the device.

[0044] Throughout this specification and in the claims, the term "connected" means a direct connection, such as an electrical, mechanical or magnetic connection, between the things that are connected, without any intermediate devices.

[0045] The term "coupled" means a direct or indirect connection, such as a direct electrical, mechanical, or magnetic connection between the things that are connected, or an indirect connection through one or more passive or active intermediary devices.

[0046] As used herein, the term "adjacent" generally refers to the location of one thing next to another (e.g., immediately adjacent or near one or more things therebetween) or adjacent to (e.g., adjacent to) another.

[0047] The term "circuit" or "module" may refer to one or more passive and / or active components arranged to cooperate with each other to provide a desired functionality.

[0048] The term "signal" may refer to at least one current signal, voltage signal, magnetic signal, or data / clock signal. The meanings of "a," "an," and "the" include plural references. The meaning of "in" includes "in" and "on."

[0049] As used herein, the term "analog signal" generally refers to any continuous signal whose time-varying characteristics (variables) are representations of some other time-varying quantities, i.e., similar to another time-varying signal.

[0050] Here, the term "digital signal" generally refers to a physical signal that is a sequence of discrete values ​​(a quantified discrete-time signal), e.g., any bit stream, or a representation of an analog signal that has been digitized (sampled and analog-to-digital converted).

[0051] The term "scaling" generally refers to converting a design (schematic and layout) from one process technology to another, followed by reducing the layout area. The term "scaling" also generally refers to miniaturizing layouts and devices within the same technology node. The term "scaling" may also refer to adjusting (e.g., slowing down or speeding up - i.e., scaling down or up, respectively) signal frequency with respect to another parameter, e.g., power supply level.

[0052] The terms "substantially," "close," "approximately," "near," and "about" generally refer to within ±10% of a target value. Unless otherwise specified in the express context of their use, for example, terms such as "substantially equal," "approximately equal," and "approximately equal" mean no more than an incidental variation between those so described. In the art, such variation is typically no more than + / - 10% of a given target value.

[0053] Unless otherwise noted, the use of ordinal adjectives such as "first," "second," and "third" to describe a common object is intended merely to indicate that different instances of a similar object are being referred to, and is not intended to imply that the objects so described must be in a given order, either temporally, spatially, ranked, or in any other manner.

[0054] For purposes of this disclosure, the phrases "A and / or B" and "A or B" mean (A), (B), or (A and B). For purposes of this disclosure, the phrase "A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).

[0055] Terms such as "left," "right," "front," "rear," "top," "bottom," "above," "below," and the like in this specification and claims, when present, are used for descriptive purposes and not necessarily to describe permanent relative positions. For example, the terms "above," "below," "front side," "rear side," "top," "bottom," "above," "below," and "above" as used herein refer to the relative position of one component, structure, or material with respect to other referenced components, structures, or materials in the device, and such physical relationship is noteworthy. These terms are used herein primarily in the context of the device z-axis for descriptive purposes only, and thus may relate to the orientation of the device. Thus, in the context of the figures provided herein, a first material that is "above" a second material may be "below" the second material if the device is oriented upside down relative to the context of the figures provided. In terms of materials, a material that is disposed above or below another material may be in direct contact or may have one or more intervening materials. Additionally, a material that is disposed between two materials may be in direct contact with the two layers or may have one or more intervening layers. In contrast, a first material on a second material is in direct contact with the second material. A similar distinction is made in the context of component assembly.

[0056] The term "between" may be used in the context of the z-axis, x-axis, or y-axis of a device. A material that is between two other materials may be in contact with one or both of those materials, or may be separated from both of the other two materials by one or more intervening materials. A material that is "between" two other materials may therefore be in contact with either of the other two materials, or may be coupled to the other two materials via an intervening material. A device that is between two other devices may be directly connected to one or both of those devices, or may be separated from both of the other two devices by one or more intervening devices.

[0057] Here, the multiple non-silicon semiconductor material layers may be stacked in a single fin structure. The multiple non-silicon semiconductor material layers may include one or more "p-type" layers suitable for p-type transistors (e.g., providing higher hole mobility than silicon). The multiple non-silicon semiconductor material layers may further include one or more "N-type" layers suitable for N-type transistors (e.g., providing higher electron mobility than silicon). The multiple non-silicon semiconductor material layers may further include one or more intervening layers separating the N-type layer from the p-type layer. The intervening layer may be at least partially sacrificial, for example, such that one or more of the gate, source, or drain may completely surround the channel region of one or more of the N-type and p-type transistors. The multiple non-silicon semiconductor material layers may be fabricated at least partially using self-aligned techniques, such that the stacked CMOS device may include both high mobility N-type and p-type transistors with the footprint of a single FET (field effect transistor).

[0058] Here, the term "back end" generally refers to the section of the die opposite the "front end" where the IC (integrated circuit) package is bonded to the IC die bumps. For example, the higher level metal layers (e.g., metal layers 6 and above in a 10 metal stack die) and corresponding vias proximate the die package are considered part of the back end of the die. Conversely, the term "front end" generally refers to the section of the die that includes the active area (e.g., where transistors are fabricated) and the lower level metal layers and corresponding vias proximate the active area (e.g., metal layers 5 and below in the example of a 10 metal stack die).

[0059] It is noted that elements of a figure having the same reference number (or name) as elements of any other figure may operate or function in a similar manner as described, but is not limited to such.

[0060] FIG. 1A shows a logic gate 100 having a three-input majority gate according to some embodiments. The logic gate 100 includes first, second and third drivers 101, 102 and 103, respectively. These drivers can be analog drivers that generate analog signals, or digital drivers that generate signals that toggle between ground and power rails, or a combination of analog or digital drivers. For example, the driver 101 is a CMOS driver such as a buffer, inverter, NAND gate, NOR gate, etc., while the driver 102 is an amplifier that generates a bias signal. The drivers provide input signals Vin1 (and current I1), Vin2 (and current I2) and Vin3 (and current I3) to three inputs of a three-input majority gate 104.

[0061] In various embodiments, the three-input majority gate 104 includes three input nodes Vin1, Vin2, and Vin3. Here, signal names and node names are used interchangeably. For example, Vin1 refers to node Vin1 or signal Vin1 depending on the context of the sentence. The three-input majority gate 104 further includes capacitors C1, C2, and C3. Here, resistors R1, R2, and R3 are wiring parasitic resistances coupled to the capacitors C1, C2, and C3, respectively. In various embodiments, the capacitors C1, C2, and C3 are non-ferroelectric capacitors. In some embodiments, the non-ferroelectric capacitors include one of a dielectric capacitor, a paraelectric capacitor, or a non-linear dielectric capacitor.

[0062] A dielectric capacitor includes first and second metal plates with a dielectric between them. Examples of such dielectrics are HfO, ABO3 perovskites, nitrides, oxyfluorides, oxides, etc.

[0063] The paraelectric capacitor includes first and second metal plates with a paraelectric material therebetween. In some embodiments, f-orbital materials (e.g., lanthanides) are doped into the ferroelectric material to create the paraelectric material. Examples of room temperature paraelectric materials include SrTiO3, Ba(x)Sr(y)TiO3 (where x is -0.5 and y is 0.95), HfZrO2, Hf-Si-O, La-substituted PbTiO3, and PMN-PT based relaxor ferroelectrics.

[0064] The dielectric capacitor includes first and second metal plates with a non-linear dielectric capacitance therebetween, with a dielectric constant ranging from 1.2 to 10000. Capacitors C1, C2 and C3 can be implemented as MIM (metal-insulator-metal) capacitor technology, transistor gate capacitors, metal capacitors or hybrid transistor capacitors.

[0065] One terminal of the capacitors C1, C2 and C3 is coupled to a common node cn. This common node is coupled to a node n1, which is coupled to a first terminal of a nonlinear polar capacitor 105. A majority function is performed on the common node cn and the resulting voltage is projected onto the capacitor 105. For example, the majority function of the currents (I1, I2 and I3) on the node cn results in a current that charges the capacitor 105. Table 1 shows the majority function f(majority Vin1, Vin2, Vin3). [Table 1]

[0066] The FE material capacitor (also called FEC) has a potential V F (Q F ) as a cubic function of its charge. FIG. 1C shows a plot 130 illustrating the characteristics of the FEC. The plot 130 shows the area (100 nm) 2 , 20 nm thick block f Pb(Zr 0.5 Ti 0.53 is a charge-voltage (QV) plot of O3. The plot is plotted with + / - V o Here, V c The term coercive voltage. When a charge V is applied across the FEC, the charge V>V o Otherwise the charge on the FEC is subject to hysteresis effects.

[0067] Referring back to FIG. 1A, in some embodiments, an odd number of N capacitors are combined into a single FEC to form a majority gate. In this case, N=3. FEC(Q F ) is the output of the majority gate. To solve the steady-state solution, the parasitic resistances are neglected and the input potential V i (or Vin) is assumed to be constant. In this case, the charge across each linear capacitor (C1, C2, C3) is:

number

[0068] Node C across FEC 105 n The charge added at is expressed as:

number

[0069] Here, C=Σ i C i is the sum of the capacitors. In the limit C → ∞, we achieve:

number

[0070] The potential across the FEC 105 is the average of all the input potentials weighted by the capacitances (eg, C1, C2 and C3).

[0071] C i= When C / N are all equal, V F is simply an average value.

[0072]

number

number

number

[0073] This means that the (N+1) / 2 input is +V s and (N-1) / 2 is -V s Then, V s >NV C ...(9)

[0074] The output of the majority gate at node n1 is represented by Figure 1D, which shows a plot 140 illustrating the output of a three-input majority gate, according to some embodiments.

[0075] As an example, if N=3, the possible inputs are:

number

[0076] Referring back to FIG. 1A, since capacitor 105 is a non-linear polarized capacitor, both terminals of the capacitor are pre-discharged to ground or a known predetermined voltage via n-type transistor, pull-down transistors MN1 and MN2, and a p-type pull-up transistor. The predetermined voltage may be programmable. The predetermined voltage may be positive or negative. In some embodiments, n-type transistor MN1 is coupled to node Vout_int1 (internal Vout node) and is controllable by a clock or reset signal Clk1. In some embodiments, n-type transistor MN2 is coupled to node Vout_int2 (internal Vout node) and is controllable by a clock or reset signal Clk2. In some embodiments, p-type transistor MP1 is coupled to node Vout_int2 and is controllable by Clk3b.

[0077] In some embodiments, n-type transistors MN1 and MN2 are replaced with p-type transistors while p-type transistor MP1 is replaced with an n-type transistor coupled to ground or the negative supply rail to precharge both terminals (Vout_int1 and Vout_int2) of capacitor 105 to a supply voltage or another predetermined voltage. The predetermined voltage may be programmable. The predetermined voltage may be positive or negative.

[0078] In some embodiments, the pre-charging or pre-discharging of the terminals of the capacitor 105 (or nodes cn and n1) is performed periodically by clock signals Clk1, Clk2, and Clk3b. The control can be a non-clocked signal generated by a control logic (not shown). For example, the control can be issued every predetermined or programmable time. In some embodiments, the clock signals Clk1, Clk2, and Clk3b are issued in a reset phase, followed by an evaluation phase, in which the inputs Vin1, Vin2, and Vin3 are received and a majority function is performed on them. FIG. 1E shows a timing diagram 190 for resetting the ferroelectric capacitors of the majority gates of FIGS. 1A-1B, according to some embodiments.

[0079] Clk1 has a pulse width greater than the pulse widths of Clk2 and Clk3b. Clk3b is the inverse of Clk3 (not shown). In some embodiments, Clk1 is asserted first to begin discharging node Vout_int1. While node Vout_int1 is being discharged, Clk2 is asserted. Clk2 may have a pulse width substantially half that of Clk1. When Clk2 is asserted, node Vout_int2 is discharged. This sequence ensures that both terminals of the nonlinear polar material of capacitor 105 are discharged consecutively. In various embodiments, before discharging node Vout_int2, Clk3b is deasserted to turn on transistor MP1, which will charge Vout_int2 to a predetermined value (e.g., a supply level). The pulse width of Clk3b is smaller than that of Clk1 to ensure that the pulsing of Clk3b occurs within the pulse window of Clk1. This is useful to ensure that the nonlinear polarized capacitor 105 is initialized to a known programmed state with the other capacitors (e.g., C1, C2, C3) initialized to 0V between them. The pulsing on Vout_int2 works in conjunction with Vout_int1 to create the correct magnetic field across the nonlinear polarized capacitor 105, putting it into the correct state, so that during the operating mode, when Vout_int1 goes higher than the Vc value (the coercive voltage value), it triggers the switching of the nonlinear polarized capacitor 105, which causes a voltage build up on Vout_int2.

[0080] In some embodiments, a load capacitor CL is added to node Vout_int2. In some embodiments, the load capacitor CL is a normal capacitor (e.g., a non-ferroelectric capacitor). The capacitance value of CL on Vout_int2 is useful to ensure that the FE switching charge (of the FE capacitor 105) provides the correct voltage level. For a given FE size (area A), the capacitance of CL with the polarization switching density (dP) and the desired voltage swing of Vdd (supply voltage) should be approximately CL=dP*A / Vdd. There is a small deviation from the above CL value because there is charge sharing on Vout_int2 due to the dielectric component of the FE capacitor 105. The charge sharing is responsive to the voltage on Vout_int1 and the capacitor division ratio between the dielectric component of the FE capacitor 105 and the load capacitor (CL). Note that the capacitance of CL may be the aggregation of all capacitances on the Vout_int2 node (e.g., parasitic routing capacitances on the node, the gate capacitance of the output stage 106, and the drain or source capacitance of the reset device (e.g., MN2, MP1)). In some embodiments, for a given size non-linear polarized capacitor 105, the CL requirement may be met by the load capacitance and parasitics of the non-FE logic 106 itself, and there may be no need to have it as a separate linear capacitor.

[0081] Referring back to FIG. 1A, in some embodiments, the nonlinear polar material of the capacitor 105 comprises one of a ferroelectric (FE) material, a paraelectric material, a relaxor ferroelectric, or a nonlinear dielectric. In various embodiments, the paraelectric material is the same as the FE material, but with chemical doping of the active ferroelectric ions with ions that have no polar distortion. In some cases, the nonpolar ions are non-s orbital ions formed with p, d, and / or f outer orbitals. In some embodiments, the nonlinear dielectric material is the same as a paraelectric material, a relaxor, and a dipolar glass.

[0082] In some embodiments, f-orbital materials (e.g., lanthanides) are doped into the ferroelectric material to make a paraelectric material. Examples of room temperature paraelectric materials include SrTiO3, Ba(x)Sr(y)TiO (where x is -0.5 and y is 0.95), HfZrO2, Hf-Si-O, La-substituted PbTiO3, and PMN-PT-based relaxor ferroelectrics.

[0083] In various embodiments, the FE material can be any suitable low voltage FE material that allows the FE material to switch its state by a low voltage (e.g., 100 mV). In some embodiments, the FE material includes an ABO3 type perovskite, where "A" and "B" are two cations of different sizes, and "O" is oxygen, an anion that bonds to both cations. In general, the atomic size of A is larger than the B atomic size. In some embodiments, the perovskite can be doped (e.g., by La or a lanthanide). The perovskite can be appropriately doped to achieve a natural strain in the range of 0.3-2%. For example, in the case of chemically substituted lead titanates, such as Zr in the Ti site; La, Nb in the Ti site, the concentrations of these substitutes are such as to achieve a natural strain in the range of 0.3-2%. For chemically substituted BiFeO3, BiCrO3, BiCoO3 class materials, La or rare earth substitutions on the Bi site can tune the natural strain.

[0084] The threshold of an FE material has a highly nonlinear transfer function in its polarization versus voltage response. The threshold is related to a) the nonlinearity of the switching transfer function and b) the squareness of the FE switching. The nonlinearity of the switching transfer function is the width of the derivative of the polarization versus voltage plot. The squareness is defined by the ratio of the remnant polarization to the saturation polarization, with perfect squareness exhibiting a value of 1.

[0085] The squareness of the FE switching can be appropriately manipulated by chemical substitution. For example, in PbTiO3, the PE (polarization-electric field) square loop can be modified by La or Nb substitution to create an S-shaped loop. The shape can be systematically tuned to ultimately produce a nonlinear dielectric. The squareness of the FE switching can also be varied by the granularity of the FE layer. A fully epitaxial single crystal FE layer will exhibit a higher squareness (e.g., ratio closer to 1) compared to polycrystalline FE. This perfect epitaxiality can be achieved by the use of lattice-matched bottom and top electrodes. In one example, BiFeO(BFO) can be epitaxially synthesized with a lattice-matched SrRuO3 bottom electrode resulting in a square PE loop. Stepwise doping with La reduces the squareness.

[0086] In some embodiments, the FE material is contacted with a conductive metal oxide, including one of the conductive perovskite metal oxides exemplified by La-Sr-CoO3, SrRuO3, La-Sr-MnO3, YBa2Cu3O7, Bi2Sr2CaCu2O8, LaNiO3, and ReO3.

[0087] In some embodiments, the FE material comprises a stack of layers including a low voltage FE material between (or sandwiched between) conductive oxides. In various embodiments, when the FE material is a perovskite, the conductive oxide is of the AA'BB'O3 type. A' is a dopant at atomic site A and can be an element of the lanthanide series. B' is a dopant at atomic site B and can be an element from the transition metal elements, in particular Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn. A' has the same valence as site A and has a different ferroelectric polarizability.

[0088] In some embodiments, the FE material comprises a hexagonal ferroelectric of h-RMnO3 type, where R is a rare earth element comprising one of cerium (Ce), dysprosium (Dy), erbium (Er), europium (Eu), gadolinium (Gd), holmium (Ho), lanthanum (La), lutetium (Lu), neodymium (Nd), praseodymium (Pr), promethium (Pm), samarium (Sm), scandium (Sc), terbium (Tb), thulium (Tm), ytterbium (Yb) or yttrium (Y). The ferroelectric phase is characterized by buckling of layered MnO5 polyhedra with displacement of Y ions, leading to net electric polarization. In some embodiments, the hexagonal FE comprises one of YMnO3 or LuFeO3. In various embodiments, when the FE material comprises a hexagonal ferroelectric, the conductive oxide adjacent to the FE material is of the A2O3 (e.g., In2O3, Fe2O3) and ABO3 type, where 'A' is a rare earth element and B is Mn.

[0089] In some embodiments, the FE material comprises an improper FE material. An improper ferroelectric is a ferroelectric whose primary order parameter is an order mechanism such as distortion or buckling of the atomic order. Examples of improper FE materials are the LuFeO3 class of materials or superlattices of ferroelectric and paraelectric materials PbTiO3 (PTO) and SnTiO3 (STO), respectively, and LaAlO3 (LAO) and STO, respectively. For example, a superlattice of [PTO / STO]n or [LAO / STO]n, where 'n' is 1 to 100. Although various embodiments are described with respect to ferroelectric materials for storing charge states, these embodiments are also applicable to paraelectric materials. For example, the capacitors of various embodiments may be formed using paraelectric materials instead of ferroelectric materials.

[0090] In some embodiments, the FE material comprises one of hafnium (Hf), zirconium (Zr), aluminum (Al), silicon (Si), an oxide thereof, or an alloyed oxide thereof. In some embodiments, the FE material comprises one of Al(1-x)Sc(x)N, Ga(1-x)Sc(x)N, Al(1-x)Y(x)N, or Al(1-xy)Mg(x)Nb(y)N, y-doped HfO2, where y contains one of Al, Ca, Ce, Dy, Er, Gd, Ge, La, Sc, Si, Sr, Sn or Y, where 'x' is fraction In some embodiments, the FE material includes bismuth ferrite (BFO), lead zirconate titanate (PZT), BFO with a doping material, or PZT with a doping material, where the doping material is one of a relaxor ferroelectric, such as Nb or PMN-PT.

[0091] In some embodiments, the FE material includes bismuth ferrite (BFO), BFO with a doping material, the doping material being one of lanthanum or any of the elements of the lanthanide series of the periodic table. In some embodiments, the FE material 105 includes lead zirconate titanate (PZT) or PZT with a doping material, the doping material being one of La or Nb. In some embodiments, the FE material includes a relaxor ferroelectric including one of lead magnesium niobate (PMN), lead magnesium niobate-lead titanate (PMN-PT), lead lanthanum zirconate titanate (PLZT), lead scandium niobate (PSN), barium titanium-bismuth zinc niobium tantalum (BT-BZNT), or barium titanium-strontium titanium (BT-BST).

[0092] In some embodiments, the FE material includes hafnium oxide of the form Hf1-xExOy, where E can be Al, Ca, Ce, Dy, Er, Gd, Ge, La, Sc, Si, Sr, Sn, or Y. In some embodiments, the FE material 105 includes a niobate compound LiNbO3, LiTaO3, lithium iron tantalum oxyfluoride, barium strontium niobate, sodium barium niobate, or potassium strontium niobate.

[0093] In some embodiments, the FE material comprises multiple layers, for example alternating layers of [Bi2O2]2+ and pseudo-perovskite blocks (Bi4Ti3O12 and related Aurivillius phases) and perovskite layers that are n-octahedral layers thick.

[0094] In some embodiments, the FE material comprises an organic material, such as polyvinylidene fluoride or polyvinylidene difluoride (PVDF).

[0095] The FE material is between two electrodes. These electrodes are conductive electrodes. In some embodiments, the electrodes are perovskite-type template conductors. In such template structures, a thin layer (e.g., about 10 nm) of a perovskite conductor (such as SrRuO3) is coated on IrO2, RuO2, PdO2, or PtO2 (non-perovskite structure, but with higher conductivity) to provide a seed or template for growing pure perovskite ferroelectrics at low temperatures. In some embodiments, when the ferroelectric comprises a hexagonal ferroelectric material, the electrodes can have a hexagonal metal, spinel, or cubic metal. Examples of hexagonal metals include PtCoO2, PdCoO2, and other delafossite-structured hexagonal metal oxides such as Al-doped ZnO. Examples of spinels include Fe3O4 and LiV2O4. Examples of cubic metals include indium tin oxide (ITO), such as Sn-doped In2O3.

[0096] The charge generated on node n1 generates a voltage and current that is the output of majority gate 104. Any suitable driver 106 may drive this output. For example, non-FE logic, FE logic, CMOS logic, BJT logic, etc. may be used to drive the output to downstream logic. Examples of drivers include inverters, buffers, NAND gates, NOR gates, XOR gates, amplifiers, comparators, digital-to-analog converters, analog-to-digital converters, etc. In some embodiments, the output "out" is reset by driver 106 via the Clk1 signal. For example, a NAND gate with one input coupled to Vout_int2 and the other input coupled to Clk1 may be used to reset "out" during the reset phase.

[0097] Although FIG. 1A shows a three-input majority gate, the same concept can be extended to more than two inputs to create an N-input majority gate, where N is greater than two.

[0098] FIG. 1B illustrates a logic gate 120 having a 5-input majority gate 124 according to some embodiments. The 5-input majority gate 124 is similar to the 3-input majority gate 104, but with additional inputs Vin4 and Vin5. These inputs can come from the same driver (e.g., any one of drivers 101, 102, 103) or from different drivers, such as drivers 121 and 122. The inputs Vin4 and Vin5 can be analog, digital, or a combination thereof. For example, Vin4 is a digital signal, while Vin5 is an analog signal. The additional inputs Vin4 and Vin5 are coupled to additional non-ferroelectric capacitors C4 and C5, respectively. The composition and size of the capacitors C4 and C5 are similar to the composition and size of C1, C2, and C3. Here, resistors R4, R5 are parasitic resistors.

[0099] The majority function is performed on a common node cn and the resulting voltage is projected onto the capacitor 105. For example, the majority function of the currents (I1, I2, I3, I4 and I5) on node cn produces a resultant current that charges the capacitor 105. Table 2 shows the majority function f(majority Vin1, Vin2, Vin3, Vin4, Vin5) of the 5-input majority gate 124. [Table 2] TIFF0007646840000010.tif144167

[0100] FIG. 1F illustrates a logic gate 180 having a three-input majority gate with a passgate-based reset mechanism, according to some embodiments. The logic gate 180 is similar to the logic gate 100, except that the reset mechanism resets the terminals of the nonlinear polarized capacitor 105. Here, the pull-down transistor MN2 is removed, and a passgate including a p-type transistor MP1 and an n-type transistor MN3 is coupled to the Vout_int2 node. In some embodiments, the transistor MN3 is controlled by Clk3, and the transistor MP1 is controlled by Clk3b, where Clk3b is the inverse of Clk3. In some embodiments, Vpulse passes through the passgate to Vout_int2 when Clk1 and Clk3 are asserted and before Clk1 and Clk3 are deasserted. Vpulse is generated during the reset phase and deasserted during the evaluation phase, as illustrated by FIG. 1G. FIG. 1G illustrates a timing diagram 170 for resetting the ferroelectric capacitor of the majority gate of FIG. 1F, according to some embodiments.

[0101] During the reset phase, node Vout_Int1 is first reset or discharged to ground by asserting a Clk1 pulse. In the same phase, transistors MP3 and MP1 are turned on and Vpulse is applied to node Vout_Int2.

[0102] Here, Vpulse eases the relative timing control in terms of signal generation. Vpulse also minimizes charge injection onto the Vout_int2 node due to the differential nature of the switching that occurs on the passgate. Note that the passgate reduces charge injection due to charge sharing, since the transistors MP1 and MN3 of the passgate nearly cancel the charge injection at the Vout_int2 node due to the switching event on the passgate. The gray dotted horizontal line shown relative to the Vout_int1(cn) node indicates where the Vc of the FE capacitor 105 creates the switching action. For majority gate designs, in some embodiments, this gray dotted horizontal line is placed near Vdd / 2 (e.g., Vc=Vdd / 2), where Vdd is a logic high value.

[0103] In some cases, when all inputs are 0 (e.g. Vin1=Vin2=Vin3=0 or Vss) (this is referred to as 3L), the voltage of Vout_int1 and / or Vout_int1 may fall below the Vss (or ground) level. It may also occur when all inputs are 1 (e.g. Vin1=Vin2=Vin3=1 or Vss) (this is referred to as 3H), in which case the voltage on Vout_int1 and / or Vout_int1 may rise above the Vdd (or supply) level. However, this may depend on the exact amount of charge injection at node cn at time 0 after the assertion of the input signal. Thus, all three inputs that are logic low (3L) are translated to slightly different levels compared to the two inputs that are logic low (2L). Here, 3H refers to all three inputs being high, 2H refers to two inputs being high and one input being low, and 1H refers to one input being high and two inputs being low. The same explanation is used for the nomenclature 3L, 2L and 1L. In the case of 1H, the voltage at nodes cn and n1 can be slightly higher than ground. The same is true for 3H, which translates to voltage levels at nodes cn and / or n1 that are slightly higher than in the cases of 2H and 1L.

[0104] Figure 1H shows a logic gate 180 having a three-input majority gate with an input reset mechanism according to some embodiments. In comparison with the reset mechanism described with reference to Figures 1A-1B and 1E-1G, here the inputs (e.g. Vin1, Vin2, Vin3) are blocked from propagating during the reset phase. Logic gate 180 is similar to logic gate 100, but differs in the determination of the input voltages during the reset of capacitor 105.

[0105] In some embodiments, for the reset mechanisms of Figures 1A-1B and 1E-1G, the logic generating the input signals (e.g., Vin1-Vin5) knows the reset timing and therefore ensures to send the correct input signal (0V in this figure) for processing when the capacitor 105 is being reset. Generating the input signals at a predetermined voltage level (e.g., 0V) ensures a predetermined voltage (e.g., 0V) across the linear capacitors (e.g., C1, C2, C3). Once such predetermined input signals are generated, pass gates at the input signal nodes can be removed to save area and cost.

[0106] In other embodiments of these multiple stages of majority gates between logic clusters, the reset sequence can be controlled from the input vector to accurately create the correct voltage levels during the reset phase in each one of these stages. In some embodiments, logic gates are provided at the inputs (e.g., Vin) so that the correct voltage levels in all stages drive the correct logic. For example, a NAND gate with one input being a reset signal and the other a logic level (e.g., Vin1) ensures that the correct voltage levels are applied to the inputs of each one of the stages during the reset phase. In another example, the output of each logic is adjusted during reset to cause the subsequent logic (e.g., majority gate logic) to receive the correct input voltage levels during reset. In one such example, the non-FE logic 106 includes a NAND gate with one of its inputs being a reset signal and the other input being a logic level (e.g., coupled to Vout_int2) to ensure that the correct voltage levels are propagated to the inputs of the next or subsequent majority gate stages during the reset phase.

[0107] In some embodiments, a first pass gate is coupled to a first capacitor C1 and a driver that generates a first input Vin1. The first pass gate includes a p-type transistor MP1r controllable by Clk1 and an n-type transistor MN1r controllable by Clk1b. The first pass gate blocks the propagation of Vin1, and a pull-down transistor MN2r can set the input to the capacitor C1 to ground via Clk1. In some embodiments, a second pass gate is coupled to a second capacitor C2 and a driver that generates a second input Vin2. The second pass gate includes a p-type transistor MP2r controllable by Clk1 and an n-type transistor MN2r controllable by Clk1b. The second pass gate blocks the propagation of Vin2, and a pull-down transistor MN3r can set the input to the capacitor C2 to ground via Clk1. In some embodiments, a third pass gate is coupled to a third capacitor C3 and a driver that generates a third input Vin3. The third passgate includes a p-type transistor MP3r controllable by Clk1 and an n-type transistor MN3r controllable by Clk1b. The third passgate blocks the propagation of Vin3, and a pull-down transistor MN4r can set the input to capacitor C3 to ground via Clk1. The same approach applies to the other inputs.

[0108] FIG. 1I shows a timing diagram 190 for resetting the ferroelectric capacitors of the majority gate of FIG. 1H, according to some embodiments. During the reset phase, Clk1 is asserted (Clkb is deasserted) to block the input voltage and set the inputs to capacitors C1, C2, and C3 to ground. The assertion of Clk1 also discharges Vout_int1. As a result, the voltages at both terminals of the input capacitors C1, C2, and C3 are discharged. Clk3b is first deasserted (during the reset phase) to turn on MP1 and precharge Vout_int2. Clk2 is then asserted to discharge Vout_int2.

[0109] The reset mechanism can be described by a two pulse sequence. The first sequence of pulses is to generate the correct magnetic field across the FE capacitor 105 and initialize it in the correct state for operation, while the second sequence of pulses ensures that all nodes are initialized to a 0 state and all linear caps (e.g., C1, C2, C3) have 0V across them. The correct sequence also allows for a glitch-less transition to minimize charge injection on high impedance nodes and ensures that the ferroelectric device 105 does not experience a transition due to the reset pulse that corrupts the initial programmed state of the FE device 105.

[0110] The reset mechanism of various embodiments can also be described in terms of four phases. In the first phase (phase 1), the linear capacitors (C1, C2, C3) are initialized to a zero state using Clk1 (e.g., by asserting Clk1) and input conditioning (e.g., setting inputs Vin1, Vin2, Vin3 to 0). In the second phase (phase 2), the FE capacitor 105 continues to be initialized using Clk3b (e.g., deasserting Clk3b) while keeping Clk1 high (e.g., Clk1 remains asserted). In the third phase (phase 3), the Vout_int2 node and the inductive component of the FE capacitor 105 are initialized to a zero state by deasserting Clk2 and asserting Clk3b, and while keeping Clk1 high (e.g., Clk1 remains asserted). In the fourth phase (phase 4), the reset switch is deactivated. For example, transistors MN1r, MP1r (and other passgate switches at the input) are turned on, MN2r (and other pulldown transistors) on the input nodes (e.g., Vin1, Vin2) are turned off, pulldown transistors MN1 and MN2 are disabled or turned off, pullup transistor MP1 is disabled or turned off, and the Vpulse passgate having transistors MP1 and MN3 is disabled.

[0111] Although the embodiments are described herein in relation to resetting the FE device 105 to ground and / or the two terminals of the non-ferroelectric linear capacitors (C1, C2, C3) to ground, the reset voltage can be a different voltage other than ground. For example, when the input signal (e.g., Vin1, Vin2, Vin3) toggles between a positive supply level and a negative supply level, then the two terminals of the FE device 105 and / or the two terminals of the non-ferroelectric linear capacitors (C1, C2, C3) are reset to the negative supply rail. For example, the definitions of logic low and logic high for controlling the various reset devices change to be positive and negative, respectively. Thus, if the previous rails were 0V and Vdd, and now they are negative to positive rails, 0V is mapped to negative and Vdd is mapped to positive.

[0112] 1J shows a plot 195 illustrating the voltage on node Vout_int2 in relation to the behavior of FE capacitor 105, according to some embodiments. In this case, FE capacitor 105 remains within a window of Vc voltage drop across FE capacitor 105, but switching helps to generate a different voltage on Vout_int2. For example, at time 0 during reset (when Clk1 is asserted and other signals such as Clk1b, Clk2, Clk3b, and Vpulse behave according to FIG. 1G and FIG. 1I), a large reset field drives FE capacitor 105 to a low state, and then FE capacitor 105 bounces between +Vc and −Vc.

[0113] FIG. 2A illustrates a logic gate 200 having a three-input threshold gate 204 that can operate as an AND or OR gate, according to some embodiments. The logic gate 200 is similar to the logic gate 100, except that it removes the third input Vin and adds an input Vbias. This additional input bias makes the logic gate a threshold gate 204. The threshold gate 204 is referred to as a three-input threshold gate because of the three inputs Vin1, Vin2, and Vbias. It can also be referred to as a two-input threshold gate if the Vbias input does not count as a separate input. In various embodiments, the threshold gate 204 includes an additional capacitor Cbias having one terminal coupled to the node cn and another terminal coupled to Vbias. The material of the capacitor Cbias can be the same as the material of the capacitors C1, C2, and C3. For example, the capacitor Cbias includes a non-ferroelectric material.

[0114] Vbias can be a positive or negative voltage depending on the desired logic function of the threshold gate 204. Any suitable source can generate Vbias. For example, a bandgap reference generator, a voltage divider such as a resistor divider, a digital-to-analog converter (DAC), etc. can generate Vbias. Vbias can be fixed or programmable (or adjustable). For example, Vbias can be adjusted by hardware (e.g., fuses, registers) or software (e.g., an operating system). In some embodiments, when Vbias is positive, the majority function on node cn is an OR function. For example, the function of node cn is OR(Vin1, Vin2, 0). In some embodiments, when Vbias is negative, the majority function on node cn is an AND function. For example, the function of node cn is AND(Vin1, Vin2, 1). Tables 2 and 3 summarize the functions of the threshold gate 206. [Table 3] [Table 4]

[0115] Compared to transition CMOS AND and OR logic gates, here the AND and OR functions are performed by a network of capacitors. The output of the majority or threshold function on node cn is then stored in a non-linear polarized capacitor 105. This capacitor provides the final state of the logic in a non-volatile form. Thus, the logic gate of various embodiments describes a non-volatile multi-input AND or OR gate with one or two transistors to pre-discharge or pre-charge nodes cn and n1. The silicon area of ​​the AND or OR gate of various embodiments is several orders of magnitude smaller than a conventional AND or OR gate. Although FIG. 2A shows a three-input threshold gate, the same concept can be extended to more than three inputs to make an N-input threshold gate, where N is greater than 2 and is an odd number. The reset mechanism of FIG. 2A is similar to that described with reference to FIG. 1A.

[0116] 2B illustrates a logic gate 220 having a three-input threshold gate with a passgate-based reset mechanism, according to some embodiments, where the three-input threshold gate can operate as an AND gate or an OR gate. Logic 220 is similar to logic 200, but differs in terms of the reset mechanism. The reset mechanism of FIG. 2B is similar to that described with reference to FIG. 1F.

[0117] 2C shows a logic gate 230 having a three-input threshold gate with an input reset mechanism according to some embodiments, where the three-input threshold gate can operate as an AND or OR gate. Logic 230 is similar to logic 200, but differs in terms of the reset mechanism. The reset mechanism of FIG. 2C is similar to the mechanism described with reference to FIG. 1H.

[0118] 2D illustrates a logic gate 240 having a 5-input AND / OR majority gate 222 that can operate as an AND gate or an OR gate with a majority function, according to some embodiments. For purposes of illustrating the 5-input AND / OR majority gate 222, the capacitances are Cbias=C3=C4=C / 2, C1=C, and C2=C, and the corresponding input potentials: Vbias=V B , Vin3=V A , Vin4=V B , Vin1=V C and Vin2=V s Here, V B =-V o is a constant bias voltage, and the rest is some V o About + / - V o are binary input voltages. Gate 222 has the function (A AND B,C,S), where the AND gate function is absorbed into the majority gate at the expense of the bias voltage.

[0119] Both are V s =V C =+V o If V A , V B Regardless of the magnitude of the output, the coercive voltage V c It is preferable that it is greater than V A =V B =-V o , the average potential is expressed as:

number

[0120] V A =V B =+V o , and V c =V d =-V o In this case, the following is achieved:

number

[0121] To check for equality with the AND operation, V A =-V B =V o Then we have:

number

[0122] By design, V A =V B =+V o According to some embodiments, gate 222 produces a positive output only when V o >7V c By setting C It is further observed that the

[0123] Here, an AND function is performed between Vin3 and Vin4, and the resulting output is used to perform a majority function on Vin1 and Vin2, which is written as: Majority(Vin3 AND Vin4, Vin1, Vin2). Table 5 shows the truth table for AND majority gate 222. Applying a negative voltage or bias van can also be equivalent to applying a logic low input signal. [Table 5]

[0124] For the OR majority function, an OR function is performed between Vin3 and Vin4, and the resulting output is used to perform a majority function on Vin1 and Vin2, which is written as: Majority(Vin3 OR Vin4, Vin1, Vin2). Table 6 shows the truth table for OR majority gate 222. Applying a positive voltage to Vbias can also be equivalent to applying a logic high input signal. [Table 6]

[0125] Logic gate 222 can perform AND and OR majority functions depending on the bias value for Vbias, where only two transistors (MN1 and MN2) are used that can be condensed into a single transistor to precharge or predischarge nodes cn and n1 while realizing the complex functions of AND and OR majority functions.

[0126] In various embodiments, majority gate 222 coupled to inverter 106 forms a minority threshold gate (majority inversion threshold), resulting in a universal logic gate.

[0127] Figure 3A shows waveforms 300 illustrating the operation of the three-input majority gate of Figure 1B, according to some embodiments. Figure 3A shows the majority function of inputs Vin1, Vin2, and Vin3.

[0128] 3B-3E show waveforms 320, 330, 340, and 350 illustrating the operation of a five-input threshold gate, each having a different Vbias value, according to some embodiments.

[0129] 4 illustrates combinational logic 400 including the logic gate of FIG. 1A with a 3D (three dimensional) view of a 3-input majority gate coupled to an inverter or buffer, according to some embodiments. Any of the reset mechanisms described herein (e.g., in connection with FIGS. 1A-1I) are applicable to logic 400.

[0130] In this example, capacitors C1 (401), C2 (402), and C3 (403) are MIM capacitors that receive inputs Vin1, Vin2, and Vin3 at their first terminals, respectively, from buffers or drivers 101, 102, and 103. However, other types of capacitors can be used. For example, the capacitors can be implemented using a metal-transistor hybrid. The second terminals of capacitors C1 (401), C2 (402), and C3 (403) are coupled to a common node interconnect 404 (Vout_int1). The outputs of drivers 101, 102, and 103 are Vin1d, Vin2d, and Vin3d, respectively. The interconnect 404 can be on any suitable metal layer. In some embodiments, the interconnect 404 includes a material including one or more of Cu, Al, Ag, Au, Co, or W. In some embodiments, capacitors C1 (401), C2 (402), and C3 (403) are formed on the back end of the die. In some embodiments, capacitors C1 (401), C2 (402), and C3 (403) are formed on the front end of the die. Interconnect 404 is coupled to a first terminal of nonlinear polar capacitor 105. In this example, capacitor 105 comprises a ferroelectric material and thus C FE However, other nonlinear polar materials described herein may be used to fabricate capacitor 105. A second terminal of capacitor 105 is coupled to node n1 (Vout_int2).

[0131] In some embodiments, the capacitor 105 is a pillar capacitor. A pillar capacitor is taller than it is wide, allowing for a compact layout in the z-direction. In one embodiment, capacitors C1 (401), C2 (402), and C3 (403) are fabricated under or directly beneath the pillar capacitor forming a vertical majority gate.

[0132] FIG. 5 shows a combinational logic 500 having the logic gate of FIG. 1B along with a 3D view of a 3-input threshold gate coupled to an inverter or buffer, according to some embodiments. Here, the 3-input threshold gate 204 is similar to the majority gate of FIG. 4, except that it removes the capacitor C3 and its associated input, and adds an extra capacitor 501 Cbias biased by Vbias. Vbias can be positive or negative. The various embodiments described in connection with FIG. 1B and FIG. 4 are applicable here. Any of the reset mechanisms described herein (e.g., in connection with FIG. 1A-FIG. 1I) are applicable to the logic 500.

[0133] FIG. 6 illustrates a low-power sequential circuit 600 (e.g., a latch) including a nonlinear polarized capacitor, according to some embodiments. In some embodiments, the sequential circuit 600 includes a data input (D), a clock input (Clk), a reset clock input (Clk1, Clk2, Clk3b), and an output (Q). In some embodiments, the sequential circuit 600 includes a load capacitor CL. The sequential circuit 600 includes an inverter 601, a pass gate 602, an inverter 603, an inverter 604, a nonlinear polarized capacitor 105, and transistors MN1 and MN2. The pass gate 602 includes an n-type transistor MNt and a p-type transistor MPt. The transistor MNt is controlled by Clk, while the transistor MPt is controlled by Clkb (the inverse of Clk). Here, node and signal names are used interchangeably. For example, Clk can refer to a clock signal or a clock node carrying a clock signal, depending on the context of the sentence.

[0134] In some embodiments, the pass gate 602 is replaced by a tri-statable inverter or a buffer. The data input D is inverted by the inverter 601. In some embodiments, the inverters 601 and 603 are replaced by buffers. The pass gate 602 is also coupled to the nonlinear polar capacitor 105. For example, the first terminal Dbd is coupled to the pass gate 602 or a tristate inverter (not shown), and the second terminal Qb is coupled to the input of the inverter 603. The output of the inverter 603 is Q. In some embodiments, the nonlinear polar capacitor 105 is implemented as two or more parallel nonlinear polar capacitors. In some embodiments, the nonlinear polar capacitor 105 is implemented as two or more series nonlinear polar capacitors. In some embodiments, an input capacitor Cin is coupled to the node Dbd. The capacitance value of the capacitor Cin depends on the parasitic capacitance on the node Dbd and the desired speed or timing of the latch 600.

[0135] In various embodiments, node Qb is a floating node, which can be grounded during logic operations by transistor MN2 to remove charge build-up. Similar to transistor MN1, in some embodiments, transistor MN1 is also used to discharge node Dbd. Nodes Dbd (same as Vout_in1) and Qb (same as Vout_int2) are reset according to the scheme described with reference to Figures 1A-1I using transistors MN1, MN2 and MP1. After the reset phase, latch 600 can perform normal operation.

[0136] Unlike conventional CMOS, the transistors of inverter 603 are not connected to the source or drain terminals when Clk=0. In various embodiments, nonlinear polar capacitor 105 is a ferroelectric capacitor. However, as mentioned herein, it may be a paraelectric capacitor or a nonlinear dielectric capacitor. In sequential circuit 600, ferroelectric capacitor 105 holds a charge, which can provide power to the gates of the transistors of inverter 603. For example, the charge on ferroelectric capacitor 105 (depending on its polarity) can turn off / on the p-type / n-type transistors of inverter 603.

[0137] When the clock Clk is 1 (e.g., a logic high value), the inverted input Dbd is allowed to flow through pass gate 602 to the ferroelectric capacitor 105, overriding any previously held charge on node Dbd and setting the ferroelectric charge to the inverse of the input D. The charge on the capacitor 105 (e.g., node Qb) is sent directly to inverter 603. In this case, the output Q is equal to the input D.

[0138] When the clock Clk is 0 (e.g., a logic low value) and the previous input was also 0, pass gate 602 is open and therefore cannot pass any voltage to ferroelectric capacitor 105. However, ferroelectric capacitor 105 retains a charge of 1 from the previous input of 0. This charge of 1 is reversed, so that output Q remains 0, regardless of the change to input D. Thus, the behavior of a sequential circuit (e.g., a latch) is achieved with just a few transistors and a ferroelectric capacitor.

[0139] Similarly, if the clock Clk is 0 and the previous input D was 1, the ferroelectric capacitor 105 holds a charge of 0 on node Qb and the output Q remains at 1, regardless of the logic state of the current input D. In some embodiments, the inverters 601, 602 and / or 603 can be replaced with NAND or NOR gates. These NAND or NOR gates can be implemented using threshold majority gates (AND and OR gates followed by inverter drivers). Thus, clock gating, scan data input multiplexing, gating and setting features based on other signals can be realized. In various embodiments, the nonlinear polarized capacitor 105 is formed or placed at the back end of the die, while the gates 601, 602, 603, 604 and / or other active devices of the transistors MN1, MN2 and MP1 can be formed at the front end of the die (e.g., in a CMOS process technology) or at the back end of the die (e.g., in a thin film transistor (TFT) process technology).

[0140] 7 illustrates a table 700 showing a truth table for the low power sequential circuit of FIG. 6, according to some embodiments. Table 700 illustrates three modes of operation: transparent, storage, and reset. During transparent mode, Clk is 1 and D is passed to output Q. During storage mode, Clk is 0 and output Q stores its previous value, i.e., Qn-1. During reset mode, Clk is 1 and Clk1 is also 1. In some embodiments, during the reset phase, Clk and D are adjusted to be 1.

[0141] 8A illustrates a low-power majority gate-based sequential circuit 800 (e.g., a latch) including a nonlinear polarized capacitor, according to some embodiments. Sequential circuit 800 includes a data input (D), a clock input (Clk), a reset clock input (Clk1, Clk2, Clk3b), and an output (Q). In some embodiments, sequential circuit 800 includes a three-input majority gate 801, a driver 802, and comparison logic 803.

[0142] The three-input majority gate 801 receives a data input D at its input node Vin, an output Qc of the comparison logic 803 at its input Vin2, and an output Q at its input Vin3. In some embodiments, the three-input majority gate 801 is the same as the gate 104 of FIG. 1A and FIG. 4. The three-input majority gate 801 performs a majority function on the input data D, the output Qc of the comparison logic 803, and the output Q. The result of the majority function is accumulated at a node cn (common node) and then stored in the nonlinear polar capacitor 105. The other terminal of the nonlinear polar capacitor 105 is a node n1. The voltage on the node n1 is driven out to the output node Q by the driver 802. The driver 802 can be any suitable driver. For example, the driver 802 is one of a buffer, an AND gate, an OR gate, an amplifier, and the like. In some embodiments, the pre-discharge transistors MN1 and MN2 (or their p-type equivalents for pre-charging nodes cn and / or n1) are controlled by a reset Rst signal.

[0143] In some embodiments, the comparison logic 803 compares the logic values ​​of the clock Clk and the output Q, and generates a logic 1 value for the output Qc when either Clk or Q has a logic 1 value. When the clock clk and the output Q have the same logic level, the comparison logic 803 generates a logic 0 value on node Qc. In various embodiments, the comparison logic 803 is an exclusive OR (XOR) gate. In some embodiments, the comparison logic 803 is an X-NOR. In other embodiments, other logic gates performing the functions described herein can be used. The embodiments are described herein with reference to a three-input majority gate, but may also be implemented using a threshold gate, as described with reference to FIG. 1B.

[0144] FIG. 8B illustrates a low-power majority gate-based flip-flop circuit 820 including a nonlinear polarized capacitor, according to some embodiments. In some embodiments, the flip-flop can be realized by a series combination of two latches 800, where a first latch 821 is an example of latch 800 and a second latch 822 is another example of latch 800. The output Q (labeled Q_int) of latch 821 is received as an input D of latch 822. Latch 821 behaves as a master latch, while latch 822 behaves as a slave latch. In various embodiments, a clock Clk is provided to a clock input Clk of latch 821, and its inverted version Clkb is provided to a clock input Clk of latch 822. In some embodiments, a NOR gate 823 is provided to generate an inverted version of Clkb by performing a NOR operation of Clk and Clk1. In some embodiments, during the reset phase (eg, when Clk1=1), Din and Clk are adjusted to zero to reset the non-linear polarized capacitors of latches 821 and 822.

[0145] FIG. 9 shows a schematic diagram 900 of the sequential circuit 800 of FIG. 8A according to some embodiments. Here, a three-input majority gate 801 is shown, which is the same as the majority gate 104, but differs in the Rst signal for controlling the pre-discharge transistors MN1 and MN2. In this example, the comparison logic 803 is shown as an XOR 803. The circuit 800 uses a ferroelectric majority gate 801 and an XOR gate 803 to create another D-flip-flop. The majority gate uses a buffer, and the output Q is connected directly to the source or drain of the buffer transistor, not to a ferroelectric, so that the output Q can be safely fed back to the gate 801 via the input Vin3 of the gate 801.

[0146] The function of the circuit 800 can be expressed as follows:

number

[0147] After the clock signal clk is set to 1, the previous output Q is still fed back to the circuit 801 before updating Qc. Due to the clock input of 1, Qc and Vin3 (or Q) will always be inverted, regardless of what the previous Q value was. This function can be expressed as:

number

[0148] If input D=1 and previous output Q=1, majority gate 801 has inputs (Vin1=1, Vin2=0, Vin3=1) that average to output 1 on common node cn. This output 1 propagates through capacitor 105 to output Q.

[0149] If input D=1 and previous output Q=0, majority gate 801 has inputs (Vin1=1, Vin2=1, Vin3=0) that average to output 1 on common node cn. This new output propagates through capacitor 105 to output Q.

[0150] If the input D=0 and the previous output Q=0, the majority gate 801 has inputs (Vin1=0, Vin2=1, Vin3=0) that on average output 0 on the common node cn. If the input D=0 and the previous output Q=1, the majority gate 801 has inputs (Vin1=0, Vin2=0, Vin3=1) that on average output 0 on the common node cn. This new output propagates through the capacitor 105 to the output Q.

[0151] In contrast, when the clock Clk is 0, Qc and Vin3 (or Q) are always equal to the previous output Q. Since Qc and Vin3 form the majority of majority gate 801, the output of majority gate 801 is equal to the previous output regardless of input D. This function is expressed as follows:

number

[0152] Table 7 provides a truth table for the operation of latch 900. [Table 7]

[0153] When Clk is 1, data D determines the output value regardless of the previous state. When Clk is 0, Qn-1 is returned to Qn, and thus latch 900 is in storage mode. During reset, Clk, D, and Qn are adjusted to 0 for correct operation. As mentioned above, adjustment can be done by ensuring that the circuits driving Clk and D force 0 during the reset phase. Adjustment can also be done by breaking paths and putting pull-down reset logic. In some embodiments, for the feedback path, Qn is forced to 0 during the reset phase (Clk1 is high) to ensure correct function. Forcing Qn to 0 can split the buffer at the output into an inverter 802a and a NOR gate 802a, where the other input of the NOR gate is Clk1. Note that Qn and Qn-1 are simply different states of node Q. Qn-1 is the node just before the input transition is applied, and Qn is the current state.

[0154] FIG. 10 illustrates a system-on-chip (SOC) using low-voltage sequential circuits (e.g., 600, 800, 820) according to some embodiments. The SOC 1000 includes memory 1001 having static random access memory (SRAM) or FE-based random access memory FE-RAM or other suitable memory. The memory can be non-volatile (NV) or volatile memory. The memory 1001 can also include logic 1003 for controlling the memory 1002. For example, write and read drivers are part of the logic 1003. These drivers and other logic are implemented using majority gates or threshold gates of various embodiments. The logic can include majority gates or threshold gates and conventional logic (e.g., CMOS-based NAND, NOR, etc.).

[0155] The SOC further comprises a memory I / O (input-output) interface 1004. The interface may be a double data rate (DDR) compliant interface or any other suitable interface for communicating with the processor. The processor 1005 of the SOC 1000 may be a single-core or multi-core processor. The processor 1005 may be a general-purpose processor (CPU), a digital signal processor (DSP), or an application-specific integrated circuit (ASIC) processor. In some embodiments, the processor 1005 is an artificial intelligence (AI) processor (e.g., a dedicated AI processor, a graphics processor configured as an AI processor).

[0156] AI is a broad area of ​​hardware and software computation in which data is analyzed, classified, and then decisions are made on the data. A model, e.g. describing the classification of data with respect to a characteristic or characteristics, is trained over time with a large amount of data. The process of training a model requires a large amount of data and processing power to analyze the data. When a model is trained, the weights or weighting coefficients are modified based on the output of the model. Once the weights of the model are calculated to a high confidence level (such as 95% or higher) by repeatedly analyzing the data and modifying the weights to obtain the expected results, the model is considered to be "trained". This trained model with fixed weights is then used to make decisions on new data. Training a model and then applying the trained model to new data is a hardware intensive activity. In some embodiments, the AI ​​processor 405 reduces the latency of computing and using the training model, which reduces the power consumption of such an AI processor system.

[0157] The processor 1005 may be coupled to multiple other chiplets, which may be on the same die as the SOC 1000 or on a separate die. These chiplets include connection circuits 1006, an I / O controller 1007, power management 1008, and a display system 1009 and peripheral connections 1100.

[0158] The connection 1006 represents hardware devices and software components for communicating with other devices. The connection 1006 may support various connection circuits and standards. For example, the connection 1006 may support a global system for mobile communications (GSM) or variants or derivatives, a code division multiplexing (CDMA) or variants or derivatives, a time division multiplexing (TDM) or variants or derivatives, a 3rd Generation Partnership Project (3GPP) Universal Mobile Telecommunications System (UMTS) system or variants or derivatives, a 3GPP Long Term Evolution (LTE) system or variants or derivatives, a 3GPP LTE-Advanced (LTE-A) system or variants or derivatives, a fifth generation (5G) wireless system or variants or derivatives, a 5G mobile network system or variants or derivatives, a 5G New Radio (NR) system or variants or derivatives, or other cellular service standards. In some embodiments, the connection 1006 may support non-cellular standards such as WiFi.

[0159] The I / O controller 1007 represents hardware devices and software components associated with interacting with a user. The I / O controller 1007 is operable to manage hardware that is part of the audio subsystem and / or the display subsystem. For example, input via a microphone or other audio device can provide input or commands for one or more applications or functions of the SOC 1000. In some embodiments, the I / O controller 1007 represents a connection point for additional devices that connect to the SOC 1000 through which a user can interact with the system. For example, devices that can be attached to the SOC 1000 can include a microphone device, a speaker or stereo system, a video system or other display device, a keyboard or keypad device, or other I / O devices for use in a particular application, such as a card reader or other device.

[0160] Power management 1008 represents hardware or software that performs power management operations based at least in part on receiving measurements from, for example, power measurement circuitry, temperature measurement circuitry, battery charge level, and / or any other suitable information that may be used for power management. Non-volatility is achieved in the output of these logics through the use of majority and threshold gates of various embodiments. Thus, power management 1008 may put such logic into a low power state without concern of losing data. Power management may select a power state for one or all components of SOC 1000 according to the Advanced Configuration and Power Interface (ACPI) specification.

[0161] Display system 1009 represents hardware (e.g., display devices) and software (e.g., drivers) components that provide a visual and / or tactile display for a user to interact with processor 1005. In some embodiments, display system 1009 includes a touch screen (or touch pad) device that provides both output and input to a user. Display system 1009 may include a display interface, which includes the particular screen or hardware device used to provide a display to a user. In some embodiments, the display interface includes logic separate from processor 1105 for performing at least some processing related to the display.

[0162] Peripheral connections 1010 may represent hardware and / or software devices for connecting to peripheral devices such as printers, chargers, cameras, etc. Peripheral connections 1010 may support communication protocols such as Peripheral Component Interconnect Express (PCIe), Universal Serial Bus (USB), Thunderbolt, High Definition Multimedia Interface (HDMI), Firewire, etc.

[0163] References herein to "an embodiment," "one embodiment," "some embodiments," or "other embodiments" mean that a particular feature, structure, or characteristic described in connection with an embodiment is included in at least some embodiments, but not necessarily all embodiments. The various occurrences of "an embodiment," "one embodiment," or "some embodiments" do not necessarily all refer to the same embodiment. When a component, feature, structure, or characteristic is described as "may," "might," or "could" be included in this specification, that particular component, feature, structure, or characteristic need not be included. When the specification or claims refer to "a" or "an" element, it does not mean that only one of the element is present. When the specification or claims refer to "additional" elements, it does not preclude two or more of the additional elements from being present.

[0164] Furthermore, the particular features, structures, functions, or characteristics may be combined in any suitable manner in one or more embodiments. For example, a first embodiment may be combined with a second embodiment whenever particular features, structures, functions, or characteristics associated with the two embodiments are not mutually exclusive.

[0165] While the present disclosure has been described in conjunction with specific embodiments thereof, many alternatives, modifications, and variations of such embodiments will be apparent to those skilled in the art in light of the foregoing description, and the embodiments of the present disclosure are intended to embrace all such alternatives, modifications, and variations that fall within the broad scope of the appended claims.

[0166] In addition, well-known power / ground connections to integrated circuit (IC) chips and other components may or may not be shown in the presented diagrams for ease of illustration and explanation, and so as not to obscure the present disclosure. Furthermore, the layout may be shown in a block diagram to avoid obscuring the present disclosure, and also taking into account the fact that details regarding the implementation of such block diagram layouts are highly dependent on the platform on which the present disclosure is implemented (i.e., such details should be well within the knowledge of one of ordinary skill in the art). Where specific details (e.g., circuits) are described to explain exemplary embodiments of the present disclosure, it will be apparent to one of ordinary skill in the art that the present disclosure can be practiced without these specific details or with variations of these specific details. Thus, the description should be considered as illustrative, rather than limiting.

[0167] The following examples are provided to illustrate various embodiments. The examples can be combined with other examples. Thus, various embodiments can be combined with other embodiments without changing the scope of the invention.

[0168] Example 1: An apparatus comprising: a three-input majority logic gate including first, second and third non-ferroelectric capacitors receiving a first input, a second input and a third input, respectively, and a non-linear polarized capacitor for storing a majority function output of the first, second and third inputs, one terminal of the non-linear polarized capacitor providing an output of the three-input majority logic gate; a driver coupled to the output of the three-input majority logic gate, the driver generating an amplified output of the three-input majority logic gate, the amplified output being coupled to a third input; and comparison logic receiving an input clock and the amplified output, the output of the comparison logic being the second input.

[0169] Example 2: In the apparatus of example 1, said first input is a data input.

[0170] Example 3: The apparatus of example 1, wherein the driver includes one of a buffer, an amplifier, a NAND, an AND, an OR, a multiplexer, or a NOR logic gate, and the comparison logic includes an exclusive OR (XOR) gate.

[0171] Example 4: The device of Example 1, further comprising: a first transistor coupled to a first terminal of the nonlinear polar capacitor, the first transistor being controllable by a first clock; a second transistor coupled to a second terminal of the nonlinear polar capacitor, the second transistor being controllable by a second clock; and a third transistor coupled to the second terminal of the nonlinear polar capacitor, the third transistor being controllable by a third clock.

[0172] Example 5: In the device of example 4, the first clock has a pulse width greater than the pulse width of the second clock and the pulse width of the third clock.

[0173] Example 6: In the device of example 4, the third clock is deasserted prior to the assertion of the second clock.

[0174] Example 7: The device of example 4, wherein the first transistor is a first n-type transistor, the second transistor is a second n-type transistor, and the third transistor is a p-type transistor.

[0175] Example 8: The apparatus of example 4, wherein the first transistor, the second transistor, and the third transistor are disabled in an evaluation phase and enabled in a reset phase, the reset phase preceding the evaluation phase.

[0176] Example 9: In the device of example 4, the first and second clocks are the same, and the first and second clocks are reset signals.

[0177] Example 10: The apparatus of example 4, wherein the first and second clocks are different signals.

[0178] Example 11: The apparatus of Example 1 includes a first driver that generates the first input and a second driver that generates the input clock.

[0179] Example 12: The apparatus of example 11, wherein the first and second drivers include CMOS transistors.

[0180] Example 13: In the device of Example 1, the first, second, and third non-ferroelectric capacitors of the three-input majority logic gate include one of a metal-insulator-metal (MIM) capacitor, a transistor gate capacitor, a hybrid of metal and transistor capacitor, or a capacitor including a paraelectric material.

[0181] Example 14: The device of example 1, wherein the nonlinear polarized capacitor comprises one of a ferroelectric material, a paraelectric material, or a nonlinear dielectric material.

[0182] Example 15: The device of example 14, wherein the ferroelectric material comprises one of the following: bismuth ferrite (BFO), BFO with a doping material, where the doping material comprises lanthanum or one of the elements of the lanthanide series of the periodic table; Lead zirconate titanate (PZT), or PZT with a doping material, where the doping material includes one of La or Nb; The relaxor ferroelectric includes one of lead magnesium niobate (PMN), lead magnesium niobate-lead titanate (PMN-PT), lead lanthanum zirconate titanate (PLZT), lead scandium niobate (PSN), barium titanium-zinc niobium tantalum (BT-BZNT) or barium titanium-barium strontium titanium (BT-BST); The perovskite ferroelectric includes one of BaTiO3, PbTiO3, KNbO3, or NaTaO3; The hexagonal ferroelectric includes one of YMnO3 or LuFeO3; h-RMnO3 type hexagonal ferroelectric, where R is a rare earth element comprising one of cerium (Ce), dysprosium (Dy), erbium (Er), europium (Eu), gadolinium (Gd), holmium (Ho), lanthanum (La), lutetium (Lu), neodymium (Nd), praseodymium (Pr), promethium (Pm), samarium (Sm), scandium (Sc), terbium (Tb), thulium (Tm), ytterbium (Yb) or yttrium (Y); Hafnium (Hf), zirconium (Zr), aluminum (Al), silicon (Si), their oxides or their alloy oxides; Hafnium oxides of the form Hf1-x Ex Oy, where E can be Al, Ca, Ce, Dy, Er, Gd, Ge, La, Sc, Si, Sr, Sn, or Y; Al(1-x)Sc(x)N, Ga(1-x)Sc(x)N, Al(1-x)Y(x)N or Al(1-xy)Mg(x)Nb(y)N, y-doped HfO2, where y contains one of Al, Ca, Ce, Dy, Er, Gd, Ge, La, Sc, Si, Sr, Sn or Y, and 'x' is fraction (fraction); Niobate compounds LiNbO3, LiTaO3, lithium iron tantalum oxyfluoride, barium strontium niobate, sodium barium niobate or potassium strontium niobate; or The improper ferroelectric includes one of [PTO / STO]n or [LAO / STO]n, where 'n' is 1-100.

[0183] Example 16: The device of example 1, wherein the nonlinear polarized capacitor is located at a back end of a die, and the driver and comparison logic transistors are located at a front end of the die.

[0184] Example 17: An apparatus comprising: a three-input majority gate having a first input, a second input, and a third input and a first output; a driver coupled to the first output, the driver generating a second output; and comparison logic receiving a clock and the second output, the comparison logic generating a third output coupled to the second input, the first input receiving data and the third input receiving the second output.

[0185] Example 18: In the device of Example 17, the three-input majority gate comprises first, second and third non-ferroelectric capacitors coupled to the first input, the second input and the third input, respectively, and a non-linear polar capacitor for storing a majority function output of the first input, the second input and the third input, one terminal of the non-linear polar capacitor providing the first output.

[0186] Example 19: The apparatus of example 17, wherein the driver includes one of a buffer, an amplifier, a NAND, an AND, an OR, a multiplexer, or a NOR logic gate, and the comparison logic includes an exclusive OR (XOR) gate.

[0187] Example 20: The device of Example 18, further comprising: a first transistor coupled to a first terminal of the nonlinear polar capacitor, the first transistor being controllable by a first signal; a second transistor coupled to a second terminal of the nonlinear polar capacitor, the second transistor being controllable by a second signal; and a third transistor coupled to the second terminal of the nonlinear polar capacitor, the third transistor being controllable by a third signal.

[0188] Example 21: The apparatus of example 20, wherein the first signal has a pulse width greater than a pulse width of the second signal and a pulse width of the third signal.

[0189] Example 22: The apparatus of example 20, wherein the third signal is deasserted prior to the assertion of the second signal.

[0190] Example 23: The device of example 20, wherein the first transistor is a first n-type transistor, the second transistor is a second n-type transistor, and the third transistor is a p-type transistor.

[0191] Example 24: The device of example 20, wherein the first transistor, the second transistor, and the third transistor are disabled in an evaluation phase and enabled in a reset phase, the reset phase preceding the evaluation phase.

[0192] Example 25: A system comprising: a processor; a communication interface communicatively coupled to the processor; and a memory coupled to the processor, the processor comprising a sequential circuit comprising: a three-input majority gate having a first input, a second input, and a third input and a first output; a driver coupled to the first output, the driver generating a second output; and comparison logic receiving a clock and the second output, the comparison logic generating a third output coupled to the second input, the first input receiving data and the third input receiving the second output.

[0193] Example 26: In the system of Example 25, the three-input majority gate comprises first, second and third non-ferroelectric capacitors respectively coupled to the first input, the second input and the third input, and a non-linear polar capacitor for storing a majority function output of the first input, the second input and the third input, one terminal of the non-linear polar capacitor providing the first output, and the comparison logic includes an exclusive OR (XOR) gate.

[0194] The Abstract is provided to allow the reader to ascertain the nature and gist of the present technical disclosure. It is submitted with the understanding that it will not be used to limit the scope or meaning of the claims. The following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate embodiment.

Claims

1. A three-input majority logic gate, first, second and third non-ferroelectric capacitors receiving the first input, the second input and the third input, respectively; a non-linear polarized capacitor for storing a majority function output of said first, second and third inputs, one terminal of said non-linear polarized capacitor providing an output of said three-input majority logic gate; said three-input majority logic gate including: a driver coupled to the output of the three-input majority logic gate, the driver generating an amplified output of the three-input majority logic gate, the amplified output being coupled to the third input; comparison logic receiving an input clock and the amplified output, the output of a gate of the comparison logic being the second input; An apparatus comprising:

2. the first input is a data input; 2. The apparatus of claim 1.

3. the driver comprises one of a buffer, an amplifier, a NAND, an AND, an OR, a multiplexer, or a NOR logic gate, and the comparison logic comprises an exclusive OR (XOR) gate; 3. Apparatus according to claim 1 or 2.

4. a first transistor coupled to a first terminal of the nonlinear polar capacitor, the first transistor being controllable by a first clock; a second transistor coupled to a second terminal of the nonlinear polarized capacitor, the second transistor being controllable by a second clock; a third transistor coupled to the second terminal of the nonlinear polarized capacitor, the third transistor being controllable by a third clock; 3. The apparatus of claim 1 or 2, comprising:

5. the first clock has a pulse width greater than a pulse width of the second clock and a pulse width of the third clock; the third clock is deasserted prior to the assertion of the second clock; the first transistor is a first n-type transistor, the second transistor is a second n-type transistor, and the third transistor is a p-type transistor; the first transistor, the second transistor, and the third transistor are disabled during an evaluation phase and enabled during a reset phase, the reset phase preceding the evaluation phase; or the first and second clocks are identical and the first and second clocks are reset signals; or the first and second clocks being different signals; 5. The apparatus of claim 4.

6. a first driver generating the first input; a second driver for generating the input clock; 3. The apparatus according to claim 1 or 2, comprising:

7. the first and second drivers include CMOS transistors; 7. The apparatus of claim 6.

8. the first, second and third non-ferroelectric capacitors of the three-input majority logic gate comprise one of a metal-insulator-metal (MIM) capacitor, a transistor gate capacitor, a hybrid metal-transistor capacitor or a capacitor comprising a paraelectric material; 3. Apparatus according to claim 1 or 2.

9. the nonlinear polar capacitor comprises one of a ferroelectric material, a paraelectric material, or a nonlinear dielectric material; 3. Apparatus according to claim 1 or 2.

10. The ferroelectric material comprises one of the following: bismuth ferrite (BFO) having a first doping material, where the first doping material comprises lanthanum or one of the elements of the lanthanide series of the periodic table; Lead zirconate titanate (PZT), or PZT with a second doping material, where the second doping material includes one of La or Nb; a relaxor ferroelectric comprising one of lead magnesium niobate (PMN), lead magnesium niobate-lead titanate (PMN-PT), lead lanthanum zirconate titanate (PLZT), lead scandium niobate (PSN), barium titanium-zinc niobium tantalum (BT-BZNT) or barium titanium-barium strontium titanium (BT-BST); Perovskite ferroelectrics, including one of BaTiO3, PbTiO3, KNbO3, or NaTaO3; hexagonal ferroelectrics, including one of YMnO3 or LuFeO3; h-RMnO3 type hexagonal ferroelectric, where R is a rare earth element including one of cerium (Ce), dysprosium (Dy), erbium (Er), europium (Eu), gadolinium (Gd), holmium (Ho), lanthanum (La), lutetium (Lu), neodymium (Nd), praseodymium (Pr), promethium (Pm), samarium (Sm), scandium (Sc), terbium (Tb), thulium (Tm), ytterbium (Yb) or yttrium (Y); Hafnium (Hf), zirconium (Zr), aluminum (Al), silicon (Si), their oxides or their alloy oxides; Hafnium oxides of the type Hf1-x Ex Oy, where E can be Al, Ca, Ce, Dy, Er, Gd, Ge, La, Sc, Si, Sr, Sn, or Y; Al(1-x)Sc(x)N, Ga(1-x)Sc(x)N, Al(1-x)Y(x)N or Al(1-xy)Mg(x)Nb(y)N, y-doped HfO2, where y comprises one of Al, Ca, Ce, Dy, Er, Gd, Ge, La, Sc, Si, Sr, Sn or Y, and 'x' is a fraction; Niobate compounds LiNbO3, LiTaO3, lithium iron tantalum oxyfluoride, barium strontium niobate, sodium barium niobate or potassium strontium niobate; or an irregular ferroelectric material comprising one of [PTO / STO]n or [LAO / STO]n, where 'n' is 1 to 100; 10. The apparatus of claim 9.

11. the nonlinear polarized capacitor is located on a back end of a die and the driver and comparison logic transistors are located on a front end of a die.

3. Apparatus according to claim 1 or 2.

12. An apparatus comprising: a three-input majority gate having a first input, a second input and a third input, and a first output; a driver coupled to the first output, the driver generating a second output; comparison logic receiving a clock and the second output, the comparison logic generating a third output coupled to the second input, the first input receiving data and the third input receiving the second output; Equipped with The three-input majority gate is first, second and third non-ferroelectric capacitors coupled to the first input, the second input and the third input, respectively; a nonlinear polarized capacitor for storing a majority function output of the first input, the second input, and the third input; one terminal of the nonlinear polarized capacitor providing the first output. Device.

13. the driver comprises one of a buffer, an amplifier, a NAND, an AND, an OR, a multiplexer, or a NOR logic gate, and the comparison logic comprises an exclusive OR (XOR) gate; 13. The apparatus of claim 12.

14. a first transistor coupled to a first terminal of the nonlinear polarized capacitor, the first transistor being controllable by a first signal; a second transistor coupled to a second terminal of the nonlinear polarized capacitor, the second transistor controllable by a second signal; a third transistor coupled to the second terminal of the nonlinear polarized capacitor, the third transistor controllable by a third signal; The apparatus of claim 12 , comprising:

15. the first signal has a pulse width greater than a pulse width of the second signal and a pulse width of the third signal; the third signal is deasserted prior to the assertion of the second signal; the first transistor is a first n-type transistor, the second transistor is a second n-type transistor, and the third transistor is a p-type transistor; or the first transistor, the second transistor, and the third transistor are disabled during an evaluation phase and enabled during a reset phase, the reset phase preceding the evaluation phase.

15. The apparatus of claim 14.

16. 1. A system comprising: A processor; a communication interface communicatively coupled to the processor; a memory coupled to the processor; A system, wherein the processor comprises a sequential circuit according to any one of claims 1 to 11.

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