Selective contact area recessed solar cell and rear contact structure thereof

Abstract

The present invention is applied to the technical field of solar cells, and provides a selective contact region embedded solar cell and its back contact structure, which includes a recess on the back surface of a silicon substrate, a first dielectric layer on the back surface of the silicon substrate, a first doped region on the first dielectric layer and in the recess, a second doped region on the first dielectric layer and outside the recess, at least one second dielectric layer between the first doped region and the second doped region, and a conductive layer on the first doped region and the second doped region. The back contact structure provided by the present invention solves the problems of the high requirements for trench width control and the poor passivation effect of the conventional technology.

Description

[Technical field]

[0001] The present invention relates to the technical field of solar cells, and in particular to a selective contact area recessed solar cell and its back contact structure. [Background technology]

[0002] In crystalline silicon solar cells, the efficiency loss of the cell can be divided into two parts: electrical loss and optical loss. An important component of the electrical loss is the composite loss and resistive loss caused by the contact between metal and semiconductor, and an important component of the optical loss is the shading by the metal grid lines on the light-receiving surface.

[0003] Here, the passivation metal contact structure has outstanding electrical performance and is compatible with low contact resistivity and low surface complexation. This structure consists of an ultra-thin tunneling oxide layer and an N-type or P-type doped polysilicon layer. Since the light absorption by the doped polysilicon layer is "parasitic", i.e., it does not contribute to the photo-generated current, the passivation metal contact structure is often used on the back side of the cell, which completely avoids the shading by metal grid lines on the front surface. The solar radiation received by the solar cell generates electrons and holes, which migrate to the doped polysilicon layer, generating a voltage difference between the doped polysilicon layers.

[0004] Conventional P-type doped polycrystalline silicon layers and N-type doped polycrystalline silicon layers are directly deposited on the back surface of a silicon wafer, but if they are connected to each other without being isolated, problems such as leakage current will occur. Therefore, in order to solve the above problem caused by no isolation, a very narrow trench is formed between the P-type doped polycrystalline silicon layer and the N-type doped polycrystalline silicon layer, thereby isolating the P-type doped polycrystalline silicon layer and the N-type doped polycrystalline silicon layer, thereby avoiding the occurrence of leakage current and reducing the open circuit voltage of the battery. However, conventional trenches are manufactured by laser drilling or wet etching. In this case, the conventional trench width is about several tens of μm, and the requirements for width control are high, so the manufacturing difficulty is high, and only a single dielectric layer is used for passivation. However, passivation by a single dielectric layer is inferior in passivation effect, and the internal back surface reflection effect obtained thereby is also inferior. Summary of the Invention

[0005] SUMMARY OF THE PRESENT EMBODIMENT An object of the present invention is to provide a back contact structure for a solar cell to solve the problems of high requirements for trench width control and poor passivation effect in the conventional technology.

[0006] An embodiment of the present invention comprises: a recess provided on a rear surface of the silicon substrate; a first dielectric layer provided on a rear surface of the silicon substrate; a first doped region disposed in the first dielectric layer and within the recess; a second doped region in the first dielectric layer outside the recess; at least one second dielectric layer disposed between the first doped region and the second doped region; and a conductive layer disposed on the first doped region and the second doped region.

[0007] Furthermore, the first doped region is a P-type doped region and the second doped region is an N-type doped region; or The first doped region is an N-type doped region and the second doped region is a P-type doped region.

[0008] Furthermore, the second doped region is provided in a portion outside the recess.

[0009] Furthermore, the sum of the thicknesses of the first dielectric layer and the first doped region disposed within the recess is equal to or less than the depth of the recess.

[0010] Furthermore, the sum of the thicknesses of the first dielectric layer and the first doped region disposed within the recess is greater than the depth of the recess.

[0011] Furthermore, the first doped region and the second doped region include doped polycrystalline silicon, or doped silicon carbide, or doped amorphous silicon.

[0012] Furthermore, the first dielectric layer is a combination of one or more of a tunneling oxide layer, an intrinsic silicon carbide layer, and an intrinsic amorphous silicon layer.

[0013] Furthermore, the second dielectric layer is a combination of one or more of an aluminum oxide layer, a silicon nitride layer, a silicon oxynitride layer, an intrinsic silicon carbide layer, an intrinsic amorphous silicon layer, and a silicon oxide layer.

[0014] Furthermore, the second dielectric layer may cover the area between the first doped region and the second doped region or may extend to cover the first doped region and / or the second doped region.

[0015] Furthermore, the rear surface of the silicon substrate located in the region between the first doped region and the second doped region has a rough texture structure.

[0016] Furthermore, the width of the P-type doped region is 300 to 600 μm, the width of the N-type doped region is 100 to 500 μm, and the depth of the recess is 0.01 to 10 μm.

[0017] Furthermore, the horizontal distance between the first doped region and the second doped region is 0 to 500 μm.

[0018] Furthermore, the first dielectric layer covers the first doped region and the second doped region, or covers the entire back surface of the silicon substrate.

[0019] Furthermore, a third doped region is provided within the silicon substrate located in a region between the first doped region and the second doped region.

[0020] Furthermore, the first dielectric layer is connected to the bottom wall and the side wall of the recess.

[0021] Furthermore, the first dielectric layer is connected to a bottom wall of the recess, and the second dielectric layer is further connected to a side wall of the recess.

[0022] Furthermore, the recess is in the shape of a circular arc, a trapezoid, or a rectangle.

[0023] Furthermore, the first dielectric layer has a thickness of 1 to 20 nm, and the sum of the thickness of the first dielectric layer and the first doped region or the second doped region is greater than 20 nm.

[0024] Further, the doped silicon carbide is doped hydrogenated silicon carbide.

[0025] Furthermore, the first dielectric layer is a tunneling oxide layer and an intrinsic silicon carbide layer.

[0026] Furthermore, the tunneling oxide layer is one or more of a silicon oxide layer, an aluminum oxide layer.

[0027] Furthermore, the intrinsic silicon carbide layer in the first dielectric layer comprises an intrinsic hydrogenated silicon carbide layer.

[0028] Furthermore, the second dielectric layer is an aluminum oxide layer and an intrinsic silicon carbide layer, or a silicon oxide layer and an intrinsic silicon carbide layer, and the thickness of the second dielectric layer is greater than 25 nm.

[0029] Furthermore, the thickness of the aluminum oxide layer or silicon oxide layer in the second dielectric layer is less than 25 nm, and the thickness of the intrinsic silicon carbide layer in the second dielectric layer is greater than 10 nm.

[0030] Furthermore, the intrinsic silicon carbide layer in the second dielectric layer is made of at least one first intrinsic silicon carbide film having a different refractive index.

[0031] Furthermore, the refractive index of the first intrinsic silicon carbide film of each layer decreases sequentially from the back surface of the silicon substrate outward.

[0032] Furthermore, a magnesium fluoride layer is further provided on the outer layer of the second dielectric layer.

[0033] Furthermore, the conductive layer is a TCO transparent conductive film and / or a metal electrode.

[0034] Furthermore, the metal electrode includes a silver electrode, a copper electrode, an aluminum electrode, a tin-clad copper electrode, or a silver-clad copper electrode.

[0035] Furthermore, the copper electrode is an electroplated copper electrode produced by an electroplating process or a copper electrode produced by physical vapor deposition.

[0036] Furthermore, the first dielectric layer corresponding to the first doped region and the first dielectric layer corresponding to the second doped region may be the same or different.

[0037] Furthermore, the first doped region extends to a portion outside the recess and is not connected to the adjacent second doped region.

[0038] Another embodiment of the present invention further comprises: A silicon substrate; the back contact structure provided on a back surface of a silicon substrate; and a third dielectric layer provided on the surface of the silicon substrate.

[0039] Furthermore, the third dielectric layer is a combination of one or more of an aluminum oxide layer, a silicon nitride layer, a silicon oxynitride layer, an intrinsic silicon carbide layer, an intrinsic amorphous silicon layer, and a silicon oxide layer.

[0040] Furthermore, the third dielectric layer is a silicon oxide layer and an intrinsic silicon carbide layer, or an aluminum oxide layer and an intrinsic silicon carbide layer, and the thickness of the third dielectric layer is greater than 50 nm.

[0041] Furthermore, the thickness of the aluminum oxide layer or silicon oxide layer in the third dielectric layer is less than 40 nm, and the thickness of the intrinsic silicon carbide layer in the third dielectric layer is greater than 10 nm.

[0042] Furthermore, the intrinsic silicon carbide layer in the third dielectric layer is made of at least one second intrinsic silicon carbide film having a different refractive index.

[0043] Furthermore, the refractive index of the second intrinsic silicon carbide film in each layer decreases sequentially from the surface of the silicon substrate outward.

[0044] Furthermore, a magnesium fluoride layer is further provided on the outer layer of the third dielectric layer.

[0045] Furthermore, a field layer or a floating junction is further provided between the surface of the silicon substrate and the third dielectric layer.

[0046] Another embodiment of the present invention further aims to provide a cell assembly including the selective contact area embedded solar cell described above.

[0047] Another embodiment of the present invention further aims to provide a solar power generation system including the above-mentioned battery assembly.

[0048] Another embodiment of the present invention further comprises: Providing a plurality of recesses at intervals on a rear surface of a silicon substrate; forming a first dielectric layer on the back side of the silicon substrate; fabricating first and second doped regions within and outside each of the recesses, respectively; fabricating a second dielectric layer and a third dielectric layer on the front and back surfaces of the silicon substrate, respectively; and forming a conductive layer on the first doped region and the second doped region.

[0049] Furthermore, the step of fabricating a first doped region and a second doped region inside and outside each of the recesses, respectively, may further include: depositing intrinsic amorphous silicon or intrinsic silicon carbide into and around each recess; alternating different types of doping inside and outside each recess; and performing a high temperature crystallization process to convert the intrinsic amorphous silicon or intrinsic silicon carbide into doped polycrystalline silicon or doped silicon carbide, thereby obtaining a first doped region disposed within the recess and a second doped region disposed outside the recess.

[0050] Furthermore, the step of fabricating a first doped region and a second doped region inside and outside each of the recesses, respectively, may further include: depositing intrinsic amorphous silicon or intrinsic silicon carbide into and around each recess; and alternating different types of doping inside and outside each recess through a mask to obtain a first doped region within the recess and a second doped region outside the recess, such that the intrinsic amorphous silicon or intrinsic silicon carbide becomes doped polycrystalline silicon or doped silicon carbide.

[0051] Furthermore, the step of fabricating a first doped region and a second doped region inside and outside each of the recesses, respectively, may further include: depositing different types of doped amorphous silicon or doped amorphous silicon carbide alternately inside and outside each recess; and performing a high temperature crystallization process to convert the doped amorphous silicon or doped amorphous silicon carbide into doped polycrystalline silicon or doped silicon carbide, thereby obtaining a first doped region disposed within the recess and a second doped region disposed outside the recess.

[0052] Furthermore, the step of alternately doping the inside and outside of each recess with different types of doping may further include: doping each recess by alternately implanting ions of a first type and ions of a second type into and out of the recess; or or - doping by alternately depositing a first type of dopant source and a second type of dopant source inside and outside each recess; The method includes a step of alternately introducing a first type of source gas and a second type of source gas into and out of each recess to perform doping.

[0053] According to the back contact structure provided by the embodiment of the present invention, a first doped region is provided in each recess by providing recesses at intervals on the back surface of a silicon substrate, and a second doped region is provided outside each recess. This allows the first doped region in the recess and the second doped region outside the recess to be isolated by the silicon substrate not covered by the first doped region in the recess or the silicon substrate not covered by the second doped region outside the recess, and the recess has a looser width control requirement than a conventional trench, is easier to manufacture than a conventional trench, and has a better deposition effect when depositing the first dielectric layer and the first doped region in the recess. At the same time, by providing the recess, the first dielectric layer contacts both the bottom wall and the side wall of the recess, so that carriers generated in the silicon substrate can easily pass through the first dielectric layer on the side wall of the recess and be separated and selectively collected in the corresponding first doped region. This not only reduces leakage current, but also enables selective transport of carriers in vertical and horizontal directions, which is favorable for multi-dimensional collection of carriers at the bottom wall and side wall of the recess. By providing at least one second dielectric layer, the rear surface of the silicon substrate realizes multi-layer passivation by at least one second dielectric layer, which provides better passivation effect and improved internal rear surface reflection, thereby solving the problems of high requirements for trench width control and poor passivation effect in the conventional technology. [Brief description of the drawings]

[0054] [Figure 1] FIG. 2 is a structural schematic diagram of a selective contact area embedded solar cell according to an embodiment of the present invention; [Diagram 2] FIG. 2 is a structural schematic diagram of a selective contact area embedded solar cell according to an embodiment of the present invention; [Diagram 3] FIG. 2 is a structural schematic diagram of a selective contact area embedded solar cell according to an embodiment of the present invention; [Figure 4]FIG. 2 is a structural schematic diagram of a selective contact area embedded solar cell according to an embodiment of the present invention; [Diagram 5] FIG. 2 is a structural schematic diagram of a selective contact area embedded solar cell according to an embodiment of the present invention; [Figure 6] FIG. 2 is a structural schematic diagram of a selective contact area embedded solar cell according to an embodiment of the present invention; [Figure 7] FIG. 2 is a structural schematic diagram of a selective contact area embedded solar cell according to an embodiment of the present invention; [Figure 8] FIG. 2 is a structural schematic diagram of a selective contact area embedded solar cell according to an embodiment of the present invention; [Figure 9] FIG. 2 is a structural schematic diagram of a selective contact area embedded solar cell according to an embodiment of the present invention; [Figure 10] FIG. 2 is a structural schematic diagram of a selective contact area embedded solar cell according to an embodiment of the present invention; [Figure 11] 4 is a flow chart of a method for fabricating a selective contact area embedded solar cell provided by another embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0055] In order to make the object, technical means and advantages of the present invention more clear, the present invention will be described in more detail below with reference to the drawings and examples. Note that the specific examples described herein are merely for the purpose of interpreting the present invention, and are not intended to limit the present invention.

[0056] In the present invention, unless otherwise clearly specified and limited, the terms "attached", "connected", "connected", "fixed" and the like should be understood in a broad sense, and may be, for example, a fixed connection, a removable connection, or an integral connection. They may also be a mechanical connection or an electrical connection. They may also be a direct connection, an indirect connection via an intermediate medium, or an internal communication between two elements. Those skilled in the art can understand the specific meaning of the above terms in the present invention according to the specific situation. As used herein, the term "and / or" includes any and all combinations of one or more associated items listed.

[0057] In the present invention, a first doped region is provided in each recess by providing recesses at intervals on the back surface of a silicon substrate, and a second doped region is provided outside each recess. As a result, the first doped region in the recess and the second doped region outside the recess are isolated by the silicon substrate not covered by the first doped region in the recess or the silicon substrate not covered by the second doped region outside the recess, and the provided recess has a looser width control requirement than a conventional trench, is easier to manufacture than a conventional trench, and has a better deposition effect when depositing the first dielectric layer and the first doped region in the recess. At the same time, by providing the recess, the first dielectric layer contacts both the bottom wall and the side wall of the recess, so that carriers generated in the silicon substrate can easily pass through the first dielectric layer on the side wall of the recess and be separated and selectively collected in the corresponding first doped region. This not only reduces leakage current, but also enables selective transport of carriers in the vertical and horizontal directions, which is advantageous for multi-dimensional collection of carriers at the bottom wall and side wall of the recess. By providing at least one second dielectric layer, the rear surface of the silicon substrate realizes multi-layer passivation by the at least one second dielectric layer, thereby providing a better passivation effect and improving the internal rear surface reflection, and solving the problems of the high requirements for trench width control and the poor passivation effect in the conventional technology. EXAMPLES

[0058] The first embodiment of the present invention provides a back contact structure of a solar cell, and for convenience of explanation, only the parts related to the embodiment of the present invention are shown. As shown in Figures 1 to 10, the back contact structure of a solar cell provided by the embodiment of the present invention includes: a recess provided on the back surface of the silicon substrate 10 at an interval; A first dielectric layer 20 provided on the back surface of the silicon substrate 10; a first doped region 30 disposed in the first dielectric layer 20 and disposed within the recess; a second doped region 40 disposed in the first dielectric layer 20 and outside the recess; at least one second dielectric layer 50 disposed between the first doped region 30 and the second doped region 40, the refractive index of which decreases gradually from the back surface of the silicon substrate 10 outward; and a conductive layer provided in the first doped region and the second doped region.

[0059] In one embodiment of the present invention, the silicon substrate 10 has a surface facing the sun during normal operation and a back surface opposite to the surface. The surface is a light receiving surface, and the back surface is provided on the other side of the silicon substrate 10 with respect to the surface, i.e., the surface and the back surface are located on different sides of the silicon substrate 10 and opposite to each other. In this embodiment, the silicon substrate 10 is an N-type silicon wafer, but of course, in other embodiments, the silicon substrate 10 may be other silicon wafers. Recesses are formed at intervals on the back surface of the silicon substrate 10. The recesses are manufactured by laser ablation or a combination of a mask (e.g., a hard mask, a silicon oxide mask, a silicon nitride mask, a photoresist mask, etc.) and wet / dry etching. In this case, the recesses are formed at intervals on the back surface of the silicon substrate 10, so that the area located between two adjacent recesses of the silicon substrate 10 becomes approximately a convex portion. As a result, the back surface pattern of the silicon substrate 10 becomes a pattern formed by approximately alternating recesses and protrusions.

[0060] Furthermore, in one embodiment of the present invention, the first dielectric layer 20 is located on the back surface of the silicon substrate 10 and covers at least the first doped region 30 and the second doped region 40. In a specific implementation, the first dielectric layer 20 may cover only the first doped region 30 and the second doped region 40, or may cover the entire back surface of the silicon substrate 10. In one embodiment of the present invention, as shown in FIG. 1, the first dielectric layer 20 covers only the first doped region 30 and the second doped region 40. In this case, the back surface of the silicon substrate 10 located in the region between the first doped region 30 and the second doped region 40 is not covered by the first dielectric layer 20. In another embodiment of the present invention, as shown in FIG. 2, the first dielectric layer 20 covers the entire back surface of the silicon substrate 10, that is, the first dielectric layer 20 covers the entire back surface of the silicon substrate 10 that is composed of the concave and convex portions. It should be noted that, as shown in FIGS. 1 and 2, when the first doped region 30 is covered with the first dielectric layer 20, the first dielectric layer 20 is connected to the bottom wall and side walls of the recess.

[0061] Furthermore, in one embodiment of the present invention, the first doped region 30 is a P-type doped region, and the second doped region 40 is an N-type doped region. Alternatively, the first doped region 30 is an N-type doped region, and the second doped region 40 is a P-type doped region. That is, the first dielectric layer 20 and the P-type doped region may be provided inside the recess, and the first dielectric layer 20 and the N-type doped region may be provided outside the recess. Alternatively, the first dielectric layer 20 and the N-type doped region may be provided inside the recess, and the first dielectric layer 20 and the P-type doped region may be provided outside the recess. In this way, the first dielectric layer 20 and the first doped region 30, and the first dielectric layer 20 and the second doped region 40 are alternately provided inside and outside the recess. In this case, the first doped region 30 within the recess and the second doped region 40 outside the recess are isolated by the silicon substrate that is not covered by the first doped region 30 within the recess or the silicon substrate that is not covered by the second doped region 40 outside the recess.

[0062] The first dielectric layer 20 is located between the silicon substrate 10 and the first doped region 30 in the recess and the second doped region 40 outside the recess, and serves as a tunneling structure. The first dielectric layer 20 and the first doped region 30 or the second doped region 40 connected thereto and covered therewith form a passivation contact structure, which provides good surface passivation for the back surface of the silicon substrate 10. In addition, generally, the first dielectric layer 20 has a sufficiently thin thickness, and a certain type of carrier is selectively transported by the tunneling principle, and another type of carrier cannot tunnel through the first dielectric layer 20 due to the existence of a barrier and a doped region field effect, so that the first dielectric layer 20 allows a certain type of carrier to tunnel into the doped region and can prevent the other type of carrier from being mixed by passing through, thereby significantly reducing the mixing at the interface, and the solar cell has a high open circuit voltage and short circuit current, and the photoelectric conversion efficiency is improved. Also, as shown in Figures 1 to 10, a plurality of internal diffusion regions corresponding to the first doped region 30 or the second doped region 40 are formed on the surface of the silicon substrate 10 in contact with the first dielectric layer 20. In addition, in this embodiment, by providing a recess, the first dielectric layer 20 contacts both the bottom wall and the side wall of the recess, so that carriers generated in the silicon substrate 10 are also separated by the first dielectric layer 20 on the side wall of the recess and tend to be selectively collected in the corresponding first doped region 30, which is advantageous for multi-dimensional collection of carriers on the bottom wall and side wall of the recess.

[0063] Furthermore, in one embodiment of the present invention, the first dielectric layer 20 is preferably one or more combinations of a tunneling oxide layer, an intrinsic silicon carbide layer, and an intrinsic amorphous silicon layer. As an example of the present invention, for example, the first dielectric layer 20 may be a single-material tunneling oxide layer, a combination of a multi-material tunneling oxide layer and an intrinsic amorphous silicon layer, or a combination of a single-material multi-material intrinsic amorphous silicon layers with different refractive indices. Of course, the specific structural arrangement of the first dielectric layer 20 includes, but is not limited to, some of the above. The first dielectric layer 20 may be set according to the requirements of actual use, but is not specifically limited here.

[0064] In a preferred embodiment of the present invention, specifically, the first dielectric layer 20 is preferably a tunneling oxide layer and an intrinsic silicon carbide layer. In this case, the tunneling oxide layer and the intrinsic silicon carbide layer are sequentially arranged from the silicon substrate 10 outward, the tunneling oxide layer contacts the rear surface of the silicon substrate 10, and the intrinsic silicon carbide layer contacts the first doped region 30 or the second doped region 40. Furthermore, the tunneling oxide layer is preferably one or more of a silicon oxide layer and an aluminum oxide layer. Thus, the first dielectric layer 20 may be a combination of a silicon oxide layer and an aluminum oxide layer in the tunneling oxide layer. The intrinsic silicon carbide layer in the first dielectric layer 20 includes an intrinsic hydrogenated silicon carbide layer. In this case, the tunneling oxide layer and the intrinsic silicon carbide layer are chemically passivated to reduce the interface state density between the silicon substrate 10 and the first doped region 30 and the second doped region 40. For example, hydrogen in the intrinsic hydrogenated silicon carbide layer enters the silicon substrate 10 through a diffusion mechanism and a thermal effect, neutralizing dangling bonds on the rear surface of the silicon substrate 10 and passivating defects on the rear surface of the silicon substrate 10. This moves the energy band in the forbidden band to the valence band or the conduction band, improving the probability that carriers pass through the first dielectric layer 20 and enter the first doped region 30 or the second doped region 40.

[0065] Generally, in the embodiment of the present invention, in a specific use, it is preferred to use a 1-2 nm silicon oxide layer and a 2-5 nm intrinsic silicon carbide layer as the first dielectric layer 20. Compared with using a silicon oxide layer as the tunneling structure, the intrinsic silicon carbide layer can further provide an additional hydrogen passivation effect, and expand the manufacturing process window of the tunneling structure without affecting the tunneling effect. Of course, a 1-2 nm silicon oxide layer, or a 1 nm silicon oxide layer and a 1 nm aluminum oxide layer, or two or more intrinsic amorphous silicon layers with different refractive indices may be directly used. Of course, the specific structural arrangement of the first dielectric layer 20 includes, but is not limited to, some of the examples listed above. In addition, the first dielectric layer 20 may be an intrinsic microcrystalline silicon layer, an intrinsic microcrystalline silicon oxide layer, an intrinsic amorphous silicon oxide layer, etc. As shown in FIGS. 1 to 10, only the first dielectric layer 20 having a single-layer structure is shown, but the specific structure of the first dielectric layer 20 is not limited to that shown in the drawings and may be set according to actual requirements.

[0066] In addition, when the first dielectric layer 20 covers only the first doped region 30 and the second doped region 40, the first dielectric layer 20 is partitioned, so the structures of the first dielectric layer 20 provided in the first doped region 30 and the second doped region 40 may be the same or different. Specifically, the first dielectric layer 20 corresponding to the first doped region 30 and the first dielectric layer 20 corresponding to the second doped region 40 may be the same or different. For example, the first dielectric layer 20 may be a silicon oxide layer and an intrinsic silicon carbide layer in the same way, and the first dielectric layer 20 in the recessed portion where the first doped region 30 is provided may be a silicon oxide layer and an intrinsic silicon carbide layer, and the first dielectric layer 20 in the protruding portion where the second doped region 40 is provided may be an aluminum oxide layer and an intrinsic silicon carbide layer. The film layer structure of the first dielectric layer 20 in each of the first doped region 30 and the second doped region 40 may be set according to the requirements of actual use, and is not specifically limited here.

[0067] Furthermore, in one embodiment of the present invention, the first doped region 30 and the second doped region 40 are provided inside and outside each recess, respectively, and the first doped region 30 and the second doped region 40 preferably include doped polycrystalline silicon, doped silicon carbide, or doped amorphous silicon. The doped silicon carbide may include doped hydrogenated silicon carbide and doped hydrogenated silicon carbide. Specifically, hydrogen gas is added during deposition of silicon carbide. Note that, when the first dielectric layer 20 is the above silicon oxide layer and intrinsic silicon carbide layer, the first doped region 30 and the second doped region 40 are specifically doped silicon carbide. When the first dielectric layer 20 is the above silicon oxide layer or other combinations, the first doped region 30 and the second doped region 40 may be doped polycrystalline silicon, etc. When the first dielectric layer 20 is the above intrinsic amorphous silicon layer, the first doped region 30 and the second doped region 40 are specifically doped amorphous silicon. It should be noted that the first doped region 30 and the second doped region 40 may be the same or different. For example, the first doped region 30 and the second doped region 40 may be doped polycrystalline silicon as well. Alternatively, the first doped region 30 may be doped polycrystalline silicon and the second doped region 40 may be doped silicon carbide. The first doped region 30 and the second doped region 40 may be set according to the requirements of actual use, and are not specifically limited here.

[0068] Furthermore, in one embodiment of the present invention, the second doped region 40 is provided in a part of the region outside the recess. In this case, as shown in FIG. 1, since the second doped region 40 is located only in a part of the region within the protrusion, the first doped region 30 and the second doped region 40 can be isolated only by the main body of the silicon substrate 10. In this case, the total thickness of the first dielectric layer 20 and the first doped region 30 provided in the recess may be greater than or less than the depth of the recess. That is, the first doped region 30 may be provided within the recess or may extend from the recess. As shown in FIG. 1 and FIG. 2, a case is shown in which the total thickness of the first dielectric layer 20 and the first doped region 30 is smaller than the depth of the recess. As shown in FIG. 3, a case is shown in which the total thickness of the first dielectric layer 20 and the first doped region 30 is the same as the depth of the recess. As shown in FIG. 4, a case is shown in which the total thickness of the first dielectric layer 20 and the first doped region 30 is greater than the depth of the recess. In one embodiment of the present invention, as shown in FIG. 5, when the first dielectric layer 20 covers the entire back surface of the silicon substrate 10 and the total thickness of the first dielectric layer 20 and the first doped region 30 is greater than the depth of the recess, the first doped region 30 may extend to a part of the protruding region outside the recess and not be connected to the adjacent second doped region 40. In this case, the first dielectric layer 20 and the first doped region 30 provided in the protruding region outside the recess also form a passivation contact structure and communicate with the first dielectric layer 20 and the first doped region 30 in the recess. This increases the contact area of ​​the first dielectric layer 20 through which carriers selectively pass.

[0069] Furthermore, in another embodiment of the present invention, the second doped region 40 is provided in the entire region outside the recess. In this case, as shown in Fig. 6, since the second doped region 40 is provided in the entire protrusion outside the recess, in order to isolate the first doped region 30 and the second doped region 40, the total thickness of the first dielectric layer 20 and the first doped region 30 provided in the recess must be equal to or less than the depth of the recess. This isolates the first doped region 30 and the second doped region 40 by the silicon substrate not covered by the first doped region 30 in the recess.

[0070] Furthermore, in one embodiment of the present invention, the thickness of the first dielectric layer 20 is 1 to 20 nm, the sum of the thicknesses of the first dielectric layer 20 and the first doped region 30 is greater than 20 nm, and the sum of the thicknesses of the first dielectric layer 20 and the second doped region 40 is greater than 20 nm. Also, the horizontal distance between the first doped region 30 and the second doped region 40 is 0 to 500 μm, that is, the second doped region 40 may cover the entire convex portion and be adjacent to the first doped region 30 in the horizontal direction. Alternatively, the second doped region 40 may cover a part of the region outside the concave portion. When the first doped region 30 is a P-type doped region, the width of the concave portion of the P-type doped region is 300 to 600 μm, the width of the N-type doped region provided in the convex portion is 100 to 500 μm, and the depth of the concave portion is 0.01 to 10 μm. When the first doped region 30 is an N-type doped region, the width of the recess of the N-type doped region is 100 to 500 μm, the width of the P-type doped region provided in the protrusion is 300 to 600 μm, and the depth of the recess is 0.01 to 10 μm. In a preferred embodiment of the present invention, the width of the P-type doped region is preferably 500 μm. The width of the N-type doped region is preferably 300 μm. The distance between the first doped region 30 and the second doped region 40 is preferably 100 μm. As can be seen from the above, the width of the provided recess has less stringent requirements for control than the width of several tens of μm of a conventional trench, and is easier to manufacture than a conventional trench.

[0071] Furthermore, in one embodiment of the present invention, the second dielectric layer 50 covers the area between the first doped region 30 and the second doped region 40, or extends to cover the first doped region 30 and / or the second doped region 40. That is, as shown in FIG. 7, the second dielectric layer 50 may only cover the area between the first doped region 30 and the second doped region 40. Accordingly, in this case, the conductive layer 60 covers the first doped region 30 and the entire back surface of the first doped region 30 to form an electrical connection. As shown in FIG. 1, the second dielectric layer 50 may extend from the protrusion to cover the first doped region 30 and / or the second doped region 40. Accordingly, the second dielectric layer 50 may extend to cover a portion of the first doped region 30, or extend to cover a portion of the second doped region 40, or extend to cover a portion of the first doped region 30 and the second doped region 40. In this case, the conductive layer 60 covers the remaining back surface portions of the first doped region 30 and the second doped region 40 that are not covered by the second dielectric layer 50, and forms electrical connections with the first doped region 30 and the second doped region 40, respectively. Of course, the second dielectric layer 50 may completely cover the entire back surface of the back contact structure during manufacturing. In this case, when the conductive layer 60 is manufactured, the conductive layer 60 is penetrated into the second dielectric layer 50 by a punch or the like, and forms electrical connections with the first doped region 30 and the second doped region 40, respectively. Note that, when the first dielectric layer 20 covers only the first doped region 30 and the second doped region 40, the second dielectric layer 50 directly contacts the back surface of the silicon substrate 10, as shown in FIG. 1. When the first dielectric layer 20 covers the entire back surface of the silicon substrate 10, the second dielectric layer 50 contacts the first dielectric layer 20, as shown in FIG. 2.

[0072] Furthermore, in one embodiment of the present invention, the second dielectric layer 50 is preferably one or more combinations of an aluminum oxide layer, a silicon nitride layer, a silicon oxynitride layer, an intrinsic silicon carbide layer, an intrinsic amorphous silicon layer, and a silicon oxide layer. The second dielectric layer 50 performs a passivation function. The second dielectric layer 50 has at least one layer structure, and each layer is arranged so that the refractive index decreases from the silicon substrate 10 outward, so that the film layer close to the silicon substrate 10 performs a passivation function, and the film layer away from the silicon substrate 10 performs a reflection reduction function, and the reflection reduction effect is enhanced, thereby increasing the absorption and utilization of light by the silicon substrate 10 and increasing the short circuit current density. Alternatively, the second dielectric layer 50 may be a doped silicon layer (e.g., a doped microcrystalline silicon layer, a doped amorphous silicon layer, a doped polycrystalline silicon layer), a doped silicon carbide layer (e.g., a doped polycrystalline silicon carbide layer), a doped silicon oxide layer (e.g., a doped polycrystalline silicon oxide, a doped amorphous silicon oxide), or the like. Alternatively, each film layer having a different structure in the second dielectric layer 50 may be composed of a plurality of films having different refractive indices. As described above, each film layer is arranged so that the refractive index decreases sequentially from the silicon substrate 10 outward. For example, the silicon oxide layer in the second dielectric layer 50 may be composed of a plurality of silicon oxide films whose refractive indexes decrease sequentially from the silicon substrate 10 outward.

[0073] As described above, in a specific example of the present invention, the second dielectric layer 50 may have a three-layer structure including a silicon oxide layer / aluminum oxide layer, an intrinsic silicon carbide layer, and a silicon nitride layer / silicon oxynitride layer, in which the thickness of the silicon oxide layer / aluminum oxide layer located on the inside as the first layer is greater than 0.5 nm, the thickness of the intrinsic silicon carbide layer located on the second layer is greater than 1 nm, and the thickness of the silicon nitride layer / silicon oxynitride layer located on the outside as the third layer is greater than 50 nm.

[0074] As a specific example of the present invention, the second dielectric layer 50 may have a two-layer structure including an aluminum oxide layer and a silicon nitride layer / silicon oxynitride layer. In this case, the thickness of the aluminum oxide layer located in the first inner layer is greater than 1 nm. The thickness of the silicon nitride layer / silicon oxynitride layer located in the second outer layer is greater than 50 nm.

[0075] As a specific example of the present invention, the second dielectric layer 50 may have a three-layer structure consisting of a silicon oxide layer / aluminum oxide layer, a doped polycrystalline silicon layer / doped polycrystalline silicon carbide layer / doped polycrystalline silicon oxide layer, and a silicon nitride layer / silicon oxynitride layer. In this case, the thickness of the silicon oxide layer / aluminum oxide layer located in the first inner layer is 0.5 to 3 nm, the thickness of the doped polycrystalline silicon layer / doped polycrystalline silicon carbide layer / doped polycrystalline silicon oxide layer located in the second layer is 20 to 100 nm, and the thickness of the silicon nitride layer / silicon oxynitride layer located in the third outer layer is greater than 50 nm.

[0076] As a specific example of the present invention, the second dielectric layer 50 may have a three-layer structure including an intrinsic amorphous silicon layer, a doped amorphous silicon layer / doped amorphous silicon oxide layer, and a silicon nitride layer / silicon oxynitride layer. In this case, the intrinsic amorphous silicon layer located in the first inner layer has a thickness of 2 to 10 nm, the doped amorphous silicon layer / doped amorphous silicon oxide layer located in the second layer has a thickness of 2 to 50 nm, and the silicon nitride layer / silicon oxynitride layer located in the third outer layer has a thickness greater than 50 nm.

[0077] As a specific example of the present invention, the second dielectric layer 50 may have a three-layer structure consisting of a silicon oxide layer / aluminum oxide layer, an intrinsic silicon carbide layer / doped amorphous silicon oxide layer, and a silicon nitride layer / silicon oxynitride layer. In this case, the thickness of the silicon oxide layer / aluminum oxide layer located in the first inner layer is 0.5 to 3 nm, the thickness of the intrinsic silicon carbide layer / doped amorphous silicon oxide layer located in the second layer is 10 to 50 nm, and the thickness of the silicon nitride layer / silicon oxynitride layer located in the third outer layer is greater than 50 nm.

[0078] Of course, the specific structural arrangement of the second dielectric layer 50 includes, but is not limited to, some of the examples listed above. In a preferred embodiment of the present invention, as shown in FIG. 1, the second dielectric layer 50 is preferably a two-layer structure of an aluminum oxide layer and an intrinsic silicon carbide layer, or a two-layer structure of a silicon oxide layer and an intrinsic silicon carbide layer. In this case, the total thickness of the second dielectric layer 50 is greater than 25 nm, and is generally 70-80 nm during normal production. In this case, the intrinsic silicon carbide layer not only provides a hydrogen passivation effect, but also has a larger optical band gap and a smaller absorption coefficient than an intrinsic amorphous silicon layer, a doped polycrystalline silicon layer, etc., and can reduce parasitic light absorption. Furthermore, the thickness of the aluminum oxide layer or silicon oxide layer in the second dielectric layer 50 is less than 25 nm, and the thickness of the intrinsic silicon carbide layer in the second dielectric layer 50 is greater than 10 nm. In addition, in the multi-layer structure presented in the embodiment of the present invention, all are arranged in sequence from the silicon substrate 10 outward. For example, when the second dielectric layer 50 is an aluminum oxide layer and an intrinsic silicon carbide layer, the aluminum oxide layer is closer to the silicon substrate 10 and the intrinsic silicon carbide layer is closer to the outside. In addition, in the drawings, as shown in Figs. 1 to 10, only the second dielectric layer 50 having a two-layer structure is shown, but it is natural that the second dielectric layer 50 may have other layers. The specific structure is not limited to the illustrated structure and may be set according to actual requirements. In addition, each figure of the present invention is merely for explaining the specific distribution of each structure in the back contact structure, and does not correspond to the actual size of each structure. For example, the thickness of the first dielectric layer 20 is 1 to 20 nm, and the thickness of the second dielectric layer 50 is greater than 25 nm, but the drawings do not correspond to the specific actual size of this embodiment, and the specific parameters provided in this embodiment should be taken as the basis.

[0079] Furthermore, the intrinsic silicon carbide layer in the second dielectric layer 50 is composed of at least one first intrinsic silicon carbide film having different refractive indexes. The refractive index of each first intrinsic silicon carbide film decreases from the rear surface of the silicon substrate 10 to the outside in sequence. Optionally, the refractive indexes of the above materials are generally as follows: single crystal silicon has a refractive index of 3.88, amorphous silicon has a refractive index of 3.5-4.2, polycrystalline silicon has a refractive index of 3.93, silicon carbide has a refractive index of 2-3.88, silicon nitride has a refractive index of 1.9-3.88, silicon oxynitride has a refractive index of 1.45-3.88, silicon oxide has a refractive index of 1.45, and aluminum oxide has a refractive index of 1.63. Naturally, the refractive indexes of the above materials may be set differently according to the requirements of actual use, and are not specifically limited here.

[0080] Furthermore, in one embodiment of the present invention, a magnesium fluoride layer is further provided on the outer layer of the second dielectric layer 50. That is, in addition to one or more combinations of an aluminum oxide layer, a silicon nitride layer, a silicon oxynitride layer, an intrinsic silicon carbide layer, an intrinsic amorphous silicon layer, and a silicon oxide layer selected as the second dielectric layer 50, a magnesium fluoride layer may be further provided on the outer layer of the second dielectric layer 50. The magnesium fluoride layer must have the lowest refractive index, and is generally set to 1.4 in order to enhance the optical effect of reducing reflection.

[0081] Furthermore, in one embodiment of the present invention, the conductive layer 60 is a TCO transparent conductive film and / or a metal electrode. The metal electrode includes a silver electrode, a copper electrode, an aluminum electrode, a tin-clad copper electrode, or a silver-clad copper electrode. Furthermore, the copper electrode is an electroplated copper electrode produced by an electroplating process, or a copper electrode produced by physical vapor deposition. The electroplated copper uses a nickel, chromium, titanium, or tungsten electrode as a seed layer or a protective layer. When the back contact structure is used in a low-temperature process HBC cell (interdigitated back-contact heterojunction solar cell), the conductive layer 60 is a TCO transparent conductive film and a metal electrode. When the back contact structure is used in a high-temperature process POLO-IBC cell (passivation-contact IBC cell), the conductive layer 60 is a metal electrode. However, the metal electrode using low-temperature silver paste can only be used in a low-temperature process HBC cell.

[0082] Furthermore, in one embodiment of the present invention, the recess is arc-shaped, trapezoidal, or rectangular. As shown in FIG. 1, in a specific embodiment, the recess is rectangular. As shown in FIG. 8, in another specific embodiment, the recess is trapezoidal. The recess is preferably arc-shaped or trapezoidal. This is because, when the recess is arc-shaped or trapezoidal, the effect of light reflection by the inner wall of the recess is improved, and the contact surface area between the first dielectric layer 20 and the silicon substrate 10 as the tunneling structure is also increased. Of course, when the recess is rectangular, the actual production process is simplified, so the shape of the recess can be set according to the requirements of actual use, and is not specifically limited here.

[0083] In another embodiment of the present invention, the first dielectric layer 20 may be connected to the bottom wall of the recess, and the second dielectric layer 50 may be connected to the side wall of the recess. The main reasons for this are considered as follows. After the recess area is covered with a mask, when the mask is removed, silicon in a part of the silicon substrate 10 close to the first doped region 30 is corroded, the width of the recess increases, and when the second dielectric layer 50 is deposited thereafter, the second dielectric layer 50 is deposited up to the blank region, and thus connected to the side wall of the recess. Alternatively, when a circular arc-shaped recess (e.g., an elliptical recess) is manufactured, the first dielectric layer 20 and the first doped region 30 cannot be deposited up to the inner wall in the major radius direction of the circular arc-shaped recess, and thus the second dielectric layer 50 is filled up to the blank region during deposition, and is connected to the side wall of the circular arc-shaped recess. Alternatively, the second dielectric layer 50 cannot be deposited up to the blank region during deposition, and thus a gap is formed between the side wall of the circular arc-shaped recess and the first dielectric layer 20 and the first doped region 30. Of course, in the embodiment of the present invention, the back contact structure is preferably such that the first dielectric layer 20 provided on the sidewall of the recess allows selective passage of carriers and thus realizes multi-dimensional collection, so that the first dielectric layer 20 is directly connected to the sidewall of the recess.

[0084] Furthermore, in one embodiment of the present invention, as shown in FIG. 9, the silicon substrate 10 located in the region between the first doped region 30 and the second doped region 40 is provided with a third doped region 70. That is, the third doped region 70 may be provided in the entire convex portion outside the concave portion, or may be provided in a part of the convex portion. The third doped region 70 is specifically a diffusion layer formed by doping the silicon substrate 10 in each convex portion with a different type of diffusion source, and is therefore a diffusion layer formed by partial diffusion of the silicon substrate 10 located in the convex portion. The diffusion layer may be a P-type diffusion layer or an N-type diffusion layer. The P-type diffusion layer is formed by doping and diffusing boron, aluminum, gallium, etc. The N-type diffusion layer is formed by doping and diffusing nitrogen, phosphorus, arsenic, etc. In this case, the N-type diffusion layer is an N+ layer for the silicon substrate 10, which is particularly an N-type silicon wafer, that is, the diffusion layer is formed by local high diffusion. Each third doped region 70 provided in the silicon substrate 10 may be a P-type diffusion layer or an N-type diffusion layer according to the requirements of actual use, and is not specifically limited here. It is preferable to form a P-type diffusion layer and an N-type diffusion layer by alternately performing different types of diffusion in each protrusion of the silicon substrate 10. In this case, the first dielectric layer 20 is provided on the sidewall of the recess and the protrusion outside the recess, and the third doped region 70 is formed by diffusion between the first doped region 30 and the second doped region 40 in the silicon substrate 10, so that carriers in the third doped region 70 selectively pass through the first dielectric layer 20 on the sidewall of the adjacent recess and are separated and collected in the corresponding first doped region 30, and selectively pass through the first dielectric layer 20 on the protrusion and are separated and collected in the corresponding second doped region 40.

[0085] Further, in one embodiment of the present invention, as shown in FIG. 10, the back surface of the silicon substrate 10 located in the region between the first doped region 30 and the second doped region 40 has a rough texture structure 80. That is, the silicon substrate 10 has the rough texture structure 80 on the convex surface. When the first dielectric layer 20 covers only the first doped region 30 and the second doped region 40, the rough texture structure 80 is located at the contact portion between the second dielectric layer 50 and the back surface of the silicon substrate 10. When the first dielectric layer 20 covers the entire back surface of the silicon substrate 10, the rough texture structure 80 is located at the contact portion between the first dielectric layer 20 and the back surface of the silicon substrate 10. The rough texture structure 80 is usually formed by texturing, and may be a random hemispherical texture formed by texturing with an acid, a pyramidal texture formed by texturing with a base, or a pyramidal texture formed by texturing with a base with the pyramidal tips chamfered by texturing with an acid. Of course, the rough texture structure 80 may be formed on the entire back surface of the silicon substrate 10, i.e., on the silicon substrate 10 located in the recess. In this case, the process is simplified because the entire back surface of the silicon substrate 10 on which the recess is formed is textured in contact with the first doped region 30 and the second doped region 40 without the need for a subsequent process of removing the rough texture structure 80 in the first doped region 30 and the second doped region 40. However, in this embodiment, in order to increase the reflection of incident light inside the silicon substrate 10 and to increase the light absorption rate, it is preferable to texture only the surface of the silicon substrate 10 in the region between the first doped region 30 and the second doped region 40, and not texture the surface of the silicon substrate 10 in the first doped region 30 and the second doped region 40.

[0086] Test results showed that the HBC and POLO-IBC batteries manufactured based on the back contact structure provided by the embodiment of the present invention had significantly improved battery conversion efficiency of about 26.0% and reliability compared to the control POLO-IBC battery manufactured by the conventional trench method. The electrical performance results are shown in Table 1 below.

[0087] [Table 1]

[0088] The embodiments of the present invention provide the following beneficial effects over the prior art.

[0089] 1. Recesses are provided at intervals on the rear surface of a silicon substrate, a first doped region is provided in each recess, and a second doped region is provided outside each recess, so that the first doped region in the recesses and the second doped region outside the recesses are isolated by the silicon substrate not covered by the first doped region in the recesses or the silicon substrate not covered by the second doped region outside the recesses, and the recesses have looser width control requirements than a conventional trench, are easier to manufacture, and have better deposition effect when depositing the first dielectric layer and the first doped region in the recesses.

[0090] 2. By providing the recess, the first dielectric layer contacts both the bottom wall and the side wall of the recess, so that the carriers generated in the silicon substrate can easily pass through the first dielectric layer on the side wall of the recess and be isolated and selectively collected in the corresponding first doped region, which not only reduces the leakage current but also realizes the selective transport of carriers in the vertical and horizontal directions, which is favorable for the multi-dimensional collection of carriers on the bottom wall and the side wall of the recess.

[0091] 3. By providing at least one second dielectric layer, the back surface of the silicon substrate can be passivated by multiple layers through at least one second dielectric layer, and the passivation effect is better. In addition, the refractive index of each layer is controlled to decrease gradually from the silicon substrate to the outside, so that the internal back surface reflection of long wavelength light in the silicon substrate is increased, and the short circuit current density is increased.

[0092] 4. Due to the certain depth of the recess, the hard mask only directly contacts the protruding part between the two recesses, but does not directly contact the bottom of the recess, which reduces the contamination by impurities, and therefore the silicon substrate at the bottom wall of the recess can be protected from damage caused by the hard mask. In addition, the damage caused by the contact of the surface of the protruding part of the silicon substrate with the hard mask can also be removed by the subsequent texturing process.

[0093] 5. In the selective deposition process of the first doped region or the second doped region using a hard mask, for example, when depositing the first doped region in the recessed region, the convex portion outside the recessed region can be shielded by the hard mask. Due to the certain depth of the recess, the hard mask does not directly contact the bottom of the recessed region, so the deposition effect is improved. In addition, since there is a convex structure of the silicon substrate with a certain width for isolation between each recess, when depositing the recessed region by shielding with a hard mask, the alignment of the hard mask does not require high accuracy, and a moderate deviation is acceptable. This simplifies the alignment of the hard mask and reduces the difficulty of the process.

[0094] 6. In the prior art, the trench area is limited in width and depth, and the chemical solution penetrates completely to the bottom of the trench due to the hydrophobicity of water and silicon wafer, making chemical wet texturing impossible. In contrast, in the present embodiment, the recesses are provided so that the back surface of the silicon substrate between adjacent recesses faces the protrusions, making it easier to obtain a rough texture structure by texturing than the conventional trench structure. The texturing of the protrusions on the back surface of the silicon substrate increases the internal back reflection of light in the silicon substrate, improving the light absorption rate of the silicon substrate.

[0095] 7. In the silicon substrate, a third doped region is provided in a region between the first doped region and the second doped region, so that carriers in the third doped region selectively pass through the first dielectric layer on the sidewall of an adjacent recess to be separated and collected in the corresponding first doped region, and also selectively pass through the first dielectric layer on the protrusion to be separated and collected in the corresponding second doped region. EXAMPLES

[0096] The second embodiment of the present invention provides a selective contact region embedded solar cell, and for convenience of explanation, only the parts related to the embodiment of the present invention are shown. As shown in Figures 1 to 10, the selective contact region embedded solar cell provided by the embodiment of the present invention has: A silicon substrate 10; A back contact structure according to the above embodiment provided on the back surface of a silicon substrate 10; and a third dielectric layer 90 provided on the surface of the silicon substrate 10.

[0097] Furthermore, in one embodiment of the present invention, the second dielectric layer 50 and the third dielectric layer 90 may be manufactured on the front and rear surfaces of the silicon substrate 10 by the same process. In this case, the third dielectric layer 90 may have the same structure as the second dielectric layer 50 in the above embodiment. Therefore, referring to the description of the above embodiment, the third dielectric layer 90 is also preferably one or more combinations of an aluminum oxide layer, a silicon nitride layer, a silicon oxynitride layer, an intrinsic silicon carbide layer, an intrinsic amorphous silicon layer, and a silicon oxide layer.

[0098] As an example of the present invention, the third dielectric layer 90 may be a three-layer structure consisting of a silicon oxide layer / aluminum oxide layer and a doped polycrystalline silicon layer / doped polycrystalline silicon carbide layer / doped polycrystalline silicon oxide layer and a silicon nitride layer / silicon oxynitride layer, or a three-layer structure consisting of an intrinsic amorphous silicon layer and a doped amorphous silicon layer / doped amorphous silicon oxide layer and a silicon nitride layer / silicon oxynitride layer, or a three-layer structure consisting of a silicon oxide layer / aluminum oxide layer and an intrinsic silicon carbide layer / doped amorphous silicon oxide layer and a silicon nitride layer / silicon oxynitride layer.

[0099] Furthermore, in a preferred embodiment of the present invention, as shown in FIG. 1, the third dielectric layer 90 is also preferably a two-layer structure of a silicon oxide layer and an intrinsic silicon carbide layer, or a two-layer structure of an aluminum oxide layer and an intrinsic silicon carbide layer. The thickness of the third dielectric layer 90 is greater than 50 nm. The thickness of the aluminum oxide layer or the silicon oxide layer in the third dielectric layer 90 is less than 40 nm, and the thickness of the intrinsic silicon carbide layer in the third dielectric layer 90 is greater than 10 nm. In this case, the intrinsic silicon carbide layer not only provides a hydrogen passivation effect, but also has a larger optical band gap and a smaller absorption coefficient than the intrinsic amorphous silicon layer, the doped polycrystalline silicon layer, etc., and therefore can reduce parasitic light absorption. Furthermore, the intrinsic silicon carbide layer in the third dielectric layer 90 is composed of at least one layer of a second intrinsic silicon carbide film with a different refractive index. The refractive index of each layer of the second intrinsic silicon carbide film sequentially decreases from the surface of the silicon substrate 10 outward. Furthermore, in one embodiment of the present invention, a magnesium fluoride layer is further provided on the outer layer of the third dielectric layer 90. The magnesium fluoride layer must have the lowest refractive index, and is generally set to 1.4 in order to enhance the optical effect of reducing reflection.

[0100] Of course, the third dielectric layer 90 may have a different structural arrangement from that of the second dielectric layer 50 in the above embodiment. The film layer structures of the second dielectric layer 50 and the third dielectric layer 90 may be set according to the requirements of actual use, and are not specifically limited here.

[0101] Furthermore, in one embodiment of the present invention, a field layer or a floating junction is further provided between the surface of the silicon substrate 10 and the third dielectric layer 90. Specifically, the field layer is fabricated by phosphorus diffusion into the silicon substrate 10, or the floating junction is fabricated by boron diffusion into the silicon substrate 10. In this case, the field layer or the floating junction is the front surface field (FSF) of the selective contact area embedded solar cell.

[0102] In this embodiment, by providing recesses at intervals on the back surface of the silicon substrate, a first doped region is provided in each recess, and a second doped region is provided outside each recess. As a result, the first doped region in the recess and the second doped region outside the recess are isolated by the silicon substrate not covered by the first doped region in the recess or the silicon substrate not covered by the second doped region outside the recess, and the provided recess has a looser width control requirement than a conventional trench, is easier to manufacture than a conventional trench, and has a better deposition effect when depositing the first dielectric layer and the first doped region in the recess. At the same time, by providing the recess, the first dielectric layer contacts both the bottom wall and the side wall of the recess, so that carriers generated in the silicon substrate can easily pass through the first dielectric layer on the side wall of the recess and be separated and selectively collected in the corresponding first doped region. This not only reduces leakage current, but also enables selective transport of carriers in the vertical and horizontal directions, which is advantageous for multi-dimensional collection of carriers at the bottom wall and side wall of the recess. By providing at least one second dielectric layer, the rear surface of the silicon substrate realizes multi-layer passivation by the at least one second dielectric layer, thereby providing a better passivation effect and improving the internal rear surface reflection, and solving the problems of the high requirements for trench width control and the poor passivation effect in the conventional technology. EXAMPLES

[0103] The third embodiment of the present invention provides a method for manufacturing a selective contact region embedded solar cell, and for convenience of description, only the parts related to the embodiment of the present invention are shown. As shown in Fig. 11, the method for manufacturing a selective contact region embedded solar cell provided by the embodiment of the present invention is a method for manufacturing the selective contact region embedded solar cell described in the above embodiment, specifically, the method includes the following steps:

[0104] In step S11, a plurality of recesses are provided at intervals on the rear surface of a silicon substrate.

[0105] The method further includes a step of performing a pretreatment on the silicon substrate before step S11.

[0106] The pretreatment includes a step of cleaning the silicon substrate to remove the damaged layer. (1) removing particles and organic matter from the surface of the silicon substrate by RCA standard cleaning; (2) After cleaning the silicon substrate, the silicon substrate is further placed in a 2-5% KOH alkaline solution (potassium hydroxide) or TMAH solution (tetramethylammonium hydroxide, i.e., a developer) at a processing temperature of 50-80°C for a processing time of 1-5 minutes to remove the surface damage layer caused by the slice process; (3) acid-washing the surface of the silicon substrate using HCl to neutralize the alkaline solution remaining on the surface of the silicon substrate and remove metal impurities remaining on the surface of the silicon wafer; (4) cleaning the silicon substrate with an HF solution to remove the silica layer on the silicon wafer surface, forming Si-H passivation bonds with the dangling bonds on the surface of the silicon substrate, and finally drying the silicon substrate with nitrogen gas.

[0107] Furthermore, after the pre-processing of the silicon substrate is completed, the recesses can be formed by the following method.

[0108] Method 1 is a method in which grooves are directly formed by a laser at locations where recesses need to be provided at intervals, and silicon crystals on the back surface of the silicon substrate are locally removed to form the desired recesses. Method 2 is a method in which silicon oxide is formed on the entire surface of the silicon substrate by performing a thermal oxidation process on the silicon substrate, silicon oxide on the front and back surfaces of the silicon substrate are locally removed by laser groove processing, and the silicon oxide is further removed by wet etching and acid (e.g., HF) to form the desired recesses. Method 3 is a method in which silicon nitride is deposited on the back surface of the silicon substrate by a PECVD method, silicon nitride on the back surface is locally removed by laser groove processing, and the silicon nitride is further removed by wet etching to form the desired recesses. Method 4 is a method of depositing silicon nitride on the back surface of a silicon substrate or forming silicon oxide by thermal oxidation of the silicon substrate, depositing a photoresist mask on the back surface, developing in the development area by patterned screen and exposure, removing the development area by wet method with a developer, removing the silicon nitride / silicon oxide in the development area by acid (e.g., HF), and further removing the photoresist mask and silicon nitride / silicon oxide by wet etching to form the desired recesses. Method 5 is a method of printing a patterned paste on the back surface of a silicon substrate as a mask, removing the paste by wet etching to form the desired recesses.

[0109] In the embodiment of the present invention, it is preferable to form a recess by the above method 2. In the above method 2, the step of thermal oxidation treatment specifically includes performing dry oxygen oxidation / steam oxidation / wet oxygen oxidation (i.e., dry oxygen + steam) in a quartz tube, with oxygen gas and / or high-purity steam as specific reactants, a reaction pressure of 50-1000 mbar, a reaction temperature of 900-1200°C, and producing silicon oxide with a thickness of more than 10 nm by the reaction. The step of removing silicon oxide by laser groove processing specifically includes performing groove processing by a laser with a laser wavelength of 532 nm, a laser power of 10-60 W, a laser frequency of 250-1500 KHz or less, and a laser pulse width of 3-50 ns, and removing silicon oxide that needs to be removed. In the wet etching step, an alkaline solution and isoacetone are used, KOH or TMAH is used as the alkaline solution, the alkaline solution concentration is 1-5%, the isoacetone content is 1-10%, the reaction temperature is 60-85° C., and the reaction time is 10-30 min. In the step of removing silicon oxide with acid, HF is used as the acid solution, the acid solution concentration is 1-5%, the reaction temperature is room temperature, and the reaction time is 3-10 min.

[0110] Specifically, when the recesses are formed by the above method 2, the depth of each recess is 0.01 to 10 μm. The recesses formed may be arc-shaped, trapezoidal, or rectangular. The trenches used in the conventional technology are manufactured by laser drilling or wet etching, which places strict requirements on trench width control and makes manufacturing difficult. However, the recesses in this embodiment are easier to manufacture than the conventional trenches and do not have the strict requirements on trench width control.

[0111] In step S21, a first dielectric layer is fabricated on the back surface of the silicon substrate.

[0112] Before step S21, the specific production process may include a step of texturing the surface of the silicon substrate. In this embodiment, the surface texturing is mainly performed by etching with an alkaline solution. The reaction between the alkaline solution and the silicon substrate produces water-soluble compounds, and at the same time, a pyramidal texture structure is formed on the surface. In this case, due to the presence of the texture structure, when the incident light is reflected once by the texture, the reflected light does not directly enter the air, but hits the nearby texture, and is reflected by the texture a second time and even a third time before entering the air. In this way, the incident light is used multiple times to reduce the surface reflectance. If a rough texture structure is also required on the back side of the silicon substrate, the front and back sides of the silicon substrate may be textured at the same time. If a rough texture structure is not required on the back side of the silicon substrate, a silicon nitride protective layer is first deposited on the back side of the silicon substrate, and then the surface is textured, and the silicon nitride protective layer on the back side is removed by a laser, thereby avoiding the texturing of the back side of the silicon substrate.

[0113] Specifically, the step of manufacturing a first dielectric layer on the back surface of the silicon substrate by a high temperature oxidation process or a deposition process, etc., is set according to the type of the first dielectric layer to be specifically deposited, and is not specifically limited here. In this case, the first dielectric layer is one or more combinations of a tunneling oxide layer, an intrinsic silicon carbide layer, and an intrinsic amorphous silicon layer, and the thickness of the first dielectric layer is 1 to 20 nm. In this case, the first dielectric layer covers the entire back surface of the silicon substrate. If it is not necessary to provide the first dielectric layer in the region between the first doped region and the second doped region in the silicon substrate, the first dielectric layer covering the region between the first doped region and the second doped region in the silicon substrate may be removed by a laser.

[0114] In step S31, a first doped region and a second doped region are fabricated inside and outside each recess, respectively.

[0115] The steps of fabricating the first doped region and the second doped region respectively inside and outside each recess include fabricating by two deposition methods: in-situ deposition and ex-situ deposition.

[0116] Specifically, in one embodiment of the present invention, when in-situ deposition is used, step S31 includes: depositing different types of doped amorphous silicon or doped amorphous silicon carbide alternately inside and outside each recess; and performing a high temperature crystallization process on the doped amorphous silicon or doped amorphous silicon carbide to become doped polycrystalline silicon or doped silicon carbide, thereby obtaining a first doped region disposed within the recess and a second doped region disposed outside the recess.

[0117] In a possible embodiment, specifically, when performing in-situ deposition of a first doped region (specifically, for example, a P-type doped region) on a recess, the position of the protruding portion where deposition is not required is shielded by a mask. At this time, in-situ deposition of P-type amorphous silicon / P-type amorphous silicon carbide is performed on the recess. Correspondingly, due to a predetermined depth of the recess, the mask is in a position abutting the protruding portion and does not directly contact the bottom of the recess, so that impurity contamination of the bottom of the recess can be reduced. After deposition on the recess, impurity contamination due to a mask (for example, a silicon nitride mask or a silicon oxide mask) or a mask (for example, a hard mask) on the protruding portion is removed by a laser, and then the recess is shielded by a mask, and in-situ deposition of N-type amorphous silicon / N-type amorphous silicon carbide is performed on the position of the protruding portion outside the recess where deposition of a second doped region is required. After alternately depositing P-type amorphous silicon / P-type amorphous silicon carbide and N-type amorphous silicon / N-type amorphous silicon carbide inside and outside each recess, the temperature is set to 700-1000°C by direct high temperature or laser heating method, and thus, by high temperature crystallization treatment, the P-type amorphous silicon / P-type amorphous silicon carbide and N-type amorphous silicon / N-type amorphous silicon carbide inside and outside each recess become P-type polycrystalline silicon / P-type silicon carbide and N-type polycrystalline silicon / N-type silicon carbide, and a first doped region (i.e., P-type doped region) provided inside the recess and a second doped region (i.e., N-type doped region) provided outside the recess are obtained. The mask may be a hard mask, a silicon nitride mask, a silicon oxide mask, a photoresist mask, etc. Since the doped amorphous silicon or doped silicon carbide may be deposited on the side and surface of the silicon substrate during in-situ deposition, it is necessary to add a wet etching process to remove the plating that has wrapped around after high temperature crystallization.

[0118] In another possible embodiment, specifically, a first doped region (specifically, for example, a P-type doped region) is in-situ deposited on the entire back surface of the silicon substrate, in which P-type amorphous silicon / P-type amorphous silicon carbide is deposited on the entire back surface of the silicon substrate, and then all of the P-type amorphous silicon / P-type amorphous silicon carbide is removed from the entire area outside the recess of the silicon substrate by laser ablation, and then N-type amorphous silicon / N-type amorphous silicon carbide is deposited on the entire back surface of the silicon substrate, and then all of the N-type amorphous silicon / N-type amorphous silicon carbide is removed from the entire area except the second doped region in the protruding portion of the silicon substrate by laser ablation. Thereafter, the temperature is increased to 700-1000°C by direct high temperature or laser heating method, whereby the P-type amorphous silicon / P-type amorphous silicon carbide and N-type amorphous silicon / N-type amorphous silicon carbide inside and outside each recess become P-type polycrystalline silicon / P-type silicon carbide and N-type polycrystalline silicon / N-type silicon carbide, and a first doped region provided inside the recess and a second doped region provided outside the recess are obtained.

[0119] Specifically, in one embodiment of the present invention, when ex-situ deposition is used, step S31 includes: depositing intrinsic amorphous silicon or intrinsic silicon carbide into and around each recess; alternating different types of doping inside and outside each recess; and performing a high temperature crystallization process to convert the intrinsic amorphous silicon or intrinsic silicon carbide into doped polycrystalline silicon or doped silicon carbide, thereby obtaining a first doped region disposed within the recess and a second doped region disposed outside the recess.

[0120] The above step of alternating different types of doping in each recess specifically includes: doping each recess by alternately implanting ions of a first type and ions of a second type into and out of the recess; or or - doping by alternately depositing a first type of dopant source and a second type of dopant source inside and outside each recess; and alternately introducing a first type of source gas and a second type of source gas into and out of each recess to perform doping.

[0121] In a possible embodiment, specifically, first, intrinsic amorphous silicon or intrinsic silicon carbide is deposited in each recess, and then different types of ions are implanted into the inside and outside of the recess. For example, if the first doped region in the recess is a P-type doped region, P-type ions containing elements such as boron, aluminum, gallium, etc. are implanted into the recess, and N-type ions containing elements such as nitrogen, phosphorus, arsenic, etc. are locally implanted outside the recess. Then, the original intrinsic amorphous silicon or original intrinsic silicon carbide becomes doped polycrystalline silicon or doped silicon carbide through a high-temperature crystallization process. Since the intrinsic amorphous silicon or intrinsic silicon carbide may be deposited on the side and surface of the silicon substrate during deposition, a wet etching process needs to be added after the high-temperature crystallization to remove the plating that has wrapped around.

[0122] In a possible embodiment, specifically, first, intrinsic amorphous silicon or intrinsic silicon carbide is deposited inside and outside each recess. Then, different types of doping sources are alternately deposited inside and outside the recess by a mask method to perform doping. For example, when the first doped region is specifically a P-type doped region, a P-type doping source (e.g., borosilicate glass) containing boron, aluminum, gallium, etc. is deposited inside the recess to perform doping, thereby forming P-type amorphous silicon / P-type silicon carbide. Then, an N-type doping source (e.g., phosphorus silicate glass) containing nitrogen, phosphorus, arsenic, etc. is locally deposited outside the recess to perform doping, thereby forming N-type amorphous silicon / N-type silicon carbide. After alternately depositing the P-type doping source and the N-type doping source inside and outside each recess, the original intrinsic amorphous silicon or original intrinsic silicon carbide becomes doped polycrystalline silicon or doped silicon carbide through a high-temperature crystallization process. However, after depositing the different doping sources and performing the doping and high temperature crystallization process, a method such as a laser is still required to remove the doping sources.

[0123] The mask includes a hard mask, a silicon nitride mask, a silicon oxide mask, a photoresist mask, and the like. Specifically, in the case of a hard mask, for example, first, the convex portion of the silicon substrate is shielded by a hard mask, and then the first type of doping source is deposited in the concave portion. Then, the concave portion is shielded by a hard mask. Then, the second type of doping source is locally deposited outside the concave portion, and thus, doping is performed by depositing different types of doping sources inside and outside the concave portion. Specifically, in the case of a silicon nitride mask, for example, first, silicon nitride is deposited on the back surface, and then holes are formed in the concave portion by a laser hole-opening method, thereby removing the silicon nitride in the concave portion. Then, the first type of doping source is deposited in the concave portion, and then silicon nitride is deposited on the back surface, thereby protecting the first type of doping source by being covered with silicon nitride. Then, holes are formed in the convex portion by a laser hole-opening method, thereby removing the silicon nitride and the first type of doping source in the convex portion. Then, the second type of doping source is deposited on the convex portion, and then the second type of doping source and silicon nitride deposited in the concave portion are removed by the laser drilling method, thus depositing different types of doping sources inside and outside the concave portion to perform doping. The same applies to the silicon oxide mask and the silicon nitride mask, and the description will not be repeated here.

[0124] In a possible embodiment, specifically, first, intrinsic amorphous silicon or intrinsic silicon carbide is deposited inside and outside each recess, and then different types of source gases are introduced into the recess by a mask method to perform doping. For example, when the first doped region is a P-type doped region, P-type source gases (e.g., borane gas, or a carrier gas carrying boron trichloride or boron tribromide) containing elements such as boron, aluminum, and gallium are introduced into the recess to perform doping, thereby forming P-type amorphous silicon / P-type silicon carbide. N-type source gases (e.g., phosphorane gas or a carrier gas carrying trichlorethoxyphos) containing elements such as nitrogen, phosphorus, and arsenic are locally introduced outside the recess to perform doping, thereby forming N-type amorphous silicon / N-type silicon carbide. After different types of first type source gases and second type source gases are alternately introduced into and outside each recess, the original intrinsic amorphous silicon or original intrinsic silicon carbide becomes doped polycrystalline silicon or doped silicon carbide through a high-temperature crystallization process. The mask includes a hard mask, a silicon nitride mask, a silicon oxide mask, a photoresist mask, etc. For specific implementation, please refer to the above description.

[0125] Specifically, in another embodiment of the present invention, when ex-situ deposition is used, step S31 includes: depositing intrinsic amorphous silicon or intrinsic silicon carbide into and around each recess; The method may further include a step of alternately performing different types of doping through a mask inside and outside each recess, such that intrinsic amorphous silicon or intrinsic silicon carbide becomes doped polycrystalline silicon or doped silicon carbide, thereby obtaining a first doped region provided within the recess and a second doped region provided outside the recess.

[0126] In a possible embodiment, specifically, intrinsic amorphous silicon or intrinsic silicon carbide is first deposited inside and outside each recess. Then, a first type of diffusion is directly performed in the recess by a mask method to form a first doped region. A second type of diffusion is locally performed outside the recess to form a second doped region. For example, if the first doped region is a P-type doped region, boron diffusion is performed in the recess to form a P-type doped region. Phosphorus diffusion is locally performed outside the recess to form an N-type doped region. The mask includes a hard mask, a silicon nitride mask, a silicon oxide mask, a photoresist mask, etc. For specific implementation, please refer to the above description.

[0127] In addition, in the process of alternately manufacturing the first doped regions and the second doped regions, a high-temperature crystallization process is required, so there will be some fractures in the thin first dielectric layer. In this case, in the high-temperature diffusion process, the first dielectric layer will adhere to the fractured parts and the back surface of the silicon substrate, so that an internal diffusion region corresponding to a plurality of first doped regions or second doped regions is formed on the contact surface between the silicon substrate and the first dielectric layer.

[0128] Specifically, first doped regions and second doped regions are fabricated alternately inside and outside each recess, the first doped regions and the second doped regions include doped polycrystalline silicon or doped silicon carbide or doped amorphous silicon, and the sum of the thicknesses of the first dielectric layer and the first doped regions or the second doped regions is greater than 20 nm.

[0129] In step S41, a second dielectric layer and a third dielectric layer are formed on the front and back surfaces of a silicon substrate, respectively.

[0130] Prior to step S41, the method further includes a step of alternately performing diffusions of different types at a position on the rear surface of the silicon substrate between the first doped region and the second doped region, thereby diffusing at a local position of the protruding portion of the rear surface of the silicon substrate to obtain a third doped region of a different type. When the third doped region is a P-type diffusion layer, specifically, the manufacturing process includes: method 1 of introducing a source gas (e.g., borane gas, or a carrier gas loaded with boron trichloride or boron tribromide) containing elements such as boron, aluminum, gallium, etc., and performing thermal diffusion to form a P-type diffusion layer; method 2 of depositing a doping source (e.g., borosilicate glass) containing boron, aluminum, gallium, etc., and performing thermal diffusion to form a P-type diffusion layer; method 3 of manufacturing an aluminum electrode above the diffusion layer, and performing a high-temperature process to form a P-type diffusion layer doped with aluminum; method 4 of spin-coating a doping source (e.g., boron tribromide) containing boron, aluminum, gallium, etc., and performing thermal diffusion to form a P-type diffusion layer; and method 5 of injecting ions containing elements such as boron, aluminum, gallium, etc., and performing high-temperature diffusion to form a P-type diffusion layer.

[0131] When the third doped region is an N-type diffusion layer, specifically, the manufacturing process includes: a method 1 of introducing a raw material gas (e.g., a carrier gas carrying phosphorane gas or trichlorethoxyphos) containing elements such as nitrogen, phosphorus, and arsenic, and performing thermal diffusion to form an N-type diffusion layer; a method 2 of depositing a doping source (e.g., phosphorus silicate glass) containing nitrogen, phosphorus, and arsenic, and performing thermal diffusion to form an N-type diffusion layer; a method 3 of spin-coating a doping source (e.g., trichlorethoxyphos) containing nitrogen, phosphorus, and arsenic, and performing thermal diffusion to form an N-type diffusion layer; and a method 4 of injecting ions containing elements such as nitrogen, phosphorus, and arsenic, and forming an N-type diffusion layer through high-temperature diffusion. Note that after depositing the doping source and performing thermal diffusion, a method such as a laser for removing the doping source is further required.

[0132] In addition, before step S41, the method may further include a step of texturing the rear surface of the silicon substrate at a position between the first doped region and the second doped region to obtain a rough texture structure. For the specific texturing process, please refer to the above description.

[0133] Specifically, in the process of manufacturing the second and third dielectric layers on the front and back surfaces of the silicon substrate, the second and third dielectric layers are manufactured according to their specific compositions, which are not specifically limited here. Accordingly, the second and third dielectric layers may be one or more combinations of an aluminum oxide layer, a silicon nitride layer, a silicon oxynitride layer, an intrinsic silicon carbide layer, an intrinsic amorphous silicon layer, and a silicon oxide layer. In addition, when the second and third dielectric layers are formed into a multi-layer structure, the refractive index of each layer may be sequentially decreased from the silicon substrate outward, and the magnesium fluoride layer, which needs to have the lowest refractive index, may be manufactured as the outermost layer.

[0134] Also, before fabricating the third dielectric layer on the surface of the silicon substrate, a field layer or a floating junction may be fabricated first, specifically, the field layer is fabricated by phosphorus diffusion into the silicon substrate, or the floating junction is fabricated by boron diffusion into the silicon substrate, in which case the field layer or the floating junction is the front surface field (FSF) of the selective contact region embedded solar cell.

[0135] In step S51, a conductive layer is fabricated in the first doped region and the second doped region.

[0136] Specifically, when the second dielectric layer covers only the region between the first doped region and the second doped region in the silicon substrate, the conductive layer covers the entire back surface of the first doped region and the second doped region to form an electrical connection. When the second dielectric layer extends to cover the first doped region and the second doped region, the conductive layer covers the remaining back surfaces of the first doped region and the second doped region that are not covered by the second dielectric layer to form an electrical connection. When the second dielectric layer covers the entire back surface of the silicon substrate, the conductive layer is formed by penetrating the second dielectric layer and the first doped region and the second doped region by a method such as punching to form an electrical connection. As a result, a first electrode is formed in the first doped region, and a second electrode is formed in the second doped region.

[0137] When manufacturing HBC cells (interdigitated back-contact heterojunction solar cells) applied to low-temperature processes, the conductive layer is a TCO transparent conductive film and a metal electrode, and when manufacturing POLO-IBC cells (passivation-contact IBC cells) applied to high-temperature processes, the conductive layer is a metal electrode. The metal electrode includes a silver electrode, a copper electrode, an aluminum electrode, a tin-clad copper electrode, or a silver-clad copper electrode. Furthermore, the copper electrode is an electroplated copper electrode manufactured by an electroplating process or a copper electrode manufactured by physical vapor deposition. The electroplated copper uses nickel, chromium, titanium, or tungsten electrode as a seed layer or a protective layer.

[0138] The embodiments of the present invention provide the following beneficial effects over the prior art.

[0139] 1. Recesses are provided at intervals on the rear surface of a silicon substrate, a first doped region is provided in each recess, and a second doped region is provided outside each recess, so that the first doped region in the recesses and the second doped region outside the recesses are isolated by the silicon substrate not covered by the first doped region in the recesses or the silicon substrate not covered by the second doped region outside the recesses, and the recesses have looser width control requirements than a conventional trench, are easier to manufacture, and have better deposition effect when depositing the first dielectric layer and the first doped region in the recesses.

[0140] 2. By providing the recess, the first dielectric layer contacts both the bottom wall and the side wall of the recess, so that the carriers generated in the silicon substrate can easily pass through the first dielectric layer on the side wall of the recess and be isolated and selectively collected in the corresponding first doped region, which not only reduces the leakage current but also realizes the selective transport of carriers in the vertical and horizontal directions, which is favorable for the multi-dimensional collection of carriers on the bottom wall and the side wall of the recess.

[0141] 3. By providing at least one second dielectric layer, the back surface of the silicon substrate can be passivated by multiple layers through at least one second dielectric layer, and the passivation effect is better. In addition, the refractive index of each layer is controlled to decrease gradually from the silicon substrate to the outside, so that the internal back surface reflection of long wavelength light in the silicon substrate is increased, and the short circuit current density is increased.

[0142] 4. Due to the certain depth of the recess, the hard mask only directly contacts the protruding part between the two recesses, but does not directly contact the bottom of the recess, which reduces the contamination by impurities, and therefore the silicon substrate at the bottom wall of the recess can be protected from damage caused by the hard mask. In addition, the damage caused by the contact of the surface of the protruding part of the silicon substrate with the hard mask can also be removed by the subsequent texturing process.

[0143] 5. In the selective deposition process of the first doped region or the second doped region using a hard mask, for example, when depositing the first doped region in the recessed region, the convex portion outside the recessed region can be shielded by the hard mask. Due to the certain depth of the recess, the hard mask does not directly contact the bottom of the recessed region, so the deposition effect is good. In addition, since there is a convex structure of the silicon substrate with a certain width for isolation between each recess, when depositing the recessed region by shielding with a hard mask, the alignment of the hard mask does not require high accuracy, and a moderate deviation is acceptable. This simplifies the alignment of the hard mask and reduces the difficulty of the process.

[0144] 6. In the prior art, the trench area is limited in width and depth, and the chemical solution penetrates completely to the bottom of the trench due to the hydrophobicity of water and silicon wafer, making chemical wet texturing impossible. In contrast, in the present embodiment, the recesses are provided so that the back surface of the silicon substrate between adjacent recesses faces the protrusions, making it easier to obtain a rough texture structure by texturing than the conventional trench structure. The texturing of the protrusions on the back surface of the silicon substrate increases the internal back reflection of light in the silicon substrate, improving the light absorption rate of the silicon substrate.

[0145] 7. In the silicon substrate, a third doped region is provided in a region between the first doped region and the second doped region, so that carriers in the third doped region selectively pass through the first dielectric layer on the sidewall of an adjacent recess to be separated and collected in the corresponding first doped region, and also selectively pass through the first dielectric layer on the protrusion to be separated and collected in the corresponding second doped region. EXAMPLES

[0146] A fourth embodiment of the present invention further provides a cell assembly including the selective contact area embedded solar cell described in the above embodiments.

[0147] According to the cell assembly of this embodiment, the selective contact region embedded solar cell is provided with recesses at intervals on the back surface of the silicon substrate, a first doped region is provided in each recess, and a second doped region is provided outside each recess. This allows the first doped region in the recess and the second doped region outside the recess to be isolated by the silicon substrate not covered by the first doped region in the recess or the silicon substrate not covered by the second doped region outside the recess, and the recess has a looser width control requirement than the conventional trench, is easier to manufacture than the conventional trench, and has a better deposition effect when depositing the first dielectric layer and the first doped region in the recess. At the same time, by providing the recess, the first dielectric layer contacts both the bottom wall and the side wall of the recess, so that carriers generated in the silicon substrate can easily pass through the first dielectric layer on the side wall of the recess and be separated and selectively collected in the corresponding first doped region. This not only reduces leakage current, but also enables selective transport of carriers in vertical and horizontal directions, which is favorable for multi-dimensional collection of carriers at the bottom wall and side wall of the recess. By providing at least one second dielectric layer, the rear surface of the silicon substrate realizes multi-layer passivation by at least one second dielectric layer, which provides better passivation effect and improved internal rear surface reflection, thereby solving the problems of high requirements for trench width control and poor passivation effect in the conventional technology. EXAMPLES

[0148] A fifth embodiment of the present invention provides a photovoltaic power generation system including a cell assembly according to any of the above embodiments.

[0149] In the photovoltaic power generation system of this embodiment, the selective contact region embedded solar cell provided in the cell assembly has recesses spaced apart on the back surface of the silicon substrate, a first doped region provided in each recess, and a second doped region provided outside each recess. This allows the first doped region in the recess and the second doped region outside the recess to be isolated by the silicon substrate not covered by the first doped region in the recess or the silicon substrate not covered by the second doped region outside the recess, and the recesses have less stringent width control requirements than conventional trenches, are easier to manufacture, and have better deposition effects when depositing the first dielectric layer and the first doped region in the recess. At the same time, by providing the recesses, the first dielectric layer contacts both the bottom wall and the sidewall of the recess, so that carriers generated in the silicon substrate can easily pass through the first dielectric layer on the sidewall of the recess and be separated and selectively collected in the corresponding first doped region. This not only reduces leakage current, but also enables selective transport of carriers in vertical and horizontal directions, which is favorable for multi-dimensional collection of carriers at the bottom wall and side wall of the recess. By providing at least one second dielectric layer, the rear surface of the silicon substrate realizes multi-layer passivation by at least one second dielectric layer, which provides better passivation effect and improved internal rear surface reflection, thereby solving the problems of high requirements for trench width control and poor passivation effect in the conventional technology.

[0150] The above description is merely a preferred embodiment of the present invention, and is not intended to limit the present invention. As long as it does not deviate from the spirit and scope of the present invention, any modifications, replacements, improvements, etc. shall be included within the protection scope of the present invention.

Claims

1. a silicon substrate including a backside surface including a plurality of spaced recesses; a first dielectric layer disposed on the back surface of the silicon substrate; a plurality of first doped regions disposed only within the recess and on a surface of the first dielectric layer in the recess opposite to a surface of the first dielectric layer that contacts the rear surface of the silicon substrate; a plurality of second doped regions disposed apart from the first doped regions on a surface of the first dielectric layer opposite to a surface of the first dielectric layer contacting a rear surface of the silicon substrate outside the recess; at least one second dielectric layer disposed between the first plurality of doped regions and the second plurality of doped regions; a conductive layer disposed on a surface of the first doped region opposite to a surface in contact with the first dielectric layer and on a surface of the second doped region opposite to a surface in contact with the first dielectric layer, the second doped region and the recess are separated by a portion of the silicon substrate; the silicon substrate between the recess and the second doped region is covered only by the second dielectric layer; the second dielectric layer extends over the first doped region and the second doped region; Solar cell back contact structure.

2. 2. The back contact structure of claim 1, wherein the plurality of first doped regions are P-type doped regions and the plurality of second doped regions are N-type doped regions, or the plurality of first doped regions are N-type doped regions and the plurality of second doped regions are P-type doped regions.

3. The back contact structure of claim 1 , wherein the second doped regions are disposed in some areas of the first dielectric layer outside the recesses.

4. 2. The backside contact structure of claim 1, wherein the first doped region and the second doped region comprise doped polycrystalline silicon, doped silicon carbide, or doped amorphous silicon.

5. 10. The back contact structure of claim 1, wherein the first dielectric layer comprises a tunneling oxide layer, an intrinsic silicon carbide layer, an intrinsic amorphous silicon layer, or a combination thereof.

6. 10. The back contact structure of claim 1, wherein the second dielectric layer comprises an aluminum oxide layer, a silicon nitride layer, a silicon oxynitride layer, an intrinsic silicon carbide layer, an intrinsic amorphous silicon layer, a silicon oxide layer, or a combination thereof.

7. 2. The back contact structure of claim 1, wherein the second dielectric layer covers an area between the first doped region and the second doped region or extends to cover the first doped region and / or the second doped region.

8. The backside contact structure of claim 1 , wherein a portion of the backside of the silicon substrate between the first plurality of doped regions and the second plurality of doped regions includes a rough texture structure.

9. 3. The back contact structure of claim 2, wherein the width of the P-type doped region is 300-600 μm, the width of the N-type doped region is 100-500 μm, and the depth of the plurality of recesses is 0.01-10 μm.

10. 2. The back contact structure of claim 1, wherein the horizontal distance between the first doped region and the second doped region is 0-500 μm.

11. The backside contact structure of claim 1 , wherein the first dielectric layer covers the first doped region and the second doped region, or covers the entire backside surface of the silicon substrate.

12. 2. The backside contact structure of claim 1, further comprising a third doped region disposed in the silicon substrate located in a region between the first doped region and the second doped region.

13. The back contact structure of claim 1 , wherein the first dielectric layer is connected to bottom and side walls of the plurality of recesses.

14. The back contact structure of claim 1 , wherein the plurality of recesses have an arc shape, a trapezoid shape, or a square shape.

15. 2. The back contact structure of claim 1, wherein the first dielectric layer has a thickness of 1-20 nm, and the sum of the thickness of the first dielectric layer and the first doped region or the second doped region is greater than 20 nm.

16. 6. The back contact structure of claim 5, wherein said first dielectric layer is said tunneling oxide layer and said intrinsic silicon carbide layer.

17. 17. The back contact structure of claim 5 or claim 16, wherein the tunneling oxide layer comprises one or more of a silicon oxide layer and an aluminum oxide layer.

18. 7. The back contact structure of claim 6, wherein the second dielectric layer comprises the aluminum oxide layer and the intrinsic silicon carbide layer, or the silicon oxide layer and the intrinsic silicon carbide layer, and a thickness of the second dielectric layer is greater than 25 nm.

19. 20. The back contact structure of claim 18, wherein a thickness of the aluminum oxide layer or the silicon oxide layer in the second dielectric layer is less than 25 nm, and a thickness of the intrinsic silicon carbide layer in the second dielectric layer is greater than 10 nm.

20. 7. The back contact structure of claim 6, further comprising a magnesium fluoride layer disposed on the outer surface of the second dielectric layer.

21. The back contact structure of claim 1 , wherein the conductive layer is a TCO film and / or a metal electrode.

22. 22. The back contact structure of claim 21, wherein the metal electrode comprises a silver electrode, a copper electrode, an aluminum electrode, a tin-clad copper electrode, or a silver-clad copper electrode.

23. 23. The back contact structure of claim 22, wherein the copper electrode is an electroplated copper electrode produced by an electroplating process or a copper electrode produced by physical vapor deposition.

24. 12. The back contact structure of claim 11, wherein a first dielectric layer corresponding to the first doped region is the same as or different from a first dielectric layer corresponding to the second doped region.

25. A back contact structure according to any one of claims 1 to 24; a third dielectric layer disposed on a surface of the silicon substrate. Selective contact area recessed solar cell.

26. 26. The selective contact area embedded solar cell of claim 25, wherein the third dielectric layer comprises an aluminum oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon carbide layer, an intrinsic amorphous silicon layer, a silicon oxide layer, or a combination thereof.

27. 27. The selective contact region embedded solar cell of claim 26, wherein the third dielectric layer comprises the silicon oxide layer and the silicon carbide layer, or the aluminum oxide layer and the silicon carbide layer, and the thickness of the third dielectric layer is greater than 50 nm.

28. 28. The selective contact region embedded solar cell of claim 27, wherein the thickness of the aluminum oxide layer or the silicon oxide layer in the third dielectric layer is less than 40 nm, and the thickness of the silicon carbide layer in the third dielectric layer is greater than 10 nm.

29. 30. The selective contact region embedded solar cell of claim 26 or 28, wherein the silicon carbide layer in the third dielectric layer comprises at least one silicon carbide film, the refractive index of the different silicon carbide films decreasing outward from the surface of the silicon substrate.

30. 27. The selective contact area embedded solar cell of claim 26, further comprising a magnesium fluoride layer disposed on an outer layer of said third dielectric layer.

31. 26. The selective contact area embedded solar cell of claim 25 further comprising a field layer or floating junction disposed between said surface of said silicon substrate and said third dielectric layer.

32. 32. A cell assembly comprising the selective contact area embedded solar cell of any one of claims 25 to 31.

33. 33. A photovoltaic power generation system comprising the battery assembly of claim 32.

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