Silicon wafers and epitaxial silicon wafers

Abstract

To reduce a dislocation loop defect density which causes a lamination defect in a silicon wafer.SOLUTION: There is provided a silicon wafer having a diameter of 200 mm, a dopant of phosphorus, a resistivity of 0.5 mΩ cm or more and 1.2 mΩ cm or less, and a carbon concentration of 3×1016 atoms / cm3 or more.SELECTED DRAWING: Figure 5

Description

[Technical field]

[0001] The present invention relates to a silicon wafer and an epitaxial silicon wafer. [Background technology]

[0002] For example, epitaxial silicon wafers for power MOS transistors require that the resistivity of the silicon wafer before the silicon epitaxial layer is formed is extremely low.For this reason, we provide epitaxial silicon wafers in which a silicon epitaxial layer is formed on the surface of a silicon wafer that is highly doped with phosphorus (P) to achieve a resistivity of 1.2 mΩ·cm or less.

[0003] In recent years, there has been a demand for n-type silicon wafers with extremely low resistivity of 0.9 mΩ·cm or less. However, when the resistivity of a silicon wafer is very low, there is a problem that stacking faults (SFs) occur in the silicon epitaxial layer when epitaxial growth processing is performed, and there is a demand for a reduction in the SF density that occurs in the silicon epitaxial layer.

[0004] The present applicant has discovered a technology for suppressing the generation of SF in a silicon epitaxial layer by using a method for adjusting the residence time (thermal history) of a single crystal ingot at 570°C±70°C during single crystal growth (shortening the residence time in the temperature range where SF nuclei are formed) as described in Patent Document 1. In addition, the applicant has discovered that the generation of SF in a silicon epitaxial layer can be suppressed by using a method for performing high-temperature heat treatment (argon annealing) before the growth of the silicon epitaxial layer as described in Patent Document 2. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] International Publication No. 2014 / 175120 [Patent Document 2] JP 2014-011293 A Summary of the Invention [Problem to be solved by the invention]

[0006] As described in Patent Document 1, if a silicon wafer is cut from a crystal region in which the time spent in the temperature range in which SF nuclei are formed is shortened (a silicon wafer with fewer SF nuclei), the SF density in the epitaxial layer after the silicon epitaxial layer is grown can be reduced. However, even if the silicon wafer is one in which the time spent in the temperature range in which SF nuclei are formed is shortened, if the resistivity of the silicon wafer falls below 0.7 mΩ·cm, there is a problem that the SF density generated in the epitaxial layer after the silicon epitaxial layer is grown increases.

[0007] In addition, as described in Patent Document 2, the SF density in the epitaxial layer after growth of the silicon epitaxial layer can be reduced by subjecting a silicon wafer (a silicon wafer with many SF nuclei) cut from a crystal region that has a long residence time in a temperature range where SF nuclei are formed to argon annealing. However, it is not possible to reduce the SF density to 100 nuclei / wafer or less. Although the techniques described in Patent Documents 1 and 2 are effective in suppressing the generation of SF in a silicon epitaxial layer, users demand a further reduction in the SF density.

[0008] An object of the present invention is to provide a silicon wafer having a low density of dislocation loop defects that cause SFs, and an epitaxial silicon wafer having a silicon epitaxial layer with low generation of SFs. [Means for solving the problem]

[0009] As a result of extensive research into the causes of SFs that occur in silicon epitaxial layers, the inventors have discovered that in silicon wafers doped with a high concentration of phosphorus, there are roughly two types of dislocation loop-shaped defects (defects in which disturbed crystal arrangements are connected in a loop shape) that are determined by the thermal history that the crystal is subjected to during the growth of a single crystal ingot.

[0010] The process by which the discovery of dislocation loop-shaped defects was made will be described below. First, a 200 mm diameter silicon single crystal ingot was grown with a high concentration of phosphorus added as a dopant, and silicon wafers were produced from a crystal region that had a long residence time in the temperature zone where SF nuclei were formed (hereinafter referred to as the SF nuclei generation temperature zone residence time), and silicon wafers were produced from a crystal region that had a short residence time in the SF nuclei generation temperature zone.

[0011] Specifically, silicon wafers with a long residence time in the SF nucleation temperature zone were manufactured as follows: those with a resistivity of 0.75 mΩ cm cut from the top side of the straight body of a single crystal ingot with a residence time at 570°C ± 70°C of 350 minutes or more; and those with a short residence time in the SF nucleation temperature zone were manufactured as follows: those with a resistivity of 0.7 mΩ cm cut from the bottom side of the straight body of a single crystal ingot with a residence time at 570°C ± 70°C of 50 minutes or less. Each silicon wafer was cleaved in the thickness direction, and the cleaved cross section was observed using a transmission electron microscope (TEM). The results are shown in Figure 1.

[0012] As a result, in silicon wafers cut from the crystal region (top crystal region) that had a long residence time in the SF nucleation temperature zone, large complex dislocation loop defects 2 in which dislocation loops overlap each other as shown in Figure 1(a) were observed, and it was confirmed that there was a high density of large defects with sizes exceeding 60 nm. Figure 1(b) is a photograph of the complex dislocation loop defect 2 shown in Figure 1(a) taken from a different angle, and it can be seen that this complex dislocation loop defect 2 has a planar shape. On the other hand, in silicon wafers cut from a crystal region with a short residence time in the SF nucleation temperature zone (the bottom crystal region), small dislocation loop defects 4 as shown in Figure 2 were observed, and it was confirmed that the density of large complex dislocation loop defects with sizes exceeding 60 nm was low.

[0013] It was confirmed that SFs are generated in silicon epitaxial layers starting from large-sized complex dislocation loop defects. This is because it is believed that the state in which SFs are generated in silicon epitaxial layers differs depending on the presence or absence of complex dislocation loop defects. Therefore, the inventors considered the mechanism by which dislocation loops are generated and came to the following conclusion.

[0014] The present inventors hypothesized the following regarding the occurrence of dislocation loop defects. First, in the process of cooling a silicon single crystal ingot, interstitial phosphorus existing between the lattices in the crystal kicks out the lattice silicon existing at the lattice position (flips off the lattice silicon), generating interstitial silicon. This excess interstitial silicon aggregates and forms dislocation loops, and interstitial phosphorus segregates in these dislocation loops, generating dislocation loop defects.

[0015] The researchers then thought that suppressing the agglomeration of interstitial silicon would be effective in suppressing the occurrence of dislocation loop defects, and that the agglomeration of interstitial silicon could be suppressed by intentionally adding an impurity element that can pair with interstitial silicon, and came up with the idea of ​​incorporating carbon into the crystal during the single crystal growth stage. The inventors have completed the present invention by doping (adding) carbon to a silicon melt to grow a silicon single crystal ingot and evaluating the defects formed in the carbon-doped silicon wafer, which has revealed that the defect density of large dislocation loops formed in the silicon wafer can be reduced.

[0016] On the other hand, Patent Document 3 describes a method of increasing the density of oxygen precipitates (BMD: Bulk Micro Defect) formed in a silicon wafer by adding carbon to the wafer, thereby improving the gettering ability of the epitaxial silicon wafer. Specifically, the invention described in Patent Document 3 is a technology that aims to solve the decrease in gettering ability caused by a decrease in oxygen concentration in the latter half of the growth of a single crystal ingot by adding carbon. It is well known that, in order to provide an epitaxial wafer with excellent gettering ability, the BMD density is increased by adding carbon to a silicon crystal, and this is not limited to Patent Document 3.

[0017] [Patent Document 3] Special Publication No. 2003-505324

[0018] In general, it is known that a region in a silicon wafer in which phosphorus is present at a high concentration by a phosphorus thermal diffusion process, a phosphorus ion implantation process, the formation of a phosphorus-containing epitaxial layer, or the like functions as a gettering layer (also called a phosphorus gettering method). That is, a silicon wafer that is doped with phosphorus at a high concentration so that the resistivity is 1.2 mΩ·cm or less, which is the subject of the present invention, has sufficient gettering characteristics simply by the presence of phosphorus at a high concentration. For this reason, there is no requirement to increase the BMD density in the epitaxial wafer that is the subject of the present invention. Therefore, there is no motivation to add carbon to a silicon wafer that is doped with phosphorus at a high concentration, such as the subject of the present invention, to increase the BMD density and thereby increase the gettering ability. Furthermore, Patent Document 3 does not consider at all the frequent occurrence of SF, which is a particular problem in silicon wafers that are doped with a high concentration of phosphorus so that the substrate resistivity is 1.2 mΩ·cm or less.

[0019] The silicon wafer of the present invention has a diameter of 200 mm, a dopant of phosphorus, a resistivity of 0.5 mΩ cm or more and 1.2 mΩ cm or less, and a carbon concentration of 3×1016 atoms / cm 3 That's all.

[0020] The resistivity of a silicon wafer as defined in the present invention is a value measured on the surface of the silicon wafer by a four-probe method. The carbon concentration of a silicon wafer as defined in the present invention is a value obtained by thinning the silicon wafer by polishing, and measuring the carbon concentration at the center of the thickness of the silicon wafer by secondary ion mass spectrometry (SIMS). Since it is difficult to accurately measure the carbon concentration at the top surface of a silicon wafer due to the large amount of noise components, accurate measurement of the carbon concentration is possible if the measurement is performed at a depth position of 1 μm or more from the wafer surface, excluding the top surface. In the present invention, in order to obtain a more accurate value, the concentration is specified as the concentration at the center of the silicon wafer thickness.

[0021] In the silicon wafer, the oxygen concentration of the silicon wafer is 4×10 17 atoms / cm 3 More than 10x10 17 atoms / cm 3 It may be the following: The oxygen concentration of a silicon wafer as defined in the present invention is a value obtained by thinning the silicon wafer by polishing, and measuring the oxygen concentration at the center of the thickness of the silicon wafer by SIMS. Since it is difficult to accurately measure the oxygen concentration at the top surface of a silicon wafer due to the large amount of noise components, accurate measurement of the oxygen concentration is possible if the measurement is performed at a depth of 1 μm or more from the wafer surface, excluding the top surface. In the present invention, in order to obtain a more accurate value, the concentration is specified as the concentration at the center of the silicon wafer thickness.

[0022] In the above silicon wafer, it is preferable that the silicon wafer is free of COPs. In the present invention, "COP is not present" refers to a silicon wafer in which no COP is detected by the observation evaluation described below. That is, first, a silicon wafer cut from a single crystal silicon ingot grown by the CZ method is subjected to SC-1 cleaning (i.e., cleaning with a mixed solution of ammonia water, hydrogen peroxide water, and ultrapure water in a ratio of 1:1:15), and the surface of the silicon wafer after cleaning is observed and evaluated using a surface defect inspection device, Surfscan SP-1 manufactured by KLA-Tencor, to identify light point defects (LPDs) estimated to be surface pits. At this time, the observation mode is set to oblique mode (oblique incidence mode), and the estimation of the surface pits is performed based on the detection size ratio of the wide / narrow channel. The LPDs thus identified are evaluated as to whether they are COPs or not using an atomic force microscope (AFM). A silicon wafer in which no COP is observed by this observation evaluation is defined as a "silicon wafer in which no COP is present".

[0023] The epitaxial silicon wafer of the present invention has a diameter of 200 mm, a dopant of phosphorus, a resistivity of 0.5 mΩ cm or more and 1.2 mΩ cm or less, and a carbon concentration of 3×10 16 atoms / cm 3 The present invention includes the silicon wafer described above and a silicon epitaxial layer on the surface of the silicon wafer.

[0024] The resistivity of the epitaxial silicon wafer defined in the present invention is a value measured by four-probe method on the back surface of the silicon wafer. When an oxide film is provided on the back surface of the epitaxial silicon wafer, the resistivity is a value measured by four-probe method on the back surface of the silicon wafer from which the back surface oxide film has been removed. The carbon concentration of the epitaxial silicon wafer defined in the present invention is a value obtained by thinning the silicon wafer by polishing and measuring the carbon concentration at the center of the thickness of the silicon wafer by SIMS.

[0025] In the manufacture of epitaxial silicon wafers, the silicon wafers are subjected to high-temperature heat treatment during epitaxial growth and high-temperature heat treatment before the epitaxial growth process, which causes carbon to diffuse outward and reduces the carbon concentration in the surface layer of the silicon wafer. For this reason, in order to measure the carbon concentration of an epitaxial silicon wafer, it is necessary to measure at a depth position where outward diffusion of carbon does not occur, and an accurate measurement of the carbon concentration is possible if the measurement is performed at a deep position of 40 μm or more from the wafer surface in the depth direction of the wafer thickness. In the present invention, in order to obtain a more accurate value, the concentration is specified as the concentration at the center of the silicon wafer thickness.

[0026] The epitaxial silicon wafer of the present invention has a diameter of 200 mm, a dopant of phosphorus, a resistivity of 0.5 mΩ cm or more and 1.2 mΩ cm or less, and a carbon concentration of 3×10 16 atoms / cm 3 and a silicon epitaxial layer on a surface of the silicon wafer, wherein the silicon wafer has a low carbon concentration layer on the surface side in contact with the silicon epitaxial layer, the carbon concentration of the low carbon concentration layer is 0.9 times or less than the carbon concentration at the center of the thickness of the silicon wafer, and the depth of the low carbon concentration layer is 5 μm or more and 15 μm or less from the boundary between the silicon wafer and the silicon epitaxial layer in the thickness direction of the silicon wafer.

[0027] The depth of the low carbon concentration layer is a value based on the carbon concentration profile in the depth direction obtained by SIMS measurement, and means the depth position (width) in the thickness direction of the silicon wafer from the boundary between the silicon epitaxial layer and the silicon wafer.

[0028] In the epitaxial silicon wafer, it is desirable that the resistivity of the silicon wafer is 0.9 mΩcm or less.

[0029] In the epitaxial silicon wafer, the carbon concentration in the silicon wafer surface in contact with the epitaxial layer is 1×10 16 atoms / cm 3 It is desirable to do the following:

[0030] In the epitaxial silicon wafer, the oxygen concentration of the silicon wafer is 4×10 17 atoms / cm 3 More than 10x10 17 atoms / cm 3 It is desirable to do the following:

[0031] The oxygen concentration of the epitaxial silicon wafer defined in the present invention is a value obtained by thinning the silicon wafer by polishing, and measuring the oxygen concentration at the center of the thickness of the silicon wafer by SIMS. To measure the oxygen concentration in an epitaxial silicon wafer, it is necessary to measure at a depth position where outward diffusion of oxygen does not occur, and accurate oxygen concentration measurement is possible if the measurement is performed at a depth position of 150 μm or more from the wafer surface in the wafer thickness direction. In the present invention, the concentration is specified as the concentration at the center of the silicon wafer thickness in order to obtain a more accurate value.

[0032] In the epitaxial silicon wafer, it is preferable that the silicon wafer is free of COPs.

[0033] In the epitaxial silicon wafer, it is preferable that an oxide film is provided on the back surface of the silicon wafer.

[0034] In the epitaxial silicon wafer, it is desirable that there be no oxide film on the edge portion and the outer periphery of the back surface of the silicon wafer.

[0035] In the epitaxial silicon wafer, it is desirable that the density of LPDs having a size of 0.09 μm or more observed on the surface of the epitaxial layer is 100 pieces / wafer or less.

[0036] In the epitaxial silicon wafer, it is desirable that the density of LPDs having a size of 0.09 μm or more observed on the surface of the epitaxial layer is 60 pieces / wafer or less.

[0037] In the epitaxial silicon wafer, it is desirable that the density of LPDs having a size of 0.09 μm or more observed on the surface of the epitaxial layer is 10 pieces / wafer or less.

[0038] The silicon wafer of the present invention has a diameter of 200 mm, a dopant of phosphorus, a resistivity of 0.5 mΩ cm or more and 1.2 mΩ cm or less, and a carbon concentration of 3×10 16 atoms / cm 3 The silicon wafer as described above has a low carbon concentration layer on a surface thereof, the carbon concentration of the low carbon concentration layer is 0.9 times or less than the carbon concentration at the center portion of the thickness of the silicon wafer, and the depth of the low carbon concentration layer is 5 μm or more and 15 μm or less from the surface of the silicon wafer in the thickness direction of the silicon wafer.

[0039] In the silicon wafer, the oxygen concentration of the silicon wafer is 4×10 17 atoms / cm 3 More than 10x10 17 atoms / cm 3 It is preferable that:

[0040] In the above silicon wafer, it is preferable that the silicon wafer is free of COPs. [Brief description of the drawings]

[0041] [Figure 1] This is a photograph of complex dislocation loops observed in a silicon wafer cut from a crystalline region that had a long residence time in the SF nucleation temperature zone. [Diagram 2] This is a photograph of dislocation loops observed in a silicon wafer cut from a crystalline region where the residence time in the SF nucleation temperature zone was short. [Diagram 3] 1 is a flowchart showing one embodiment of a method for producing an epitaxial silicon wafer according to the present invention. [Figure 4] 1 is a cross-sectional view of one embodiment of an epitaxial silicon wafer according to the present invention. [Diagram 5] 1 is a graph showing the evaluation results of dislocation loops in the epitaxial silicon wafers of Example 1 and Comparative Example 1. [Figure 6] 1 is a graph showing the results of investigating the carbon concentration profiles of the epitaxial silicon wafers of Examples 4 and 5. [Figure 7] 1 shows X-ray topography photographs of the surfaces of silicon wafers of Examples 6 and 7 and Comparative Examples 4 and 5. [Figure 8] 1 is a graph showing the relationship between LPD density and resistivity when an epitaxial layer is formed on the surface of each of silicon wafers in Examples 8 and 9 and Comparative Examples 6 and 7. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0042] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. The silicon wafer according to the present invention is a silicon wafer having a diameter of 200 mm, and is doped with phosphorus (P) as a dopant for adjusting resistivity, so that the resistivity is set to 0.5 mΩ cm or more and 1.2 mΩ cm or less, and the carbon concentration is 3×10 16 atoms / cm 3 That is all about the silicon wafer. The silicon wafer having a diameter of 200 mm as defined in the present invention means a silicon wafer having a diameter of 200±0.5 mm, taking into account processing errors and the like. An epitaxial silicon wafer according to the present invention comprises the above-mentioned silicon wafer and a silicon epitaxial layer formed on the silicon wafer.

[0043] A suitable manufacturing flow for obtaining the epitaxial silicon wafer according to the present invention is shown in Fig. 3. The manufacturing flow preferably includes a single crystal ingot manufacturing step S1, a back surface oxide film forming step S2, a peripheral oxide film removing step S3, an argon annealing step S4, a pre-baking step S5, and an epitaxial layer forming step S6.

[0044] In the single crystal ingot manufacturing process S1, a single crystal silicon ingot doped with phosphorus as an n-type dopant and having a diameter of 200 mm is manufactured by the CZ method (Czochralski method) using a single crystal ingot pulling device (not shown) so as to satisfy the following conditions.

[0045] (Phosphorus concentration) The phosphorus concentration in the single crystal ingot is 6×10 19 atoms / cm 3 More than 1.64×10 20 atoms / cm 3 By doping red phosphorus so that the resistivity is 0.5 mΩ cm to 1.2 mΩ cm, it is possible to obtain a single crystal ingot with a resistivity of 0.5 mΩ cm to 1.2 mΩ cm. In addition, the phosphorus concentration is 8.3 × 10 19 atoms / cm 3 By doing so, it is possible to obtain a single crystal ingot with a resistivity of 0.9 mΩ·cm or less. The phosphorus concentration of the silicon wafer is the value measured by SIMS at the center of the silicon wafer thickness. The phosphorus concentration can also be calculated from the resistivity measured by the four-point probe method using the formula or graph specified in SEMI MF723-0307. If the silicon raw material is doped with phosphorus before being melted, the phosphorus will evaporate when the silicon raw material is melted, making it impossible to obtain the desired resistivity. Therefore, it is desirable to dope the silicon melt with red phosphorus after the silicon raw material is melted.

[0046] (carbon concentration) The carbon concentration in the single crystal ingot is 3×10 16 atoms / cm 3 5×10 or more 17 atoms / cm 3As described below, by adding carbon powder together with silicon raw material to a crucible and melting them, a single crystal ingot having a predetermined carbon concentration can be grown. Carbon concentration 3×10 16 atoms / cm 3 By doing so, it is possible to reduce the size and density of dislocation loop defects formed in the silicon wafer, and to significantly reduce the SF density generated in the epitaxial layer after the epitaxial growth process. Specifically, even if the silicon wafer is cut from the top side of the crystal, where the residence time in the SF nucleation temperature zone is longer, the silicon wafer functions as a silicon wafer that can reliably reduce the LPD density on the silicon epitaxial layer surface after the epitaxial growth process to 100 pieces / wafer or less.

[0047] In addition, the effect of reducing the LPD density (SF density) generated in the epitaxial layer increases as the carbon concentration increases. 17 atoms / cm 3 If the carbon concentration exceeds 3×10, dislocations are likely to occur in the single crystal during the growth process of the single crystal ingot, making it difficult to grow a single crystal ingot without dislocations. 17 atoms / cm 3 It is more preferable to do the following:

[0048] (Oxygen concentration) When the oxygen concentration in the silicon wafer is high, as described later, it tends to deteriorate the device breakdown voltage characteristics. Therefore, it is desirable to lower the oxygen concentration in the single crystal ingot. The oxygen concentration should be 4×10 17 atoms / cm 3 More than 10x10 17 atoms / cm 3 The following range is desirable:

[0049] In order to grow a single crystal ingot with a low oxygen concentration, it is desirable to apply a magnetic field to the silicon melt. A well-known horizontal magnetic field or cusp magnetic field may be applied, and the oxygen concentration incorporated into the single crystal can be reduced to the desired concentration by slowing down the rotation speed of the crucible containing the silicon melt or by lowering the pressure inside the pulling furnace. In addition, the oxygen concentration is 4×10 17 atoms / cm 3 If the oxygen concentration is less than 4×10, the strength of the silicon wafer is low and there is a risk of slip dislocation occurring when the wafer is subjected to high-temperature heat treatment. 17 atoms / cm 3 It is desirable to have more than this.

[0050] Thereafter, silicon wafers are cut out from the single crystal ingot produced in the single crystal ingot production process S1 and subjected to predetermined processing (grinding, etching, polishing, etc.) to produce mirror-finished silicon wafers with excellent surface roughness and flatness.

[0051] In the rear surface oxide film forming step S2, it is desirable to form an oxide film (hereinafter referred to as a rear surface oxide film) on the rear surface of the silicon wafer using a CVD apparatus within the following condition range. Source gas: A mixture of monosilane (SiH4) and oxygen (O2) Thickness of backside oxide film: 100nm to 1500nm Film forming temperature: 400℃ or higher and 450℃ or lower By providing such a back surface oxide film, the autodoping phenomenon can be suppressed, and the resistance fluctuation of the epitaxial layer can be suppressed.

[0052] In the backside oxide film forming step S2, it is difficult to form an oxide film only on the backside of the silicon wafer, and an oxide film is inevitably formed on the edge (chamfered portion) of the silicon wafer after the backside oxide film forming step S2. If an epitaxial layer is formed on the surface of the oxide film, there is a risk of nodules (granular silicon) being generated in that portion, so it is desirable to remove the oxide film formed on the edge of the silicon wafer and on the outer periphery of the backside of the wafer.

[0053] For this reason, in the peripheral oxide film removal step S3, it is sufficient to remove the oxide film present on the edge (chamfered portion) of the silicon wafer and on the peripheral portion of the back surface of the wafer using various techniques such as polishing and etching, and it is preferable that the removal width of the oxide film present on the peripheral portion of the back surface of the wafer is less than 5 mm from the outer edge of the silicon wafer. By removing the edge of the silicon wafer and the outer periphery of the back surface oxide film in this manner, it is possible to prevent the generation of nodules during the growth of the silicon epitaxial layer, and also to prevent the generation of particles from the wafer edge.

[0054] In the argon annealing step S4, it is preferable to perform the heat treatment within the following condition range. Gas atmosphere: Argon gas Heat treatment temperature: 1150℃ to 1250℃ Heat treatment time: 30 minutes or more and 120 minutes or less It is preferable to use a batch furnace (vertical heat treatment device) capable of performing heat treatment on a plurality of silicon wafers at once as the heat treatment device.

[0055] High-concentration carbon doping suppresses the generation of large dislocation loop defects in silicon wafers, and small dislocation loop defects present in silicon wafers can be eliminated by argon annealing of the silicon wafer, thereby minimizing the generation of SFs in the epitaxial layer.

[0056] Furthermore, by performing argon annealing on the silicon wafer before the epitaxial growth process, it is possible to reduce the diffusion of carbon from the silicon wafer to the silicon epitaxial layer during the epitaxial layer formation step S6. This point will be described below. FIG. 4(a) is a schematic diagram showing a low carbon concentration layer formed in the surface layer of a silicon wafer by argon annealing. 4(a), high-temperature argon annealing of silicon wafer 11 causes outward diffusion of carbon in the surface layer of silicon wafer 11, lowering the carbon concentration in the surface layer. As a result, low-carbon concentration layers 12 having a lower carbon concentration than the carbon concentration in thickness center C of silicon wafer 11 where no outward diffusion of carbon has occurred are formed on the front and back sides of silicon wafer 11.

[0057] FIG. 4(b) is a schematic diagram showing a carbon concentration profile when epitaxial growth is performed on an argon-annealed silicon wafer. 4(b), the carbon concentration after the epitaxial layer formation step S6 shows a concentration profile in which the carbon concentration in the surface layer of the silicon wafer is reduced. If a region in which the carbon concentration is 0.9 times or less the carbon concentration in the thickness center C of the silicon wafer 11 where no outward diffusion of carbon occurs is defined as the low carbon concentration layer 12, the depth D of the low carbon concentration layer 12 formed on the surface 11a side of the silicon wafer 11 in contact with the silicon epitaxial layer 13 after the epitaxial growth process can be set to 5 μm or more and 15 μm or less from the boundary between the silicon wafer 11 and the silicon epitaxial layer 13 in the thickness direction of the silicon wafer 11. The formation of this low carbon concentration layer 12 makes it possible to further reduce the diffusion of carbon from the silicon wafer 11 to the silicon epitaxial layer 13 during the epitaxial layer formation step S6. The thickness of the low carbon concentration layer 12 can be adjusted as desired by adjusting the heat treatment temperature and time of the argon annealing.

[0058] In the pre-bake step S5 in a gas atmosphere containing hydrogen and hydrogen chloride, it is preferable to subject the silicon wafer to heat treatment in an epitaxial device (Centura (registered trademark) manufactured by Applied Materials, Inc.) within the following condition range. Atmosphere: Hydrogen gas, hydrogen chloride gas Hydrogen gas flow rate: 40L / min Hydrogen chloride gas flow rate: 1L / min Heat treatment temperature: 1050℃ to 1250℃ Heat treatment time: 30 seconds or more and 300 seconds or less

[0059] The removal amount of the surface layer of the silicon wafer in the pre-bake step S5 is preferably 100 nm or more and 300 nm or less, and more preferably 150 nm±10 nm.

[0060] In the epitaxial layer forming step S6, it is desirable to grow an epitaxial layer on the silicon wafer that has been subjected to the pre-baking step S5 within the following condition range. Dopant gas: Phosphine (PH3) gas Raw material source gas: Trichlorosilane (SiHCl3) gas Carrier gas: Hydrogen gas Growth temperature: 1050℃ or higher and 1150℃ or lower Epitaxial layer thickness: 1 μm to 10 μm Epitaxial layer resistivity: 0.01 Ω·cm to 10 Ω·cm Phosphorus concentration: 4.44 x 10 14 atoms / cm 3 More than 4.53 x 10 18 atoms / cm 3 below By performing the epitaxial layer forming step S6, an epitaxial silicon wafer in which a silicon epitaxial layer is formed on the surface of a silicon wafer is manufactured.

[0061] By carrying out the above process flow, it is possible to provide a silicon wafer capable of reducing the generation of SFs in the epitaxial layer, and an epitaxial silicon wafer having a reduced SF density in the epitaxial layer. Specifically, the diameter is 200 mm, phosphorus is added so that the resistivity is between 0.5 mΩ cm and 1.2 mΩ cm, and the carbon concentration is 3×10 16 atoms / cm 3 As described above, a silicon wafer doped with a high concentration of carbon is provided, which is a novel silicon wafer not previously available.

[0062] The high concentration of carbon doping results in a silicon wafer with a reduced defect density of large dislocation loops. This silicon wafer effectively functions as a bulk wafer for epitaxial growth, reducing the occurrence of epitaxial defects (LPD / SF observed on the epitaxial layer surface).

[0063] In addition, the oxygen concentration of the silicon wafer is set to 4×10 17 atoms / cm 3 More than 10x10 17 atoms / cm 3 By setting the content to the range below, it is possible to prevent a failure in the device breakdown voltage even when carbon is doped.

[0064] Furthermore, by subjecting a silicon wafer before forming a silicon epitaxial layer to argon annealing, the carbon concentration in the surface layer of the silicon wafer is reduced, and the amount of carbon diffusing into the silicon epitaxial layer during the formation of the silicon epitaxial layer can be reduced. By reducing the amount of carbon diffused into the silicon epitaxial layer, it is possible to suppress the deterioration of electrical characteristics due to the generation of defects caused by carbon incorporated into the silicon epitaxial layer during heat treatment in the device process for fabricating devices on the epitaxial silicon wafer.

[0065] In the above embodiment, the resistivity of the silicon wafer is set to 0.5 mΩ·cm or more and 1.2 mΩ·cm or less, but for a silicon wafer with lower resistance, the resistivity is preferably set to 0.5 mΩ·cm or more and 0.9 mΩ·cm or less. The lower the resistivity, the more significant the generation of SF in the epitaxial layer becomes, and therefore the effect of the carbon doping of the present invention is more pronounced.

[0066] Furthermore, the silicon wafer of this embodiment is manufactured from a single crystal ingot made from a silicon melt doped with phosphorus so that the resistivity is 1.2 mΩ·cm or less. Due to the high concentration of phosphorus added, the OSF ring region in which oxidation induced stacking faults (OSFs) occur during the manufacturing process of the single crystal ingot disappears at the center of the ingot, resulting in a crystal region without COPs. In other words, the silicon wafer of this embodiment can be made into a wafer without COPs due to the high concentration of phosphorus added, and the occurrence of defects due to COPs in the epitaxial layer can be prevented. EXAMPLES

[0067] The experimental conditions and evaluation results of the examples and comparative examples of the present invention will be described below. <Dislocation Loop Evaluation> The following Example 1 and Comparative Example 1 were evaluated for dislocation loops. <Example 1> In Example 1, epitaxial silicon wafers were manufactured within the condition range of the epitaxial silicon wafer manufacturing flow described with reference to Fig. 3. The conditions for growing the single crystal ingot were as follows: carbon powder was added before melting the silicon raw material, and phosphorus was added to the silicon melt after melting the raw material so that the resistivity at the top end of the straight body of the single crystal ingot was 0.9 mΩ cm. A sample wafer was cut from the top of the carbon-added single crystal ingot and processed to produce a mirror-finished silicon wafer. The resistivity of this silicon wafer was measured by the four-point probe method and found to be 0.75 mΩ cm, and the carbon concentration of the silicon wafer was 5×10 16 atoms / cm 3 It was.

[0068] <Comparative Example 1> Compared to the above Example 1, except that carbon doping was not performed at the stage of growing the single crystal ingot, silicon wafers were manufactured under the same manufacturing conditions as in Example 1. As in Example 1, a sample wafer with a resistivity of 0.75 mΩ cm was cut out and subjected to a predetermined processing treatment to produce a mirror-finished silicon wafer.

[0069] The silicon wafers of Example 1 and Comparative Example 1 were cleaved in the thickness direction, and the cleaved cross sections were observed with a transmission electron microscope (TEM). Figure 5 is a graph showing the evaluation results of dislocation loops in the epitaxial silicon wafers of Example 1 and Comparative Example 1. The horizontal axis of Figure 5 represents the dislocation loop size, and the vertical axis represents the dislocation loop density. FIG. 5(a) shows the results for the silicon wafer of Comparative Example 1, which was not doped with carbon. Since the sample wafer was cut from the top side of the crystal, where the residence time in the SF nucleation temperature zone is longer, many large dislocation loop defects exceeding 60 nm were observed. On the other hand, FIG. 5(b) shows the results for the silicon wafer of Example 1 doped with a high concentration of carbon. Since the sample wafer was cut from the top side of the crystal, where the residence time in the SF nucleation temperature zone is long, many small dislocation loops were observed, but it was confirmed that the density of large dislocation loops exceeding 60 nm was significantly reduced. That is, it was confirmed that the density of large dislocation loops formed in the silicon wafer was reduced by carbon doping.

[0070] [LPD density evaluation] When a silicon epitaxial layer is formed using a sample silicon wafer cut from the top side of the straight body of an ingot, where the residence time in the temperature range where SF nuclei are formed is long, SFs occur frequently in the epitaxial layer, and the LPD density increases. Therefore, in this experiment, sample silicon wafers of the following Examples 2 and 3 and Comparative Examples 2 and 3 cut from the top side of the straight body were prepared, and the LPD density observed on the epitaxial layer surface after the epitaxial layer was formed was measured.

[0071] Specific conditions for the back surface oxide film forming process and the epitaxial layer forming process, which were carried out as common processing steps in each of the examples and comparative examples, are as follows: [Conditions for forming oxide film on the back surface] A backside oxide film was formed on the backside of each silicon wafer (the surface opposite to the surface on which the epitaxial film was formed) under the following conditions. Source gas: A mixture of monosilane (SiH4) and oxygen (O2) Film formation method: CVD method Film forming temperature: 400℃ Backside oxide thickness: 550nm The oxide film present on the chamfered portion and the outer periphery of the rear surface of each silicon wafer was removed by etching. [Hydrogen baking conditions] Atmosphere: Hydrogen gas Heat treatment temperature: 1200℃ Heat treatment time: 30 seconds [Epitaxial film growth conditions] Dopant gas: Phosphine (PH3) gas Raw material source gas: Trichlorosilane (SiHCl3) gas Carrier gas: Hydrogen gas Growth temperature: 1080℃ Epitaxial film thickness: 4μm Resistivity (epitaxial film resistivity): 0.3 Ω cm

[0072] <Comparative Example 2> An epitaxial silicon wafer was produced by forming a silicon epitaxial layer having a thickness of 4 μm on the surface of the silicon wafer of Comparative Example 1, in which no carbon doping was performed and many dislocation loops were observed.

[0073] <Comparative Example 3> The silicon wafer of Comparative Example 1 was subjected to argon annealing (heat treatment in an argon gas atmosphere at 1200° C. for 30 minutes), and then a silicon epitaxial layer having a thickness of 4 μm was formed on the surface of the silicon wafer to produce an epitaxial silicon wafer.

[0074] <Example 2> The carbon-doped silicon wafer of Example 1 was not subjected to argon annealing, and a silicon epitaxial layer having a thickness of 4 μm was formed on the surface of the silicon wafer to produce an epitaxial silicon wafer.

[0075] <Example 3> The carbon-doped silicon wafer of Example 1 was subjected to argon annealing (heat treatment in an argon gas atmosphere at 1200°C for 30 minutes), and then a silicon epitaxial layer having a thickness of 4 μm was formed on the surface of the silicon wafer to produce an epitaxial silicon wafer. The epitaxial growth treatment conditions were the same for Examples 2 and 3 and Comparative Examples 2 and 3.

[0076] The LPD density on the silicon epitaxial layer surface of the epitaxial silicon wafer of Comparative Example 2 was measured using a surface defect inspection device (Surfscan SP-1, manufactured by KLA-Tencor). Specifically, the measurement was performed in Normal mode (DCN mode) to measure the density of LPDs of 90 nm or more in size observed on the epitaxial film surface. The measurement area was the epitaxial layer surface excluding an annular region extending from the outermost periphery of the epitaxial silicon wafer to 3 mm inward in the radial direction. The number of counted LPDs can be regarded as the number of SFs. As a result, the number of detected LPDs was too large, causing overflow (100,000 or more per wafer), and the LPD measurement itself could not be performed. In Comparative Example 3, in which the silicon wafer was subjected to argon annealing, the LPD density was reduced compared to Comparative Example 2, but 235 LPDs / wafer were observed. Below, the LPD density of each Example and Comparative Example was measured under the same measurement conditions as those of Comparative Example 2.

[0077] When the LPD density on the surface of the silicon epitaxial layer of the epitaxial silicon wafer of Example 2 was measured, more than 90,000 LPDs were observed per wafer. This is presumably because, although the density of large-sized complex dislocation loops in the silicon wafer was reduced by carbon doping, there were still many small dislocation loops less than 60 nm in size.

[0078] In Example 3, in which the silicon wafer was subjected to argon annealing before the epitaxial growth process, the LPD density on the epitaxial layer surface was significantly reduced to 56 LPDs / wafer. This is believed to be due to the disappearance of small dislocation loops with sizes of less than 60 nm that existed in the silicon wafer surface layer by argon annealing.

[0079] From the above, it was revealed that when carbon is doped and argon annealing is performed on the silicon wafer, the effect of reducing SF generation in the silicon epitaxial layer is enhanced, and the LPD density after the formation of the epitaxial layer can be reduced to about 1 / 4 compared to Comparative Example 3.

[0080] [Carbon concentration profile evaluation] When carbon is doped at a high concentration, carbon diffusion into the silicon epitaxial layer occurs due to heat treatment during the formation of the silicon epitaxial layer. Therefore, the behavior of carbon diffusion into the silicon epitaxial layer was evaluated. <Example 4> Silicon wafer with high carbon concentration (carbon concentration at the center of the wafer thickness: 6.5×10 16 atoms / cm 3 ) was prepared, and an epitaxial silicon wafer was manufactured in which a silicon epitaxial layer was formed similarly to that in Example 2 without performing argon annealing. <Example 5> A silicon wafer similar to that in Example 4 was subjected to argon annealing similar to that in Example 3, and then a silicon epitaxial layer was formed to produce an epitaxial silicon wafer.

[0081] Fig. 6 is a graph showing the results of a carbon concentration profile measurement using secondary ion mass spectrometry for the epitaxial silicon wafers of Examples 4 and 5. The horizontal axis of Fig. 6 represents the depth from the surface of the epitaxial silicon wafer, and the vertical axis represents the carbon concentration. It can be seen that the interface between the silicon epitaxial layer and the silicon wafer is located at a depth of 4 μm from the surface of the epitaxial silicon wafer.

[0082] In Example 4, in which the silicon wafer was not subjected to argon annealing, the width of the low carbon concentration layer was less than 1 μm. On the other hand, in Example 5, in which argon annealing was performed before the formation of the silicon epitaxial layer, a low carbon concentration layer having a thickness of 8.2 μm was formed in the depth direction of the wafer from the interface between the silicon epitaxial layer and the silicon wafer, and the carbon concentration of the silicon epitaxial layer was below the detection limit (2×10 15 atoms / cm 3 It was confirmed that the thickness of the low carbon concentration layer was 5.6 μm when the heat treatment conditions were changed to 1150° C.×10 min under the same conditions as in Example 5, 7.3 μm when the heat treatment conditions were changed to 1150° C.×10 min, 9.4 μm when the heat treatment conditions were changed to 1200° C.×60 min, and 15 μm when the heat treatment conditions were changed to 1300° C.×60 min. That is, the thickness of the low carbon concentration layer can be adjusted arbitrarily by adjusting the heat treatment temperature and time in the argon annealing. By forming a low carbon concentration layer of a predetermined thickness in the surface layer of the silicon wafer, the amount of carbon diffusing from the silicon wafer to the epitaxial layer can be reduced.

[0083] [Evaluation of slip dislocation] For the following Comparative Examples 4 and 5 and Examples 6 and 7, the presence or absence of slip dislocations (defects along the crystal plane of silicon) was investigated depending on the presence or absence of carbon doping and argon annealing. The specifications and conditions common to the silicon wafers of Comparative Examples 4 and 5 and Examples 6 and 7 are listed below. Resistivity: 0.82mΩ·cm Carbon concentration: 4×10 16 atoms / cm 3 The argon annealing in Comparative Example 5 and Example 7 was a heat treatment in an argon gas atmosphere at 1200° C. for 30 minutes. In addition, in the following description, "heat treatment corresponding to the epitaxial layer growth conditions" refers to heat treatment performed without introducing raw material source gas into the epitaxial apparatus (Centura (registered trademark) manufactured by Applied Materials, Inc.), and refers to heat treatment at 1150°C for 1 minute in a hydrogen gas atmosphere. <Comparative Example 4> Silicon wafers that were not doped with carbon were subjected to heat treatment corresponding to the epitaxial layer growth conditions without argon annealing (only heat treatment was performed, and no silicon epitaxial layer was grown). <Comparative Example 5> The silicon wafer that was not doped with carbon was subjected to argon annealing, and a heat treatment corresponding to the epitaxial layer growth conditions was performed. <Example 6> The carbon-doped silicon wafer was subjected to a heat treatment corresponding to the epitaxial layer growth conditions without argon annealing. <Example 7> The carbon-doped silicon wafer was subjected to argon annealing, and a heat treatment corresponding to the epitaxial layer growth conditions was carried out.

[0084] The presence or absence of slip dislocations observed on the wafer surface was confirmed for each silicon wafer by X-ray topography. As a result, as shown in Figure 7, no slip dislocations were observed in any of the silicon wafers, and it was confirmed that slip dislocations do not occur even when high-concentration carbon doping is performed.

[0085] [Verification of resistivity, carbon concentration, and LPD density] In order to verify the correlation between resistivity, carbon concentration, and LPD density for the following Comparative Examples 6 and 7 and Examples 8 and 9, silicon wafers were manufactured under a plurality of conditions, an epitaxial layer was formed on the surface of each silicon wafer, and the LPD density observed on the epitaxial layer surface was measured. The argon annealing in the following Comparative Example 7 and Example 9 was a heat treatment in an argon gas atmosphere at 1200° C. for 30 minutes. <Comparative Example 6> Without carbon doping, phosphorus was doped so that the resistivity of the upper end of the straight body of the single crystal ingot was 1.2 mΩ cm, and single crystal ingots with resistivity ranging from 0.5 mΩ cm to 1.2 mΩ cm were grown, and multiple silicon wafers with different resistivities were manufactured from the single crystal ingots. A 4 μm thick epitaxial layer was formed on each silicon wafer without argon annealing. <Comparative Example 7> As in Comparative Example 6, single crystal ingots with resistivity ranging from 0.5 mΩ cm to 1.2 mΩ cm were grown without carbon doping, and multiple silicon wafers with different resistivities were manufactured from the single crystal ingots. No carbon doping was performed, and each silicon wafer was subjected to argon annealing, after which an epitaxial layer with a thickness of 4 μm was formed.

[0086] <Example 8> As in Comparative Example 6, a single crystal ingot with a resistivity range of 0.5 mΩ cm to 1.2 mΩ cm was grown, and a plurality of silicon wafers with different resistivities were produced from the single crystal ingot. 16 atoms / cm 3However, each silicon wafer was not subjected to argon annealing, and an epitaxial layer having a thickness of 4 μm was formed. <Example 9> As in Comparative Example 6, a single crystal ingot with a resistivity range of 0.5 mΩ cm to 1.2 mΩ cm was grown, and a plurality of silicon wafers with different resistivities were produced from the single crystal ingot. 16 atoms / cm 3 After each silicon wafer was subjected to argon annealing, an epitaxial layer having a thickness of 4 μm was formed.

[0087] Fig. 8 is a graph showing the relationship between the resistivity of the silicon wafer and the LPD density observed on the epitaxial layer surface for each of the epitaxial silicon wafers of Example 8, Example 9, and Comparative Examples 6 and 7. The horizontal axis of Fig. 8 shows the position from which the silicon wafer was sliced ​​in terms of the solidification rate of the body of the ingot, when the solidification amount of the entire length of the body of the grown ingot is set to 1.

[0088] 8, in Example 8 in which carbon doping was performed and argon annealing was not performed before epitaxial growth processing, an LPD density of about 5000 particles / wafer was observed in the silicon wafer cut from the ingot body position where the solidification rate is about 0.1, which is the crystal region on the top side, and although the effect of reducing the LPD density was confirmed, the LPD density overflowed in the silicon wafer cut from the ingot body position where the solidification rate is about 0.3. In addition, when a silicon wafer cut from the crystal region on the bottom side was used, the LPD density could be reduced to 150 particles / wafer or less, even in a silicon wafer with an extremely high resistivity of 0.5 mΩ·cm.

[0089] In Example 9, in which the silicon wafer was carbon doped and argon annealed before the epitaxial growth process, the LPD density was 60 / wafer or less even when the silicon wafer was cut from the top crystal region. This is because the high concentration of carbon doping was used to reduce the size of the dislocation loop defects, and the argon annealing of the silicon wafer eliminated the reduced size of the dislocation loop defects. It was revealed that the synergistic effect of the high concentration of carbon doping and argon annealing was extremely large in reducing SF. On the other hand, when the silicon wafer was used from the bottom crystal region (crystal region with a solidification rate of 0.6 or more) where the residence time in the SF nucleation temperature zone was shorter, the LPD density was 10 / wafer or less for all of the cases.

[0090] On the other hand, in Comparative Example 6, in which carbon doping was not performed and argon annealing was not performed on the silicon wafers, when a silicon wafer cut from the top crystal region was used, the LPD density overflowed, and when a silicon wafer cut from the bottom crystal region was used, the LPD density significantly decreased; however, the LPD density was 100 particles / wafer or more in a silicon wafer with a resistivity of 0.5 mΩ cm. In Comparative Example 7, in which carbon doping was not performed and the silicon wafer was subjected to argon annealing before the epitaxial growth process, the LPD density was reduced compared to Comparative Example 6. However, when a silicon wafer cut from the top crystal region was used, the LPD density decreased from 100 / wafer to 300 / wafer.

[0091] From the above results, 3×10 16 atoms / cm 3It was found that by performing the above carbon doping and by subjecting the silicon wafer to argon annealing before the epitaxial growth process, the LPD density observed on the epitaxial layer surface in all crystal regions of the single crystal ingot can be made at least 100 / wafer. Furthermore, even if the silicon wafer is not subjected to argon annealing, by performing carbon doping, the LPD density in the bottom crystal region can be made 100 / wafer or less. Note that this embodiment does not disclose all experimental examples that were developed, but the inventors have found that the LPD density can be made at least 3×10 16 atoms / cm 3 It was confirmed that adding carbon to a high concentration as described above can reduce the LPD density after epitaxial growth processing for silicon wafers with resistivities of 0.5 mΩ cm to 1.2 mΩ cm, compared to cases where no carbon is added.

[0092] [Evaluation of device breakdown voltage characteristics] The device breakdown voltage characteristics were evaluated. Here, device breakdown voltage is one of the quality characteristics of a semiconductor device, and refers to the voltage at which breakdown occurs when the gate and source of a semiconductor device are shorted and the voltage between the drain and source is gradually increased.

[0093] There is a concern that if oxygen in a silicon wafer diffuses into the epitaxial layer on which a semiconductor device is fabricated, it may affect the device's breakdown voltage characteristics. For this reason, the inventors prepared silicon wafers with six different oxygen concentrations, formed silicon epitaxial layers on each silicon wafer, and investigated whether there is a difference in the device's breakdown voltage characteristics due to the difference in oxygen concentration. Furthermore, they investigated whether there is a difference in the device's breakdown voltage characteristics due to the presence or absence of carbon doping in the silicon wafer.

[0094] Specifically, a semiconductor device was fabricated for each of the epitaxial silicon wafers of Samples 1 to 12 shown in Table 1, and a predetermined voltage was applied between the drain and source while the gate and source constituting the semiconductor device were short-circuited. If breakdown occurred, the withstand voltage characteristics were judged to be "bad," and if no breakdown occurred, the withstand voltage characteristics were judged to be "good."

[0095] The epitaxial silicon wafers of Samples 1 to 6 are 200 mm in diameter, and are formed by forming a 4 μm thick silicon epitaxial layer on a phosphorus-doped silicon wafer with a resistivity of 0.75 mΩcm. The sample wafers are formed by forming an epitaxial layer on each of six silicon wafers with different oxygen concentrations without adding carbon. The epitaxial silicon wafers of samples 7 to 12, like samples 1 to 6, are 200 mm in diameter, and are formed by forming a silicon epitaxial layer of 4 μm in thickness on a silicon wafer doped with phosphorus and having a resistivity of 0.75 mΩcm. The carbon concentration is 6×10 16 atoms / cm 3 The sample wafers were made by forming an epitaxial layer on each of six silicon wafers with different oxygen concentrations. The carbon concentration and oxygen concentration were measured by polishing the silicon wafer to make it thin, and measuring the concentration at the center of the thickness of the silicon wafer by SIMS.

[0096] [Table 1]

[0097] As shown in Table 1, it was confirmed that in Samples 7 to 9, when carbon was doped, the device breakdown voltage was easily impaired. However, even when carbon was doped, the oxygen concentration was increased to 10×10 17 atoms / cm 3 It has been confirmed that the following can prevent failure in the device withstand voltage. [Explanation of symbols]

[0098] 10... epitaxial silicon wafer, 11... silicon wafer, 11a... surface, 12... low carbon concentration layer, 13... epitaxial layer, C... center, D... depth.

Claims

1. The diameter is 200 mm, The dopant is phosphorus, the resistivity is 0.5 mΩ cm or more and 1.2 mΩ cm or less, and the carbon concentration is 3×10 １６ atoms / cm ３ That's it for silicon wafers.

2. The silicon wafer according to claim 1, The oxygen concentration of the silicon wafer is 4×10 １７ atoms / cm ３ Above 10 x 10 １７ atoms / cm ３ Below is a silicon wafer.

3. The silicon wafer according to claim 1 or 2, The silicon wafer is free of COPs.

4. The diameter is 200 mm, the dopant is phosphorus, the resistivity is 0.5 mΩ cm or more and 1.2 mΩ cm or less, and the carbon concentration is 3×10 １６ atoms / cm ３ The silicon wafer described above; and a silicon epitaxial layer on a surface of the silicon wafer.

5. The diameter is 200 mm, the dopant is phosphorus, the resistivity is 0.5 mΩ cm or more and 1.2 mΩ cm or less, and the carbon concentration is 3×10 １６ atoms / cm ３ The silicon wafer described above; a silicon epitaxial layer on the surface of the silicon wafer; the silicon wafer has a low carbon concentration layer on a surface side in contact with the silicon epitaxial layer, The carbon concentration of the low carbon concentration layer is 0.9 times or less than the carbon concentration at the thickness center of the silicon wafer, and An epitaxial silicon wafer, wherein a depth of the low carbon concentration layer is 5 μm or more and 15 μm or less from a boundary between the silicon wafer and the silicon epitaxial layer in a thickness direction of the silicon wafer.

6. The epitaxial silicon wafer according to claim 4 or 5, The epitaxial silicon wafer has a resistivity of 0.9 mΩcm or less.

7. The epitaxial silicon wafer according to claim 4 or 5, The carbon concentration in the silicon wafer surface in contact with the epitaxial layer is 1×10 １６ atoms / cm ３ An epitaxial silicon wafer is shown below.

8. The epitaxial silicon wafer according to claim 4 or 5, The oxygen concentration of the silicon wafer is 4×10 １７ atoms / cm ３ Above 10 x 10 １７ atoms / cm ３ An epitaxial silicon wafer is shown below.

9. The epitaxial silicon wafer according to claim 4 or 5, An epitaxial silicon wafer, wherein no COPs are present in the silicon wafer.

10. The epitaxial silicon wafer according to claim 4 or 5, An epitaxial silicon wafer having an oxide film on a back surface of the silicon wafer.

11. The epitaxial silicon wafer of claim 10, An epitaxial silicon wafer, wherein the edge and the outer periphery of the back surface of the silicon wafer are free of an oxide film.

12. The epitaxial silicon wafer according to claim 4 or 5, An epitaxial silicon wafer, in which the density of LPDs having a size of 0.09 μm or more observed on the surface of the epitaxial layer is 100 pieces / wafer or less.

13. The epitaxial silicon wafer according to claim 4 or 5, An epitaxial silicon wafer, in which the density of LPDs having a size of 0.09 μm or more observed on the surface of the epitaxial layer is 60 or less per wafer.

14. The epitaxial silicon wafer according to claim 4 or 5, An epitaxial silicon wafer, in which the density of LPDs having a size of 0.09 μm or more observed on the surface of the epitaxial layer is 10 or less per wafer.

15. The diameter is 200 mm, the dopant is phosphorus, the resistivity is 0.5 mΩ cm or more and 1.2 mΩ cm or less, and the carbon concentration is 3×10 １６ atoms / cm ３ The silicon wafer as described above, the silicon wafer has a low carbon concentration layer on a surface thereof; The carbon concentration of the low carbon concentration layer is 0.9 times or less than the carbon concentration at the thickness center of the silicon wafer, and A silicon wafer, wherein the depth of the low carbon concentration layer is 5 μm or more and 15 μm or less from the surface of the silicon wafer in a thickness direction of the silicon wafer.

16. The silicon wafer according to claim 15, The oxygen concentration of the silicon wafer is 4×10 １７ atoms / cm ３ Above 10 x 10 １７ atoms / cm ３ Below is a silicon wafer.

17. The silicon wafer according to claim 15 or 16, The silicon wafer is free of COPs.

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