Multilayer structure, method for manufacturing multilayer structure, and method for manufacturing semiconductor device

Abstract

To provide: a multilayer structure capable of preventing a stacking fault from expanding and capable of suppressing deterioration in forward direction characteristics of a semiconductor device; a method for manufacturing the same; and a method for manufacturing the semiconductor device.SOLUTION: A multilayer structure comprises a first conductivity type silicon carbide substrate 1s and a first conductivity type epitaxial growth layer 3e provided on the substrate 1s and having an impurity density lower than that of the substrate 1s. A first immobilized layer 21 having crystal defects immobilizing a growth layer side basal plane dislocation 22 continuously occurring in the inside of the epitaxial growth layer 3e from a substrate side basal plane dislocation 12 existing in the substrate 1s is provided in the inside of the epitaxial growth layer 3e to 50 nm from an interface between the substrate 1s and the epitaxial growth layer 3e.SELECTED DRAWING: Figure 7

Description

[Technical field]

[0001] The present invention relates to a multilayer structure (SiC epitaxial growth substrate) which is a composite structure in which a silicon carbide (SiC) single crystal is epitaxially grown on an underlying single crystal substrate, a method for manufacturing the multilayer structure, and a method for manufacturing a semiconductor device. [Background technology]

[0002] It is known that a multilayer structure including an epitaxially grown layer of SiC contains many stacking faults, which adversely affect the characteristics of a semiconductor device. Commercially available SiC substrates contain threading screw dislocations and edge dislocations that propagate in the c-axis direction, and basal plane dislocations (BPDs) that propagate in the basal plane. There are also many mixed dislocations (dislocation loops) in which screw dislocations and edge dislocations are mixed. These dislocations in the multilayer structure propagate into the epitaxial layer during epitaxial growth and are inherited. It is known that threading dislocations such as screw dislocations and edge dislocations increase the leakage current of a semiconductor device using a SiC single crystal (hereinafter referred to as "SiC semiconductor device"). Patent Document 1 describes that ions are implanted into the main surface of a substrate constituting a multilayer structure to reduce crystallinity, and then heat treatment is performed to restore crystallinity, thereby eliminating screw dislocations from threading mixed dislocations in the surface layer of the substrate.

[0003] On the other hand, basal plane dislocations cause the degradation of the characteristics, especially the forward characteristics, of power semiconductor devices using SiC single crystals (hereinafter referred to as "SiC power devices"). For example, it is known that the forward resistance increases when a forward current is passed through a pin diode using a SiC multilayer structure. The increase in the forward resistance of a pin diode occurs when stacking faults expand starting from basal plane dislocations present in the drift region of the n-type epitaxial layer. The basal plane dislocations continue from the substrate to the epitaxial layer, penetrating the epitaxial layer to the surface. The basal plane dislocations in the drift region can become the starting point of stacking faults when minority carriers (holes in the n-type epitaxial layer) are injected from the p-type anode region into the drift region due to current flow.

[0004] It is known that dislocations are converted during the process of dislocations in the substrate propagating to the epitaxial layer. Most of the basal plane dislocations in the substrate are converted to threading dislocations during epitaxial growth, and the remaining few propagate through the epitaxial layer as basal plane dislocations. Since threading dislocations do not expand into stacking faults, it is possible to suppress the occurrence of stacking faults by increasing the conversion rate of basal plane dislocations to threading dislocations in the drift region to nearly 100% and further reducing the density of holes injected into the basal plane dislocations.

[0005] The conversion rate of basal plane dislocations to threading dislocations is about 95%, and about 5% of them remain in the epitaxial layer. Non-Patent Document 1 reports that the conversion rate of BPDs to TEDs is increased by implanting argon (Ar) ions near the top surface of the substrate. However, although they are converted into harmless threading dislocations, the basal plane dislocations at the root of the threading dislocations remain near the substrate interface in the epitaxial layer, making it difficult to completely prevent the defects that cause the expansion of stacking faults. Furthermore, even with regard to the method of reducing the hole density injected from the p-type anode region by using a buffer layer, the threshold hole density at which basal plane dislocations start to expand into stacking faults varies greatly depending on the stress in the substrate. Therefore, in order to prevent the expansion of basal plane dislocations with a small threshold into stacking faults, the current flow cannot be increased, making it difficult to use at the limit performance of the device. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] JP 2011-168453 A [Non-patent literature]

[0007] [Non-Patent Document 1] C. Heidorn et al., "Basal Plane Dislocation Enhancement in 4H-SiC homo-epitaxial Layers by Ion Implantation into the Wafer Substrate," 12th European Conference on Silicon Carbide and Related Materials, 2018, Proceedings ID: 1228 Summary of the Invention [Problem to be solved by the invention]

[0008] In view of the above problems, the present invention aims to provide a multilayer structure capable of preventing the expansion of stacking faults and suppressing deterioration of the forward characteristics of a semiconductor device using SiC, a method for manufacturing the multilayer structure, and a method for manufacturing a semiconductor device. [Means for solving the problem]

[0009] In order to achieve the above object, one aspect of the present invention includes: (a) a silicon carbide substrate of a first conductivity type; and (b) an epitaxial growth layer of the first conductivity type provided on the substrate and having a lower impurity concentration than the substrate, wherein a basal plane dislocation that occurs in the epitaxial growth layer continuously from a basal plane dislocation present in the substrate is immobilized in the epitaxial growth layer within 50 nm from an interface between the substrate and the epitaxial growth layer. The peak of the atomic concentration distribution is located a first passivation layer, the first passivation layer including atoms that immobilize basal plane dislocations; and provided on the entire surface of the substrate in the in-plane direction, The present invention relates to a multilayer structure in which the atoms that immobilize basal plane dislocations are at least one type of atom selected from the group consisting of magnesium, calcium, barium, and manganese.

[0010] Another aspect of the present invention includes the steps of: (a) epitaxially growing an epitaxial growth layer of a first conductivity type on a silicon carbide substrate of a first conductivity type with a lower impurity density than the substrate; and (b) forming a first passivation layer in the epitaxial growth layer, the first passivation layer being located within 50 nm from an interface between the substrate and the epitaxial growth layer, the first passivation layer passing through a crystal defect to passivate basal plane dislocations occurring in the epitaxial growth layer successively from basal plane dislocations present in the substrate. On the entire surface of the epitaxial growth layer The method for manufacturing a multilayer structure includes a step of forming a first passivation layer, and the step of forming a first passivation layer includes a step of injecting atoms that immobilize basal plane dislocations from the upper surface of the epitaxial growth layer with a projected range that is within 50 nm from the interface into the epitaxial growth layer, and the atoms that immobilize basal plane dislocations are at least one type of atom selected from magnesium, calcium, barium, and manganese.

[0011] Another aspect of the present invention includes the steps of: (a) epitaxially growing a buffer layer of a first conductivity type on a silicon carbide substrate of a first conductivity type, the buffer layer having a lower impurity density than the substrate; and (b) forming a first passivation layer in the buffer layer, the first passivation layer being located within 50 nm from the interface between the substrate and the buffer layer, the first passivation layer passing through the buffer layer and configured to passivate, by crystal defects, basal plane dislocations that occur in the buffer layer successively from basal plane dislocations present in the substrate. On the entire in-plane surface of the buffer layer The method includes the steps of: (a) forming a first conductivity type passivation layer on the buffer layer; (b) epitaxially growing a first conductivity type travel layer on the buffer layer with an impurity density lower than that of the buffer layer; and (c) forming a second conductivity type carrier injection region on the surface of the travel layer for injecting carriers into the travel layer, wherein the step of forming a first passivation layer includes a step of injecting atoms that passivate basal plane dislocations from the upper surface of the buffer layer with a projected range that is within 50 nm of the buffer layer from the interface between the substrate and the buffer layer, and the atoms that passivate basal plane dislocations are at least one type of atom selected from magnesium, calcium, barium, and manganese. Effect of the Invention

[0012] According to the present invention, it is possible to provide a multilayer structure capable of preventing the expansion of stacking faults and suppressing deterioration of the forward characteristics of a semiconductor device using SiC, a method for manufacturing the multilayer structure, and a method for manufacturing a semiconductor device. [Brief description of the drawings]

[0013] [Figure 1] 1 is a schematic cross-sectional view showing an example of a semiconductor device according to a first embodiment of the present invention. [Diagram 2] FIG. 2(a) is a schematic top view showing an example of a basal plane defect in a SiC substrate, and FIG. 2(b) is a corresponding schematic cross-sectional view. [Diagram 3] FIG. 3(a) is a schematic top view showing an example of the behavior of dislocation defects in a SiC substrate and an epitaxial layer, and FIG. 3(b) is a corresponding schematic cross-sectional view. [Figure 4] FIG. 1 is a top view schematic diagram illustrating the expansion of the spacing between partial dislocations in a SiC substrate. [Diagram 5] 1 is a schematic cross-sectional view showing an example of a position where secondary impurity atoms are introduced by ion implantation into an upper portion of a SiC substrate. [Figure 6] FIG. 6(a) is a schematic top view showing an example of the behavior of dislocation defects in the SiC substrate and growth layer shown in FIG. 5, and FIG. 6(b) is a corresponding schematic cross-sectional view. [Figure 7] FIG. 7(a) is a schematic top view showing an example of a multilayer structure (epitaxial growth substrate) according to the first embodiment, and FIG. 7(b) is a corresponding schematic cross-sectional view. [Figure 8] FIG. 8(a) is a schematic top view showing another example of the multilayer structure according to the first embodiment, and FIG. 8(b) is a corresponding schematic cross-sectional view. [Figure 9] FIG. 9(a) is a schematic top view showing another example of the multilayer structure according to the first embodiment, and FIG. 9(b) is a corresponding schematic cross-sectional view. [Figure 10]FIG. 10(a) shows an example of an n-type impurity distribution measured by SIMS for the multilayer structure according to the first embodiment, FIG. 10(b) shows an example of an impurity distribution of atoms that immobilize corresponding basal plane dislocations, and FIG. 10(c) shows another example of an impurity distribution of atoms that immobilize corresponding basal plane dislocations. [Figure 11] 1A to 1C are schematic cross-sectional views illustrating an example of a process for manufacturing a semiconductor device using the multilayer structure according to the first embodiment. [Figure 12] 12 is a schematic cross-sectional view illustrating an example of a step subsequent to FIG. 11 in the method for manufacturing a semiconductor device using the multilayer structure according to the first embodiment. FIG. [Figure 13] 13 is a schematic cross-sectional view illustrating an example of a step subsequent to FIG. 12 in the method for manufacturing a semiconductor device using the multilayer structure according to the first embodiment. FIG. [Figure 14] 14 is a schematic cross-sectional view illustrating an example of a step subsequent to FIG. 13 in the method for manufacturing a semiconductor device using the multilayer structure according to the first embodiment. FIG. [Figure 15] 15 is a schematic cross-sectional view illustrating an example of a step subsequent to FIG. 14 in the method for manufacturing a semiconductor device using the multilayer structure according to the first embodiment. FIG. [Figure 16] 13 is a schematic cross-sectional view illustrating another example of a step subsequent to FIG. 12 in the method for manufacturing a semiconductor device using the multilayer structure according to the first embodiment. FIG. [Figure 17] 17 is a schematic cross-sectional view illustrating an example of a step subsequent to FIG. 16 in the method for manufacturing a semiconductor device using the multilayer structure according to the first embodiment. FIG. [Figure 18] 5A to 5C are schematic cross-sectional views illustrating an example of a process for manufacturing a semiconductor device using a multilayer structure according to a modified example of the first embodiment. [Figure 19] 20 is a schematic cross-sectional view illustrating an example of a step subsequent to that of FIG. 19 in a method for manufacturing a semiconductor device using a multilayer structure according to a modified example of the first embodiment. FIG. [Figure 20] FIG. 13 is a diagram showing (a) an example of an n-type impurity distribution and (b) an example of an impurity distribution of atoms that immobilize basal plane dislocations, measured by SIMS, for a multilayer structure according to a modified example of the first embodiment. [Figure 21]FIG. 11 is a schematic cross-sectional view showing an example of a semiconductor device used to explain a second embodiment of the present invention. [Figure 22] FIG. 6 is a schematic cross-sectional view illustrating an example of a process for producing a multilayer structure according to a second embodiment. [Figure 23] 23 is a schematic cross-sectional view illustrating an example of a step subsequent to FIG. 22 in the method for producing a multilayer structure according to the second embodiment. FIG. [Figure 24] FIG. 24 is a schematic cross-sectional view illustrating an example of a step subsequent to FIG. 23 in the method for producing a multilayer structure according to the second embodiment. [Diagram 25] 10 is a schematic cross-sectional view illustrating another example of the process of the method for producing a multilayer structure according to the second embodiment. FIG. [Figure 26] 26 is a schematic cross-sectional view illustrating another example of a step subsequent to FIG. 25 in the method for producing a multilayer structure according to the second embodiment. FIG. [Figure 27] FIG. 11 is a schematic cross-sectional view showing an example of a semiconductor device used to explain a modified example of the second embodiment. [Figure 28] FIG. 13 is a schematic cross-sectional view illustrating another example of the semiconductor device according to the modified example of the second embodiment. [Figure 29] FIG. 13 is a schematic cross-sectional view illustrating another example of the semiconductor device according to the modified example of the second embodiment. [Diagram 30] FIG. 13 is a schematic cross-sectional view illustrating another example of the semiconductor device according to the modified example of the second embodiment. [Diagram 31] FIG. 11 is a schematic cross-sectional view illustrating an example of a process for producing a multilayer structure according to a modified example of the second embodiment. [Diagram 32] FIG. 33 is a schematic cross-sectional view illustrating an example of a step subsequent to that in FIG. 32 in the method for producing a multilayer structure according to a modified example of the second embodiment. [Diagram 33] FIG. 34 is a schematic cross-sectional view illustrating an example of a step subsequent to that of FIG. 33 in the method for producing a multilayer structure according to a modified example of the second embodiment. [Diagram 34] FIG. 35 is a schematic cross-sectional view illustrating an example of a step subsequent to that shown in FIG. 34 in the method for producing a multilayer structure according to a modified example of the second embodiment. [Diagram 35] FIG. 11 is a schematic cross-sectional view showing an example of a semiconductor device used to explain other embodiments. [Diagram 36] 37 is a plan view seen from the direction of line AA in FIG. 36. [Figure 37] 37 is a schematic cross-sectional view showing an example of a dislocation immobilization layer provided in the semiconductor device shown in FIG. 36. [Figure 38] 5A to 5C are schematic cross-sectional views illustrating an example of a process for producing a multilayer structure according to another embodiment. [Figure 39] FIG. 40 is a schematic cross-sectional view illustrating an example of a step subsequent to that of FIG. 39 in a method for producing a multilayer structure according to another embodiment. [Diagram 40] FIG. 11 is a schematic cross-sectional view showing another example of a multilayer structure used in a semiconductor device according to another embodiment. [Diagram 41] FIG. 11 is a schematic cross-sectional view showing another example of a multilayer structure used in a semiconductor device according to another embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the description of the drawings, the same or similar parts are given the same or similar reference numerals, and duplicated explanations are omitted. However, the drawings are schematic, and the relationship between thickness and planar dimensions, the ratio of thickness of each layer, etc. may differ from the actual ones. In addition, parts with different dimensional relationships and ratios may be included between the drawings. In addition, the embodiments shown below are examples of devices and methods for embodying the technical idea of ​​the present invention, and the technical idea of ​​the present invention does not specify the materials, shapes, structures, arrangements, etc. of the components as described below.

[0015] In addition, the definitions of directions such as up and down in the following description are merely for the convenience of explanation and do not limit the technical idea of ​​the present invention. For example, if an object is rotated 90 degrees and observed, up and down are converted to left and right and read, and if it is rotated 180 degrees and observed, up and down are read inverted. In the following description, the case where the first conductivity type is n type and the second conductivity type is p type will be described as an example. However, the conductivity types may be selected in the opposite relationship, with the first conductivity type being p type and the second conductivity type being n type. In addition, + and - added to n and p mean that the semiconductor region has a relatively high or low impurity density, respectively, compared to a semiconductor region without + and -. However, even if the semiconductor regions have the same n and n, it does not mean that the impurity density of each semiconductor region is strictly the same. In addition, in the notation of Miller indices in this specification, "-" means a bar attached to the index immediately after it, and adding "-" before the index represents a negative index.

[0016] In the following description, a pin diode will be used as a representative example of a semiconductor device, but the semiconductor device of the present invention is not limited to a pin diode. For example, the semiconductor device may be a bipolar device such as an insulated gate bipolar transistor (IGBT) in which a forward current flows through a pn junction, a static induction thyristor (SI thyristor), or a gate turn-off (GTO) thyristor. In addition, the semiconductor device may be a MOS field effect transistor (FET), MISFET, or static induction transistor (SIT) having a structure in which a body diode having a drain region epitaxially grown on a substrate is parasitic.

[0017] (First embodiment) As shown in FIG. 1, the semiconductor device according to the first embodiment of the present invention includes a first conductivity type (n + The semiconductor device according to the first embodiment has a vertical structure including a carrier collection layer 1 made of a semiconductor region of a n-type (n-type) in the lower part. The semiconductor device according to the first embodiment further has a n-type (n-type) in which carriers collected by the carrier collection layer 1 move vertically in a drift electric field. - A second conductivity type (p +The carrier injection region 5 is provided with a first immobilization layer 21 in the vicinity of the interface between the carrier collection layer 1 and the traveling layer 3. + The p-type carrier injection region 5 is locally embedded in the upper part of the n-type transport layer 3, thereby forming a potential barrier that controls the injection of carriers into the transport layer 3. + -n - A junction is formed. In the vertical two-terminal structure shown in FIG. 1, the carrier collection layer 1 functions as a "cathode region" and the carrier injection region 5 functions as an "anode region". In the multilayer structure shown in FIG. 1, a substrate made of SiC crystal is used as the carrier collection layer 1, and an epitaxially grown layer in which SiC crystal is vertically epitaxially grown on the substrate is used as the transport layer 3. The transport layer 3 functions as a "drift region" where carriers, which are the main current, drift and transport. To form a two-terminal structure, a cathode electrode 9 is provided as an ohmic electrode on the lower surface of the carrier collection layer 1, and an anode electrode 7 is provided as an ohmic electrode on the upper surface of the carrier injection region 5. A current from an external circuit is supplied to the carrier injection region 5 via the anode electrode 7, and the carriers supplied to the carrier collection layer 1 are supplied to the external circuit as a current via the cathode electrode 9. It is desirable that the impurity density of the transport layer 3 is low, close to that of an intrinsic semiconductor. When the impurity density of the traveling layer 3 is close to that of an intrinsic semiconductor, it can be considered as an "i-layer." In this case, + The i-type carrier injection region 5, the i-type running layer 3 and the n + A "pin diode" can be formed by using the carrier collection layer 1 of this type.

[0018] The carrier injection region 5 is also a semiconductor region made of SiC crystal. The n-type (first conductivity type) impurity element of the carrier collection layer 1 is, for example, nitrogen (N), and the impurity density is 5×10 17 cm -3 ~1×10 18 cm -3The thickness of the carrier collection layer 1 is in the range of about 100 μm to 600 μm. The surface of the carrier collection layer 1 is a (0001) Si surface. <0001> The carrier collection layer 1 has an off-angle of about 0° to 8° in the <11-20> direction with respect to the (c-axis) direction. The transport layer 3 and the carrier injection region 5 epitaxially grown on the carrier collection layer 1 also have the same off-angle as the carrier collection layer 1. The n-type impurity of the transport layer 3 is, for example, N, and the impurity density is 1×10 14 cm -3 ~1×10 17 cm -3 The thickness of the travel layer 3 is in the range of about 10 μm to several hundred μm, and the optimum thickness and impurity density are selected according to the withstand voltage specifications of the pin diode. For example, about 10 μm is selected for a withstand voltage of 1000 V, and about 100 μm is selected for a withstand voltage of 10 kV. The carrier injection region 5 is formed by selectively adding p-type (second conductivity type) impurity elements, which are the opposite conductivity type to the impurities in the travel layer 3, to the upper part of the travel layer 3 to form a p + -n - The anode electrode 7 may include a contact layer, a barrier metal layer, a surface electrode layer, and the like. For example, the contact layer may be nickel silicide (NiSi x The cathode 9 can be made of, for example, a single layer of gold (Au) or a metal film laminated in the order of Al, nickel (Ni) and Au.

[0019] SiC crystals have crystal polymorphism, the main ones being cubic 3C, and hexagonal 4H and 6H. The band gap at room temperature has been reported to be 2.23 eV for 3C-SiC, 3.26 eV for 4H-SiC, and 3.02 eV for 6H-SiC. In the present invention, 4H-SiC will be used for explanation.

[0020] The first passivation layer 21 provided at the interface between the carrier collection layer 1 and the traveling layer 3 that constitute the substrate is a region provided in the lower part of the traveling layer 3, approximately 50 nm from the interface. This first passivation layer 21 is formed by implanting impurity ions that become atoms that immobilize basal plane dislocations in the lower part of the traveling layer 3. Any one or more types of atoms from silicon (Si), carbon (C), hydrogen (H), helium (He), argon (Ar), magnesium (Mg), calcium (Ca), barium (Ba), titanium (Ti), vanadium (V), chromium (Cr), manganese (Mn), and iron (Fe) that become atoms that immobilize basal plane dislocations can be used. The impurity density of atoms that immobilize basal plane dislocations is set to 1×10 to avoid an increase in resistance due to excessive defects caused by ion implantation. 14 cm -3 That's it, 1×10 18 cm -3 The impurity density is preferably in the range of 3×10 15 cm -3 That's it, 3 x 10 16 cm -3 The range is as follows. By doing this, it is possible to form a number of crystal defects equivalent to the impurity density. Atoms that immobilize basal plane dislocations other than Si and C, which are the constituent atoms of SiC crystals, can be detected by secondary ion mass spectrometry (SIMS).

[0021] As shown in FIG. 2(a) and (b), a substrate used as the carrier collection layer 1 is + A large number of basal plane dislocations (BPDs) exist in the 4H-SiC substrate 1s. The two-dot chain line shown in FIG. 2(a) is the intersection line Lb between the surface of the substrate 1s and the basal plane including the substrate-side basal plane dislocation 12 shown in FIG. 2(b). The substrate-side basal plane dislocation 12 is decomposed into two partial dislocations, a silicon (Si) core 12s and a carbon (C) core 12c, within the basal plane, and reaches the intersection line Lb. The distance between the substrate-side Si core 12s and the substrate-side C core 12c is about 30 nm to 70 nm.

[0022] An epitaxial growth layer (intermediate growth layer) 3e having a lower impurity density than the substrate 1s is grown on the substrate 1s to a thickness of, for example, about 1 μm. As shown in FIGS. 3(a) and 3(b), the substrate-side basal plane dislocation 12 of the substrate 1s extends into the intermediate growth layer 3e and continues to the growth-layer-side basal plane dislocation 22. As shown in FIG. 3(b), most of the growth-layer-side basal plane dislocations 22 are converted to threading dislocations (TEDs) 14 near the interface between the substrate 1s and the intermediate growth layer 3e during film formation. In this case, as shown in FIG. 3(a), the substrate-side Si core 12s and the substrate-side C core 12c of the substrate-side basal plane dislocation 12, which had been decomposed into two in the substrate 1s during the epitaxial growth process, are succeeded by the growth-layer-side Si core 22s and the growth-layer-side C core 22c of the growth-layer-side basal plane dislocation 22 in the intermediate growth layer 3e. Here, the substrate-side Si core 12s is a Si-Si bond, and the substrate-side C core 12c is a C-C bond. Since the energy of the Si-Si bond is smaller than that of the C-C bond, the partial dislocation having the Si core is movable by the energy given by heating or current flow, but the partial dislocation having the C core is not movable. Therefore, as shown in FIG. 3(a), the growth layer-side Si core 22s approaches the growth layer-side C core 22c and is converted into one threading dislocation 14. However, a part of the growth layer-side basal plane dislocation 22 is not converted into the threading dislocation 14 even inside the intermediate growth layer 3e, but is inherited as the growth layer-side basal plane dislocation 22z, and reaches the surface of the intermediate growth layer 3e at the intersection line Ls.

[0023] The increase in forward resistance of the pin diode is caused by the expansion of stacking faults starting from the growth layer side basal plane dislocations 22z present in the intermediate growth layer 3e shown in Figures 3(a) and (b). More specifically, this occurs when minority carriers are injected from the p-type carrier injection region 5 shown in Figure 1 into the electronic level created by stacking faults in the n-type intermediate growth layer 3e. In the n-type transit layer 3 shown in Figure 1, holes are injected from the carrier injection region 5 as "minority carriers (minority carriers)". It is known that the electronic level of this stacking fault is 0.2 eV to 0.3 eV lower than the lower end of the conduction band of the 4H-SiC crystal. The expansion of stacking faults occurs when electrons in the conduction band generated by current flow or photoexcitation recombine with holes at the electronic level of the stacking faults. The substrate side basal plane dislocations 12 in the substrate 1s are generated to relieve stress inside the crystal caused by non-uniform temperature during the substrate manufacturing stage, and there are 1000 / cm in the substrate 1s. 2 As shown in FIG. 3(b), the growth layer side basal plane dislocation 22z is a portion extending from the substrate side basal plane dislocation 12 of the substrate 1s to the intermediate growth layer 3e, and the growth layer side basal plane dislocation 22z penetrates the intermediate growth layer 3e to reach the surface. When a pin diode is manufactured by growing a main growth layer (upper growth layer) thereon using such a multilayer structure (1s, 3e) as an intermediate product, the growth layer side basal plane dislocation 22z in the intermediate growth layer 3e can become the starting point of the expansion of stacking faults by energization. That is, holes are injected as minority carriers from the p-type carrier injection region constituting the anode region into the running layer constituting the main growth layer (upper growth layer) grown on the intermediate growth layer 3e, and the growth layer side basal plane dislocation 22z can become the starting point of the expansion of stacking faults.

[0024] On the other hand, as shown in FIG. 3(b), the growth layer side basal plane dislocation 22 corresponds to the portion continuing from the substrate side basal plane dislocation 12 of the substrate 1s to the intermediate growth layer 3e, but is converted into a threading dislocation 14 parallel to the c-axis of the SiC crystal in the intermediate growth layer 3e. The threading dislocation 14 does not expand into a stacking fault. However, in the structure shown in FIG. 1, when the holes injected from the p-type carrier injection region 5 travel through the running layer 3 constituted by the main growth layer (upper growth layer) grown on the intermediate growth layer 3e and reach the vicinity of the interface between the carrier collection layer 1 and the running layer 3, the stacking fault may expand. As shown in FIG. 3(b), when the injected holes reach the vicinity of the interface between the substrate 1s and the intermediate growth layer 3e, the holes are injected into the electron level of the stacking fault originating from the growth layer side basal plane dislocation 22. Stacking faults originating from basal plane dislocations 22 on the growth layer side occur when the hole density near the interface between the substrate 1s and the intermediate growth layer 3e exceeds the threshold value of 1×10 15 cm -3 This is said to be where the expansion begins.

[0025] It is known that when an intermediate growth layer 3e is epitaxially grown on a substrate 1s, the conversion rate of the growth layer side basal plane dislocations 22 in the peripheral part of the substrate 1s to threading dislocations 14 is lower than in other parts. It is presumed that the reason for this is that the temperature distribution around the substrate 1s is large. Figure 4 explains the mechanism of the cause of the low dislocation conversion rate in the peripheral part of the substrate 1s. As shown in Figure 4, the substrate side basal plane dislocations 12 in the substrate 1s are decomposed into partial dislocations consisting of the substrate side C core 12c and the substrate side Si core 12s. The temperature when forming the first intermediate growth layer and the upper growth layer on the substrate 1s is about 1600°C, but before increasing the temperature to 1600°C, the temperature is increased to 900°C to 1000°C and maintained for a certain period of time. If the temperature distribution in the substrate 1s during this period of time is large, the temperature difference applies shear stress to the substrate side basal plane dislocations 12. Therefore, as shown in Fig. 4, the interval between the substrate-side Si core 12s and the substrate-side C core 12c increases near the surface of the substrate 1s. Fig. 4 shows a state in which the substrate-side Si core 12s, which is more mobile than the substrate-side C core 12c, moves near the surface, and the interval Db between the partial dislocations formed by the substrate-side Si core 12b and the substrate-side C core 12c increases from the interval Ds between the partial dislocations formed by the original substrate-side Si core 12s and the substrate-side C core 12c. In this way, if the interval Db between the partial dislocations between the substrate-side Si core 12b and the substrate-side C core 12c increases significantly before the epitaxial growth of the first intermediate growth layer and the upper growth layer, the substrate-side basal plane dislocations 12 are less likely to be converted to threading dislocations 14 during epitaxial growth.

[0026] As shown in FIG. 5, by providing a second passivation layer 11 in which crystal defects are introduced by ion implantation on the surface of the substrate 1s, it is possible to prevent the spacing between partial dislocations from expanding during the temperature rise in epitaxial growth. That is, it is known that the introduction of crystal defects has the effect of suppressing the movement of partial dislocations. For example, Non-Patent Document 1 reports that the conversion rate of substrate-side basal plane dislocations to threading dislocations is increased by ion implanting argon (Ar) ions into the substrate surface. The second passivation layer 11 is provided on the surface of the substrate 1s by ion implantation before epitaxial growth to suppress the movement of partial dislocations. As a result, as shown in FIG. 6(a) and (b), the conversion rate of growth layer-side basal plane dislocations 22 to threading dislocations 14 is improved in the intermediate growth layer 3e during epitaxial growth on the substrate 1s.

[0027] Since the expansion of stacking faults due to forward current flow to the p-n junction does not originate from threading dislocations 14, converting the substrate-side basal plane dislocations 12 in the substrate 1s to threading dislocations 14 has a certain effect on preventing the expansion of stacking faults. However, if the current flow amount or current flow time is increased, the expansion of stacking faults originates from the vicinity of the interface between the intermediate growth layer 3e and the substrate 1s, and the expansion cannot be completely prevented. This is because, as shown in FIG. 6(a), partial dislocations of the growth layer-side Si core 22s remain at the portion at the interface between the substrate 1s and the intermediate growth layer 3e where the growth layer-side basal plane dislocations 22 are converted to threading dislocations 14. These partial dislocations of the growth layer-side Si core 22s are not in the substrate 1s where the substrate-side basal plane dislocations 12 are immobile due to ion implantation, but in the intermediate growth layer 3e. Therefore, the growth layer-side Si core 22s is in a movable state, and when the energy required for movement is obtained by current flow, it moves and becomes the origin of stacking faults. By providing the second passivation layer 11 on the surface of the substrate 1s, the conversion rate of the substrate-side basal plane dislocations 12 in the substrate 1s to threading dislocations 14 can be increased to about 99%. However, since no measures are taken for the growth layer-side Si cores 22s at the interface between the substrate 1s and the intermediate growth layer 3e where the growth layer-side basal plane dislocations 22 are converted to threading dislocations 14, the expansion of stacking faults cannot be completely prevented.

[0028] As shown in FIG. 1, in the semiconductor device according to the first embodiment, a first passivation layer 21 is provided in the travel layer 3 near the interface between the carrier collection layer 1 and the travel layer 3. Specifically, as shown in FIGS. 7(a) and 7(b), a first passivation layer 21 is provided in the intermediate growth layer 3e near the interface between the substrate 1s and the intermediate growth layer 3e, in which crystal defects are introduced to immobilize the growth layer side basal plane dislocations 22. The crystal defects are formed by ion implantation of atoms that immobilize the crystal defects. The first passivation layer 21 can immobilize the growth layer side Si cores 22s shown in FIG. 7(a), which remain in the intermediate growth layer 3e after the growth layer side basal plane dislocations 22 are converted to threading dislocations 14 at the interface between the substrate 1s and the intermediate growth layer 3e. As shown in FIG. 7(b), for example, impurity ions that immobilize the growth layer side basal plane dislocations 22 remaining in the intermediate growth layer 3e epitaxially grown to a thickness of about 1 μm are implanted from the surface of the intermediate growth layer 3e to form a first immobilization layer 21. In the first immobilization layer 21, defects induced by implanting atoms that immobilize the growth layer side basal plane dislocations 22 immobilize the growth layer side Si cores 22s of the growth layer side basal plane dislocations 22. Most of the growth layer side basal plane dislocations 22 are converted into threading dislocations 14 within a range of about 50 nm from the interface between the substrate 1s and the intermediate growth layer 3e. Therefore, the first immobilization layer 21 may be provided in the intermediate growth layer 3e within a range of about 50 nm from the interface between the substrate 1s and the intermediate growth layer 3e. As a result, when a forward current is passed through the semiconductor device of the first embodiment, the expansion of stacking faults caused by the growth layer-side basal plane dislocations 22 can be prevented, and degradation of the forward characteristics of the semiconductor device can be suppressed.

[0029] In the structure of the semiconductor device according to the first embodiment shown in FIG. 1, the density of holes injected from the p-type carrier injection region 5 is n +In the substrate 1s, the hole density is rapidly reduced by recombination with electrons. However, the decrease in the hole density is small on the substrate 1s side near the interface between the substrate 1s and the intermediate growth layer 3e, and the partial dislocations at the Si core of the substrate-side basal plane dislocations 12 are not immobilized. Therefore, the substrate-side basal plane dislocations 12 present near the surface of the substrate 1s can be the starting point for the expansion of stacking faults due to forward current application. Therefore, as shown in Figures 8(a) and (b), it is desirable to provide a second immobilization layer 11 and a first immobilization layer 21 on the substrate 1s side and the growth layer 3e side, respectively, near the interface between the substrate 1s and the intermediate growth layer 3e. For example, the accelerating voltage of ion implantation may be changed from the surface of the intermediate growth layer 3e having a thickness of 1 μm or less to adjust the peak position of the implantation dose distribution of atoms that immobilize the basal plane dislocations. The second passivation layer 11 is preferably provided within the substrate 1s 1 μm from the interface between the substrate 1s and the intermediate growth layer 3e, ie, in a region 1 μm deep on the surface of the substrate 1s on the intermediate growth layer 3e side.

[0030] In the above description, the first passivation layer 21 is provided over the entire surface near the interface between the substrate 1s and the intermediate growth layer 3e in plan view, but this is not limited thereto. For example, as shown in Figures 9(a) and (b), in a planar pattern, a plurality of first passivation layers 21a may be provided in stripes parallel to each other in a direction perpendicular to the [11-20] direction. The substrate-side basal plane dislocations 12 tend to propagate in the [11-20] direction. For example, if the substrate 1s is off by 4°, the extension of the growth layer-side basal plane dislocations 22 can be prevented by setting the interval s of the first passivation layers 21a to about 2 μm and the height h to about 0.14 μm or more.

[0031] -Method of manufacturing semiconductor device- Next, a method for manufacturing a semiconductor device according to the first embodiment of the present invention will be described using an example of a pin diode, with reference to the impurity profile shown in Fig. 10 and the process diagrams shown in Fig. 11 to Fig. 15. Note that the method for manufacturing a pin diode described below is only one example, and it goes without saying that various other manufacturing methods, including modifications thereof, can be used within the scope of the spirit described in the claims.

[0032] As shown in FIG. 11, the n+ A type substrate 1s is prepared. The main surface of the substrate 1s is a (0001) Si surface that is off by 4° in the <11-20> direction, and the thickness is about 100 μm to 600 μm. The substrate 1s contains 5×10 n-type impurity elements such as nitrogen (N). 17 cm -3 ~1×10 18 cm -3 The substrate 1s is doped with an impurity density of about 100 μm. The substrate 1s contains a large number of basal plane dislocations 12 on the substrate side, but FIG. 11 shows only one basal plane dislocation 12 on the substrate side.

[0033] As shown in Fig. 12, an n-type intermediate growth layer 3e is epitaxially grown on a substrate 1s by vapor phase epitaxial growth or the like to produce a multilayer structure (1s, 3e) as an intermediate product. As shown in Fig. 10(a), the intermediate growth layer 3e contains an n-type impurity element such as N at a lower impurity density of 1 × 10 14 cm -3 ~1×10 17 cm -3 The intermediate growth layer 3e is doped at about 1 μm in thickness. Substrate-side basal plane dislocations 12 present in the substrate 1s propagate into the intermediate growth layer 3e as growth-layer-side basal plane dislocations 22. Within the intermediate growth layer 3e within a range of 50 nm or less from the interface between the substrate 1s and the intermediate growth layer 3e, the growth-layer-side basal plane dislocations 22 are converted to threading dislocations 14 at a conversion rate of about 95%.

[0034] As shown in Fig. 13, by ion implantation technology, atoms that immobilize basal plane dislocations, for example, Ar atoms 221, are implanted into the intermediate growth layer 3e so that the vicinity of the interface between the substrate 1s and the intermediate growth layer 3e is the projected range. As shown in Fig. 7(a), the growth layer side Si core 22s of the growth layer side basal plane dislocation 22 remains at the position where the growth layer side basal plane dislocation 22 rises from the basal plane to the threading dislocation 14. Therefore, as shown in Fig. 10(b), the dose peak P2 of the implantation of the Ar atoms 221 ions is adjusted to be near the rising position of the threading dislocation 14. In reality, the rising position where the growth layer side basal plane dislocation 22 is converted to the threading dislocation 14 during epitaxial growth varies during epitaxial growth. Therefore, it is desirable to use multi-stage ion implantation in which the acceleration voltage of ion implantation is changed so that the peak of the dose of the implanted Ar ions is distributed near the interface between the intermediate growth layer 3e and the substrate 1s, for example, within the intermediate growth layer 3e at a distance of about 50 nm from the interface. Note that although Ar is used as an atom that immobilizes basal plane dislocations, any one or more of the following atoms may be used: H, He, Ar, Mg, Ca, Ba, Ti, V, Cr, Mn, and Fe.

[0035] Thereafter, as shown in Fig. 14, in order to control the state of the defects introduced by the ion implantation, a heat treatment is performed at about 900°C to 1400°C for about 30 minutes to 2 hours to form a first passivation layer 21. An n-type main growth layer (upper growth layer) is further epitaxially grown on the intermediate growth layer 3e, and a travel layer 3 consisting of the first intermediate growth layer and the upper growth layer is formed on the substrate 1s. The travel layer 3 contains an n-type impurity element such as N at a lower impurity density of 1 x 10 14 cm -3 ~1×10 17 cm -3 The thickness of the travel layer 3 is in the range of about 10 μm to several hundreds of μm, and the optimum thickness and impurity density are selected according to the withstand voltage specifications of the pin diode. For example, about 10 μm is selected for a withstand voltage of 1000 V, and about 100 μm is selected for a withstand voltage of 10 kV. Threading dislocations 14 present in the intermediate growth layer 3e propagate into the upper growth layer of the travel layer 3. The heat treatment of the ion-implanted layer may be performed during the additional epitaxial growth of the travel layer 3.

[0036] Next, as shown in FIG. 15, a p-type carrier injection region 5 of Al or the like is selectively formed on the upper part of the running layer 3. For example, a mask for ion injection is formed by photolithography, and p-type impurity ions of Al or the like are injected at a high impurity density on the upper part of the running layer 3. Subsequently, the lower surface of the substrate 1s is polished by chemical mechanical polishing (CMP) or the like to adjust the thickness, and the carrier collection layer 1 is finished to a thickness specified by the electrical characteristics required by the semiconductor device. A back electrode (cathode electrode) 9 made of Au or the like is formed on the lower surface of the carrier collection layer 1 by sputtering or vacuum deposition or the like. Furthermore, a metal film of Al or the like is deposited by sputtering or vacuum deposition or the like to form a front electrode (anode electrode) 7. In this manner, the semiconductor device according to the first embodiment shown in FIG. 1 is completed.

[0037] In the structure shown in FIG. 1, the density of holes injected from the p-type carrier injection region 5 is n + In the carrier collection layer 1 of the mold, the hole density is rapidly reduced by recombination with electrons. However, the decrease in the hole density in the carrier collection layer 1 is small near the interface between the carrier collection layer 1 and the running layer 3, and the partial dislocations at the Si core of the substrate-side basal plane dislocations 12 are not immobilized. Therefore, the substrate-side basal plane dislocations 12 present near the surface of the carrier collection layer 1 can be the starting point for the expansion of stacking faults due to forward current flow. For this reason, when the first passivation layer 21 is formed by ion implantation of Ar atoms 221, the second passivation layer 11 may be formed at the same time. Here, the second passivation layer 11 is preferably formed in the substrate 1s within 1 μm from the interface between the substrate 1s and the intermediate growth layer 3e. In addition, the first passivation layer 21 may be formed so that the second passivation layer 11 is in contact with the interface between the carrier collection layer 1 and the running layer 3 by ion implantation of Ar atoms 221.

[0038] For example, as shown in FIG. 16, near the interface between the substrate 1s and the intermediate growth layer 3e, Ar atoms 221a are ion-implanted into the intermediate growth layer 3e, Ar atoms 221b are ion-implanted into the interface, and Ar atoms 221c are ion-implanted into the substrate side. Thereafter, as shown in FIG. 17, an n-type main growth layer (upper growth layer) is epitaxially grown on the intermediate growth layer 3e to form a running layer 3 on the substrate 1s. Near the interface between the substrate 1s and the running layer 3, a second passivation layer 11 is formed on the substrate 1s side, and a first passivation layer 21 is formed on the running layer side. The first passivation layer 21 and the second passivation layer 11 can be formed such that the peaks P2a, P2b, and P2c of the dose distribution corresponding to the ion-implanted Ar atoms 221a, 221b, and 221c, respectively, overlap with each other to form a substantially flat distribution, as shown in FIG. 10(c), for example. As a result, the first passivation layer 21 and the second passivation layer 11 come into contact with each other at the interface between the substrate 1s and the intermediate growth layer 3e. This makes it possible to passivate the growth-layer-side Si cores 22s of the growth-layer-side basal-plane dislocations 22 that exist on the substrate 1s side near the interface between the substrate 1s and the traveling layer 3, and to prevent the expansion of stacking faults due to forward current flow.

[0039] In the manufacturing method of the semiconductor device according to the first embodiment, the intermediate growth layer 3e is epitaxially grown on the substrate 1s, and the first passivation layer 21 is formed by ion implantation of Ar atoms 221 from the upper surface of the intermediate growth layer 3e. This allows the position of the crystal defect introduced by ion implantation of the Ar atoms 221 to be controlled with high precision in the travel layer 3 near the interface between the carrier collection layer 1 and the travel layer 3, where the threading dislocation 14 stands up. This makes it possible to immobilize the partial dislocations of the growth layer side Si core 22s of the growth layer side basal plane dislocations 22 remaining in the travel layer 3 near the interface between the carrier collection layer 1 and the travel layer 3. In addition, the second passivation layer 11 is formed in the substrate 1s within 1 μm from the interface between the substrate 1s and the intermediate growth layer 3e by ion implantation. This immobilizes the partial dislocations in the substrate 1s, and increases the conversion rate of the substrate side basal plane dislocations 12 to threading dislocations 14. As a result, when a forward current is passed through the semiconductor device of the first embodiment, the expansion of stacking faults caused by the growth layer-side basal plane dislocations 22 can be prevented, and degradation of the forward characteristics of the semiconductor device can be suppressed.

[0040] (Modification of the first embodiment) As described above, in the semiconductor device according to the first embodiment of the present invention, the intermediate growth layer 3e converts about 95% of the growth layer side basal plane dislocations 22 into threading dislocations 14, but about 5% of them propagate through the upper growth layer epitaxially grown on the intermediate growth layer 3e and can become the starting point for the expansion of stacking faults. In the modified example of the first embodiment, as shown in FIG. 18, a second passivation layer 11 in which crystal defects are introduced by ion implantation is provided in advance near the upper surface of the substrate 1s. The second passivation layer 11 can improve the conversion efficiency of the substrate side basal plane dislocations 12 into threading dislocations 14. The semiconductor device according to the modified example of the first embodiment differs from the first embodiment in that the second passivation layer 11 is provided by ion implantation in advance on the surface of the substrate 1s before the epitaxial growth of the intermediate growth layer 3e. Since the other configurations are the same as those of the first embodiment, the overlapping descriptions will be omitted.

[0041] -Method of manufacturing intermediate products- A method for manufacturing a multilayer structure (1s, 3e) as an intermediate product according to a modified example of the first embodiment of the present invention will be described with reference to the process diagrams shown in Figures 18 and 19 and the impurity profile shown in Figure 20. Note that the method for manufacturing a multilayer structure (1s, 3e) as an intermediate product described below is one example before growing an upper growth layer, and it goes without saying that various other manufacturing methods, including this modified example, can be used within the scope of the spirit described in the claims.

[0042] First, as shown in FIG. 18, before epitaxial growth, n-type impurity elements such as N are added at 5×10 17 cm -3 ~1×10 18 cm -3 The second passivation layer 11 is formed by implanting impurity ions, such as Ar, which become atoms that immobilize basal plane dislocations 12 on the substrate side, from the top surface of the substrate 1s doped with an impurity density of about 1 μm. The second passivation layer 11 is formed by ion implantation with the projected range adjusted so that the atoms that immobilize basal plane dislocations are distributed within a range of about 1 μm from the top surface of the substrate 1s.

[0043] Thereafter, as shown in Fig. 19, an n-type intermediate growth layer 3e is epitaxially grown on the substrate 1s to produce a multilayer structure (1s, 3e) as an intermediate product. As shown in Fig. 20(a), the intermediate growth layer 3e contains an n-type impurity element such as N at a lower impurity density of 1 × 10 14 cm -3 ~1×10 17 cm -3 The intermediate growth layer 3e is doped at about 1 μm in thickness. The substrate-side basal plane dislocations 12 present in the substrate 1s propagate into the intermediate growth layer 3e as growth-layer-side basal plane dislocations 22. The partial dislocations at the substrate-side Si cores 12s of the substrate-side basal plane dislocations 12 are immobilized by the second immobilization layer 11, as described in FIGS. 6(a) and 6(b). Therefore, the growth-layer-side basal plane dislocations 22 propagated from the substrate 1s are converted into threading dislocations 14 at a high conversion rate of about 99% in the intermediate growth layer 3e within a range of 50 nm or less from the interface between the substrate 1s and the intermediate growth layer 3e.

[0044] Furthermore, after the epitaxial growth of the intermediate growth layer 3e, ions of, for example, Ar atoms, which become atoms that immobilize basal plane dislocations on the growth layer side, are implanted into the intermediate growth layer 3e near the interface between the substrate 1s and the intermediate growth layer 3e. After the ion implantation, a heat treatment is performed at about 900°C to 1400°C for about 30 minutes to 2 hours to control the state of the defects introduced by the ion implantation, and a first passivation layer 21 is formed as shown in Figure 19. As shown in Figures 20(a) and (b), Ar atoms are distributed in the second passivation layer 11 such that a peak P1 of the dose distribution is located within 1 μm from the interface on the substrate 1s side, and in the first passivation layer 21 such that a peak P2 of the dose distribution is located within 50 nm from the interface on the intermediate growth layer 3e side. In this manner, a multilayer structure (1s, 3e) is produced as an intermediate product having a second passivation layer 11 on the side of the substrate 1s to which N is highly doped, and a first passivation layer 21 on the side of the intermediate growth layer 3e to which N is doped at a lower impurity density than the substrate 1s.

[0045] In the modified example of the first embodiment, impurity ions that become atoms that immobilize the substrate-side basal plane dislocations 12 are implanted in advance near the surface of the substrate 1s to form a second immobilization layer 11, and then an intermediate growth layer 3e of about 1 μm is epitaxially grown on the substrate 1s. Furthermore, impurity ions that become atoms that immobilize the growth layer-side basal plane dislocations 22 are implanted from the upper surface of the intermediate growth layer 3e to form a first immobilization layer 21. Since the second immobilization layer 11 is provided on the substrate 1s, partial dislocations of the substrate-side basal plane dislocations 12 present in the substrate 1s can be immobilized during the epitaxial growth of the intermediate growth layer 3e. Therefore, when the main growth layer is epitaxially grown on the multilayer structure (1s, 3e) as the intermediate product, the conversion rate of the growth layer-side basal plane dislocations 22 propagating to the intermediate growth layer 3e during the epitaxial growth to threading dislocations 14 can be increased. As a result, it is possible to reduce the growth layer side basal plane dislocations 22 propagating to the main growth layer (upper growth layer) on the upper surface of the intermediate growth layer 3e. In addition, the intermediate growth layer 3e is epitaxially grown to a thickness of about 1 μm on the substrate 1s, and the first immobilization layer 21 is provided by ion-implanting Ar atoms 221 from the upper surface of the intermediate growth layer 3e near the interface between the substrate 1s and the intermediate growth layer 3e. Therefore, it is possible to immobilize the partial dislocations of the growth layer side Si cores 22s remaining in the intermediate growth layer 3e near the interface between the substrate 1s and the intermediate growth layer 3e after the growth layer side basal plane dislocations 22 are converted to threading dislocations 14. As a result, when a forward current is passed through a semiconductor device having a structure in which the main growth layer (upper growth layer) is epitaxially grown on the multilayer structure (1s, 3e) as an intermediate product, it is possible to prevent the expansion of stacking faults caused by the growth layer side basal plane dislocations 22 and suppress the deterioration of the forward characteristics of the semiconductor device.

[0046] Second embodiment As shown in FIG. 21, the semiconductor device according to the second embodiment of the present invention has n + n-type carrier collection layer 1, n-type buffer layer 2, - Mold running layer 3, p + The carrier collection layer 1 includes an n-type carrier injection region 5, an anode electrode 7, and a cathode electrode 9. The carrier collection layer 1 contains an n-type impurity element such as N at a concentration of 5×10 17 cm -3 ~1×10 18 cm -3The buffer layer 2 as the first intermediate growth layer is doped with an n-type impurity element such as N at a lower impurity density than the carrier collection layer 1 and at a higher impurity density than the running layer 3, for example, at 1×10 17 cm -3 ~5×10 17 cm -3 The buffer layer 2 is provided between the carrier collection layer 1 and the running layer 3, and converts the growth layer side basal plane dislocations 22 (not shown) into threading dislocations 14 (not shown). Furthermore, the electron density in the buffer layer 2 is higher than that in the running layer 3, and the electron density can be reduced by recombining with the holes injected from the running layer 3 when a current is applied. The second embodiment differs from the first embodiment in that the buffer layer 2 has a higher impurity density than the running layer 3, and is provided between the carrier collection layer 1 and the running layer 3, which is the upper growth layer. Other configurations are the same as those of the first embodiment, so duplicated descriptions will be omitted.

[0047] In the semiconductor device according to the second embodiment, in the buffer layer 2 grown on the carrier collection layer 1, about 95% of the growth layer side basal plane dislocations 22 are converted to threading dislocations 14. In this way, the growth layer side basal plane dislocations 22 that have propagated from the carrier collection layer 1 and changed to threading dislocations 14 are present in the buffer layer 2. The buffer layer 2 is doped with n-type impurity elements at a higher impurity density than the travel layer 3, so that the electron density is higher than that of the travel layer 3, and the density of holes injected as minority carriers from the carrier injection region 5 to the travel layer 3 can be greatly reduced in the buffer layer 2. As a result, the density of holes injected into the growth layer side basal plane dislocations 22 remaining in the buffer layer 2 can be reduced, and it is possible to prevent the expansion of stacking faults due to current flow. In addition, impurity ions that become atoms that immobilize the growth layer side basal plane dislocations 22 are implanted into the buffer layer 2 near the interface between the carrier collection layer 1 and the buffer layer 2 to provide a first immobilization layer 21. The implanted atoms that immobilize basal plane dislocations induce crystal defects in the first passivation layer 21, immobilizing the partial dislocations of the growth layer-side basal plane dislocations 22. Furthermore, the implanted atoms that immobilize basal plane dislocations can form a hole trapping level, and are also effective in reducing the hole density. As a result, when a forward current is passed through the semiconductor device, the expansion of stacking faults caused by the growth layer-side basal plane dislocations 22 can be prevented, and the deterioration of the forward characteristics of the semiconductor device can be suppressed.

[0048] -Method of manufacturing semiconductor device- Next, a method for manufacturing a semiconductor device according to the second embodiment of the present invention will be described with reference to the process diagrams shown in Fig. 22 and Fig. 24, taking a pin diode as an example. First, as shown in Fig. 22, n of a 4H-SiC crystal is + A substrate 1s having a lattice structure is prepared. The main surface of the substrate 1s is a (0001) Si surface that is off-axis by 4° in the <11-20> direction. The substrate 1s is doped with 5×10 n-type impurity elements such as nitrogen (N). 17 cm -3 ~1×10 18 cm -3 Although not shown in the figure, the substrate 1s contains a large number of basal plane dislocations 12 on the substrate side.

[0049] 23, an n-type buffer layer 2 is epitaxially grown on a substrate 1s to a thickness of about 1 μm to 10 μm by vapor phase epitaxial growth or the like. The buffer layer 2, which serves as a first intermediate growth layer, contains an n-type impurity element such as nitrogen (N) at a concentration of 1×10 17 cm -3 ~5×10 17 cm -3 Then, by ion implantation technology, ions of, for example, Ar atoms, which become atoms that immobilize the basal plane dislocations 22 on the growth layer side, are implanted into the buffer layer 2 near the interface between the substrate 1s and the buffer layer 2 at a density of about 1×10 14 cm -3 ~1×10 18 cm -3 24, in order to control the state of defects introduced by the ion implantation, a heat treatment is performed at about 900° C. to 1400° C. for about 30 minutes to 2 hours to form a first passivation layer 21.

[0050] Thereafter, an n-type main growth layer (upper growth layer) is epitaxially grown on the buffer layer 2 by vapor phase epitaxial growth or the like to form the travel layer 3 shown in FIG. 21. The travel layer 3 contains an n-type impurity element such as N at a concentration of 1×10 14 cm -3 ~1×10 17 cm -3 The thickness of the travel layer 3 is in the range of about 10 μm to several hundred μm, and the optimum thickness and impurity density are selected according to the withstand voltage specifications of the pin diode. For example, about 10 μm is selected for a withstand voltage of 1000 V, and about 100 μm is selected for a withstand voltage of 10 kV.

[0051] Next, a p-type impurity element such as Al is ion-implanted into the upper part of the traveling layer 3 by photolithography and ion implantation techniques, to selectively form a p-type carrier implantation region 5. Subsequently, the lower surface of the substrate 1s is polished by chemical mechanical polishing (CMP) or the like to adjust the thickness, and the carrier collection layer 1 is finished to the specifications for the cathode region. A back electrode (cathode electrode) 9 made of Au or the like is formed on the lower surface of the carrier collection layer 1 by sputtering or vacuum deposition or the like. Furthermore, a metal film such as Al is deposited by sputtering or vacuum deposition or the like to form a front electrode (anode electrode) 7. In this manner, the semiconductor device according to the second embodiment shown in FIG. 21 is completed.

[0052] In the semiconductor device according to the second embodiment, an n-type buffer layer 2 is epitaxially grown on a substrate 1s as a first intermediate growth layer. Therefore, the growth layer side basal plane dislocations 22 propagating from the substrate 1s are converted into threading dislocations in the buffer layer 2. The buffer layer 2 is doped with an n-type impurity element at a higher impurity density than the upper growth layer, i.e., the travel layer 3. Therefore, the density of holes injected through the travel layer 3 into the growth layer side basal plane dislocations 22 present at the interface between the substrate 1s and the buffer layer 2 can be reduced. As a result, the basal plane dislocations can be prevented from expanding into stacking faults.

[0053] Also, as shown in FIG. 25, in order to improve the conversion rate of the growth layer side basal plane dislocations 22 propagating from the substrate 1s to the buffer layer 2 during the epitaxial growth of the buffer layer 2 into threading dislocations 14, a second passivation layer 11 may be provided near the upper surface of the substrate 1s. For example, impurity ions that become atoms that immobilize the substrate side basal plane dislocations 12 are implanted in advance near the upper surface of the substrate 1s to form the second passivation layer 11 with crystal defects introduced therein. Thereafter, as shown in FIG. 26, an n-type buffer layer 2 is epitaxially grown on the substrate 1s to a thickness of about 1 μm by vapor phase epitaxial growth technology or the like. Next, impurity ions that become atoms that immobilize the growth layer side basal plane dislocations 22 are implanted by ion implantation technology into the buffer layer 2 near the interface between the substrate 1s and the buffer layer 2 to form a first passivation layer 21. The second passivation layer 11 provided in the vicinity of the upper surface of the substrate 1s can improve the conversion efficiency of the substrate-side basal plane dislocations 12 into threading dislocations 14.

[0054] (Modification of the second embodiment) As shown in FIG. 27, a semiconductor device according to a modification of the second embodiment of the present invention has n + n-type carrier collection layer 1, n-type buffer layer 2, - Mold running layer 3, p + The semiconductor device according to the second embodiment includes a carrier injection region 5, an anode electrode 7, and a cathode electrode 9. The buffer layer 2 is provided between the carrier collection layer 1 and the travel layer 3, and includes a defect conversion layer 2a that converts basal plane dislocations into threading dislocations, and a recombination promotion layer 2b that reduces minority carriers injected from the travel layer 3 side to the carrier collection layer 1 side. A first passivation layer 21 is provided in the defect conversion layer 2a near the interface between the carrier collection layer 1 and the defect conversion layer 2a, for example, within a range of about 50 nm from the interface. The semiconductor device according to the second embodiment is different from the semiconductor device according to the first and second embodiments in that the buffer layer 2 provided between the carrier collection layer 1 and the travel layer 3 includes the defect conversion layer 2a and the recombination promotion layer 2b. Other configurations are the same as those of the semiconductor device according to the first and second embodiments, so duplicated descriptions will be omitted.

[0055] In the semiconductor device according to the modified example of the second embodiment, about 95% of the basal plane dislocations are converted to threading dislocations in the defect conversion layer 2a grown as the first intermediate growth layer on the carrier collection layer 1. The basal plane defects remaining in the defect conversion layer 2a after being converted to threading dislocations in the defect conversion layer 2a are immobilized near the interface with the carrier collection layer 1 by the first immobilization layer 21. Furthermore, in the recombination promotion layer 2b grown as the second and third intermediate growth layers on the defect conversion layer 2a, p + In this way, in the semiconductor device according to the modified example of the second embodiment, the basal plane dislocations propagated from the carrier collection layer 1 are present in the defect conversion layer 2a. The thicker the defect conversion layer 2a, the lower the frequency of stacking faults. However, making the layer thicker leads to a decrease in the throughput of epitaxial growth, so it is desirable to make the layer thin, about 1 μm. In addition, in order to reduce the density of holes injected into the basal plane dislocations present in the defect conversion layer 2a, it is desirable to use an n-type epitaxial layer with a higher impurity density than the travel layer 3 for the defect conversion layer 2a. Furthermore, the hole density is set to a threshold value of 1×10 15 cm -3 In order to reduce the n-type recombination promotion layer 2b having a higher impurity density than the defect conversion layer 2a, an n-type recombination promotion layer 2b having a higher impurity density than the defect conversion layer 2a is added.

[0056] For example, the carrier collection layer 1 contains 5×10 n-type impurity elements such as N. 17 cm -3 ~1×10 18 cm -3 The defect conversion layer 2a as the first intermediate growth layer has a thickness of about 1 μm and is doped with an n-type impurity element such as N at a lower impurity density than the carrier collection layer 1 and a higher impurity density than the running layer 3, for example, 1×10 17 cm -3 The recombination promotion layer 2b as the second and third intermediate growth layers has a thickness of about 5 μm to 10 μm, and contains n-type impurity elements such as N at an impurity density about two to three times higher than that of the defect conversion layer 2a, for example, at 2×10 17 cm -3 ~5×10 17 cm -3The running layer 3 as the fourth intermediate growth layer has a thickness of about 10 μm to 100 μm, and is doped with an n-type impurity element such as N at a concentration of about 1×10 14 cm -3 ~1×10 17 cm -3 The first passivation layer 21 is provided in the defect conversion layer 2a near the interface between the carrier collection layer 1 and the defect conversion layer 2a, for example, within a range of about 50 nm from the interface. The first passivation layer 21 contains impurity ions, which become atoms that immobilize the growth layer side basal plane dislocations 22, at an impurity density of about 1×10 14 cm -3 ~1×10 18 cm -3 More preferably, the impurity density is about 3×10 15 cm -3 That's it, 3 x 10 16 cm -3 The range is as follows: In addition to the n-type impurity element, the recombination promoting layer 2b may contain impurity elements that form a hole capture level, such as B, V, Ti, Fe, and Cr.

[0057] In the semiconductor device according to the modified example of the second embodiment, a buffer layer 2 having a defect conversion layer 2a as a first intermediate growth layer and a recombination promotion layer 2b as a second and third intermediate growth layer is epitaxially grown on a carrier collection layer 1. Furthermore, a first passivation layer 21 is provided in the defect conversion layer 2a near the interface with the carrier collection layer 1 by ion implantation. Therefore, the growth layer side basal plane dislocations 22 propagating from the substrate 1s are converted into threading dislocations in the defect conversion layer 2a. In addition, the recombination promotion layer 2b is doped with an n-type impurity element having a higher impurity density than the travel layer 3 and the defect conversion layer 2a. Therefore, the density of holes injected from the defect conversion layer 2a through the travel layer 3 as a fourth intermediate growth layer into the growth layer side basal plane dislocations 22 present at the interface between the carrier collection layer 1 and the defect conversion layer 2a is set to a threshold value of 1×10 15 cm -3 As a result, when a forward current is passed through the semiconductor device, the growth layer-side basal plane dislocations 22 are prevented from expanding into stacking faults, and degradation of the forward characteristics of the semiconductor device can be suppressed.

[0058] As shown in FIG. 28, a second passivation layer 11 may be provided near the top surface of the carrier collection layer 1 in order to improve the conversion rate of the growth layer side basal plane dislocations 22 to threading dislocations in the defect conversion layer 2a. As shown in FIG. 29, a third passivation layer 21d may be provided in the recombination promotion layer 2b as the second and third intermediate growth layers near the interface between the defect conversion layer 2a and the recombination promotion layer 2b. The third passivation layer 21d immobilizes the growth layer side basal plane dislocations 22 propagating from the defect conversion layer 2a to the recombination promotion layer 2b, thereby improving the conversion rate of the growth layer side basal plane dislocations 22 to threading dislocations in the recombination promotion layer 2b. Furthermore, as shown in FIG. 30, a fourth passivation layer 21e may be provided in the running layer 3 as the fourth intermediate growth layer near the interface between the recombination promotion layer 2b and the running layer 3. The fourth passivation layer 21e immobilizes the growth layer-side basal plane dislocations 22 that propagate from the recombination promotion layer 2b to the travel layer 3, thereby improving the conversion rate of the growth layer-side basal plane dislocations 22 to threading dislocations within the travel layer 3.

[0059] -Method of manufacturing semiconductor device- Next, a method for manufacturing a semiconductor device according to a modified example of the second embodiment will be described with reference to the process diagrams shown in Figures 31 to 34, taking the pin diode shown in Figure 30 as an example. First, as shown in Figure 31, the n-type 4H-SiC crystal on which the second passivation layer 11 is formed is grown by vapor phase epitaxial growth or the like. + An n-type defect conversion layer (first intermediate growth layer) 2a is epitaxially grown on a n-type substrate 1s. The substrate 1s has a (0001) Si surface with a 4° offset in the <11-20> direction. The defect conversion layer 2a has a thickness of, for example, about 1 μm and contains 1×10 n-type impurity elements such as N. 17 cm -3 The impurity is doped at a density of about 1×10. Then, by ion implantation technology, ions of, for example, Ar atoms, which become atoms that immobilize the growth layer side basal plane dislocations 22, are implanted in the defect conversion layer 2a near the interface between the substrate 1s and the defect conversion layer 2a. 14 cm -3 ~1×10 18 cm -3Subsequently, in order to control the state of defects introduced by the ion implantation, heat treatment is performed at about 900° C. to 1400° C. for about 30 minutes to 2 hours to form a first passivation layer 21.

[0060] 32, an n-type second intermediate growth layer 2bs is epitaxially grown on the defect conversion layer 2a by a vapor phase epitaxial growth technique or the like. The second intermediate growth layer 2bs has a thickness of, for example, about 1 μm and contains 2×10 n-type impurity elements such as N. 17 cm -3 ~5×10 17 cm -3 Then, by ion implantation technology, ions of, for example, Ar atoms, which become atoms that immobilize the growth layer side basal plane dislocations 22, are implanted in the second intermediate growth layer 2bs near the interface between the first intermediate growth layer (defect conversion layer) 2a and the second intermediate growth layer 2bs at an impurity density of 1×10 14 cm -3 ~1×10 18 cm -3 More preferably, the impurity density is about 3×10 15 cm -3 That's it, 3 x 10 16 cm -3 The range is as follows: Subsequently, a heat treatment is performed at about 900° C. to 1400° C. for about 30 minutes to 2 hours to form a third immobilization layer 21d.

[0061] 33, a third intermediate growth layer is further epitaxially grown on the second intermediate growth layer 2bs by vapor phase epitaxial growth or the like, and a recombination promotion layer 2b consisting of the second intermediate growth layer 2bs and the third intermediate growth layer is formed on the defect conversion layer 2a. The recombination promotion layer 2b has a thickness of, for example, about 5 μm to 10 μm and contains 2×10 n-type impurity elements such as nitrogen (N). 17 cm -3 ~5×10 17 cm -3 The impurity density is about 100 nm.

[0062] 34, an intermediate growth layer 3e is epitaxially grown as a fourth intermediate growth layer on the recombination promotion layer 2b by a vapor phase epitaxial growth technique or the like. The intermediate growth layer (fourth intermediate growth layer) 3e has a thickness of, for example, about 1 μm and contains 1×10 n-type impurity elements such as N. 14 cm -3 ~1×10 17 cm -3 The recombination promotion layer 2b is doped with an impurity density of about 1×10. Then, by ion implantation technology, ions of, for example, Ar atoms, which become atoms that immobilize the basal plane dislocations 22 on the growth layer side, are implanted into the intermediate growth layer 3e near the interface between the recombination promotion layer 2b and the intermediate growth layer 3e. 14 cm -3 ~1×10 18 cm -3 Subsequently, a heat treatment is performed at about 900° C. to 1400° C. for about 30 minutes to 2 hours to form a fourth passivation layer 21e.

[0063] Thereafter, an n-type upper growth layer that will become a main epitaxial growth layer is epitaxially grown on the intermediate growth layer (fourth intermediate growth layer) 3e by a vapor phase epitaxial growth technique or the like, to form the traveling layer 3 shown in Fig. 30. The traveling layer 3 contains an n-type impurity element such as N at a lower impurity density of 1 x 10 14 cm -3 ~1×10 17 cm -3 The thickness of the travel layer 3 is in the range of about 10 μm to several hundred μm, and the optimum thickness and impurity density are selected according to the withstand voltage specifications of the pin diode. For example, about 10 μm is selected for a withstand voltage of 1000 V, and about 100 μm is selected for a withstand voltage of 10 kV.

[0064] Next, as shown in FIG. 27, a p-type carrier injection region 5 made of Al or the like is selectively formed on the upper part of the running layer 3 by photolithography, ion implantation, or the like. Subsequently, the lower surface of the substrate 1s is polished by chemical mechanical polishing (CMP) or the like to adjust the thickness, and the carrier collection layer 1 is finished to the specifications for the cathode region. A back electrode (cathode electrode) 9 made of Au or the like is formed on the lower surface of the carrier collection layer 1 by sputtering, vacuum deposition, or the like. Furthermore, a metal film made of Al or the like is deposited by sputtering, vacuum deposition, or the like to form a front electrode (anode electrode) 7. In this manner, the semiconductor device according to the modified example of the second embodiment is completed.

[0065] In the manufacturing method of the semiconductor device according to the modified example of the second embodiment, a substrate 1s having a second passivation layer 11 provided on its upper surface is used. A first passivation layer 21, a third passivation layer 21d, and a fourth passivation layer 21e are provided near the respective interfaces of the defect conversion layer 2a on the substrate 1s, the recombination promotion layer 2b on the defect conversion layer 2a, and the travel layer 3 on the recombination promotion layer 2b. Therefore, the conversion efficiency of the growth layer side basal plane dislocations 22 propagating during the respective epitaxial growth into threading dislocations can be improved. In addition, a recombination promotion layer 2b having a higher impurity density than the defect conversion layer 2a is epitaxially grown on the defect conversion layer 2a having a higher impurity density than the travel layer 3. Therefore, the density of holes injected from the travel layer 3 into the growth layer side basal plane dislocations 22 present at the interface between the carrier collection layer 1 and the defect conversion layer 2a is set to a threshold value of 1×10 15 cm -3 As a result, when a forward current is passed through the semiconductor device, the expansion of stacking faults caused by the growth layer-side basal plane dislocations 22 can be prevented, and degradation of the forward characteristics of the semiconductor device can be suppressed.

[0066] In the semiconductor device according to the modified example of the second embodiment, the defect conversion layer 2a is epitaxially grown on the substrate 1s. Therefore, the growth layer side basal plane dislocations 22 propagating from the substrate 1s are converted into threading dislocations in the defect conversion layer 2a. The recombination promotion layer 2b is doped with an n-type impurity element at a higher impurity density than the intermediate growth layer (fourth intermediate growth layer) 3e. Therefore, the density of holes injected from the intermediate growth layer 3e into the growth layer side basal plane dislocations 22 present at the interface between the substrate 1s and the buffer layer 2 is increased to a threshold value of 1×10 15 cm -3 As a result, it is possible to prevent the growth layer side basal plane dislocations 22 from expanding into stacking faults.

[0067] (Other embodiments) As described above, the embodiment of the present invention has been described, but the description and drawings forming a part of this disclosure should not be understood as limiting the present invention. From this disclosure, various alternative embodiments, examples and operating techniques will become apparent to those skilled in the art.

[0068] As described above, the growth layer side basal plane dislocations are immobilized by crystal defects introduced during the implantation of impurity ions that become atoms that immobilize the basal plane dislocations, but this is not limited thereto. For example, the propagation of the basal plane dislocations can also be prevented by a p-type semiconductor region. Therefore, as shown in FIG. 35, a plurality of p-type semiconductor regions 30 may be selectively provided in the buffer layer 2 on the carrier collection layer 1 to immobilize the growth layer side basal plane dislocations 22. The semiconductor regions 30 are provided so as to extend from the interface between the carrier collection layer 1 and the buffer layer 2 into the buffer layer 2. The surface of the carrier collection layer 1 is a (0001) Si surface, and has an off angle of about 0° to 8° in the [11-20] direction with respect to the

[0001] (c-axis) direction. As shown in FIG. 36, a plurality of stripe-shaped semiconductor regions 30 are provided on the upper surface of the buffer layer 2 epitaxially grown on the carrier collection layer 1, the stripe-shaped semiconductor regions 30 extending parallel to each other in a direction perpendicular to the [11-20] direction. 37, the multiple semiconductor regions 30 are arranged with a height of h and a distance d between adjacent semiconductor regions 30. The width of the semiconductor regions 30 is preferably 5 μm or less. For example, if the off angle is θ, and h / d>tan θ, then basal plane dislocations present between adjacent semiconductor regions 30 are prevented from propagating to the semiconductor regions and are confined within the buffer layer 2. As a result, the movement of basal plane dislocations in the [11-20] direction is prevented, and the expansion of stacking faults can be prevented.

[0069] Using the process diagrams shown in Figures 38 and 39, a process for producing a semiconductor region 30 in a method for producing a multilayer structure according to another embodiment will be described. As shown in Figure 38, a plurality of masks 35 such as resist are selectively formed on the upper surface of a buffer layer 2 epitaxially grown on a substrate 1s by using photolithography or the like. Ions of p-type impurities such as Al are implanted into the buffer layer 2 through openings between adjacent masks 35. Multi-stage ion implantation is performed by adjusting the acceleration voltage so that the implantation depth of the p-type impurity ions reaches the interface between the substrate 1s and the buffer layer 2. After the ion implantation, the mask 35 is removed, and a heat treatment for activating the p-type impurities is performed. In this way, a plurality of semiconductor regions 30 extending from the interface between the substrate 1s and the buffer layer 2 into the buffer layer 2 are formed, as shown in Figure 39.

[0070] As shown in Fig. 40, a second immobilization layer 11 may be provided near the upper surface of the substrate 1s before the epitaxial growth of the buffer layer 2. The substrate-side basal plane dislocations 12 present in the substrate 1s may be immobilized to increase the conversion rate to threading dislocations. Also, as shown in Fig. 41, each of the multiple semiconductor regions 30 may extend in the thickness direction of the buffer layer 2 from the interface with the substrate 1s to the interface with the traveling layer 3.

[0071] Thus, the present invention naturally includes various embodiments not described here, such as configurations obtained by arbitrarily applying the configurations described in the above embodiments and modifications. Therefore, the technical scope of the present invention is determined only by the invention-specifying matters according to the scope of the claims that are appropriate from the above description. [Explanation of symbols]

[0072] 1...Carrier collection layer (cathode region) 1s…Board (1s,3e)…intermediate complex 2…Buffer layer 2a…Defect conversion layer 2b…Recombination promotion layer 3…Running layer 3e: Intermediate growth layer (epitaxial growth layer) 5...Carrier injection region (anode region) 7...Anode electrode (surface electrode) 9...Cathode electrode (rear electrode) 11…Second immobilization layer 21...1st immobilization layer 21d…Third immobilization layer 21e…4th immobilization layer 12, 12a, 22…Basal plane dislocations 12c, 22c...carbon core 12s, 22s...Silicone core 14...Threading dislocation 30…Semiconductor area 221, 221a, 221b, 221c...Atoms that immobilize basal plane dislocations

Claims

1. a silicon carbide substrate of a first conductivity type; an epitaxially grown layer of a first conductivity type provided on the substrate and having a lower impurity concentration than the substrate; a first passivation layer is provided within the epitaxial growth layer within a region of 50 nm from an interface between the substrate and the epitaxial growth layer, the first passivation layer having a peak in a concentration distribution of atoms that passivate, by crystal defects, basal plane dislocations that occur in the epitaxial growth layer continuously from basal plane dislocations present in the substrate; the first passivation layer includes atoms that immobilize basal plane dislocations and is provided on the entire in-plane surface of the substrate; A multilayer structure, wherein the atoms that immobilize basal plane dislocations are at least one type of atom selected from the group consisting of magnesium, calcium, barium, and manganese.

2. The multilayer structure described in claim 1, further comprising a second passivation layer, the second passivation layer having a peak in a concentration distribution of atoms that immobilize basal plane dislocations present from the inside of the substrate to the interface by crystal defects, located within 1 μm from the interface into the substrate, on the entire in-plane direction of the substrate.

3. 3. The multi-layer structure of claim 2, wherein the second passivation layer comprises atoms that immobilize basal plane dislocations.

4. 4. The multilayer structure according to claim 2, wherein the first passivation layer and the second passivation layer are in contact with each other at the interface.

5. 5. The multilayer structure according to claim 3, wherein the atoms contained in the second passivation layer that passivate the basal plane dislocations are at least one type of atoms selected from the group consisting of silicon, carbon, hydrogen, helium, argon, magnesium, calcium, barium, titanium, vanadium, chromium, manganese, and iron.

6. The impurity density of the atoms that immobilize the basal plane dislocations contained in the first passivation layer is 1×10 14 cm -3 That's it, 1 x 10 18 cm -3 The multilayer structure according to any one of claims 3 to 5, characterized in that:

7. The impurity density of the atoms that immobilize the basal plane dislocations contained in the first passivation layer is 3×10 15 cm -3 That's it, 3 x 10 16 cm -3 The multilayer structure according to any one of claims 3 to 5, characterized in that:

8. epitaxially growing an epitaxially grown layer of a first conductivity type on a silicon carbide substrate of a first conductivity type, the epitaxially grown layer having an impurity density lower than that of the substrate; forming a first passivation layer over the entire in-plane direction of the epitaxial growth layer, the first passivation layer being disposed within the epitaxial growth layer within a distance of 50 nm from an interface between the substrate and the epitaxial growth layer, the first passivation layer being configured to passivate basal plane dislocations that are generated within the epitaxial growth layer in succession to basal plane dislocations present within the substrate by using crystal defects; Including, forming the first passivation layer includes implanting atoms that passivate basal plane dislocations from a top surface of the epitaxial growth layer to an interior of the epitaxial growth layer within 50 nm from the interface; The method for producing a multilayer structure, wherein the atoms that immobilize basal plane dislocations are at least one type of atom selected from the group consisting of magnesium, calcium, barium, and manganese.

9. The method further includes forming a second passivation layer on the entire in-plane direction of the substrate, the second passivation layer immobilizing basal plane dislocations present at the interface from the inside of the substrate to the interface within 1 μm into the substrate, by using crystal defects; 9. The method of claim 8, wherein the step of forming the second passivation layer comprises implanting atoms that immobilize basal plane dislocations from a top surface of the substrate with a projected range that is within 1 μm of the substrate from the interface.

10. 10. The method for producing a multilayer structure according to claim 9, wherein the first passivation layer and the second passivation layer are formed so as to be in contact with each other at the interface.

11. 11. The method for producing a multilayer structure according to claim 10, wherein the atoms contained in the second passivation layer that passivate the basal plane dislocations are at least one type of atom selected from the group consisting of silicon, carbon, hydrogen, helium, argon, magnesium, calcium, barium, titanium, vanadium, chromium, manganese, and iron.

12. epitaxially growing a buffer layer of a first conductivity type on a silicon carbide substrate of a first conductivity type, the buffer layer having a lower impurity density than the substrate; forming a first passivation layer on the entire in-plane direction of the buffer layer within 50 nm of the interface between the substrate and the buffer layer, the first passivation layer immobilizing basal plane dislocations that occur in the buffer layer continuously from basal plane dislocations present in the substrate by using crystal defects; epitaxially growing a first conductivity type traveling layer on the buffer layer with a lower impurity density than the buffer layer; forming a second conductive type carrier injection region on a surface of the traveling layer for injecting carriers into the traveling layer; Including, forming the first passivation layer includes implanting atoms that passivate basal plane dislocations from an upper surface of the buffer layer to an interior of the buffer layer within 50 nm from an interface between the substrate and the buffer layer; The method for manufacturing a semiconductor device, wherein the atoms that immobilize basal plane dislocations are at least one type of atom selected from the group consisting of magnesium, calcium, barium, and manganese.

13. The method further includes forming a second passivation layer on the entire in-plane direction of the substrate, the second passivation layer immobilizing basal plane dislocations present from the inside of the substrate toward the top surface of the substrate by crystal defects, within 1 μm of the inside of the substrate from the top surface of the substrate; 13. The method for manufacturing a semiconductor device according to claim 12, wherein in the step of forming the second passivation layer, atoms that passivate basal plane dislocations are implanted from the top surface of the substrate with a projected range that is within 1 μm inside the substrate from the top surface of the substrate.

14. 14. The method for manufacturing a semiconductor device according to claim 13, wherein the first passivation layer and the second passivation layer are formed so as to be in contact with each other at an interface between the substrate and the buffer layer.

15. A method for manufacturing a semiconductor device as described in claim 13 or 14, characterized in that the atoms contained in the second passivation layer that immobilize the basal plane dislocations are at least one type of atom selected from the group consisting of silicon, carbon, hydrogen, helium, argon, magnesium, calcium, barium, titanium, vanadium, chromium, manganese, and iron.

16. The step of epitaxially growing the buffer layer comprises: epitaxially growing a defect conversion layer on the substrate to convert basal plane dislocations into threading dislocations; epitaxially growing a recombination enhancement layer on the defect conversion layer, the recombination enhancement layer having a higher impurity density than the defect conversion layer and reducing injected minority carriers through recombination; The method for manufacturing a semiconductor device according to any one of claims 12 to 15, further comprising the steps of:

17. forming a third passivation layer on the entire in-plane direction of the recombination-promoting layer, the third passivation layer being disposed within 50 nm from the interface between the defect conversion layer and the recombination-promoting layer, the third passivation layer immobilizing basal plane dislocations present in the recombination-promoting layer by crystal defects; 17. The method for manufacturing a semiconductor device according to claim 16, wherein in the step of forming the third passivation layer, atoms that passivate basal plane dislocations are implanted from an upper surface of the recombination promotion layer with a projected range that is within 50 nm of the interior of the recombination promotion layer from an interface between the defect conversion layer and the recombination promotion layer.

18. The method for manufacturing a semiconductor device described in Claim 17, characterized in that the atoms contained in the third passivation layer that immobilize the basal plane dislocations are at least one type of atom selected from the group consisting of silicon, carbon, hydrogen, helium, argon, magnesium, calcium, barium, titanium, vanadium, chromium, manganese, and iron.

19. The method further includes forming a fourth passivation layer on the entire in-plane direction of the traveling layer, the fourth passivation layer being located within 50 nm from the interface between the buffer layer and the traveling layer, the fourth passivation layer immobilizing basal plane dislocations present in the traveling layer by crystal defects; 19. The method for manufacturing a semiconductor device according to claim 12, wherein in the step of forming the fourth passivation layer, atoms that passivate basal plane dislocations are implanted from the top surface of the current layer with a projected range that is within 50 nm of the interior of the current layer from the interface between the buffer layer and the current layer.

20. The method for manufacturing a semiconductor device described in Claim 19, characterized in that the atoms contained in the fourth passivation layer that immobilize the basal plane dislocations are at least one type of atom selected from the group consisting of silicon, carbon, hydrogen, helium, argon, magnesium, calcium, barium, titanium, vanadium, chromium, manganese, and iron.

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