Semiconductor Device

Abstract

To provide a semiconductor device in which the state of a battery or the like can be monitored, by which the state of each of a plurality of batteries inside a battery module is acquired easily.SOLUTION: A semiconductor device that can be attached to an electrode such as a battery includes a first substrate, an element layer, and first to third conductive layers. The element layer includes a first circuit and a second circuit, and is provided on a first surface side of the first substrate. The first conductive layer and the second conductive layer are provided on a second surface side, which is on the opposite side to the first surface of the first substrate. The first conductive layer and the first circuit, and the second conductive layer and the first circuit are electrically connected through openings provided in the first substrate. The third conductive layer is provided while being stacked on the side of the element layer opposite to the first substrate, and is connected electrically to the second circuit. Each of the first conductive layer and the second conductive layer functions as a terminal. The third conductive layer functions as an antenna.SELECTED DRAWING: Figure 6

Description

[Technical field]

[0001] 1. Field of the Invention One embodiment of the present invention relates to a semiconductor device, a battery unit or a battery module having a battery, and a method for controlling a battery.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. Examples of the technical field of one embodiment of the present invention disclosed in this specification and the like include a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, an electronic device, a lighting device, an input device, an input / output device, a driving method thereof, or a manufacturing method thereof.

[0003] In this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. A transistor, a semiconductor circuit, an arithmetic device, a memory device, and the like are examples of semiconductor devices. In addition, imaging devices, electro-optical devices, power generation devices (including thin-film solar cells, organic thin-film solar cells, and the like), and electronic devices may include semiconductor devices. [Background technology]

[0004] In recent years, various types of power storage devices, such as lithium-ion secondary batteries, lithium-ion capacitors, and air batteries, have been actively developed. In particular, the demand for lithium-ion secondary batteries, which have high output and high energy density, has rapidly increased along with the development of the semiconductor industry, and they have become indispensable in the modern information society as a rechargeable energy source. For example, they are used in mobile information terminals such as mobile phones, smartphones, tablets, and notebook computers, portable music players, digital cameras, medical equipment, and next-generation clean energy automobiles such as hybrid electric vehicles (HEVs), electric vehicles (EVs), and plug-in hybrid electric vehicles (PHEVs).

[0005] In portable information terminals, electric vehicles, and the like, battery modules (also called battery packs or assembled batteries) that have multiple secondary batteries connected in series or parallel and a protection circuit are often used. A battery module refers to a storage device in which multiple secondary batteries are housed inside a container (such as a metal can or a film exterior) together with a specified circuit to facilitate the handling of the secondary batteries. An ECU (Electronic Control Unit) is provided in the battery module to manage the operating state.

[0006] If the multiple secondary batteries that make up a battery module have variations in their individual characteristics, some of the secondary batteries will be overcharged or not fully charged, resulting in a decrease in the overall apparent capacity.

[0007] In addition, because a single battery module charges or discharges multiple secondary batteries collectively, if the deterioration rates of the individual secondary batteries differ, the characteristics will vary. This creates a vicious cycle in which the battery module's lifespan is shortened by repeated charging and discharging.

[0008] Patent Document 1 describes that the conductive state of a transistor is controlled in accordance with the capacity of a battery cell, thereby controlling charging and discharging from a discharging battery cell to a charging battery cell. [Prior art documents] [Patent documents]

[0009] [Patent Document 1] JP 2017-22928 A Summary of the Invention [Problem to be solved by the invention]

[0010] In many cases, control circuits such as ECUs installed in battery modules are mounted on printed circuit boards and connected to multiple secondary batteries via wiring. Wire bonding, welding, or screw fastening are often used to connect secondary batteries to wiring. Therefore, the more secondary batteries there are per battery module, the more contacts there are, and the higher the mounting costs become. In addition, the strength of the contacts is required to prevent the connection between the wiring and secondary batteries from being broken due to external environmental factors such as vibration and operating temperature.

[0011] An object of one embodiment of the present invention is to provide a semiconductor device capable of monitoring the state of a battery or the like. Another object is to provide a semiconductor device capable of outputting information on the state of a battery or the like with high reliability. Another object is to reduce the mounting cost or the number of mounting steps in a battery module. Another object is to easily obtain the individual states of a plurality of batteries in a battery module. Another object is to provide a lightweight battery module.

[0012] Another object of one embodiment of the present invention is to provide a novel semiconductor device, a novel battery unit, or a novel battery module. Another object of one embodiment of the present invention is to provide a highly reliable semiconductor device, a battery unit, or a battery module.

[0013] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these can be extracted from the description of the specification, drawings, claims, etc. [Means for solving the problem]

[0014] One embodiment of the present invention is a semiconductor device including a first substrate, an element layer, a first conductive layer, a second conductive layer, and a third conductive layer. The element layer includes a first circuit and a second circuit, and is provided on a first surface side of the first substrate. The first conductive layer and the second conductive layer are each provided on a second surface side of the first substrate opposite to the first surface. The first conductive layer and the first circuit, and the second conductive layer and the first circuit are each electrically connected through an opening provided in the first substrate. The third conductive layer is stacked on the side opposite to the first substrate of the element layer, and is electrically connected to the second circuit. The first conductive layer and the second conductive layer each function as a terminal, and the third conductive layer functions as an antenna.

[0015] In the above, the second circuit preferably has a function of performing wireless communication through the third conductive layer.

[0016] In addition, in the above, it is preferable that the first circuit has at least one of a function of detecting a voltage between the first conductive layer and the second conductive layer, a function of detecting a current flowing between the first conductive layer and the second conductive layer, and a function of detecting a temperature.

[0017] In the above, the first substrate is preferably flexible.

[0018] In the above, a second substrate is preferably provided facing the first substrate with the element layer and the third conductive layer interposed therebetween. In this case, the second substrate is preferably flexible.

[0019] Another embodiment of the present invention is a battery unit including any one of the above semiconductor devices and a battery, in which a first conductive layer of the semiconductor device is in contact with a positive terminal of the battery and a second conductive layer of the semiconductor device is in contact with a negative terminal of the battery.

[0020] Another embodiment of the present invention is a battery unit including any one of the semiconductor devices described above and a plurality of batteries. The plurality of batteries are connected in series. The first conductive layer of the semiconductor device is electrically connected to a positive terminal or a negative terminal of one battery, and the second conductive layer is electrically connected to a positive terminal or a negative terminal of another battery.

[0021] In the above, the plurality of batteries are preferably cylindrical batteries, and the first conductive layer and the second conductive layer of the semiconductor device are preferably provided in contact with side surfaces of cylindrical exterior bodies of the different batteries.

[0022] Another aspect of the present invention is a battery module including a plurality of battery units according to any one of the above, a control device, and an exterior body. The plurality of battery units and the control device are provided inside the exterior body. The control device includes an antenna, a wireless communication unit, and a control unit. The control unit has a function of wirelessly communicating with the plurality of battery units via the wireless communication unit and the antenna. In addition, it is preferable that the control unit includes a neural network. Effect of the Invention

[0023] According to one embodiment of the present invention, a semiconductor device capable of monitoring a battery state can be provided. Alternatively, a semiconductor device capable of outputting information on a battery state with high reliability can be provided. Alternatively, a reduction in mounting cost or a reduction in the number of mounting steps in a battery module can be realized. Alternatively, the individual states of a plurality of batteries in a battery module can be easily obtained.

[0024] According to one embodiment of the present invention, a novel semiconductor device, a novel battery unit, or a novel battery module can be provided. Alternatively, a highly reliable semiconductor device, battery unit, or battery module can be provided.

[0025] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. Note that effects other than these can be extracted from the description in the specification, drawings, claims, etc. [Brief description of the drawings]

[0026] [Figure 1] 1 shows a configuration example of a semiconductor device. [Diagram 2] 1 shows a configuration example of a semiconductor device. [Diagram 3] An example of a battery unit configuration. [Figure 4] An example of a battery module configuration. [Diagram 5] An example of a battery module configuration. [Figure 6] 1 shows an example of the configuration of a battery unit and a battery module. [Figure 7] 1 shows an example of the configuration of a battery unit and a battery module. [Figure 8] 1 shows a configuration example of a semiconductor device. [Figure 9] 1A to 1C illustrate a method for manufacturing a semiconductor device. [Figure 10] 1A to 1C illustrate a method for manufacturing a semiconductor device. [Figure 11] 1A to 1C illustrate a method for manufacturing a semiconductor device. [Figure 12] 1A to 1C illustrate a method for manufacturing a semiconductor device. [Figure 13] An example of neural network configuration. [Figure 14] 1 shows a configuration example of a semiconductor device. [Figure 15] 1 shows an example of a memory cell configuration. [Figure 16] 1 shows an example of an offset circuit configuration. [Figure 17] Timing chart. [Figure 18] An example of a vehicle. [Figure 19] An example of a vehicle. [Figure 20] An example of electronic equipment. [Figure 21]An example of battery module application. [Figure 22] An example of electronic equipment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0027] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be easily understood by those skilled in the art that the modes and details of the present invention can be modified in various ways without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below.

[0028] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and the repeated explanations are omitted. In addition, when referring to similar functions, the same hatch pattern may be used and no particular reference numeral may be used.

[0029] In addition, in each figure described in this specification, the size of each component, the thickness of a layer, or an area may be exaggerated for clarity, and therefore, the drawings are not necessarily limited to the scale.

[0030] In addition, ordinal numbers such as "first" and "second" in this specification are used to avoid confusion of components and do not limit the numbers.

[0031] A transistor is a type of semiconductor element that can amplify current or voltage, and perform switching operations to control conduction or non-conduction, etc. In this specification, the term "transistor" includes an IGFET (Insulated Gate Field Effect Transistor) and a thin film transistor (TFT).

[0032] (Embodiment 1) In this embodiment, a semiconductor device, a battery unit, a battery module, or the like according to one embodiment of the present invention will be described with reference to drawings.

[0033] The semiconductor device exemplified below has a function of detecting the voltage, current, temperature, etc. of a battery and outputting the information by wireless communication. Therefore, the semiconductor device exemplified below can also be called an information processing device, an information communication device, a wireless tag, or the like.

[0034] A semiconductor device according to one embodiment of the present invention includes an element layer including a first circuit that functions as a circuit for detecting voltage, current, temperature, or the like, and a second circuit that performs wireless communication. The element layer includes at least one transistor. The element layer is formed over a substrate (also referred to as a first substrate).

[0035] Furthermore, the semiconductor device has a pair of conductive layers (also referred to as a first conductive layer and a second conductive layer) each functioning as a terminal portion on the back side of the substrate (opposite to the element layer). The terminal portion can also be referred to as an external connection terminal, and can be used as a terminal for connecting to an electrode of a battery or the like. Each conductive layer is electrically connected to a first circuit of the element layer through an opening provided in the substrate.

[0036] In addition, the semiconductor device has a conductive layer (also referred to as a third conductive layer) functioning as an antenna over the element layer. This conductive layer is electrically connected to a second circuit. The second circuit can perform wireless communication with the outside through the antenna.

[0037] The conductive layer constituting the antenna and the conductive layer constituting the terminal portion may be interchanged. That is, the conductive layer provided on the element layer may be used as the terminal portion, and the conductive layer provided on the back side of the substrate may be used as the antenna. In this case, the conductive layer of the terminal portion may be connected to the first circuit, and the conductive layer of the antenna may be connected to the second circuit through an opening provided in the substrate.

[0038] A semiconductor device having such a configuration can detect the voltage and current of the battery by connecting a pair of terminals to the positive and negative terminals of the battery, respectively, and transmit the information to an external control circuit via wireless communication. In addition, if the first circuit has a function for detecting temperature, the semiconductor device can be attached to the battery or placed near the battery to transmit information on the temperature of the battery or its vicinity to an external control device via wireless communication. The semiconductor device may have a function for controlling the charging and discharging of the battery in response to a command transmitted from the control device.

[0039] Here, it is preferable to use a flexible substrate for the substrate on which the element layer is formed. This allows the semiconductor device to be bendable. This increases the degree of freedom in the shape of components such as a battery to which the semiconductor device is connected, and the semiconductor device can be attached to surfaces of various shapes. Furthermore, by using a flexible substrate, the semiconductor device can be made extremely light in weight compared to a case where a glass substrate or a semiconductor substrate is used. Therefore, when the semiconductor device is applied to a battery, for example, an increase in weight due to the attachment of the semiconductor device can be suppressed.

[0040] Here, a unit configuration in which one or more batteries are connected to a semiconductor device can be called a battery unit. In one embodiment of the present invention, information such as the voltage, current, or temperature of each battery can be obtained for each battery unit and wirelessly output to an external control device.

[0041] The external control device may have a printed circuit board or the like provided with a circuit functioning as a control unit and a circuit functioning as a wireless communication unit, and an antenna. A configuration in which the control device and a plurality of battery units are provided inside an exterior body may be called a battery module. The battery module may be incorporated into various electronic devices, automobiles, or large-scale installed power storage devices used in housing facilities, etc.

[0042] By arranging multiple battery units within a battery module, if an abnormality is detected in one battery unit, it becomes possible to replace each battery unit individually. This makes battery replacement easier and significantly reduces maintenance costs compared to managing the voltage, current, temperature, etc. on a battery module basis.

[0043] Furthermore, a neural network may be applied to the control unit of the control device, and detection of battery abnormalities and derivation of optimal control methods may be performed by inference using the neural network.

[0044] In the case of a battery module in which a plurality of batteries and a control circuit are connected by wiring, the wiring must be reconnected when replacing a defective battery, and therefore the entire battery module must be replaced. However, in one embodiment of the present invention, the battery unit and the control circuit communicate wirelessly, so that the battery unit can be easily replaced. Furthermore, replacement by the user is also made easier, and maintenance costs can be further reduced.

[0045] A more specific example will be described below with reference to the drawings.

[0046] [Example of semiconductor device configuration] 1(A) and (B) show examples of external views of a semiconductor device 10 exemplified below. Fig. 1(A) is a perspective view of the semiconductor device 10, and Fig. 1(B) is a schematic perspective view as seen from the back side of Fig. 1(A). Fig. 1(C) shows a schematic cross-sectional view of the semiconductor device 10.

[0047] As shown in FIGS. 1A and 1B, a semiconductor device 10 has a sheet-like shape and has an antenna 14 on one surface and a terminal 13a and a terminal 13b on the other surface.

[0048] 1C, the semiconductor device 10 includes a substrate 11, an element layer 12, terminals 13a and 13b, and an antenna 14. The element layer 12 is provided over the substrate 11 and includes a first circuit and a second circuit, which will be described later. The antenna 14 is provided over the element layer 12. The terminals 13a and 13b are provided on a surface of the substrate 11 opposite to the element layer 12. The element layer 12 is electrically connected to the terminal 13a or the terminal 13b by a connection portion 15 located in an opening provided in the substrate 11.

[0049] In addition, a protective layer 16 may be provided to cover the antenna 14 and the element layer 12 .

[0050] 2, a substrate 17 may be provided to cover the antenna 14 and the element layer 12. In this case, the protective layer 16 can be used as an adhesive layer.

[0051] It is preferable to use a flexible material for the substrate 11 (and substrate 17). For example, a film-like substrate containing an organic resin can be used. Alternatively, a glass substrate or a metal substrate that is thin enough to be flexible may be used. When attaching the semiconductor device 10 to the object to be detected, if the portion to which the semiconductor device 10 is attached has a flat surface, a substrate material with poor flexibility may be used.

[0052] The semiconductor device 10 has two functions: a function as a monitor device that electrically monitors the state of the detected object by connecting the terminals 13a and 13b to electrodes of the detected object, and a function as an information communication device that wirelessly transmits the monitored information to an external device via the antenna 14. Furthermore, the semiconductor device 10 may have a function as a control device that controls the operation of the detected object in response to a command wirelessly transmitted from the external device.

[0053] Here, an example of the semiconductor device 10 applied to a battery as an example of a detected object will be described. The semiconductor device 10 can detect the state of the battery and output the information to the outside. The detected object is not limited to a battery, and can be applied to various electronic devices, non-electronic devices, parts, members, equipment, buildings, vehicles, etc., and can be used for managing and controlling the state of the devices. In addition, by attaching the semiconductor device to the human body, it can also be used as a device that acquires various biological information such as body temperature, pulse rate, blood flow rate, and blood oxygen concentration, and outputs the information to an external device.

[0054] [Example of battery unit configuration] The following describes an example of a battery unit formed by combining a battery with the semiconductor device 10. For simplicity, the following describes a case in which the semiconductor device 10 has a function of monitoring the voltage of the battery.

[0055] FIG. 3(A1) shows an example of a battery unit 20p having one cell 30 and one semiconductor device 10.

[0056] The battery 30 in the battery unit 20p is a cylindrical battery, and has a cylindrical negative electrode terminal 31n and a convex positive electrode terminal 31p. The negative electrode terminal 31n functions as an exterior body.

[0057] The semiconductor device 10 is fixed so that one terminal 13a contacts the positive electrode terminal 31p and the other terminal 13b contacts the side of the exterior body which is the negative electrode terminal 31n. The terminal of the semiconductor device 10 and the terminal of the battery 30 are joined by a conductive tape, a conductive adhesive, a conductive paste, or the like. The method of fixing the semiconductor device 10 to the battery 30 is not particularly limited, and they may be attached to each other by an adhesive tape, a bonding tape, a double-sided tape, or the like, or an insulating exterior film may be wrapped around the outside of the semiconductor device 10 and the battery 30.

[0058] 3(A2) shows an equivalent circuit of the battery unit 20p. The semiconductor device 10 is connected in parallel to the battery 30, and can monitor the voltage V between the positive and negative electrodes of the battery 30.

[0059] FIG. 3(B1) shows an example of a battery unit 20 having two batteries (battery 30a, battery 30b) and one semiconductor device 10.

[0060] The battery 30a and the battery 30b are connected in series. The semiconductor device 10 is fixed across the exterior bodies of the two batteries. Furthermore, one terminal 13a of the semiconductor device 10 is connected to the negative terminal 31n of the battery 30a, and the other terminal 13b is connected to the negative terminal 31n of the battery 30b.

[0061] 3B2 shows an equivalent circuit of the battery unit 20. The semiconductor device 10 is connected in parallel to the battery 30b, which is the negative battery of the two batteries, and can monitor the voltage V2 of the battery 30b. Here, the voltage of the battery 30a (also called voltage V1) is calculated by multiplying the voltage V2 of the two batteries connected in series by the voltage V2 of the battery 30b. U This can be estimated by subtracting the voltage V2 from the battery 30a. This makes it possible to monitor the voltage states of the batteries 30a and 30b using a single semiconductor device 10.

[0062] FIG. 3(C1) shows an example of a battery unit 20a having three batteries (battery 30a, battery 30b, battery 30c) and two semiconductor devices (semiconductor device 10a, semiconductor device 10b).

[0063] The battery 30a, the battery 30b, and the battery 30c are connected in series in this order. The semiconductor device 10a is fixed so as to traverse the exterior bodies of the batteries 30a and 30b, and the semiconductor device 10b is fixed so as to traverse the exterior bodies of the batteries 30b and 30c.

[0064] Furthermore, the semiconductor device 10a has a terminal 13a connected to the negative terminal 31n of the battery 30a, and a terminal 13b connected to the negative terminal 31n of the battery 30b. The semiconductor device 10b has a terminal 13a connected to the negative terminal 31n of the battery 30b, and a terminal 13b connected to the negative terminal 31n of the battery 30c.

[0065] FIG. 3(C2) shows an equivalent circuit of the battery unit 20a. The semiconductor device 10a is connected in parallel to the battery 30b, and can monitor the voltage V2 of the battery 30b. On the other hand, the semiconductor device 10b is connected in parallel to the battery 30c, and can monitor the voltage V3 of the battery 30b. Here, the voltage of the battery 30a (voltage V1) is calculated by multiplying the voltage V of the three batteries connected in series by V2. U It can be estimated by subtracting voltage V2 and voltage V3 from

[0066] 3(D1) shows a battery unit 20b having three batteries, the connection method of which is different from that of the battery unit 20a. The battery unit 20b has a semiconductor device 10c and a semiconductor device 10d.

[0067] The semiconductor device 10c is fixed so as to traverse the exterior bodies of the batteries 30a and 30b, while the semiconductor device 10d is fixed so as to traverse the exterior bodies of the batteries 30a, 30b, and 30c.

[0068] In the semiconductor device 10c, the terminal 13a is connected to the negative terminal 31n of the battery 30a, and the terminal 13b is connected to the negative terminal 31n of the battery 30b. In the semiconductor device 10d, the terminal 13a is connected to the negative terminal 31n of the battery 30a, and the terminal 13b is connected to the negative terminal 31n of the battery 30c.

[0069] FIG. 3(D2) shows an equivalent circuit of the battery unit 20b. The semiconductor device 10c is connected in parallel to the battery 30b, and can monitor the voltage V2 of the battery 30b. Meanwhile, the semiconductor device 10d is connected in parallel to the series-connected batteries 30b and 30c, and can monitor the sum (V2+V3) of the voltage V2 of the battery 30b and the voltage V3 of the battery 30c. The voltage V3 of the battery 30c can be estimated by subtracting the voltage V2 monitored by the semiconductor device 10c from the voltage (V2+V3) monitored by the semiconductor device 10d. Also, the voltage of the battery 30a (voltage V1) is calculated by subtracting the voltage V2 of the three series-connected batteries from the voltage V3 of the three series-connected batteries. U It can be estimated by subtracting the voltage (V2+V3) monitored in the semiconductor device 10d from

[0070] The battery unit shown here can monitor the voltage of each battery using a semiconductor device and output the voltage to the outside via wireless communication. Therefore, even in a battery module having multiple battery units, the state of each battery can be managed. In addition, since a battery having an abnormality can be identified, it is possible to replace the battery unit, thereby reducing the maintenance cost of the battery module.

[0071] [Battery module configuration example 1] A configuration example of a battery module including a semiconductor device of one embodiment of the present invention, a battery, and a control device that controls the battery will be described below.

[0072] 4(A) is a block diagram showing the configuration of a battery module 20M. The battery module 20M has a plurality of battery units 20 and a control device 40. The control device 40 can wirelessly communicate with each battery unit 20 individually.

[0073] 4(B) shows a more specific block diagram of the battery module 20M. For simplicity, the block diagram shows one battery unit 20 having one semiconductor device 10 and one battery 30, and one control device 40.

[0074] The semiconductor device 10 includes a first circuit 50 and a second circuit 60. The first circuit 50 includes a voltage detection circuit 51 and an AD conversion circuit 55a. The second circuit 60 includes a control unit 61, a wireless communication unit 62, and an antenna 63.

[0075] The voltage detection circuit 51 is a circuit that detects the voltage of the battery 30, and outputs the detection signal as an analog signal to the AD conversion circuit 55a. The AD conversion circuit 55a converts the input analog signal into a digital signal and outputs it to the control unit 61 of the second circuit 60.

[0076] The control unit 61 has a circuit for analyzing and processing the input signal. The control unit 61 may have, for example, an arithmetic circuit, a logic circuit, a memory circuit, etc. Furthermore, the memory circuit of the control unit 61 may store a unique number (ID) of the semiconductor device 10.

[0077] The wireless communication unit 62 has a function of demodulating a signal input from the control device 40 via the antenna 63 to generate a demodulated signal, and a function of modulating a signal input from the control unit 61 to generate a signal to be output to the antenna 63. The wireless communication unit 62 can be configured to have analog circuits such as a rectifier circuit, a demodulation circuit, a modulation circuit, an AD conversion circuit, and a DA conversion circuit.

[0078] The control unit 61 controls the first circuit 50 to acquire information on the voltage of the battery 30 in response to a command from the control device 40. The control unit 61 can also generate a signal including the information on the voltage input from the first circuit 50 and output the signal to the wireless communication unit 62.

[0079] The control device 40 includes a control unit 41, a wireless communication unit 42, and an antenna 43. The wireless communication unit 42 has a similar configuration to the wireless communication unit 62 described above.

[0080] The control unit 41 may be provided with a control circuit or the like that realizes a battery management unit (BMU) that performs, based on information input from the battery unit 20, monitoring for overcharging and overdischarging, monitoring for overcurrent, managing the battery degradation state, calculating SOC (State Of Charge: remaining capacity rate), and controlling fault detection.

[0081] In addition to the above, the control unit 41 may have an arithmetic circuit such as a CPU or a GPU, a memory circuit, etc., as a control circuit. In particular, it is preferable to have a product-sum operation circuit having transistors to which an oxide semiconductor is applied.

[0082] The control unit 41 may also have a neural network NN. By executing inference using the neural network NN based on information input from the multiple battery units 20, it is possible to improve the accuracy of abnormality detection of the battery units 20 and the batteries 30 included therein, for example.

[0083] When analog data is used as the information input to the control unit 41, it is preferable that the neural network NN has a function of performing analog calculation. For example, it is preferable that the neural network NN has a product-sum calculation circuit, and the product-sum calculation circuit has a function of performing analog calculation. When the neural network NN has a function of performing analog calculation, it may be possible to reduce the area of ​​the circuit constituting the neural network NN. For example, an analog-digital conversion circuit (AD conversion circuit) may become unnecessary, and the circuit area of ​​the control device 40 may be reduced.

[0084] Although not shown, it is preferable that the control device 40 is connected to the positive and negative terminals of each battery unit 20 and has a function of controlling charging and discharging to and from each battery unit.

[0085] Here, the power supply voltage for driving the semiconductor device 10 may be supplied from a battery 30 to which it is connected. Alternatively, the power supply voltage may be generated from a carrier wave of a wireless signal input from the control device 40. In this case, the second circuit 60 may be configured to include a rectifier circuit, a regulator circuit (constant voltage circuit), a reset circuit, and the like.

[0086] 4C shows an example in which the first circuit 50 further includes a current detection circuit 52 and an AD conversion circuit 55b. The current detection circuit 52 has a function of detecting the current flowing through the battery 30 and outputting the information as an analog signal to the AD conversion circuit 55b.

[0087] 5(A) shows an example in which the first circuit 50 further includes a temperature sensor 53 and an AD conversion circuit 55c. By arranging the temperature sensor 53 in contact with or near the battery 30, the control device 40 can acquire temperature information of each battery unit 20.

[0088] FIG. 5B shows an example in which the first circuit 50 further includes a balancing circuit 54. The balancing circuit 54 is a circuit that transfers electric charge among the multiple batteries 30 and controls the balance of the remaining charge of each battery 30. For example, when a difference in the remaining charge occurs among the multiple batteries 30 in one battery unit 20 due to variations in battery characteristics, the balancing circuit 54 charges and discharges the multiple batteries 30, thereby equalizing the remaining charge. For example, the control device 40 can transmit a command to the battery unit 20 to drive the balancing circuit 54 based on input information such as the voltage of each battery 30.

[0089] Here, in the above, the first circuit 50 is configured to output a digital signal to the control unit 61 using the AD conversion circuit 55a etc., but if the control unit 61 has a function of processing an analog signal, the first circuit 50 may be configured not to include each AD conversion circuit.

[0090] [Battery module configuration example 2] A more specific configuration example of the battery module will be described below.

[0091] [Configuration Example 1] Fig. 6(A) shows an external view of a battery unit 20 having cylindrical batteries 30a and 30b, and a semiconductor device 10. Fig. 6(B) shows an external view of a battery module 20M having six battery units 20.

[0092] In the battery unit 20, two batteries are connected in series by a conductive member 34. Lead wires 33 are respectively joined to the positive terminal of the battery 30a and the negative terminal of the battery 30b. The semiconductor device 10 is fixed so as to be wound around the exterior bodies of the two batteries. The antenna 14 of the semiconductor device 10 is disposed along the side of the battery 30a. Although not shown, the terminal 13a of the semiconductor device 10 is electrically connected to the exterior body of the battery 30a, and the terminal 13b is electrically connected to the exterior body of the battery 30b.

[0093] The battery module 20M includes an exterior body 21a, an exterior body 21b, a printed circuit board 22, an IC 23, an antenna 24, a connector wiring 25, a pair of conductive members (conductive members 26p, 26n), a pair of wirings (wirings 27p, 27n), etc. In Fig. 6(B), only the outlines of the exterior body 21a and the exterior body 21b are indicated by dashed lines.

[0094] The battery module 20M is configured by connecting six battery units 20 in parallel, each of which has two batteries connected in series. The positive terminals 31p of the six batteries 30 on one side are joined to the conductive members 26p by leads 33. The negative terminals 31n of the six batteries 30 on the other side are joined to the conductive members 26n by leads 33. The conductive members 26p and 26n are electrically connected to the wiring 27p and wiring 27n, respectively. The wiring 27p and wiring 27n are taken out to the outside through holes provided in the exterior body 21b.

[0095] An IC 23 is mounted on the printed circuit board 22. The IC 23 corresponds to the control unit 41, wireless communication unit 42, etc. of the control device 40. Note that a plurality of ICs with different functions may be mounted. The printed circuit board 22 and a board (indicated by a dashed line) on which the antenna 24 is provided are connected by a connector wiring 25.

[0096] The antenna 24 is fixed to the exterior body 21 a so as to face the antennas 14 of the battery units 20 .

[0097] [Configuration Example 2] Fig. 7(A) shows an external view of a battery unit 20 having a box-shaped battery 30d and a semiconductor device 10. Fig. 7(B) shows an external view of a battery module 20M having four battery units 20. The battery module 20M shown in Fig. 7(B) has a configuration in which four batteries 30d are connected in series.

[0098] The battery unit 20 is provided with a positive electrode terminal 31p and a negative electrode terminal 31n on the upper part of the exterior body 35. In addition, the positive electrode terminal 31p and the negative electrode terminal 31n are provided with connection terminals 36p and 36n which are threaded, respectively.

[0099] The semiconductor device 10 is fixed so as to traverse the positive electrode terminal 31p and the negative electrode terminal 31n. The antenna 14 of the semiconductor device 10 is located above the battery unit 20. Although not shown, the terminal 13a of the semiconductor device 10 is electrically connected to the positive electrode terminal 31p, and the terminal 13b is electrically connected to the negative electrode terminal 31n.

[0100] 7(B) includes an exterior body 21a, an exterior body 21b, a printed circuit board 22, an IC 23, an antenna 24, a connector wiring 25, a conductive member 26, wiring 27p, wiring 27n, etc. The conductive member 26 is screwed to connection terminals of two batteries 30d with different polarities to electrically connect them. The wiring 27p and wiring 27n are screwed to the connection terminals of the batteries 30d and electrically connected thereto.

[0101] The board on which the antenna 24 is provided is provided on the exterior body 21b side so as to face the antennas 14 of the four battery units 20. The board on which the antenna 24 is provided is electrically connected to the printed circuit board 22 via a connector wiring 25.

[0102] The battery module 20M shown in FIG. 7(B) can have a large capacity per battery unit 20, and therefore can be suitably used in stationary power storage devices such as home power storage equipment and uninterruptible power supplies, or in automobiles such as electric vehicles and hybrid vehicles.

[0103] [Configuration example 2 of semiconductor device] A more specific configuration example of the semiconductor device 10 and an example of a manufacturing method thereof will be described below with reference to the drawings.

[0104] [Configuration example] Fig. 8(A) shows a schematic cross-sectional view of the semiconductor device 10 shown in Fig. 2. Fig. 8(A) shows a schematic cross-sectional view of a region including the connection portion 15 of the semiconductor device 10, a region including the first circuit 50, and a region including the second circuit 60. Fig. 8(A) shows an example in which a transistor 80a and a transistor 80b are provided as the first circuit 50 and the second circuit 60, respectively.

[0105] The semiconductor device 10 illustrated in Fig. 8(A) includes a substrate 11, a substrate 17, a transistor 80a, a transistor 80b, a plurality of conductive layers 88, a conductive layer 89, etc. It further includes an insulating layer 91, an insulating layer 92, an insulating layer 93, a protective layer 16, an adhesive layer 90, etc. Note that the configuration in Fig. 8(A) excluding the substrate 17 corresponds to the semiconductor device 10 illustrated in Fig. 1(C).

[0106] Each of the conductive layers 88 functions as a terminal (external connection terminal) and corresponds to the terminal 13a or the terminal 13b in Fig. 2 etc. The conductive layer 89 functions as an antenna and corresponds to the antenna 14 in Fig. 2 etc.

[0107] The substrate 11 is attached to one surface of an insulating layer 91 via an adhesive layer 90. The transistors 80a, 80b, etc. are provided on the other surface of the insulating layer 91. In addition, an insulating layer 93 is provided to cover the transistors 80a, 80b, etc.

[0108] Each of the transistors 80a and 80b includes a semiconductor layer 81, an insulating layer 82 functioning as a gate insulating layer, a conductive layer 83 functioning as a gate electrode, and a pair of conductive layers (conductive layer 84a and conductive layer 84b) functioning as a source electrode and a drain electrode.

[0109] 8A are so-called top-gate transistors each having a gate electrode over a semiconductor layer 81. A portion of the semiconductor layer 81 overlapping with the conductive layer 83 functions as a channel formation region. A portion of the semiconductor layer 81 in contact with the conductive layer 84a or the conductive layer 84b functions as a low-resistance region.

[0110] The conductive layer 89 functioning as an antenna is provided over the insulating layer 93. The conductive layer 89 is electrically connected to the conductive layer 84b of the transistor 80b through an opening provided in the insulating layer 93.

[0111] The conductive layer 88 functioning as a terminal is provided on the back side of the substrate 11. At the connection portion 15, the conductive layer 84c and the conductive layer 88 are electrically connected. The conductive layer 84c is a wiring obtained by processing the same conductive film as the conductive layer 84a, etc. Furthermore, a portion of the conductive layer 84c that is provided to cover the openings provided in the insulating layer 92 and the insulating layer 91 functions as a contact surface with the conductive layer 88. Furthermore, in a region overlapping with the contact surface of the conductive layer 84c, the adhesive layer 90 and the substrate 11 are partially opened, and the conductive layer 88 is electrically connected to the conductive layer 84c through the opening.

[0112] 8A, the stacked structure from the insulating layer 91 to the insulating layer 93 corresponds to the element layer 12. The semiconductor device 10 has a structure in which a conductive layer 89 functioning as an antenna is provided on one side of the element layer 12, and a conductive layer 88 functioning as a terminal is provided on the other side. By providing the terminal and the antenna back to back, the semiconductor device 10 can be easily miniaturized and the response of wireless communication can be significantly improved compared to the case in which they are provided on the same side.

[0113] Furthermore, by using a flexible substrate as the substrate 11, the semiconductor device 10 can be attached along the curved surface of the object to be detected. This increases the degree of freedom in the shape of the object to be detected and the position where the semiconductor device 10 is attached, thereby improving convenience and versatility. In addition, since it is easy to reduce the weight of the semiconductor device 10 itself, it is also suitable for mobile applications and bioinformation terminal devices.

[0114] FIG. 8B shows an example in which the configurations of the transistors 80a and 80b are different from those in FIG. 8A.

[0115] The transistor 80a and the transistor 80b each have an insulating layer 86 between the semiconductor layer 81 and the insulating layer 91. In addition, a conductive layer 85 overlapping with the semiconductor layer 81 and the conductive layer 83 is provided between the insulating layer 86 and the insulating layer 91. The conductive layer 85 functions as a second gate electrode, and a part of the insulating layer 86 functions as a second gate insulating layer.

[0116] For example, by applying a predetermined potential to one gate electrode, the threshold voltage when the transistor is driven by the other gate electrode can be controlled. In addition, by applying the same potential to a pair of gate electrodes to drive the transistor, the current that the transistor can pass (also called on-current) can be increased.

[0117] At the connection portion 15, a conductive layer 85a obtained by processing the same conductive film as the conductive layer 85 is electrically connected to the conductive layer 88. The conductive layer 85a is electrically connected to the conductive layer 84c through openings provided in the insulating layer 86 and the insulating layer 92.

[0118] In the transistor 80a and the transistor 80b illustrated in FIGS. 8A and 8B, a semiconductor layer 81 in which a channel is formed can be formed using a semiconductor material such as silicon, germanium, or an oxide semiconductor.

[0119] Although amorphous silicon may be used as the silicon, it is preferable to use crystalline silicon such as single crystal silicon or polycrystalline silicon, since this makes it possible to provide a transistor with high reliability and capable of passing a large current.

[0120] In particular, it is preferable to use a transistor using an oxide semiconductor (a metal oxide having semiconductor characteristics) for the transistor 80a and the transistor 80b. In particular, when an oxide semiconductor having crystallinity is used, a transistor having high reliability and high field-effect mobility can be obtained. In particular, when an oxide semiconductor with a sufficiently reduced carrier concentration is used, a transistor having an extremely low leakage current (off-state current) in an off state can be realized, which is preferable because the standby power of the semiconductor device 10 can be reduced.

[0121] [Example of manufacturing method] In the following, as an example of a method for manufacturing a semiconductor device, the semiconductor device 10 shown in FIG. 8B will be described as an example.

[0122] Each of the drawings shown in FIGS. 9 to 12 is a schematic cross-sectional view at each step in the manufacturing method described below.

[0123] The thin films (insulating film, semiconductor film, conductive film, etc.) constituting the semiconductor device can be formed by using a sputtering method, a chemical vapor deposition (CVD) method, a vacuum deposition method, a pulsed laser deposition (PLD) method, an atomic layer deposition (ALD) method, etc. Examples of the CVD method include a plasma enhanced chemical vapor deposition (PECVD) method and a thermal CVD method. Another type of thermal CVD method is a metal organic chemical vapor deposition (MOCVD) method.

[0124] Furthermore, thin films (insulating films, semiconductor films, conductive films, etc.) constituting the semiconductor device can be formed by methods such as spin coating, dipping, spray coating, inkjet, dispensing, screen printing, offset printing, doctor knife, slit coating, roll coating, curtain coating, and knife coating.

[0125] Furthermore, when processing the thin film constituting the semiconductor device, it can be processed using a photolithography method or the like. Alternatively, the thin film may be processed using a nanoimprint method, a sandblasting method, a lift-off method or the like. Furthermore, an island-shaped thin film may be directly formed by a film formation method using a shielding mask.

[0126] There are two typical photolithography methods. One is a method in which a resist mask is formed on the thin film to be processed, the thin film is processed by etching or the like, and the resist mask is then removed. The other is a method in which a photosensitive thin film is formed, and then exposed and developed to process the thin film into the desired shape.

[0127] In the photolithography method, the light used for exposure may be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these. In addition, ultraviolet light, KrF laser light, ArF laser light, or the like may be used. Exposure may also be performed by immersion exposure technology. Extreme ultraviolet light (EUV: Extreme Ultra-violet) or X-rays may also be used as the light used for exposure. An electron beam may also be used instead of the light used for exposure. Extreme ultraviolet light, X-rays, or an electron beam are preferable because they enable extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, a photomask is not required.

[0128] For etching the thin film, a dry etching method, a wet etching method, a sandblasting method, or the like can be used.

[0129] First, a support substrate 71 is prepared, and a release layer 72 and an insulating layer 91 are laminated on the support substrate 71 (FIG. 9(A)).

[0130] The support substrate 71 may be a substrate having sufficient rigidity to be easily transported within or between devices. In addition, a substrate having heat resistance to the heat applied during the manufacturing process may be used. For example, a semiconductor substrate, a metal substrate, or an insulating substrate such as a glass substrate may be used. For example, a glass substrate having a thickness of 0.3 mm or more and 1 mm or less may be used.

[0131] Materials used for the release layer 72 and the insulating layer 91 can be selected such that peeling occurs at the interface between the release layer 72 and the insulating layer 91 or within the release layer 72 .

[0132] For example, a layer containing a high-melting point metal material such as tungsten and a layer containing an oxide of the metal material can be stacked as the peeling layer 72, and a layer of an inorganic insulating material such as silicon nitride, silicon oxide, silicon oxynitride, or silicon nitride oxide can be stacked as the insulating layer 91. When a high-melting point metal material is used for the peeling layer 72, it is possible to perform a treatment at a high temperature in the subsequent steps, and therefore the freedom of selection of materials and formation methods is increased, which is preferable.

[0133] When a laminated structure of tungsten and tungsten oxide is used as the peeling layer 72, peeling can occur at the interface between tungsten and tungsten oxide, in the tungsten oxide, or at the interface between the tungsten oxide and the insulating layer 91.

[0134] Alternatively, an organic resin may be used as the peeling layer 72 , and peeling may occur at the interface between the support substrate 71 and the peeling layer 72 , in the peeling layer 72 , or at the interface between the peeling layer 72 and the insulating layer 91 .

[0135] Typically, polyimide resin can be used as the release layer 72. Polyimide resin is preferable because of its excellent heat resistance. In addition, acrylic resin, epoxy resin, polyamide resin, polyimideamide resin, siloxane resin, benzocyclobutene resin, phenol resin, etc. can be used as the release layer 72.

[0136] The release layer 72 containing an organic resin is formed by first forming a mixed material of a resin precursor and a solvent on the support substrate 71 by a method such as spin coating, dipping, spray coating, inkjet, dispensing, screen printing, offset printing, doctor knife, slit coating, roll coating, curtain coating, knife coating, etc. Then, a heat treatment is performed to harden the material while removing the solvent, thereby forming the release layer 72 containing an organic resin.

[0137] For example, when polyimide is used for the release layer 72, a resin precursor that generates imide bonds upon dehydration can be used, or a material containing a soluble polyimide resin can be used.

[0138] When an organic resin is used for the peeling layer 72, either a photosensitive or non-photosensitive resin may be used. Photosensitive polyimide is a material that is preferably used for a planarizing film or the like, and therefore a forming device and material can be shared. Therefore, no new device or material is required to realize the configuration of one embodiment of the present invention. In addition, by using a photosensitive resin material, it is possible to process the peeling layer 72 by performing exposure and development processing. For example, it is possible to form an opening or remove unnecessary parts. Furthermore, it is possible to form an uneven shape on the surface by optimizing the exposure method and exposure conditions. For example, a multiple exposure technique or an exposure technique using a halftone mask or a graytone mask may be used.

[0139] When an organic resin is used for the peeling layer 72, the peeling property may be improved by locally heating the peeling layer 72. For example, a heating method may be irradiating with laser light. In this case, it is preferable to use a linear laser as the laser light and irradiate the laser light by scanning the laser light. This makes it possible to shorten the process time when the area of ​​the support substrate is increased. As the laser light, an excimer laser with a wavelength of 308 nm can be suitably used.

[0140] When the peelability is improved by irradiating light such as laser light, a heat generating layer may be provided overlapping the peeling layer 72. The heat generating layer is a layer having a function of absorbing light and generating heat. The heat generating layer is preferably provided between the support substrate 71 and the peeling layer 72, but may be disposed on the peeling layer 72. The heat generating layer may be made of a material capable of absorbing a part of the light used for the laser light or the like. For example, when a 308 nm excimer laser is used as the laser light, the heat generating layer may be made of a metal or an oxide. For example, a metal such as titanium or tungsten, an oxide conductor material such as titanium oxide, tungsten oxide, indium oxide, or indium tin oxide, or an oxide semiconductor material containing indium, or the like may be used.

[0141] Further, a layer containing oxygen, hydrogen, water, or the like may be provided in contact with the peeling layer 72, and oxygen, hydrogen, water, or the like may be supplied into the peeling layer 72 or to the interface between the peeling layer 72 and the layer by heat treatment, thereby improving the peelability. Alternatively, oxygen, hydrogen, water, or the like may be supplied to the supporting substrate 71. Alternatively, oxygen, hydrogen, water, or the like may be supplied to the peeling layer 72. By performing heat treatment or plasma treatment in an atmosphere containing oxygen, hydrogen, water, or the like, these can be supplied to the supporting substrate 71 or the peeling layer 72. This eliminates the need for a laser device or the like, and allows a semiconductor device to be manufactured at lower cost.

[0142] In addition, a part of the peeling layer 72 may remain after peeling. If the remaining peeling layer 72 has conductivity, it is preferable to remove it by etching since there is a risk of causing an electrical short circuit. Note that the peeling layer 72 may be left as it is.

[0143] Subsequently, a portion of the insulating layer 91 is removed by etching to expose the release layer 72 (FIG. 9(B)).

[0144] Subsequently, a conductive film 85f is formed on the insulating layer 91 (FIG. 9C). A part of the conductive film 85f is provided so as to cover the opening provided in the insulating layer 91.

[0145] Next, the conductive film 85f is processed to form the conductive layer 85 and the conductive layer 85a (FIG. 9(D)). The conductive layer 85 and the conductive layer 85a can be formed by forming a resist mask over the conductive film 85f, etching a part of the conductive film 85f, and then removing the resist mask.

[0146] Subsequently, insulating layer 86 is formed to cover insulating layer 91, conductive layer 85, and conductive layer 85a (FIG. 9(E)).

[0147] Next, the semiconductor layer 81 is formed on the insulating layer 86 (FIG. 9(F)). The semiconductor layer 81 can be formed by forming a semiconductor film (not shown) on the insulating layer 86, forming a resist mask on the semiconductor film, removing a part of the semiconductor film by etching, and then removing the resist mask.

[0148] Subsequently, an insulating layer 82 and a conductive layer 83 are formed on the semiconductor layer 81 (FIG. 10(A)). The insulating layer 82 and the conductive layer 83 can be formed, for example, by laminating an insulating film and a conductive film to cover the semiconductor layer 81, forming a resist mask on the conductive film, and etching the conductive film and the insulating film using the resist mask. This makes it possible to form the insulating layer 82 and the conductive layer 83 whose top surface shapes are approximately the same.

[0149] In this specification, the phrase "top surface shapes roughly match" refers to at least a portion of the contours of stacked layers overlapping. For example, this includes cases where the upper and lower layers are processed using the same mask pattern, or where a portion of the mask pattern is the same. However, strictly speaking, the contours may not overlap, and the upper layer may be located inside the lower layer, or outside the lower layer, and in this case, it is also called "top surface shapes roughly match."

[0150] Note that a structure may be adopted in which only the conductive film that becomes the conductive layer 83 is etched, and the insulating film that becomes the insulating layer 82 is not etched. In this case, for example, the insulating layer 82 is provided over the entire substrate, covering the end portion of the semiconductor layer 81 and the insulating layer 86.

[0151] Next, an insulating layer 92 is formed to cover the insulating layer 86, the semiconductor layer 81, the insulating layer 82, the conductive layer 83, etc. (FIG. 10(B)). Then, a part of the insulating layer 92 is etched to form an opening that reaches the semiconductor layer 81. At the same time, a part of the insulating layer 92 and the insulating layer 86 located on the conductive layer 85a is etched to form an opening that reaches the conductive layer 85a.

[0152] Subsequently, a conductive film is formed and a part of it is removed by etching to form conductive layers 84a, 84b, 84c, and the like (FIG. 10C).

[0153] At this stage, transistor 80a and transistor 80b can be formed.

[0154] Next, an insulating layer 93 is formed to cover the transistors 80a and 80b and to have an opening that reaches the conductive layer 84b of the transistor 80b (FIG. 10(D)). By using a photosensitive material for the insulating layer 93, the opening can be formed by a photolithography method or the like. In particular, it is preferable to use an organic insulating film for the insulating layer 93 because the flatness of the surface is improved. Note that after forming the insulating layer 93 without an opening, an opening may be formed in the insulating layer 93 by etching using a resist mask.

[0155] Subsequently, a conductive layer 89 is formed in contact with the conductive layer 84b through the opening in the insulating layer 93. The conductive layer 89 can be formed by the same method as the conductive layer 83 and the like.

[0156] Next, a substrate 17 is attached via a protective layer 16 that functions as an adhesive layer (FIG. 11(A)). A curable organic resin is preferably used as the protective layer 16. A flexible material is preferably used as the substrate 17.

[0157] It is also possible to provide only the protective layer 16 and not have the substrate 17 .

[0158] Next, the insulating layer 91 and the conductive layer 85a are peeled off from the peeling layer 72, thereby removing the support substrate 71 and the peeling layer 72 (FIG. 11(B)).

[0159] Examples of the peeling method include applying a mechanical force, etching the peeling layer, or dripping or impregnating a liquid into the peeling interface, etc. Alternatively, the peeling may be performed by heating or cooling, utilizing the difference in thermal expansion coefficient between the two layers that form the peeling interface.

[0160] Also, a heat treatment may be performed to improve the peelability. The heat treatment can be performed at any time after the insulating layer 91 is formed, but is preferably performed immediately before peeling. If a method capable of instantaneous and localized heating, such as laser annealing or lamp annealing, is used as the heat treatment, it is possible to suppress deterioration of the transistors, wiring, and the like due to heat.

[0161] Furthermore, before peeling, a process for exposing a part of the peeling interface may be performed. For example, a laser or a sharp member is used to remove a part of the insulating layer 91 on the peeling layer 72. This allows peeling to proceed from the part from which the insulating layer 91 has been removed as the starting point (starting point).

[0162] After the peeling is completed, a part of the peeling layer 72 may remain. In that case, it is preferable to remove the remaining peeling layer 72 by cleaning, etching, plasma treatment, wiping treatment, or the like. In particular, when the peeling layer 72 has conductivity, it is preferable to remove it. In addition, in order to prevent the surface of the conductive layer 85a from being insulated due to oxidation or the like, it is preferable to perform a reduction treatment after removing the peeling layer 72.

[0163] FIG. 11C shows a state in which the support substrate 71 and the release layer 72 have been removed and part of the conductive layer 85a is exposed.

[0164] Next, the insulating layer 91 and the substrate 11 are bonded together by the adhesive layer 90 (FIG. 12(A)). At this time, it is preferable to use a substrate having a cut or opening in the portion that overlaps with the exposed portion of the conductive layer 85a as the substrate 11. It is also preferable to form the adhesive layer 90 so that it does not adhere to the exposed portion of the conductive layer 85a.

[0165] Thereafter, a conductive layer 88 is formed on the back surface of the substrate 11 so as to be in contact with the conductive layer 85a (FIG. 12(B)).

[0166] Through the above steps, it is possible to manufacture the semiconductor device 10. The diagram shown in Figure 12(B) is the same as Figure 8(B).

[0167] The above is a description of an example of a method for manufacturing the semiconductor device 10.

[0168] [Note] In this specification, etc., a transistor is an element having at least three terminals including a gate, a drain, and a source. A channel-forming region is formed between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), and a current can flow between the source and the drain through the channel-forming region. In this specification, etc., the channel-forming region refers to a region through which a current mainly flows.

[0169] In addition, the functions of the source and drain may be interchanged when transistors of different polarities are used, when the direction of current changes during circuit operation, etc. For this reason, in this specification and the like, the terms source and drain may be used interchangeably.

[0170] In addition, in this specification, "electrical connection" includes a case where a connection is made via "something having some electrical action." Here, "something having some electrical action" is not particularly limited as long as it enables transmission and reception of an electrical signal between the connection objects. For example, "something having some electrical action" includes electrodes and wiring, as well as switching elements such as transistors, resistive elements, inductors, capacitors, and other elements having various functions.

[0171] In addition, in this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it also includes cases where the angle is -5° or more and 5° or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes cases where the angle is 85° or more and 95° or less.

[0172] In addition, in this specification and the like, the term "film" and the term "layer" can be interchanged. For example, the term "conductive layer" may be changed to the term "conductive film." Or, for example, the term "insulating film" may be changed to the term "insulating layer."

[0173] In this specification and the like, unless otherwise specified, the off-state current refers to the drain current when a transistor is in an off state (also referred to as a non-conducting state or a cut-off state). Unless otherwise specified, the off-state refers to a state in which the voltage Vgs between the gate and the source is lower than the threshold voltage Vth in an n-channel transistor, and a state in which the voltage Vgs between the gate and the source is higher than the threshold voltage Vth in a p-channel transistor.

[0174] The off-state current of a transistor may depend on Vgs. Thus, the off-state current of a transistor being I or less may refer to the existence of a value of Vgs at which the off-state current of the transistor is I or less. The off-state current of a transistor may refer to an off-state at a predetermined Vgs, an off-state at a Vgs within a predetermined range, or an off-state at a Vgs at which a sufficiently reduced off-state current is obtained, etc.

[0175] As an example, when the threshold voltage Vth is 0.5 V and Vgs is 0.5 V, the drain current is 1×10 -9 A, and the drain current at Vgs of 0.1 V is 1×10 -13 A, and the drain current at Vgs -0.5 V is 1×10 -19 A, and the drain current at Vgs -0.8 V is 1 × 10-22 Assume an n-channel transistor with a drain current of 1×10 A at Vgs of −0.5 V or in the range of Vgs from −0.5 V to −0.8 V. -19 A or less, the off-current of the transistor is 1×10 -19 A is sometimes called a drain current of 1×10 A or less. -22 Since there exists a Vgs below A, the off-state current of the transistor is 1×10 -22 It may be said that it is below A.

[0176] In this specification and the like, the off-current of a transistor having a channel width W may be expressed as a current value flowing per channel width W. Also, it may be expressed as a current value flowing per a predetermined channel width (e.g., 1 μm). In the latter case, the unit of the off-current may be expressed in a unit having the dimension of current / length (e.g., A / μm).

[0177] The off-current of a transistor may depend on temperature. In this specification, unless otherwise specified, the off-current may refer to the off-current at room temperature, 60° C., 85° C., 95° C., or 125° C. Alternatively, the off-current may refer to the off-current at a temperature at which the reliability of a semiconductor device including the transistor is ensured, or at a temperature at which a semiconductor device including the transistor is used (for example, any one of temperatures from 5° C. to 35° C.). The off-current of a transistor being I or less may refer to the presence of a value of Vgs at which the off-current of the transistor is I or less at room temperature, 60° C., 85° C., 95° C., 125° C., the temperature at which the reliability of a semiconductor device including the transistor is ensured, or the temperature at which a semiconductor device including the transistor is used (for example, any one of temperatures from 5° C. to 35° C.).

[0178] The off-current of a transistor may depend on the voltage Vds between the drain and the source. In this specification, unless otherwise specified, the off-current may represent the off-current at Vds of 0.1V, 0.8V, 1V, 1.2V, 1.8V, 2.5V, 3V, 3.3V, 10V, 12V, 16V, or 20V. Alternatively, the off-current may represent the off-current at Vds at which the reliability of a semiconductor device including the transistor is guaranteed, or at Vds used in a semiconductor device including the transistor. The off-current of a transistor being I or less may refer to the existence of a value of Vgs at which the off-current of a transistor is I or less at Vds of 0.1V, 0.8V, 1V, 1.2V, 1.8V, 2.5V, 3V, 3.3V, 10V, 12V, 16V, or 20V, at Vds at which the reliability of a semiconductor device including the transistor is guaranteed, or at Vds used in a semiconductor device including the transistor.

[0179] In the above description of the off-state current, the drain may be read as the source, that is, the off-state current may refer to the current that flows through the source when the transistor is in the off state.

[0180] In this specification, the term "leakage current" may be used to mean the same thing as "off-state current." In this specification, the term "off-state current" may refer to, for example, a current that flows between a source and a drain when a transistor is in an off state.

[0181] In this specification and the like, the threshold voltage of a transistor refers to the gate voltage (Vg) when a channel is formed in the transistor. Specifically, the threshold voltage of a transistor may refer to the gate voltage (Vg) at the intersection point between a straight line obtained by extrapolating a tangent with a maximum slope in a curve (Vg-√Id characteristics) in which the gate voltage (Vg) is plotted on the horizontal axis and the square root of the drain current (Id) is plotted on the vertical axis, and the straight line is obtained when the square root of the drain current (Id) is 0 (Id is 0 A). Alternatively, the threshold voltage of a transistor may refer to a value of Id[A]×L[μm] / W[μm], where L is the channel length and W is the channel width, and the value of Id[A]×L[μm] / W[μm] is 1×10-9 It may also refer to the gate voltage (Vg) at which [A] is reached.

[0182] In addition, even when a material is described as a "semiconductor" in this specification, for example, if the electrical conductivity is sufficiently low, the material may have the characteristics of an "insulator." Furthermore, the boundary between a "semiconductor" and an "insulator" is unclear, and they may not be strictly distinguishable from each other. Therefore, the "semiconductor" and the "insulator" described in this specification may be interchangeable.

[0183] In addition, even when a material is described as a "semiconductor" in this specification, for example, if the electrical conductivity is sufficiently high, the material may have the characteristics of a "conductor." Furthermore, the boundary between a "semiconductor" and a "conductor" is unclear, and they may not be strictly distinguishable from each other. Therefore, the "semiconductor" and the "conductor" described in this specification may be interchangeable.

[0184] In the present specification, the atomic ratio of In:Ga:Zn=4:2:3 or thereabout means that, when the ratio of In to the sum of the numbers of In, Ga, and Zn atoms is 4, the ratio of Ga is 1 or more and 3 or less, and the ratio of Zn is 2 or more and 4 or less. In addition, the atomic ratio of In:Ga:Zn=5:1:6 or thereabout means that, when the ratio of In to the sum of the numbers of In, Ga, and Zn atoms is 5, the ratio of Ga is greater than 0.1 and 2 or less, and the ratio of Zn is 5 or more and 7 or less. In addition, the atomic ratio of In:Ga:Zn=1:1:1 or thereabout means that, when the ratio of In to the sum of the numbers of In, Ga, and Zn atoms is 1, the ratio of Ga is greater than 0.1 and 2 or less, and the ratio of Zn is greater than 0.1 and 2 or less.

[0185] In this specification and the like, the term "metal oxide" refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply OS), and the like. For example, when a metal oxide is used in an active layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. In addition, when the term "OS FET" is used, it can be rephrased as a transistor having a metal oxide or an oxide semiconductor.

[0186] In this specification and the like, nitrogen-containing metal oxides may also be collectively referred to as metal oxides. Nitrogen-containing metal oxides may also be referred to as metal oxynitrides.

[0187] In addition, in this specification, etc., it may be described as CAAC (c-axis aligned crystal) and CAC (Cloud-Aligned Composite). Note that CAAC represents an example of a crystal structure, and CAC represents an example of a function or material configuration.

[0188] In addition, in this specification and the like, CAC-OS or CAC-metal oxide has a conductive function in a part of the material and an insulating function in a part of the material, and has a function as a semiconductor in the whole material. When CAC-OS or CAC-metal oxide is used in an active layer of a transistor, the conductive function is a function of flowing electrons (or holes) as carriers, and the insulating function is a function of not flowing electrons as carriers. By making the conductive function and the insulating function act complementarily, a switching function (on / off function) can be imparted to CAC-OS or CAC-metal oxide. By separating the respective functions in CAC-OS or CAC-metal oxide, both functions can be maximized.

[0189] In the present specification and the like, the CAC-OS or CAC-metal oxide has a conductive region and an insulating region. The conductive region has the above-mentioned conductive function, and the insulating region has the above-mentioned insulating function. In addition, in the material, the conductive region and the insulating region may be separated at the nanoparticle level. In addition, the conductive region and the insulating region may be unevenly distributed in the material. In addition, the conductive region may be observed to be connected in a cloud shape with a blurred periphery.

[0190] In addition, in the CAC-OS or CAC-metal oxide, the conductive regions and the insulating regions may each be dispersed in the material with a size of 0.5 nm to 10 nm, preferably 0.5 nm to 3 nm.

[0191] Also, the CAC-OS or CAC-metal oxide is composed of components having different band gaps. For example, the CAC-OS or CAC-metal oxide is composed of a component having a wide gap due to an insulating region and a component having a narrow gap due to a conductive region. In this configuration, when carriers are caused to flow, the carriers mainly flow in the component having the narrow gap. Also, the component having the narrow gap acts complementarily on the component having the wide gap, and carriers also flow in the component having the wide gap in conjunction with the component having the narrow gap. Therefore, when the above CAC-OS or CAC-metal oxide is used in the channel region of a transistor, a high current driving force, that is, a large on-current and a high field effect mobility can be obtained in the on-state of the transistor.

[0192] That is, CAC-OS or CAC-metal oxide can also be called a matrix composite or a metal matrix composite.

[0193] An example of the crystal structure of a metal oxide will be described. In the following, a metal oxide formed by sputtering using an In-Ga-Zn oxide target (In:Ga:Zn=4:2:4.1 [atomic ratio]) will be described as an example. A metal oxide formed by sputtering using the above target at a substrate temperature of 100°C to 130°C will be called sIGZO, and a metal oxide formed by sputtering using the above target at a substrate temperature of room temperature (RT) will be called tIGZO. For example, sIGZO has either one or both of the crystal structures of nc (nano crystal) and CAAC. Also, tIGZO has the crystal structure of nc. Note that room temperature (RT) here includes the temperature when the substrate is not intentionally heated.

[0194] The CAAC structure is one of the crystal structures of thin films having multiple nanocrystals (crystal regions with a maximum diameter of less than 10 nm), and each nanocrystal has a c-axis oriented in a specific direction, and the a-axis and b-axis have no orientation, and the nanocrystals are continuously connected to each other without forming grain boundaries. In particular, thin films having a CAAC structure have a characteristic that the c-axis of each nanocrystal is likely to be oriented in the thickness direction of the thin film, the normal direction of the surface on which it is formed, or the normal direction of the thin film surface.

[0195] Here, in crystallography, it is common to take a unit cell with a specific axis as the c-axis for the three axes (crystal axes) of the a-axis, b-axis, and c-axis that constitute the unit cell. In particular, in a crystal having a layered structure, it is common to take two axes parallel to the plane direction of the layer as the a-axis and b-axis, and an axis intersecting the layer as the c-axis. A representative example of a crystal having such a layered structure is graphite, which is classified as a hexagonal system, and the a-axis and b-axis of the unit cell are parallel to the cleavage plane, and the c-axis is perpendicular to the cleavage plane. For example, a crystal of InGaZnO4 having a YbFe2O4 type crystal structure can be classified as a hexagonal system, and the a-axis and b-axis of the unit cell are parallel to the plane direction of the layer, and the c-axis is perpendicular to the layer (i.e., the a-axis and b-axis).

[0196] At least a part of the configuration examples, manufacturing method examples, and corresponding drawings, etc., illustrated in this embodiment mode can be implemented by appropriately combining with other configuration examples, manufacturing method examples, drawings, etc.

[0197] This embodiment mode can be implemented by appropriately combining at least a part of it with other embodiment modes described in this specification.

[0198] (Embodiment 2) In this embodiment, an example of a control method using a neural network in a battery module of one embodiment of the present invention will be described.

[0199] In this specification, the term "neural network" refers to a general model that imitates the neural circuit network of living organisms, determines the connection strength between neurons through learning, and has problem-solving capabilities. A neural network has an input layer, an intermediate layer (also called a hidden layer), and an output layer.

[0200] Furthermore, in this specification, when discussing neural networks, determining the connection strengths (also called weighting coefficients) between neurons from existing information may be referred to as "learning".

[0201] In this specification, the process of constructing a neural network using the connection weights obtained by learning and deriving a new conclusion therefrom may be referred to as "inference."

[0202] A system using a neural network according to one embodiment of the present invention can be realized, for example, by a circuit using transistors in which an oxide semiconductor or a metal oxide is used for a channel formation region.

[0203] The system using the neural network according to one embodiment of the present invention can be configured with software and hardware. In this case, the hardware may include a memory having a transistor including an oxide semiconductor or a metal oxide in a channel formation region, or may include other known hardware. The operating system of the software may be any of various operating systems such as Windows (registered trademark), UNIX (registered trademark), and macOS (registered trademark). The software application may be written in any of various programming languages ​​such as Python (registered trademark), Go, Perl, Ruby, Prelog, Visual Basic (registered trademark), C, C++, Swift, Java (registered trademark), and .NET. The application may be created using a framework such as Chainer (registered trademark) (available in Python), Caffe (available in Python and C++), or TensorFlow (available in C, C++, and Python).

[0204] The battery module 20M exemplified in the above embodiment can input the parameters of the battery 30 to a neural network in a NN format, and analyze the state of the battery 30.

[0205] In addition to the reversible reactions of charging and discharging, other phenomena that may cause deterioration in the safety of the battery may occur inside the battery. For example, side reactions such as decomposition of the electrolyte, metal deposition on the electrode surface, etc. These phenomena may not only reduce the capacity of the battery, but also reduce the safety of the battery.

[0206] In addition, when a battery is charged or discharged, the temperature may rise, and the charge / discharge characteristics of the battery change depending on the temperature, so it is important to precisely control the battery temperature.

[0207] A battery module according to an embodiment of the present invention can analyze the state of a battery by measuring parameters such as voltage, current, and temperature during charging and discharging of the battery, and can determine the operating conditions of the battery according to the state of the battery. For example, a charge curve or a discharge curve is analyzed. Here, the charge curve refers to the transition of voltage or capacity during the charging process. Also, the discharge curve refers to the transition of voltage or capacity during the discharging process.

[0208] It is preferable to use measurement data related to the battery as input parameters to the neural network. For example, a set of the battery current and voltage can be simultaneously sampled and read at regular intervals, a predetermined number of sets can be stored, and used as input parameters. Alternatively, for example, the time and a set of data of the battery current and voltage at each time can be used as input parameters. Here, the battery voltage is, for example, the potential difference between both ends of the battery.

[0209] In addition, a combination of the battery capacity and voltage can be used as input parameters. The battery capacity can be calculated, for example, by multiplying the battery current by time. The battery capacity can also be calculated using a coulomb counter CC.

[0210] The SOC of the battery may also be used as an input parameter. For example, the SOC of the battery is calculated by subtracting the absolute value of the discharge capacity from the absolute value of the charge capacity of the battery, and expressed as a ratio to the full charge capacity. Alternatively, the SOC of the battery may be estimated from the voltage of the battery.

[0211] In general, when charging and discharging a battery, the voltage changes depending on the magnitude of the current value. For example, the voltage drop due to the resistance of the battery changes depending on the magnitude of the current value. Therefore, the resistance of the battery may be calculated from the relationship between the magnitude of the current value and the voltage. The resistance value calculated in this way may be used as an input parameter.

[0212] Furthermore, the open circuit voltage (OCV) of a battery may be used as an input parameter. The open circuit voltage of a battery is, for example, the potential difference between both ends of a battery when no current flows through the battery. Here, a state in which no current flows through the battery refers, for example, to a state in which no load is applied to the battery and a state in which a charging circuit is not electrically connected to the battery. By comparing the open circuit voltage with the voltage when a significant current flows through the battery, for example, it may be possible to calculate the resistance of the battery.

[0213] A battery module according to one aspect of the present invention has a control device equipped with a pre-trained neural network, and the voltage, current, temperature, or other measured values ​​of the battery for each battery unit are input to the control device via wireless communication. The battery module inputs the information into the neural network and executes inference to identify batteries that are deemed to have abnormal characteristics. Alternatively, by executing inference, optimal charge / discharge control can be executed for each battery unit.

[0214] Below, configuration examples of a neural network and a product-sum calculation circuit that can be used in a battery module of one embodiment of the present invention will be described with reference to the drawings.

[0215] As shown in FIG. 13(A), the neural network NN can be composed of an input layer IL, an output layer OL, and an intermediate layer (hidden layer) HL. The input layer IL, the output layer OL, and the intermediate layer HL each have one or more neurons (units). The intermediate layer HL may be one layer or two or more layers. A neural network having two or more intermediate layers HL may be called a DNN (deep neural network), and learning using a deep neural network may be called deep learning.

[0216] Input data is input to each neuron in the input layer IL, an output signal of a neuron in the previous or next layer is input to each neuron in the hidden layer HL, and an output signal of a neuron in the previous layer is input to each neuron in the output layer OL. Each neuron may be connected to all neurons in the previous or next layer (full connection), or may be connected to only a portion of the neurons.

[0217] FIG. 13(B) shows an example of a computation by a neuron. Here, neuron N and two neurons in the previous layer that output signals to neuron N are shown. Neuron N receives the output x1 of a neuron in the previous layer and the output x2 of a neuron in the previous layer. Neuron N then calculates the sum x1w1+x2w2 of the multiplication result (x1w1) of the output x1 and the weight w1 and the multiplication result (x2w2) of the output x2 and the weight w2, and then adds a bias b as necessary to obtain a value a=x1w1+x2w2+b. The value a is then transformed by the activation function h, and neuron N outputs an output signal y=h(a).

[0218] In this way, the calculations performed by neurons include an operation of adding up the product of the output of a neuron in the previous layer and the weight, that is, a product-sum calculation (x1w1+x2w2 above). This product-sum calculation may be performed on software using a program, or it may be performed by hardware. When the product-sum calculation is performed by hardware, a product-sum calculation circuit can be used. As this product-sum calculation circuit, a digital circuit or an analog circuit may be used. When an analog circuit is used for the product-sum calculation circuit, it is possible to reduce the circuit scale of the product-sum calculation circuit, or to reduce the number of memory accesses, thereby improving the processing speed and reducing power consumption.

[0219] The product-sum operation circuit may be formed using transistors including silicon (such as single crystal silicon) in a channel formation region (hereinafter also referred to as Si transistors) or transistors including an oxide semiconductor in a channel formation region (hereinafter also referred to as OS transistors). In particular, OS transistors have an extremely small off-state current and are therefore suitable as transistors that constitute the memory of the product-sum operation circuit. Note that the product-sum operation circuit may be formed using both Si transistors and OS transistors. Hereinafter, a configuration example of a semiconductor device having the function of a product-sum operation circuit will be described.

[0220] <Example of semiconductor device configuration> 14 shows a configuration example of a semiconductor device MAC having a function of performing neural network calculations. The semiconductor device MAC has a function of performing a product-sum calculation of first data corresponding to the connection strength (weight) between neurons and second data corresponding to input data. The first data and the second data can be analog data or multi-valued digital data (discrete data). The semiconductor device MAC also has a function of converting the data obtained by the product-sum calculation using an activation function.

[0221] The semiconductor device MAC includes a cell array CA, a current source circuit CS, a current mirror circuit CM, a circuit WDD, a circuit WLD, a circuit CLD, an offset circuit OFST, and an activation function circuit ACTV.

[0222] The cell array CA has a plurality of memory cells MC and a plurality of memory cells MCref. FIG. 14 shows a configuration example in which the cell array CA has m rows and n columns (m and n are integers equal to or greater than 1) of memory cells MC (MC[1,1] to [m,n]) and m memory cells MCref (MCref[1] to [m]). The memory cells MC have a function of storing first data. The memory cells MCref also have a function of storing reference data used in a product-sum operation. The reference data can be analog data or multi-valued digital data.

[0223] Memory cell MC[i,j] (i is an integer between 1 and m, and j is an integer between 1 and n) is connected to wiring WL[i], wiring RW[i], wiring WD[j], and wiring BL[j]. Memory cell MCref[i] is connected to wiring WL[i], wiring RW[i], wiring WDref, and wiring BLref. Here, the current flowing between memory cell MC[i,j] and wiring BL[j] is defined as I MC[i,j] and the current flowing between the memory cell MCref[i] and the line BLref is I MCref[i] It is written as follows.

[0224] A specific configuration example of the memory cell MC and the memory cell MCref is shown in Fig. 15. Although Fig. 15 shows memory cells MC[1,1], [2,1] and memory cells MCref[1], [2] as representative examples, similar configurations can be used for other memory cells MC and memory cells MCref. The memory cell MC and the memory cell MCref each have transistors Tr11, Tr12, and a capacitance element C11. Here, a case where the transistors Tr11 and Tr12 are n-channel transistors will be described.

[0225] In the memory cell MC, the gate of the transistor Tr11 is connected to the wiring WL, one of the source or drain is connected to the gate of the transistor Tr12 and a first electrode of the capacitance element C11, and the other of the source or drain is connected to the wiring WD. One of the source or drain of the transistor Tr12 is connected to the wiring BL, and the other of the source or drain is connected to the wiring VR. The second electrode of the capacitance element C11 is connected to the wiring RW. The wiring VR is a wiring having a function of supplying a predetermined potential. Here, as an example, a case where a low power supply potential (such as a ground potential) is supplied from the wiring VR will be described.

[0226] A node connected to one of the source or drain of the transistor Tr11, the gate of the transistor Tr12, and the first electrode of the capacitive element C11 is referred to as a node NM. The nodes NM of the memory cells MC[1,1] and MC[2,1] are respectively referred to as nodes NM[1,1] and NM[2,1].

[0227] The memory cell MCref has a similar configuration to the memory cell MC. However, the memory cell MCref is connected to a wiring WDref instead of the wiring WD, and is connected to a wiring BLref instead of the wiring BL. In addition, in the memory cells MCref[1] and [2], the nodes connected to one of the source or drain of the transistor Tr11, the gate of the transistor Tr12, and the first electrode of the capacitance element C11 are denoted as nodes NMref[1] and [2], respectively.

[0228] The node NM and the node NMref function as the storage nodes of the memory cell MC and the memory cell MCref, respectively. The node NM stores first data, and the node NMref stores reference data. In addition, a current I MC[1,1] , I MC[2,1] In addition, a current I MCref[1] , I MCref[2] flows.

[0229] Since the transistor Tr11 has a function of holding the potential of the node NM or the node NMref, it is preferable that the off-state current of the transistor Tr11 is small. Therefore, it is preferable to use an OS transistor with an extremely small off-state current as the transistor Tr11. This can suppress fluctuations in the potential of the node NM or the node NMref, thereby improving the accuracy of the calculation. In addition, it is possible to reduce the frequency of operations for refreshing the potential of the node NM or the node NMref, thereby reducing power consumption.

[0230] The transistor Tr12 is not particularly limited, and may be, for example, a Si transistor or an OS transistor. When an OS transistor is used as the transistor Tr12, the transistor Tr12 can be manufactured using the same manufacturing equipment as that of the transistor Tr11, thereby reducing manufacturing costs. The transistor Tr12 may be an n-channel type or a p-channel type.

[0231] The current source circuit CS is connected to the wirings BL[1] to [n] and the wiring BLref. The current source circuit CS has a function of supplying current to the wirings BL[1] to [n] and the wiring BLref. Note that the value of the current supplied to the wirings BL[1] to [n] may be different from the value of the current supplied to the wiring BLref. Here, the current supplied from the current source circuit CS to the wirings BL[1] to [n] is defined as I C The current supplied from the current source circuit CS to the wiring BLref is I Cref It is written as follows.

[0232] The current mirror circuit CM has wiring IL[1] to [n] and wiring ILref. The wiring IL[1] to [n] are connected to wiring BL[1] to [n], respectively, and the wiring ILref is connected to wiring BLref. Here, the connection points of the wiring IL[1] to [n] and the wiring BL[1] to [n] are represented as nodes NP[1] to [n]. Also, the connection point of the wiring ILref and the wiring BLref is represented as node NPref.

[0233] The current mirror circuit CM generates a current I CM The function of passing this current I CM In FIG. 14, the current I CM is discharged, and a current I flows from the wirings BL[1] to [n] to the wirings IL[1] to [n]. CM In addition, the current flowing from the current mirror circuit CM to the cell array CA via the wirings BL[1] to [n] is represented as I BThe current flowing from the current mirror circuit CM to the cell array CA via the wiring BLref is represented as I Bref It is written as follows.

[0234] The circuit WDD is connected to the wirings WD[1] to [n] and the wiring WDref. The circuit WDD has a function of supplying a potential corresponding to the first data stored in the memory cell MC to the wirings WD[1] to [n]. The circuit WDD also has a function of supplying a potential corresponding to the reference data stored in the memory cell MCref to the wiring WDref. The circuit WLD is connected to the wirings WL[1] to [m]. The circuit WLD has a function of supplying a signal for selecting the memory cell MC or the memory cell MCref to which data is written to the wirings WL[1] to [m]. The circuit CLD is connected to the wirings RW[1] to [m]. The circuit CLD has a function of supplying a potential corresponding to the second data to the wirings RW[1] to [m].

[0235] The offset circuit OFST is connected to the wirings BL[1] to [n] and the wirings OL[1] to [n]. The offset circuit OFST has a function of detecting the amount of current flowing from the wirings BL[1] to [n] to the offset circuit OFST and / or the amount of change in the current flowing from the wirings BL[1] to [n] to the offset circuit OFST. The offset circuit OFST also has a function of outputting the detection result to the wirings OL[1] to [n]. Note that the offset circuit OFST may output a current corresponding to the detection result to the wiring OL, or may convert the current corresponding to the detection result into a voltage and output it to the wiring OL. The current flowing between the cell array CA and the offset circuit OFST is expressed as I α These are written as [1] through [n].

[0236] A configuration example of the offset circuit OFST is shown in FIG. 16. The offset circuit OFST shown in FIG. 16 has circuits OC[1] to [n]. Also, the circuits OC[1] to [n] each have a transistor Tr21, a transistor Tr22, a transistor Tr23, a capacitance element C21, and a resistance element R1. The connection relationship of each element is as shown in FIG. 16. Note that a node connected to a first electrode of the capacitance element C21 and a first terminal of the resistance element R1 is a node Na. Also, a node connected to a second electrode of the capacitance element C21, one of the source or drain of the transistor Tr21, and a gate of the transistor Tr22 is a node Nb.

[0237] The wiring VrefL has a function of supplying a potential Vref, the wiring VaL has a function of supplying a potential Va, and the wiring VbL has a function of supplying a potential Vb. The wiring VDDL has a function of supplying a potential VDD, and the wiring VSSL has a function of supplying a potential VSS. Here, a case will be described in which the potential VDD is a high power supply potential and the potential VSS is a low power supply potential. The wiring RST has a function of supplying a potential for controlling the conduction state of the transistor Tr21. A source follower circuit is formed by the transistor Tr22, the transistor Tr23, the wiring VDDL, the wiring VSSL, and the wiring VbL.

[0238] Next, an operation example of the circuits OC[1] to [n] will be described. Note that, although an operation example of the circuit OC[1] will be described here as a representative example, the circuits OC[2] to [n] can be operated in the same manner. First, when a first current flows through the wiring BL[1], the potential of the node Na becomes a potential according to the first current and the resistance value of the resistor element R1. At this time, the transistor Tr21 is in an on state, and a potential Va is supplied to the node Nb. After that, the transistor Tr21 is turned off.

[0239] Next, when a second current flows through the wiring BL[1], the potential of the node Na changes to a potential corresponding to the second current and the resistance value of the resistor element R1. At this time, the transistor Tr21 is in an off state and the node Nb is in a floating state, so that the potential of the node Nb changes due to capacitive coupling as the potential of the node Na changes. Here, the change in the potential of the node Na is defined as ΔV Na If the capacitance coupling coefficient is 1, the potential of node Nb is Va+ΔV Na Then, the threshold voltage of the transistor Tr22 is V th Then, the potential from the wiring OL[1] is Va+ΔV Na -V th is output, where Va=V th By doing so, the potential ΔV Na can be output.

[0240] Potential ΔV Na is determined according to the change in the first current to the second current, the resistance element R1, and the potential Vref. Here, since the resistance element R1 and the potential Vref are known, the potential ΔV Na From this, the amount of change in the current flowing through the wiring BL can be obtained.

[0241] A signal corresponding to the amount of current and / or the amount of change in current detected by the offset circuit OFST as described above is input to the activation function circuit ACTV via lines OL[1] to [n].

[0242] The activation function circuit ACTV is connected to the wirings OL[1] to [n] and NIL[1] to [n]. The activation function circuit ACTV has a function of performing calculations to convert the signal input from the offset circuit OFST according to a predefined activation function. For example, a sigmoid function, a tanh function, a softmax function, a ReLU function, a threshold function, etc. can be used as the activation function. The signal converted by the activation function circuit ACTV is output to the wirings NIL[1] to [n] as output data.

[0243] <Example of operation of semiconductor device> Using the above semiconductor device MAC, it is possible to perform a multiply-and-accumulate operation on the first data and the second data. An example of the operation of the semiconductor device MAC when performing the multiply-and-accumulate operation will be described below.

[0244] 17 shows a timing chart of an operation example of the semiconductor device MAC. FIG. 17 shows the transition of the potentials of the wiring WL[1], the wiring WL[2], the wiring WD[1], the wiring WDref, the node NM[1,1], the node NM[2,1], the node NMref[1], the node NMref[2], the wiring RW[1], and the wiring RW[2] in FIG. 15, and the current I B [1]-I α [1], and the current I Bref The graph shows the transition of the current I B [1]-I α [1] corresponds to the sum of currents flowing from the wiring BL[1] to the memory cells MC[1,1] and MC[2,1].

[0245] Note that, here, the operation will be explained focusing on memory cells MC[1,1], [2,1] and memory cells MCref[1], [2] shown in FIG. 15 as representative examples, but other memory cells MC and memory cells MCref can be operated in the same manner.

[0246] [Storage of the first data] First, at time T01-T02, the potential of the wiring WL[1] becomes high level, and the potential of the wiring WD[1] becomes V higher than the ground potential (GND). PR -V W[1,1] The potential of the wiring WDref becomes V higher than the ground potential. PR The potential of the wiring RW[1] and the wiring RW[2] becomes the reference potential (REFP). W[1,1] is a potential corresponding to the first data stored in the memory cell MC[1,1]. PR is a potential corresponding to the reference data. As a result, the transistors Tr11 in the memory cells MC[1,1] and MCref[1] are turned on, and the potential of the node NM[1,1] becomes V PR -VW[1,1] , the potential of node NMref[1] is V PR It becomes.

[0247] At this time, a current I flows from the wiring BL[1] to the transistor Tr12 of the memory cell MC[1,1]. MC[1,1],0 can be expressed by the following formula, where k is a constant determined by the channel length, channel width, mobility, and capacitance of the gate insulating film of the transistor Tr12. th is the threshold voltage of transistor Tr12.

[0248] I MC[1,1],0 =k(V PR -V W[1,1] -V th ) 2 (E1)

[0249] In addition, the current I flows from the wiring BLref to the transistor Tr12 of the memory cell MCref[1]. MCref[1],0 can be expressed by the following formula:

[0250] I MCref[1],0 =k(V PR -V th ) 2 (E2)

[0251] Next, at time T02-T03, the potential of the line WL[1] becomes low level, which turns off the transistors Tr11 of the memory cells MC[1,1] and MCref[1], and maintains the potentials of the nodes NM[1,1] and NMref[1].

[0252] As described above, it is preferable to use an OS transistor as the transistor Tr11, which can suppress leakage current of the transistor Tr11 and accurately hold the potentials of the nodes NM[1,1] and NMref[1].

[0253] Next, at time T03-T04, the potential of the wiring WL[2] becomes high level, and the potential of the wiring WD[1] becomes V higher than the ground potential.PR -V W[2,1] The potential of the wiring WDref becomes V higher than the ground potential. PR The potential V W[2,1] is a potential corresponding to the first data stored in the memory cell MC[2,1]. As a result, the transistors Tr11 in the memory cells MC[2,1] and MCref[2] are turned on, and the potential of the node NM[2,1] becomes V PR -V W[2,1] , the potential of node NMref[2] is V PR It becomes.

[0254] At this time, a current I flows from the wiring BL[1] to the transistor Tr12 of the memory cell MC[2,1]. MC[2,1],0 can be expressed by the following formula:

[0255] I MC[2,1],0 =k(V PR -V W[2,1] -V th ) 2 (E3)

[0256] In addition, the current I flows from the wiring BLref to the transistor Tr12 of the memory cell MCref[2]. MCref[2],0 can be expressed by the following formula:

[0257] I MCref[2],0 =k(V PR -V th ) 2 (E4)

[0258] Next, at time T04-T05, the potential of the line WL[2] becomes low, which turns off the transistors Tr11 of the memory cells MC[2,1] and MCref[2], and maintains the potentials of the nodes NM[2,1] and NMref[2].

[0259] Through the above operations, the first data is stored in the memory cells MC[1,1] and MC[2,1], and the reference data is stored in the memory cells MCref[1] and MCref[2].

[0260] Here, consider the current flowing through the wiring BL[1] and the wiring BLref at time T04-T05. A current is supplied to the wiring BLref from the current source circuit CS. The current flowing through the wiring BLref is discharged to the current mirror circuit CM and the memory cells MCref[1] and [2]. The current supplied from the current source circuit CS to the wiring BLref is defined as I Cref The current flowing from the wiring BLref to the current mirror circuit CM is I CM,0 Then, the following equation holds:

[0261] I Cref -I CM,0 =I MCref[1],0 +I MCref[2],0 (E5)

[0262] A current is supplied to the wiring BL[1] from the current source circuit CS. The current flowing through the wiring BL[1] is discharged to the current mirror circuit CM and the memory cells MC[1,1] and [2,1]. A current also flows from the wiring BL[1] to the offset circuit OFST. The current supplied from the current source circuit CS to the wiring BL[1] is referred to as I C,0 , the current flowing from the wiring BL[1] to the offset circuit OFST is I α,0 Then, the following equation holds:

[0263] I C -I CM,0 =I MC[1,1],0 +I MC[2,1],0 +I α,0 (E6)

[0264] [Multiply and add the first data and the second data] Next, at time T05-T06, the potential of the wiring RW[1] becomes V X[1] At this time, the capacitance elements C11 of the memory cells MC[1,1] and MCref[1] are supplied with a potential V X[1] is supplied, and the potential of the gate of the transistor Tr12 rises due to capacitive coupling. [1]is a potential corresponding to the second data supplied to the memory cell MC[1,1] and the memory cell MCref[1].

[0265] The change in the potential of the gate of transistor Tr12 is calculated by multiplying the change in the potential of the wiring RW by a capacitance coupling coefficient determined by the configuration of the memory cell. The capacitance coupling coefficient is calculated from the capacitance of the capacitance element C11, the gate capacitance of transistor Tr12, and the parasitic capacitance. For the sake of convenience, the following description will be given assuming that the change in the potential of the wiring RW and the change in the potential of the gate of transistor Tr12 are the same, that is, the capacitance coupling coefficient is 1. In practice, the potential Vx can be determined by taking the capacitance coupling coefficient into consideration.

[0266] A potential V X[1] When the voltages of the nodes NM[1,1] and NMref[1] are V X[1] to rise.

[0267] Here, during the period from time T05 to time T06, a current I flows from the wiring BL[1] to the transistor Tr12 of the memory cell MC[1,1]. MC[1,1],1 can be expressed by the following formula:

[0268] I MC[1,1],1 =k(V PR -V W[1,1] +V X[1] -V th ) 2 (E7)

[0269] That is, the potential V X[1] By supplying the current ΔI MC[1,1] =I MC[1,1],1 -I MC[1,1],0 Increase.

[0270] In addition, at time T05-T06, a current I flows from the wiring BLref to the transistor Tr12 of the memory cell MCref[1]. MCref[1],1can be expressed by the following formula:

[0271] I MCref[1],1 =k(V PR +V X[1] -V th ) 2 (E8)

[0272] That is, the potential V X[1] By supplying the current from the wiring BLref to the transistor Tr12 of the memory cell MCref[1], the current flowing from the wiring BLref to the transistor Tr12 of the memory cell MCref[1] is ΔI MCref[1] =I MCref[1],1 -I MCref[1],0 Increase.

[0273] Next, consider the current flowing through the wiring BL[1] and wiring BLref. The wiring BLref is supplied with a current I Cref The current flowing through the wiring BLref is discharged to the current mirror circuit CM and the memory cells MCref[1] and [2]. The current discharged from the wiring BLref to the current mirror circuit CM is I CM,1 Then, the following equation holds:

[0274] I Cref -I CM,1 =I MCref[1],1 +I MCref[2],1 (E9)

[0275] The wire BL[1] carries the current I C The current flowing through the wiring BL[1] is discharged to the current mirror circuit CM and the memory cells MC[1,1] and [2,1]. Furthermore, a current also flows from the wiring BL[1] to the offset circuit OFST. The current flowing from the wiring BL[1] to the offset circuit OFST is defined as I α,1 Then, the following equation holds:

[0276] I C -I CM,1 =I MC[1,1],1 +I MC[2,1],1 +I α,1 (E10)

[0277] Then, from equations (E1) to (E10), the current I α,0 and current I α,1 Difference between the current (ΔI α ) can be expressed by the following formula:

[0278] ΔI α =I α,1 -I α,0 =2kV W[1,1] V X[1] (E11)

[0279] Thus, the differential current ΔI α is the potential V W[1,1] and V X[1] The value depends on the product of these.

[0280] After that, during the period from time T06 to time T07, the potential of the line RW[1] becomes the ground potential, and the potentials of the nodes NM[1,1] and NMref[1] become the same as those during the period from time T04 to time T05.

[0281] Next, at time T07-T08, the potential of the wiring RW[1] becomes V X[1] The potential of the wiring RW[2] becomes V higher than the reference potential. X[2] As a result, a potential V X[1] is supplied, and the potentials of the nodes NM[1,1] and NMref[1] are V X[1] In addition, a potential V X[2] is supplied, and the potentials of the nodes NM[2,1] and NMref[2] are V X[2] to rise.

[0282] Here, at time T07-T08, a current I flows from the wiring BL[1] to the transistor Tr12 of the memory cell MC[2,1]. MC[2,1],1 can be expressed by the following formula:

[0283] IMC[2,1],1 =k(V PR -V W[2,1] +V X[2] -V th ) 2 (E12)

[0284] That is, the potential V X[2] By supplying the current ΔI MC[2,1] =I MC[2,1],1 -I MC[2,1],0 Increase.

[0285] In addition, at time T05-T06, a current I flows from the wiring BLref to the transistor Tr12 of the memory cell MCref[2]. MCref[2],1 can be expressed by the following formula:

[0286] I MCref[2],1 =k(V PR +V X[2] -V th ) 2 (E13)

[0287] That is, the potential V X[2] By supplying the current from the wiring BLref to the transistor Tr12 of the memory cell MCref[2], the current flowing from the wiring BLref to the transistor Tr12 of the memory cell MCref[2] is ΔI MCref[2] =I MCref[2],1 -I MCref[2],0 Increase.

[0288] Next, consider the current flowing through the wiring BL[1] and wiring BLref. The wiring BLref is supplied with a current I Cref The current flowing through the wiring BLref is discharged to the current mirror circuit CM and the memory cells MCref[1] and [2]. The current discharged from the wiring BLref to the current mirror circuit CM is I CM,2 Then, the following equation holds:

[0289] I Cref -I CM,2 =I MCref[1],1 +I MCref[2],1(E14)

[0290] The wire BL[1] carries the current I C The current flowing through the wiring BL[1] is discharged to the current mirror circuit CM and the memory cells MC[1,1] and [2,1]. Furthermore, a current also flows from the wiring BL[1] to the offset circuit OFST. The current flowing from the wiring BL[1] to the offset circuit OFST is defined as I α,2 Then, the following equation holds:

[0291] I C -I CM,2 =I MC[1,1],1 +I MC[2,1],1 +I α,2 (E15)

[0292] From the formulas (E1) to (E8) and the formulas (E12) to (E15), the current I α,0 and current I α,2 Difference between the current (ΔI α ) can be expressed by the following formula:

[0293] ΔI α =I α,2 -I α,0 =2k(V W[1,1] V X[1] +V W[2,1] V X[2] ) (E16)

[0294] Thus, the differential current ΔI α is the potential V W[1,1] and potential V X[1] and the potential V W[2,1] and potential V X[2] The value is determined by adding the product of and .

[0295] After that, at times T08-T09, the potentials of the wirings RW[1] and [2] become the ground potential, and the potentials of the nodes NM[1,1] and [2,1] and the nodes NMref[1] and [2] become the same as at times T04-T05.

[0296] As shown in equations (E9) and (E16), the differential current ΔI α is the potential V corresponding to the first data (weight) X and the potential V corresponding to the second data (input data) W The value corresponds to the sum of the products of the above. In other words, the differential current ΔI α By measuring this with the offset circuit OFST, the result of the multiplication and accumulation operation of the first data and the second data can be obtained.

[0297] In the above, attention has been paid to memory cells MC[1,1], [2,1] and memory cells MCref[1], [2], but the number of memory cells MC and memory cells MCref can be set arbitrarily. α can be expressed by the following formula:

[0298] ΔI α =2kΣ i V W[i,1] V X[i] (E17)

[0299] Moreover, by increasing the number n of columns of memory cells MC and memory cells MCref, the number of product-sum operations executed in parallel can be increased.

[0300] As described above, by using the semiconductor device MAC, it is possible to perform a product-sum operation on the first data and the second data. Note that by using the configuration shown in FIG. 15 for the memory cells MC and the memory cells MCref, it is possible to configure a product-sum operation circuit with a small number of transistors. Therefore, it is possible to reduce the circuit scale of the semiconductor device MAC.

[0301] When the semiconductor device MAC is used for calculations in a neural network, the number of rows m of the memory cells MC can be set to correspond to the number of input data supplied to one neuron, and the number of columns n of the memory cells MC can be set to the number of neurons. For example, consider a case where a multiply-and-accumulate operation is performed using the semiconductor device MAC in the hidden layer HL shown in Figure 13(A). In this case, the number of rows m of the memory cells MC can be set to the number of input data supplied from the input layer IL (the number of neurons in the input layer IL), and the number of columns n of the memory cells MC can be set to the number of neurons in the hidden layer HL.

[0302] The structure of the neural network to which the semiconductor device MAC is applied is not particularly limited. For example, the semiconductor device MAC can be used for a convolutional neural network (CNN), a recurrent neural network (RNN), an autoencoder, a Boltzmann machine (including a restricted Boltzmann machine), etc.

[0303] As described above, by using the semiconductor device MAC, it is possible to perform the product-sum operation of a neural network. Furthermore, by using the memory cell MC and the memory cell MCref shown in FIG. 15 in the cell array CA, it is possible to provide an integrated circuit capable of improving the operation accuracy, reducing the power consumption, or reducing the circuit scale.

[0304] This embodiment mode can be implemented by appropriately combining at least a part of it with other embodiment modes described in this specification.

[0305] (Embodiment 3) In this embodiment, an example in which a battery module according to one embodiment of the present invention is mounted on a vehicle will be described. Examples of vehicles include automobiles, motorcycles, and bicycles.

[0306] By installing a battery module in a vehicle, next-generation clean energy vehicles such as hybrid electric vehicles (HEVs), electric vehicles (EVs), and plug-in hybrid electric vehicles (PHEVs) can be realized.

[0307] 18A and 18B illustrate a vehicle using a battery module according to one embodiment of the present invention. An automobile 8400 shown in FIG. 18A is an electric automobile using an electric motor as a power source for running. Alternatively, the automobile 8400 is a hybrid automobile in which an electric motor and an engine can be appropriately selected and used as a power source for running. By using one embodiment of the present invention, a vehicle with a long cruising distance can be realized. The automobile 8400 includes a battery module. The battery module not only drives an electric motor 8406 but also supplies power to a light-emitting device such as a headlight 8401 or a room light (not shown).

[0308] The battery module can also supply power to display devices such as a speedometer and a tachometer included in the automobile 8400. The battery module can also supply power to a navigation system included in the automobile 8400.

[0309] The automobile 8500 shown in FIG. 18(B) can be charged by receiving power supply from an external charging facility to a battery module of the automobile 8500 by a plug-in method, a non-contact power supply method, or the like. FIG. 18(B) shows a state in which charging is being performed from a ground-mounted charging device 8021 to a battery module 8024 mounted on the automobile 8500 via a cable 8022. When charging, the charging method and connector standards may be appropriately performed by a predetermined method such as CHAdeMO (registered trademark) or Combo. The charging device 8021 may be a charging station installed in a commercial facility, or may be a home power source. For example, the battery module 8024 mounted on the automobile 8500 can be charged by an external power supply by plug-in technology. Charging can be performed by converting AC power to DC power via a conversion device such as an ACDC converter.

[0310] Although not shown, a power receiving device may be mounted on a vehicle, and power may be supplied contactlessly from a ground power transmitting device to charge the vehicle. In the case of this contactless power supply method, by incorporating a power transmitting device in a road or an exterior wall, charging may be performed not only while the vehicle is stopped but also while the vehicle is moving. This contactless power supply method may also be used to transmit and receive power between vehicles. Furthermore, a solar cell may be provided on the exterior of the vehicle to charge the battery module while the vehicle is stopped or moving. An electromagnetic induction method or a magnetic resonance method may be used for such contactless power supply.

[0311] 18C is an example of a two-wheeled vehicle using the battery module of one embodiment of the present invention. A scooter 8600 shown in FIG. 18C includes a battery module 8602, a side mirror 8601, and a turn signal light 8603. The battery module 8602 can supply electricity to the turn signal light 8603.

[0312] 18(C) is capable of storing the battery module 8602 in the under-seat storage 8604. The battery module 8602 can be stored in the under-seat storage 8604 even if the under-seat storage 8604 is small in size.

[0313] 19A is an example of an electric bicycle using the battery module of one embodiment of the present invention. The battery module of one embodiment of the present invention can be applied to an electric bicycle 8700 shown in FIG.

[0314] The electric bicycle 8700 includes a battery pack 8702. The battery pack 8702 can supply electricity to a motor that assists a rider. The battery pack 8702 is portable and is shown in a state removed from the bicycle in FIG. 19B. The battery pack 8702 includes a plurality of built-in storage batteries 8701 included in a battery module of one embodiment of the present invention, and the remaining battery charge and the like can be displayed on a display unit 8703. The battery pack 8702 preferably includes a protection circuit, a neural network, and the like.

[0315] 19C illustrates an electric motorcycle 8710 using the battery module of one embodiment of the present invention. The battery module of one embodiment of the present invention can be applied to the electric motorcycle 8710 illustrated in FIG.

[0316] The electric motorcycle 8710 includes a storage battery 8711, a display unit 8712, and a handlebar 8713. The storage battery 8711 can supply electricity to a motor that serves as a power source. The display unit 8712 can display the remaining charge of the storage battery 8711, the speed of the electric motorcycle 8710, the horizontal state, and the like. The storage battery 8711 is preferably equipped with a protection circuit, a neural network, and the like.

[0317] This embodiment mode can be appropriately combined with the descriptions of other embodiment modes.

[0318] (Embodiment 4) In this embodiment, an example in which the battery module shown in the above embodiment is mounted on an electronic device will be described.

[0319] 20(A) and 20(B) show an example of a tablet terminal that can be folded in two. The tablet terminal 9600 shown in FIG. 20(A) and FIG. 20(B) has a housing 9630a, a housing 9630b, a movable part 9640 that connects the housings 9630a and 9630b, a display part 9631, a display mode changeover switch 9626, a power switch 9627, a power saving mode changeover switch 9625, a fastener 9629, and an operation switch 9628. By using a flexible panel for the display part 9631, a tablet terminal having a larger display part can be obtained. FIG. 20(A) shows the tablet terminal 9600 in an open state, and FIG. 20(B) shows the tablet terminal 9600 in a closed state.

[0320] The tablet terminal 9600 also includes a power storage unit 9635 inside the housing 9630a and the housing 9630b. The power storage unit 9635 passes through the movable portion 9640 and is provided across the housings 9630a and 9630b.

[0321] A part of the display portion 9631 can be a touch panel area, and data can be input by touching the displayed operation keys. Also, keyboard buttons can be displayed on the display portion 9631 by touching a position on the touch panel where a keyboard display switching button is displayed with a finger or a stylus.

[0322] Furthermore, the display mode changeover switch 9626 can change the display orientation, such as portrait or landscape, and can select black and white or color display. The power saving mode changeover switch 9625 can optimize the display brightness according to the amount of external light during use detected by an optical sensor built into the tablet terminal 9600. The tablet terminal may be equipped with not only an optical sensor, but also other detection devices such as a gyro, an acceleration sensor, or other sensors that detect tilt.

[0323] 20B shows a tablet terminal in a closed state, which includes a housing 9630, a solar cell 9633, and a charge / discharge control circuit 9634 including a DC-DC converter 9636. In addition, as a power storage unit 9635, a battery module according to one embodiment of the present invention can be used.

[0324] As described in the above embodiment, the battery module of one embodiment of the present invention preferably includes a storage battery, a protection circuit, a control circuit, and a neural network. Here, integrated circuits such as the control circuit, the neural network, and the protection circuit included in the battery module of one embodiment of the present invention may be provided on an IC chip together with a circuit for controlling the display portion 9631, such as a driver circuit, or the like. Alternatively, they may be provided on an IC chip together with the charge and discharge control circuit 9634.

[0325] Note that the tablet terminal 9600 can be folded in half, so that the housing 9630a and the housing 9630b can be folded together when not in use. By folding, the display portion 9631 can be protected, and therefore durability of the tablet terminal 9600 can be improved.

[0326] In addition, the tablet terminals shown in Figures 20(A) and 20(B) can have a function to display various information (still images, videos, text images, etc.), a function to display a calendar, date or time on the display unit, a touch input function to perform touch input operations or edit information displayed on the display unit, and a function to control processing using various software (programs), etc.

[0327] A solar cell 9633 attached to the surface of the tablet terminal can supply power to a touch panel, a display unit, a video signal processor, or the like. Note that the solar cell 9633 can be provided on one or both sides of the housing 9630, and a configuration can be adopted in which the power storage unit 9635 can be efficiently charged.

[0328] The configuration and operation of the charge / discharge control circuit 9634 shown in Fig. 20B are described with reference to a block diagram in Fig. 20C. Fig. 20C shows a solar cell 9633, a power storage unit 9635, a DCDC converter 9636, a converter 9637, switches SW1 to SW3, and a display unit 9631. The power storage unit 9635, the DCDC converter 9636, the converter 9637, and the switches SW1 to SW3 correspond to the charge / discharge control circuit 9634 shown in Fig. 20B.

[0329] First, an example of operation in the case where power is generated by the solar cell 9633 using external light will be described. The power generated by the solar cell is stepped up or stepped down by a DC-DC converter 9636 to a voltage for charging a power storage unit 9635. When power from the solar cell 9633 is used for the operation of the display unit 9631, a switch SW1 is turned on, and the converter 9637 steps up or steps down the voltage to a voltage required for the display unit 9631. When no display is to be performed on the display unit 9631, SW1 is turned off and SW2 is turned on to charge the power storage unit 9635.

[0330] Note that the solar cell 9633 is shown as an example of a power generating means, but is not particularly limited thereto, and may be configured to charge the power storage unit 9635 using other power generating means such as a piezoelectric element (piezo element) or a thermoelectric conversion element (Peltier element). For example, a non-contact power transmission module that transmits and receives power wirelessly (non-contact) for charging, or a combination with other charging means may be used.

[0331] 21A and 21B show examples of other battery modules and electronic devices. Fig. 21A shows an example of a house including a battery module 8300 according to one embodiment of the present invention and a solar panel 8230. The house is preferably provided with a ground-mounted charging device 8240. The battery module 8300 preferably includes a protection circuit, a control circuit, and a neural network.

[0332] The battery module 8300, the solar panel 8230, and the charging device 8240 are electrically connected via wiring 8231 and the like. The power obtained by the solar panel 8230 can be charged to the battery module 8300. The power stored in the battery module 8300 can be charged to a storage battery 8251 included in an automobile 8250. Note that the automobile 8250 is an electric automobile or a plug-in hybrid automobile.

[0333] The power stored in the battery module 8300 can also be supplied to other electronic devices. For example, as shown in FIG. 21B, the battery module 8300 and a stationary lighting device 8100 are electrically connected to supply power to the lighting device 8100. The lighting device 8100 includes a housing 8101, a light source 8102, a control circuit 8103, and the like. The lighting device 8100 can receive power from a commercial power source or can use power stored in the battery module 8300. Thus, even when power cannot be supplied from a commercial power source due to a power outage or the like, the lighting device 8100 can be used by using the battery module 8300 according to one embodiment of the present invention as an uninterruptible power source.

[0334] Note that although FIG. 21B illustrates an example of a stationary lighting device 8100 provided on a ceiling 8104, the battery module 8300 according to one embodiment of the present invention may supply power to a stationary lighting device provided on a surface other than the ceiling 8104, such as a side wall, a floor, or a window, or may supply power to a tabletop lighting device.

[0335] An artificial light source that artificially obtains light using electric power can be used as the light source 8102. Specifically, examples of the artificial light source include discharge lamps such as incandescent lamps and fluorescent lamps, and light-emitting elements such as LEDs and organic EL elements.

[0336] Similarly, the battery module 8300 can supply power to the display device 8000. The display device 8000 has a housing 8001, a display unit 8002, a speaker unit 8003, a control circuit 8004, and the like. The display device 8000 can receive power from a commercial power source, or can use power stored in the battery module 8300. For the display unit 8002, a display device such as a liquid crystal display device, a light-emitting device having a light-emitting element such as an organic EL element in each pixel, an electrophoretic display device, a DMD (Digital Micromirror Device), a PDP (Plasma Display Panel), or an FED (Field Emission Display) can be used.

[0337] The display device includes all display devices for displaying information, such as display devices for receiving TV broadcasts, display devices for personal computers, display devices for advertisements, and the like.

[0338] Similarly, the battery module 8300 can supply power to an air conditioner having an indoor unit 8200 and an outdoor unit 8204. The indoor unit 8200 has a housing 8201, an air outlet 8202, a control circuit 8203, and the like. The air conditioner can receive power from a commercial power source or can use power stored in the battery module 8300.

[0339] Note that, although Figure 21(B) illustrates an example of a separate-type air conditioner composed of an indoor unit and an outdoor unit, power may be supplied from a battery module according to one embodiment of the present invention to an integrated air conditioner that has the functions of both the indoor unit and the outdoor unit in a single housing.

[0340] Moreover, the battery module 8300 preferably includes a charging device 8301. With the charging device 8301, various electronic devices can be charged from the battery module 8300. The charging device 8301 may be a charging device for wired charging or wireless charging (also referred to as non-contact charging or wireless power transmission). With the battery module 8300 including a charging device for wireless charging, a smartphone 8302 or the like equipped with a wireless charging system can be charged.

[0341] 22A to 22F show examples of electronic devices to which a battery module of one embodiment of the present invention is applied. Examples of electronic devices to which a battery module of one embodiment of the present invention is applied include television sets (also referred to as televisions or television receivers), monitors for computers, digital cameras, digital video cameras, digital photo frames, mobile phones (also referred to as mobile phones or mobile phone devices), portable game machines, personal digital assistants, audio playback devices, and large game machines such as pachinko machines.

[0342] 22A illustrates an example of a mobile phone. The mobile phone 7400 includes a display portion 7402 built into a housing 7401, operation buttons 7403, an external connection port 7404, a speaker 7405, a microphone 7406, and the like. Note that the mobile phone 7400 includes a battery module of one embodiment of the present invention. The battery module of one embodiment of the present invention includes, for example, a storage battery 7407, a protection circuit, a control circuit, and a neural network.

[0343] 22B shows a state in which the mobile phone 7400 is bent. When the mobile phone 7400 is deformed by an external force and bent as a whole, the storage battery 7407 provided inside may also be bent. In such a case, it is preferable to use a flexible storage battery as the storage battery 7407. The bent state of the flexible storage battery is shown in FIG. 22C.

[0344] In addition, a storage battery having a flexible shape can be installed along the curved surfaces of the inner or outer walls of a house or building, or the interior or exterior of an automobile.

[0345] 22D illustrates an example of a bangle-type display device. A portable display device 7100 includes a housing 7101, a display portion 7102, operation buttons 7103, and a battery module of one embodiment of the present invention. The battery module of one embodiment of the present invention includes, for example, a storage battery 7104, a protection circuit, a control circuit, and a neural network.

[0346] 22E shows an example of a wristwatch-type portable information terminal. A portable information terminal 7200 includes a housing 7201, a display portion 7202, a band 7203, a buckle 7204, operation buttons 7205, an input / output terminal 7206, and the like.

[0347] The portable information terminal 7200 can execute various applications such as mobile telephone, e-mail, document browsing and creation, music playback, Internet communication, and computer games.

[0348] The display surface of the display portion 7202 is curved, and display can be performed along the curved display surface. The display portion 7202 is also provided with a touch sensor, and can be operated by touching the screen with a finger, a stylus, or the like. For example, an application can be started by touching an icon 7207 displayed on the display portion 7202.

[0349] The operation button 7205 can have various functions, such as time setting, power on / off operation, wireless communication on / off operation, silent mode activation / cancellation, power saving mode activation / cancellation, etc. For example, the function of the operation button 7205 can be freely set by an operating system built into the mobile information terminal 7200.

[0350] The mobile information terminal 7200 can also perform short-distance wireless communication according to a communication standard. For example, the mobile information terminal 7200 can communicate with a wireless headset to enable hands-free calling.

[0351] The portable information terminal 7200 also includes an input / output terminal 7206, and can directly exchange data with other information terminals via a connector. Charging can also be performed via the input / output terminal 7206. Note that charging may be performed by wireless power supply without using the input / output terminal 7206.

[0352] The portable information terminal 7200 includes a battery module according to one embodiment of the present invention.

[0353] The portable information terminal 7200 preferably has a sensor. For example, it is preferable to mount a human body sensor such as a fingerprint sensor, a pulse sensor, or a body temperature sensor, a touch sensor, a pressure sensor, an acceleration sensor, or the like, as the sensor.

[0354] 22(F) shows an unmanned aerial vehicle 7300 having multiple rotors 7302. The unmanned aerial vehicle 7300 includes a storage battery system 7301 according to one embodiment of the present invention, a camera 7303, and an antenna (not shown). The unmanned aerial vehicle 7300 can be remotely controlled via the antenna.

[0355] This embodiment mode can be implemented by appropriately combining at least a part of it with other embodiment modes described in this specification. [Explanation of symbols]

[0356] 10: semiconductor device, 10a to d: semiconductor device, 11: substrate, 12: element layer, 13a to b: terminal, 14: antenna, 15: connection portion, 16: protective layer, 17: substrate, 20: battery unit, 20a to b: battery unit, 20p: battery unit, 20M: battery module, 21a to b: exterior body, 22: printed circuit board, 23: IC, 24: antenna, 25: connector wiring, 26: conductive member, 26n: conductive member, 26p: conductive member, 27n: wiring, 27p: wiring, 30: battery, 30a to d: battery, 31n: negative terminal, 31p: positive terminal, 33: lead, 34: conductive portion material, 35: exterior body, 36n: connection terminal, 36p: connection terminal, 40: control device, 41: control unit, 42: wireless communication unit, 43: antenna, 50: circuit, 51: voltage detection circuit, 52: current detection circuit, 53: temperature sensor, 54: balance circuit, 55a-c: AD conversion circuit, 60: circuit, 61: control unit, 62: wireless communication unit, 63: antenna, 71: support substrate, 72: peeling layer, 80a-b: transistor, 81: semiconductor layer, 82: insulating layer, 83: conductive layer, 84a-c: conductive layer, 85: conductive layer, 85a: conductive layer, 85f: conductive film, 86: insulating layer, 88: conductive layer, 89: conductive layer, 90-93: insulating layers

Claims

[Claim 1] a first substrate, an element layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer; the element layer includes a first circuit and a second circuit, and is provided on a first surface side of the first substrate; the first circuit includes a transistor; the transistor includes a semiconductor layer, a first gate electrode having a region located above the semiconductor layer, and a second gate electrode having a region located below the semiconductor layer; the fourth conductive layer is provided in the same layer as the second gate electrode, the first conductive layer and the second conductive layer are each provided on a second surface side of the first substrate opposite to the first surface, the first conductive layer and the first circuit, and the second conductive layer and the first circuit are electrically connected to each other through openings provided in the first substrate, the third conductive layer is laminated on a side of the element layer opposite to the first substrate, and is electrically connected to the second circuit; the first conductive layer and the second conductive layer each function as a terminal; At least one of the first conductive layer and the second conductive layer has a region in contact with the fourth conductive layer, The third conductive layer functions as an antenna.

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