Epitaxial wafer and manufacturing method thereof

Abstract

To provide an epitaxial wafer having improved flatness and uniformity, and a method for manufacturing the same.SOLUTION: A method for manufacturing an epitaxial wafer which includes a silicon substrate 802 having one main surface and an epitaxial layer formed on one main surface, in which a thickness of the epitaxial layer is 0.3-1.0 μm, and variation in a thickness is 1% or less, arranges a silicon substrate in a susceptor 804 of an epitaxial reactor, rotates the susceptor at a rotation speed (D), introduces a raw material gas into the epitaxial reactor, and grows the epitaxial layer having a desired thickness (B) on the silicon substrate at a growth speed (A). The raw material gas is supplied in growth time (C) satisfying C=B / A, and the rotation speed (D) is selected from a range of 22-70 rpm that the susceptor can be rotatable at the integer rotation number (E) of rotation based on a relation of D=E / C.SELECTED DRAWING: Figure 8

Description

[Technical field]

[0001] The present invention relates to an epitaxial wafer and a method for manufacturing an epitaxial wafer. [Background technology]

[0002] As shown in FIG. 1A, a fin field effect transistor (finFET) has three-dimensional fins 102, each of which provides a channel that connects to a gate 104 on three sides. This structure has the effect of reducing leakage current compared to conventional metal oxide semiconductor field effect transistors (MOSFETs). However, as design rules require higher density of semiconductor devices, the transistor channel length becomes shorter, making it more susceptible to leakage current even with the three-sided contact to the gate provided by the vertical fin channel of a fin field effect transistor. In a gate-all-around (GAA) field effect transistor as shown in FIG. 1B, a channel 106 is deposited on the surface of a silicon wafer 108, and a gate 110 surrounds the channel on all four sides. Summary of the Invention [Problem to be solved by the invention]

[0003] Because such channels 106 are deposited on a silicon wafer 108, the surface 112 of the silicon wafer 108 is required to have improved flatness and uniformity.

[0004] An object of the present invention is to provide an epitaxial wafer having improved flatness and uniformity, and a method for manufacturing the same. [Means for solving the problem]

[0005] The present invention relates to a particular epitaxial wafer useful for devices using gate-all-around field effect transistors (GAA FETs). The very thin epitaxial layers of the present invention provide flat, smooth surfaces with very little or no thickness variation.

[0006] A first aspect of the present invention includes a silicon substrate having a major surface (top surface) and a thin epitaxial layer formed on the major surface, the thin epitaxial layer being substantially unaffected by surface irregularities caused by process induced defects (PIDs) in the underlying silicon substrate.

[0007] A second aspect of the present invention relates to improving the edge site flatness (ie, maximum ESFQR) of an epitaxial wafer, thereby improving the flatness across the surface of the epitaxial wafer.

[0008] A third aspect of the present invention includes excellent maximum ESFQR in the edge exclusion region of 1 mm to 2 mm.

[0009] A fourth aspect of the present invention includes a chamfer width in the range of 150 μm to 450 μm.

[0010] In a fifth aspect of the present invention, the silicon substrate is free of dislocation clusters and COP defects.

[0011] A sixth aspect of the invention includes a silicon substrate free of COP defects having a maximum cross-sectional width of 110 nm or greater.

[0012] A seventh aspect of the invention includes a nitrogen-containing silicon substrate.

[0013] An eighth aspect of the present invention includes a silicon substrate cut from a crystal with a {110} plane at a tilt angle of 0.1 to 1.2 degrees.

[0014] A ninth aspect of the present invention includes the epitaxial layer having a haze level of 1.20 ppm or less.

[0015] A tenth aspect of the present invention includes an epitaxial layer having a thickness variation and thickness uniformity both less than or equal to 1.0%.

[0016] An eleventh aspect of the present invention includes a method for manufacturing an epitaxial wafer, comprising placing a silicon substrate on a susceptor in an epitaxial reactor, rotating the susceptor at a rotation speed (D), introducing a source gas into the epitaxial reactor, and growing an epitaxial layer of a desired thickness (B) on the silicon substrate at a growth speed (A), wherein the source gas is supplied for a growth time (C) that satisfies C=B / A, and the rotation speed (D) is selected from the range of 22 to 70 rpm so that the susceptor can rotate at a strict integer number of rotations (E) based on the relationship D=E / C. [Brief description of the drawings]

[0017] [Figure 1A] FIG. 1 is an overall view of a FinFET device. [Figure 1B] FIG. 1 is an overall view of a GAA FET device. [Figure 2A] FIG. 1 illustrates a method for determining the ESFQR of a wafer. [Figure 2B] FIG. 1 illustrates a method for determining the ESFQR of a wafer. [Diagram 3] FIG. 1 illustrates a cubic crystal defined by Miller indices. [Figure 4] FIG. 2 is a diagram showing a measurement principle for calculating the variation in the film thickness of an epitaxial layer. [Diagram 5] FIG. 2 is a diagram showing a measurement principle for calculating the uniformity of the film thickness of an epitaxial layer. [Figure 6A] 1A-1D are diagrams illustrating a method for manufacturing a silicon substrate having a tilt angle according to an embodiment of the present invention. [Figure 6B] FIG. 6B is a diagram showing the silicon substrate cut from the inclined surface of FIG. 6A in a separated state. [Figure 7A] <110> FIG. 1 shows a reference notch for crystal orientation (along the Y axis). [Figure 7B]<100> FIG. 1 shows a reference notch for crystal orientation (along the X-axis). [Figure 8] 1A to 1C are diagrams illustrating a method for manufacturing an epitaxial wafer according to an embodiment of the present invention. [Figure 9] FIG. 1 is a cross-sectional view showing an example of a short chamfer width and a long chamfer width of a wafer. [Figure 10A] FIG. 1 is a cross-sectional view of a preferred epitaxial wafer having a thin epitaxial layer according to an embodiment of the present invention. [Figure 10B] FIG. 1 is a cross-sectional view of a preferred epitaxial wafer having a thin epitaxial layer according to an embodiment of the present invention. [Figure 10C] FIG. 1 is a cross-sectional view of a conventional epitaxial wafer having a thicker epitaxial layer. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0018] The details shown in this specification are presented as examples only for the purpose of illustrative discussion of the exemplary features of the present disclosure, and to show what is believed to be the most useful and easily understood explanation of the principles and conceptual aspects of the exemplary features. In this regard, the structural details of the configuration of the example are not shown in more detail than is necessary for a basic understanding thereof. The description using the drawings will make it clear to those skilled in the art how the form of the exemplary features can be embodied in practice.

[0019] When the terms "about" or "substantially" are used herein in connection with a numerical value, the associated numerical value is intended to include a tolerance of ±10% around the stated numerical value. Furthermore, when percentages are referred to herein, it is intended that the percentages are by weight, i.e., weight percentages. The term "up to" includes the amount from zero to the upper limit expressed, and all values ​​therebetween. When a range is specified, it is intended that the range includes all values ​​therebetween (such as increments of 0.1%). Furthermore, when the terms "approximately" and "substantially" are used in connection with a geometric shape, it is intended that precision of the geometric shape is not required, but freedom of shape is within the scope of the disclosure.

[0020] In the figures, the dimensions of layers and regions may be exaggerated for clarity of illustration. The same reference numbers in the figures refer to similar elements throughout the figures. The same reference numbers also refer to the same components throughout the specification. Spatially relative terms, such as "under" and "over," may be used herein to describe the relationship of one element or configuration to another element or configuration shown in the figures for ease of description. The spatially relative terms are intended to encompass various orientations of the device in use or operation in addition to the orientation shown in the figures. For example, if a device in the figures is turned over, an element described as "under" or "below" another element or feature would be "above" that other element or configuration. Thus, the example term "under" encompasses both an upward and downward orientation. The device may be oriented in another direction (rotated 90 degrees or in another direction) and the spatially relative descriptors used herein would be interpreted accordingly.

[0021] The exemplary configurations are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized configurations (and intermediate structures) of the exemplary configurations. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances are expected. Thus, the exemplary configurations should not be construed as limited to the particular shapes of regions illustrated herein but should include deviations in shapes that result, for example, from manufacturing. The regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shapes of regions of material and are not intended to limit the scope of the exemplary configurations.

[0022] The present invention relates to a particular epitaxial wafer useful for devices using gate-all-around field effect transistors (GAA FETs). The very thin epitaxial layer of the present invention provides a flat, smooth surface with very little or no thickness variation (within-wafer thickness variation). The thin epitaxial layer formed on the top surface of a silicon substrate is substantially unaffected by surface irregularities caused by process-induced defects (PIDs) on the top surface of the silicon substrate below it.

[0023] The preferred thickness of the epitaxial layer of the present invention is in the range of 0.3 μm to 1.0 μm. Preferably, the epitaxial wafer of the present invention has an epitaxial layer thickness of about 0.5 μm.

[0024] One of the important aspects of the present invention is the inclusion of Edge Site Frontside least squares Range (ESFQR), which is related to the overall flatness of the wafer. ESFQR is an analytical characteristic near the edge of the wafer and affects the flatness of the entire wafer. In contrast, Site Frontside least squares Range (SFQR) is a small segment measurement of the flatness along the entire wafer surface. ESFQR is an index of flatness determined by measuring SFQR in a sector area formed at the periphery of the wafer. A smaller ESFQR indicates a higher flatness. ESFQR and SFQR are indices for measuring the flatness of a wafer according to SEMI standards (M1, M67, or M1530). ESFQR can be determined using a flatness measurement system such as the WAFERSIGHT2 manufactured by KLA-Tencor Corporation.

[0025] The ESFQR of a wafer can be determined as shown in Figures 2A and 2B. In Figure 2A, a 300 mm wafer 202 is divided into 72 sectors or sites 204, each site having a 5 degree arc, and each site has an edge exclusion region 206 of 1 mm. The length of the sector or site is 15 mm. Here, the edge exclusion region is arbitrarily selected and may be 1 mm to 2 mm. In this case, "maximum ESFQR" means the maximum ESFQR value determined among the 72 sites.

[0026] 2B, the maximum value α of a site 204 is determined as its maximum height from the least squares site datum 208 and the minimum value β is determined as its minimum value below the least squares site datum 208. Mathematically speaking, ESFQR is the absolute value of the maximum extent from the least squares site datum 208 at an edge site, or ESFQR=|α|+|β|.

[0027] Preferably, the maximum ESFQR in an embodiment of the present invention is 11.3 nm or less in an edge exclusion region 206 (meaning the region inside, excluding the region about 1 mm from the edge) about 1 mm from the edge of the wafer.

[0028] In the nomenclature of basic crystal planes and directions, Miller indices are a three-dimensional coordinate system of a crystal based on a unit cell. In such a coordinate system, directions or planes can be indicated and are denoted (hkl). As shown in FIG. 3, examples of Miller indices for a cubic crystal 302 include

[0111] , the lattice diagonal 304,

[0110] , the face diagonal 306, (100), and the face plane 308. The brackets around hkl have a specific meaning: [hkl] denotes a direction, and <hkl>denotes a set of directions, (hkl) denotes a plane, and {hkl} denotes a set of faces. A silicon crystal having a cubic silicon lattice can be defined according to an equivalent set of planes determined by its seed crystal, i.e., a silicon crystal having {hkl} faces. In this regard, when a crystal is pulled from molten silicon to grow either the {100} or the {110} faces, it is possible to grow either the {100} or the {110} faces by initially selecting a different seed crystal. The {110} and {100} faces, <110> and <100> Determination of crystal orientation, and related wafer sawing techniques, are known in the art, for example, as shown in US Pat. Nos. 8,152,919 and 5,904,136.

[0029] Tables 1 and 2 show how the epitaxial layer thickness affects the ESFQR. Table 1 summarizes measurements from epitaxial wafers using {100} silicon substrates and epitaxial layer thicknesses ranging from 0.3 μm to 2.0 μm. Table 2 summarizes measurements from epitaxial wafers using {110} silicon substrates and epitaxial layer thicknesses ranging from 0.3 μm to 2.0 μm.

[0030] [Table 1]

[0031] [Table 2]

[0032] Tables 1 and 2 show that the preferred range for the epitaxial layer thickness is 0.3 μm to 1.0 μm, which, as shown, keeps the maximum ESFQR below 11.1 nm for both {100} and {110} substrates.

[0033] Another aspect of the present invention relates to improving the variation in thickness of an epitaxial layer. Yet another aspect of the present invention relates to the uniformity of the thickness of an epitaxial layer. The principle of measuring the variation in thickness of an epitaxial layer is shown in FIG.

[0034] As shown in Fig. 4, the thickness variation [%] of the epitaxial layer can be calculated as {|AB| / (A+B)} x 100, where A and B are any two measured thicknesses of the epitaxial layer 10 mm inward from the edge of the wafer. However, as shown in Fig. 4, A and B are symmetrical points with respect to the center. The thickness variation of the epitaxial layer of the present invention is preferably 1.0% or less.

[0035] 5, the thickness uniformity [%] of the epitaxial layer of the present invention can be calculated as {(Max-Min) / (Max+Min)}×100, where "Max" and "Min" are the maximum and minimum thicknesses of the epitaxial layer 502 at any four symmetrical points (i.e., two pairs of symmetrical points) 10 mm or more inward from the edge of the wafer and at the center of the epitaxial layer. The thickness uniformity of the epitaxial layer of the present invention is preferably 1.0% or less.

[0036] The thickness variation and thickness uniformity of the epitaxial layer of the present invention can be achieved by a specific manufacturing method. In particular, the preferred silicon substrate on which the epitaxial layer is grown according to the present invention is a silicon substrate cut from a {110} plane with a tilt angle of ±0.1-1.2 degrees. Preferably, such a tilt angle can be achieved by rotating the {110} plane with respect to the Y axis (tilt direction) in the XY plane. This configuration is shown in FIG. 6A and is further described below.

[0037] Figure 6A shows a single crystal silicon ingot 602 being pulled vertically along a Z-axis 604. As can be seen, the axes shown in Figure 6A represent the following directions with respect to the crystal structure: Z-axis 604 coincides with the crystal pull direction <110> The Y-axis 606 is a direction perpendicular to the Z-axis. <110> The X-axis 608 is in a plane perpendicular to the Z-axis. <100> It is a direction.

[0038] On silicon substrate <110> When there is a notch in the direction, the Y axis is a straight line passing from the notch to the center of the silicon substrate as shown in FIG. <100> When there is a notch in the direction, the Y axis is a straight line perpendicular to another straight line passing from the notch through the center of the silicon substrate, as shown in FIG. 7B.

[0039] Returning to Figure 6A, X'-axis 610 is the X-axis rotated about the Y-axis. Tilt angle θ 612 is the angle between the X-axis and the X'-axis. Both positive and negative tilt angles represent the same silicon substrate.

[0040] The {110} silicon substrate of the present invention is cut at a specific directional angle, referred to herein as the "tilt angle" 612 and the "tilt direction" 614, respectively. Consider, for example, a {110} silicon substrate from a crystal set in three dimensional axes (X, Y, and Z axes), as shown in FIG. 6A. If the direction of crystal growth is set along the Z axis ( <110> direction), the silicon substrate cut from the crystal lies in the XY plane perpendicular to the Z axis. Here, the X axis is <100> direction, and the Y axis is <110> The tilt angle and tilt direction in this configuration means that such an XY plane is rotated by a small angular displacement (in either direction) with respect to the Y axis. Such a plane of rotation is referred to herein as an "inclined plane" 616, and thus a silicon substrate cut at an inclined angle is on an inclined plane. Preferably, the inclination angle is in the range of 0.1 degrees to 1.2 degrees.

[0041] 6B is an exploded view of a silicon substrate cut from the inclined surface 616 shown in FIG. 6A, where a normal vector 618 is perpendicular to such inclined surface 616 (i.e., perpendicular to the surface of the silicon substrate), and the inclination angle θ 612 is the ratio of the normal vector 618 to the inclined surface 616. <110> The first vector 620 is the direction of the crystal pull. The first vector 620 is also angled with respect to a second vector 622 that extends in the radial direction of the silicon substrate within the inclined surface 616. <110> In addition, <100> A third vector 624 of the direction is orthogonal to the second vector 622. Also, as shown in FIG. 6B, a fourth vector 626 is orthogonal to the normal vector 618, and the angle between the third vector 624 and the fourth vector 626 again constitutes the tilt angle θ 612. FIG. 6B further shows that the second vector 622 and the fourth vector 626 lie in the tilted plane 616. Given a {110}-faceted wafer (silicon substrate), these vectors, including the first vector and the normal vector 618, can be determined by X-ray diffraction, and thus the tilt angle θ 612.

[0042] It should be noted that growing a crystal in the {110} plane is not a straightforward approach. For example, a slight deviation in the crystal orientation may be necessary to prevent dislocation defects in the early stages of crystal growth. Such a small deviation will be within the acceptable range if the resulting silicon substrate exhibits the electrical properties expected in the {110} plane. And if the resulting silicon substrate exhibits more or less the electrical properties expected in the {110} plane, one skilled in the art can understand that a crystal grown with such a small deviation is still a {110} crystal.

[0043] Silicon substrates with {110} planes exhibit improved hole mobility, but suffer from higher haze levels and rougher surfaces, compared to substrates with {100} planes. Therefore, {110} wafers with improved hole mobility should be particularly useful for the GAA FET applications. However, the use of only conventional {110} substrates is unacceptable in terms of surface roughness and high haze levels. In another embodiment of the present invention, silicon substrates are cut from {110} crystals with a tilt angle of ±0.1 to 1.2 degrees, and such tilt angle is achieved by rotating the {110} plane with respect to the Y axis in the XY plane.

[0044] Such a tilt angle of the present invention is suitable for maintaining a desired haze level and a desired level of surface roughness, which are difficult to obtain from a conventional {110} silicon substrate. Thus, by providing a silicon substrate from the {110} plane at a tilt angle, as in the preferred embodiment of the present invention, a higher carrier mobility can be obtained without compromising the surface roughness or haze level. The haze level of the epitaxial layer of the present invention is preferably 1.2 ppm or less. The haze level can be measured using the DWO mode of a SURFSCAN SP2 manufactured by KLA-Tencor.

[0045] 7A and 7B show a method for forming a fiducial notch on a {110} wafer. <110> FIG. 7B shows the notch 702 in the crystal orientation. <100> A notch 704 in the crystal orientation is shown.

[0046] Table 3 shows the measured haze levels (ppm) for various epitaxial wafers with different epitaxial layer thicknesses and tilt angles, each having a {110} silicon substrate.

[0047] [Table 3]

[0048] Table 3 shows that tilt angles between 0.1 degrees and 1.2 degrees result in low haze levels below 0.88 ppm for a thin range of epitaxial layer thicknesses.

[0049] A method for manufacturing an epitaxial wafer according to an embodiment of the present invention is as follows. As shown in FIG. 8, a silicon substrate 802 is placed on a susceptor 804 and rotates in the reaction chamber. A gas inlet 806 receives a silicon source gas 808, such as SiHCl3, and a carrier gas, such as H2. A dopant gas, such as B2H6, can also be introduced through the gas inlet 806. The silicon substrate 802 is heated from above and below and exposed to the silicon source gas for growth of an epitaxial layer. The dopant is contained in the silicon source gas 808 and carried by the carrier gas. The susceptor 804 rotates while an epitaxial layer is grown on the silicon substrate 802.

[0050] The flow rate of the carrier gas is typically 30-100 standard liters per minute (SLM). The flow rate of the silicon source gas is typically 3-20 SLM. The growth temperature is typically fixed between 1100°C and 1175°C. The growth time of the epitaxial layer is 0.1-1.0 min. The rotation speed of the susceptor 804 is preferably 22-70 revolutions per minute (RPM). It has been confirmed that if the rotation speed of the susceptor 804 is slower than the above-mentioned preferred lower limit (22 RPM), the thickness of the epitaxial layer at or near the edge tends to be too thick. On the other hand, if the rotation speed of the susceptor 804 is faster than the above-mentioned preferred upper limit (70 RPM), the thickness of the epitaxial layer at the center of the wafer tends to be too thick. Therefore, it is important to set the rotation speed of the susceptor to 22-70 RPM and to keep the uniformity of the overall thickness of the epitaxial layer to 1.0% or less.

[0051] Table 4 shows the results of how the rotation speed of the susceptor 804 affects the thickness uniformity of the epitaxial layer. In this example, a silicon substrate cut from the {100} face was placed in the reaction chamber and spun to grow a 0.5 μm epitaxial layer. The susceptor 804 was rotated between 22 and 70 RPM.

[0052] [Table 4]

[0053] Table 5 again shows the results of how the rotation speed of the susceptor 804 affects the thickness uniformity of the epitaxial layer. In this example, a silicon substrate cut from the {110} plane at a tilt angle of 1.0 degree was placed in the reaction chamber and rotated to grow a 0.5 μm epitaxial layer. The susceptor 804 was rotated between 22 and 70 RPM.

[0054] [Table 5]

[0055] As shown in Tables 4 and 5, the thickness uniformity of the epitaxial layer can be maintained below 1.0% for both {100} and {110} silicon substrate epitaxial wafers by setting the susceptor rotation speed in the range of 22-70 RPM.

[0056] Traditionally, the growth of an epitaxial layer on an epitaxial wafer is controlled by the growth rate, which is influenced by gas flow rates, and the reaction time to achieve a particular desired thickness. In the present invention, the number of susceptor rotations (how many times the susceptor has rotated) is an integer value to ensure achievement of the desired thickness of the epitaxial layer as well as the desired thickness variation. In one embodiment of the present invention, the integer number of rotations can be determined using the following estimate at the desired level: epitaxial layer thickness (B) = 0.5 μm; Rotation speed of susceptor (D) = 25 rpm; Epitaxial growth rate (A) = 2 μm / min; Growth time (C) = undetermined; If the number of integer rotations (E) is undetermined, then C = B / A = 0.25 minutes, and E can be calculated as D = E / C or E = D x C or 6.25. E is 6.25, the integer closest to 6 rotations.

[0057] Table 6 shows the effect of rotating the susceptor an integer number of rotations compared to a non-integer number of rotations on the variation in thickness of the epitaxial layer. In these examples, epitaxial wafers were used having silicon substrates cut from the {100} plane and epitaxial layers of 0.5 μm thickness. The temperature and gas flow rates were set to achieve an epitaxial growth rate of 2.0 μm / min. In each of Examples 1 and 2, the number of rotations was adjusted to an integer value as described above. The variation in thickness of the epitaxial layer was measured and recorded. In the comparative examples, the conditions were the same except that the number of susceptor rotations was a non-integer value.

[0058] [Table 6]

[0059] Table 7 again shows the effect on epitaxial layer thickness variation of rotating the susceptor an integer number of rotations compared to a non-integer number of rotations. In these examples, epitaxial wafers were used having silicon substrates cut from the {110} plane and epitaxial layers of 0.5 μm thickness. Temperature and gas flow rates were set to achieve an epitaxial growth rate of 2.0 μm / min. In each of Examples 1 and 2, the number of rotations was adjusted to an integer value as above. The epitaxial layer thickness variation was measured and recorded. In the comparative examples, the conditions were the same except for the non-integer number of susceptor rotations.

[0060] [Table 7]

[0061] The results in Tables 6 and 7 show that rotating the susceptor an integer number of times is important to keep the epitaxial layer thickness variation low enough, and also show that both {100} and {110} epitaxial wafers benefit from an integer number of susceptor rotations during epitaxial growth.

[0062] Additionally, Table 8 shows how rotating the susceptor an integer number of times affects the thickness variation of various epitaxial layers. Table 8 summarizes the thickness variation data for {100} epitaxial wafers having three different epitaxial layer thicknesses: 0.3, 0.5, and 1.0 μm.

[0063] [Table 8]

[0064] Table 9 again shows how rotating the susceptor an integer number of times affects the thickness variation of the various epitaxial layers. Table 9 summarizes the thickness variation data for {110} epitaxial wafers having three different epitaxial layer thicknesses: 0.3, 0.5, and 1.0 μm.

[0065] [Table 9]

[0066] The results in Tables 8 and 9 show that regardless of the epitaxial layer thickness, rotating the susceptor an integer number of times keeps the thickness variation significantly lower for various wafer types and epitaxial layer thicknesses.

[0067] Another aspect of the epitaxial wafer of the present invention includes a preferred chamfer width at the top surface of the silicon substrate in the range of 150 μm to 450 μm. Conventionally, the chamfer width of epitaxial wafers tends to be wider than the preferred chamfer width of the present invention, resulting in a smaller overall active area. As shown in FIG. 9, the preferred epitaxial wafer 902 of the present invention includes a thinner thickness of the epitaxial layer 904 and a shorter chamfer width 906 compared to the conventional chamfer width 908 of a conventional epitaxial wafer.

[0068] Figure 9 illustrates in dotted line the conventional thickness of epitaxial layer 910. Typically, conventional epitaxial layers have a thickness of about 2 μm. In contrast, Figure 9 further illustrates the preferred thickness of epitaxial layer 904 (below the dotted line) of the present invention, which is in the range of 0.3 to 1.0 μm.

[0069] The shorter chamfer width of the present invention further improves ESFQR. Table 10 shows the effect of chamfer width on ESFQR. In this experiment, {100} epitaxial wafers with epitaxial layer thicknesses of 0.3 μm to 2.0 μm were used and chamfer widths of 150 μm to 550 μm were tested, respectively. The maximum ESFQR was measured at different chamfer widths for each wafer.

[0070] [Table 10]

[0071] Table 11 shows again the effect of chamfer width on ESFQR. In this experiment, {110} epitaxial wafers with epitaxial layer thicknesses from 0.3 μm to 2.0 μm were used and chamfer widths from 150 μm to 550 μm were tested, respectively. The maximum ESFQR was measured at different chamfer widths for each wafer.

[0072] [Table 11]

[0073] The results in Tables 10 and 11 show that a chamfer width in the range of 150 μm to 450 μm provides a maximum ESFQR below the desired 11.1 nm. More importantly, such a chamfer width range provides an acceptable maximum ESFQR for wafers with various epitaxial layer thicknesses (i.e., in the range of 0.3 to 1.0 μm).

[0074] As previously discussed, the very thin epitaxial layers of the present invention provide flat, smooth surfaces with little or no thickness variation, and such thin epitaxial layers formed on the top surface of a silicon substrate are substantially unaffected by surface irregularities caused by the silicon substrate, such as process induced defects (PIDs) on the top surface of the underlying silicon substrate. Nevertheless, the present invention preferably includes silicon substrates that are substantially free of COP defects having a maximum cross-sectional width of 110 nm or greater. It is particularly preferred that the present invention includes silicon substrates that are substantially free of dislocation clusters and COP defects.

[0075] 10A and 10B show preferred epitaxial wafers of the present invention. FIG. 10A shows an epitaxial wafer having a relatively thin epitaxial layer 1001 between 0.3-1.0 μm in a silicon substrate 1002 that is substantially free of COP defects. FIG. 10B shows a relatively thin epitaxial layer 1001 in a silicon substrate 1002 that has a COP defect 1005 with a cross-sectional width of less than 110 nm and is substantially free of larger sized COP defects, e.g., with a cross-sectional width of 110 nm or more. In contrast, FIG. 10C shows a conventional epitaxial wafer having an undesirably thick epitaxial layer 1003 between 2-4 μm and a COP defect 1006 with a cross-sectional width of 110 nm or more.

[0076] The present disclosure is not limited to the above-mentioned features, and various variations and modifications may be possible without departing from the scope of the present disclosure.< / hkl>

Claims

1. a silicon substrate having one main surface; an epitaxial layer formed on the one main surface, The epitaxial layer is The thickness is 0.3 μm to 1.0 μm, An epitaxial wafer having a thickness variation of 1% or less, defined as the percentage of the absolute value of the difference in thickness at any two symmetrical points of the epitaxial layer 10 mm inside from the outer edge of the epitaxial wafer, divided by the sum of the thicknesses.

2. The epitaxial wafer according to claim 1 , wherein the maximum ESFQR is 11.3 nm or less.

3. 3. The epitaxial wafer of claim 2, wherein the maximum ESFQR is determined at an edge exclusion region of 1 mm to 2 mm.

4. 2. The epitaxial wafer according to claim 1, wherein the chamfer width of the first main surface is 150 μm to 450 μm.

5. A silicon substrate having one principal surface; an epitaxial layer formed on the one main surface, The epitaxial layer is The thickness is 0.3 μm to 1.0 μm, a thickness variation defined as a percentage of the absolute value of the difference in thickness at any two symmetrical points of the epitaxial layer 10 mm inside from the outer edge of the epitaxial wafer divided by the sum of the thicknesses is 1% or less; a maximum ESFQR determined over an edge exclusion region of 1 mm to 2 mm is less than or equal to 11.3 nm; An epitaxial wafer, wherein the chamfer width of the one main surface is 150 μm to 450 μm.

6. The epitaxial wafer according to claim 1 or 5, wherein the silicon substrate is substantially free of dislocation clusters and COP defects.

7. 6. The epitaxial wafer according to claim 1, wherein the silicon substrate is substantially free of COP defects having a maximum cross-sectional width of 110 nm or more.

8. The epitaxial wafer of claim 7 , wherein the silicon substrate contains nitrogen.

9. The silicon substrate is cut from a crystal that forms a {110} plane growing along the Z axis; the silicon substrate forms an X-Y plane perpendicular to the Z-axis; the X-Y plane includes an X axis in the <100> direction and a Y axis in the <110> direction; 6. The epitaxial wafer according to claim 1, wherein the silicon substrate is cut at an inclination angle obtained by rotating the XY plane with respect to the Y axis.

10. 10. The epitaxial wafer according to claim 9, wherein the tilt angle is 0.1 to 1.2 degrees.

11. 11. The epitaxial wafer according to claim 10, wherein the epitaxial layer has a haze level of 1.20 ppm or less.

12. a silicon substrate having one main surface; an epitaxial layer formed on the one main surface, The epitaxial layer is The thickness is 0.3 μm to 1.0 μm, a thickness uniformity defined as a percentage of a difference between a maximum thickness and a minimum thickness at any two pairs of symmetrical points and a center point of the epitaxial layer within 10 mm inside from an outer edge of the epitaxial wafer, divided by the sum of the maximum thickness and the minimum thickness, of 1% or less; a maximum ESFQR determined over an edge exclusion region of 1 mm to 2 mm is less than or equal to 11.3 nm; The epitaxial wafer, wherein the chamfer width of the one main surface is 250 μm to 450 μm.

13. 13. The epitaxial wafer of claim 12, wherein the silicon substrate is substantially free of dislocation clusters and COP defects.

14. 13. The epitaxial wafer of claim 12, wherein the silicon substrate is substantially free of COP defects having a maximum cross-sectional width of 110 nm or more.

15. 15. The epitaxial wafer of claim 14, wherein the silicon substrate comprises nitrogen.

16. The silicon substrate is cut from a crystal that forms a {110} plane growing along the Z axis; the silicon substrate forms an X-Y plane perpendicular to the Z-axis; the X-Y plane includes an X axis in the <100> direction and a Y axis in the <110> direction; The epitaxial wafer according to claim 12 , wherein the silicon substrate is cut at an inclination angle obtained by rotating the X-Y plane with respect to the Y axis.

17. 17. The epitaxial wafer according to claim 16, wherein the tilt angle is 0.1 to 1.2 degrees.

18. 18. The epitaxial wafer of claim 17, wherein the epitaxial layer has a haze level of 1.20 ppm or less.

19. a silicon substrate having one main surface; an epitaxial layer formed on the one main surface, The epitaxial layer is The thickness is 0.3 μm to 1.0 μm, a thickness variation defined as a percentage of the absolute value of the difference in thickness at any two symmetrical points of the epitaxial layer 10 mm inside from the outer edge of the epitaxial wafer divided by the sum of the thicknesses is 1% or less; the silicon substrate is cut from a crystal grown perpendicular to a first vector in a <110> direction; The silicon substrate is an epitaxial wafer orthogonal to the normal vector such that a tilt angle is formed between the first vector and the normal vector.

20. 20. The epitaxial wafer according to claim 19, wherein the tilt angle is 0.1 to 1.2 degrees.

21. the first vector is orthogonal to a second vector in a <110> direction; 20. The epitaxial wafer of claim 19, wherein the second vector is aligned along a radial direction of the silicon substrate.

22. 13. The epitaxial wafer according to claim 1, 5 or 12, wherein the chamfer width of the epitaxial layer is 150 μm to 450 μm.

23. the silicon substrate has a crystal structure formed by X-Y-Z coordinates including an X-axis in a <100> direction, a Y-axis in a <110> direction, an X-Y plane along a {110} plane, a Z-axis in a <110> direction perpendicular to the X-Y plane, and an X-Z plane along a {110} plane perpendicular to the Y-axis; 13. The epitaxial wafer according to claim 1, 5 or 12, wherein the silicon substrate is in a plane including the Y axis and an X' axis displaced in the XZ plane from the X axis by an inclination angle.

24. The epitaxial wafer according to claim 23, wherein the tilt angle is 0.1 to 1.2 degrees.

25. 25. The epitaxial wafer of claim 24, wherein the epitaxial layer has a haze level of 1.20 ppm or less.

26. 25. The epitaxial wafer of claim 24, wherein the epitaxial layer has a haze level of 0.88 ppm or less.

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