Method for manufacturing a semiconductor substrate structure

Abstract

A semiconductor substrate structure that has stable bonding strength and high reliability even in a high-temperature environment, and a power semiconductor device that includes this semiconductor substrate structure are provided. [Solution] A semiconductor substrate structure 1 includes a substrate 10SB, a surface roughness improvement layer 16R disposed on the substrate 10SB, and a single crystal body 12 that is room-temperature bonded or diffusion bonded to the substrate 10SB via the surface roughness improvement layer 16R. The surface roughness improvement layer 16R may be made of the same type of material as the substrate 10SB, and the single crystal body 12 may be made of the same type of material as the surface roughness improvement layer 16R.

Description

[Technical field]

[0001] In this embodiment, Method for manufacturing a semiconductor substrate structure Regarding. [Background technology]

[0002] In recent years, silicon carbide (SiC) semiconductors have been attracting attention because they have a wider band gap energy and high electric field withstand voltage compared to Si and GaAs semiconductors, allowing them to achieve high withstand voltage, large current, low on-resistance, high efficiency, low power consumption, high-speed switching, etc. SiC is also attracting attention from the perspective of environmental protection, as its low power consumption makes it possible to reduce the generation of carbon dioxide (CO2).

[0003] Recently, SiC devices have been applied to many fields of application, such as air conditioners, solar power generation systems, automotive systems, and train and vehicle systems. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent No. 5628530 Summary of the Invention [Problem to be solved by the invention]

[0005] When bonding a single crystal wafer to a porous support substrate, it is difficult to obtain a flat surface of the support substrate due to the influence of recesses on the surface and internal cavities of the support substrate, and therefore it is not possible to obtain sufficient bonding strength. Therefore, a method has been devised in which an adhesive or molten material is cooled and fixed at the interface between the single crystal wafer and the porous support substrate, followed by polishing. However, bonding in a high-temperature atmosphere where the adhesive would decompose is difficult. It is also difficult to use a material that is difficult to form a stable liquid phase as the molten material.

[0006] This embodiment has stable and reliable bonding strength even in high temperature environments. Method for manufacturing a semiconductor substrate structure to provide. [Means for solving the problem]

[0008] In this embodiment One aspect According to the method, a method for manufacturing a semiconductor substrate structure is provided, comprising: preparing a substrate and a single crystal body; forming a surface roughness improvement layer having a thickness of 1 nm to 10 μm on a surface of the substrate; bonding the respective surfaces of the substrate and the single crystal body via the surface roughness improvement layer; and heating and pressurizing the bonded substrate and the single crystal body via the surface roughness improvement layer in a vacuum or a controlled atmosphere in an inert gas to diffusion bond the bonded substrate and the single crystal body, the surface roughness improvement layer including at least one type or a plurality of types of amorphous material selected from the group consisting of silicon carbide, gallium nitride, silicon, aluminum nitride, and gallium oxide; one surface of the surface roughness improvement layer is bonded to the substrate, and the other surface of the surface roughness improvement layer is bonded to the single crystal body; a SiC polycrystalline body is used as the substrate; a SiC epitaxial growth layer is used as the single crystal body; the heating temperature is about 200° C. to 350° C.; and the pressurizing pressure is about 10 MPa to 80 MPa. Effect of the Invention

[0009] According to this embodiment, the bonding strength is stable and highly reliable even in a high-temperature environment. Method for manufacturing a semiconductor substrate structure can be provided. [Brief description of the drawings]

[0010] [Figure 1] FIG. 1 is a schematic cross-sectional view of an ideal structure in which a single crystal body and a polycrystalline body are bonded to each other, illustrating a semiconductor substrate structure according to a basic technology; (a) is a schematic cross-sectional view of a structure in which a polycrystalline body is disposed on a single crystal body; and (b) is a schematic cross-sectional view of an ideal structure in which a single crystal body and a polycrystalline body are bonded to each other. [Diagram 2] FIG. 1 is an explanatory diagram of a method for manufacturing a semiconductor substrate structure according to an embodiment to which the present technology is applied, and is a schematic cross-sectional structural diagram of a SiC polycrystalline body. [Diagram 3]FIG. 2 is an explanatory diagram of a method for manufacturing a semiconductor substrate structure according to an embodiment to which the present technology is applied, and is a schematic cross-sectional structural diagram of a step of forming a surface roughness improving layer on a SiC polycrystalline body. [Figure 4] FIG. 1 is an explanatory diagram of a manufacturing method of a semiconductor substrate structure according to an embodiment to which the present technology is applied, and is a schematic cross-sectional structural diagram of a step of bonding a SiC epitaxial growth layer onto a SiC polycrystalline body via a surface roughness improvement layer. [Diagram 5] 1 is a schematic cross-sectional structural view of a semiconductor substrate structure according to an embodiment to which the present technology is applied; [Figure 6] FIG. 2A is another schematic cross-sectional structural view of a semiconductor substrate structure according to an embodiment to which the present technology is applied; FIG. 2B is yet another schematic cross-sectional structural view of a semiconductor substrate structure according to an embodiment to which the present technology is applied; [Figure 7] 1A is a schematic cross-sectional view of a semiconductor substrate structure according to an embodiment to which the present technology is applied; FIG. 1B is a schematic cross-sectional view of a semiconductor substrate structure according to an embodiment to which the present technology is applied; FIG. [Figure 8] FIG. 11 is an explanation of room temperature bonding applicable to a manufacturing method of a semiconductor substrate structure according to an embodiment of the present technology, including (a) a schematic diagram of a first substrate covered with contaminants, (b) a schematic diagram of a second substrate covered with contaminants, (c) a schematic diagram of an etching process for a surface of the first substrate covered with contaminants, (d) a schematic diagram of an etching process for a surface of the second substrate covered with contaminants, (e) a schematic diagram of a process for forming bonds between a cleaned first substrate active surface and a cleaned second substrate active surface, and (f) a schematic diagram of a process for room temperature bonding of the first substrate active surface and the second substrate active surface. [Figure 9] 1A to 1C are explanatory diagrams of a diffusion bonding method applicable to a manufacturing method of a semiconductor substrate structure according to an embodiment to which the present technology is applied. [Figure 10] 10(a) is a schematic diagram of a state in which a bonding material is disposed on a substrate, (b) is a schematic diagram of a state in which a pressure and heat step is performed in the state of FIG. 10(a) to form a diffusion bond having a void, and (c) is a schematic diagram of a state in which a pressure and heat step is further performed to form a void-free diffusion bond. [Figure 11] 11(a) is a schematic diagram of a state in which a bonding material is disposed on a substrate via an insert metal layer, (b) is a schematic diagram of a state in which a pressure and heat step is performed in the state of FIG. 11(a) to form a solid-state diffusion bond, and (c) is a schematic diagram of a state in which a further pressure and heat step is performed to form a solid-state diffusion bond. [Figure 12] FIG. 1 is an explanatory diagram of the crystalline state of ceramics; (a) is a schematic diagram of a polycrystalline body, and (b) is a schematic diagram of an amorphous non-crystalline solid. [Figure 13] 1 is a schematic diagram of a manufacturing apparatus for a polycrystalline body (a sintered SiC body) of a semiconductor substrate structure according to an embodiment to which the present technology is applied; [Figure 14] 1 is a schematic cross-sectional structural view of a semiconductor substrate structure according to an embodiment to which the present technology is applied; [Figure 15] 1 is a schematic bird's-eye view configuration diagram of a graphite substrate applicable to a semiconductor substrate structure according to an embodiment to which the present technology is applied; [Figure 16] 1A and 1B are schematic bird's-eye view configuration diagrams of an XY-oriented graphite substrate as an example of a graphite substrate applicable to a semiconductor substrate structure according to an embodiment to which the present technology is applied, and FIG. 1B is a schematic bird's-eye view configuration diagram of an XZ-oriented graphite substrate; [Figure 17] 1 is a schematic cross-sectional structural diagram of a Schottky barrier diode manufactured using a semiconductor substrate structure according to an embodiment to which the present technology is applied. [Figure 18] 1 is a schematic cross-sectional structural diagram of a trench-gate MOSFET manufactured using a semiconductor substrate structure according to an embodiment to which the present technology is applied. [Figure 19] 1 is a schematic cross-sectional structural diagram of a planar gate MOSFET manufactured using a semiconductor substrate structure according to an embodiment to which the present technology is applied. [Figure 20] FIG. 2A is a schematic bird's-eye view of a semiconductor substrate structure (wafer) according to a comparative example; FIG. 2B is a schematic bird's-eye view of a semiconductor substrate structure (wafer) according to an embodiment to which the present technology is applied. [Figure 21](a) A schematic bird's-eye view diagram of a unit cell of a 4H—SiC crystal applicable to a SiC epitaxial substrate of a semiconductor substrate structure according to one embodiment of the present technology, (b) a schematic diagram of a two-layer portion of the 4H—SiC crystal, and (c) a schematic diagram of a four-layer portion of the 4H—SiC crystal. [Figure 22] Schematic diagram of the unit cell of the 4H—SiC crystal shown in FIG. 21(a) viewed from directly above the (0001) plane. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Next, the present embodiment will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are given the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between the thickness and planar dimensions of each component is different from the actual relationship. Therefore, the specific thickness and dimensions should be determined with reference to the following description. In addition, it goes without saying that the drawings include parts with different dimensional relationships and ratios.

[0012] The following embodiments are merely examples of devices and methods for embodying the technical ideas, and do not specify the materials, shapes, structures, arrangements, etc. of the components. Various modifications can be made to these embodiments within the scope of the claims.

[0013] A schematic cross-sectional structure of a semiconductor substrate structure according to the basic technology, in which a polycrystalline body is disposed on a single crystal body, is shown in Fig. 1(a), while a schematic cross-sectional structure of an ideal structure in which a single crystal body and a polycrystalline body are bonded is shown in Fig. 1(b).

[0014] 1, the single crystal body is an SiC epitaxial growth layer (SiC-epi) 12, and the polycrystalline body is an SiC sintered body (SiCSB) 10SB. The SiC polycrystalline body 10SB has a plurality of voids 13 and a plurality of SiC polycrystalline grains 15. Although the shape of the voids is shown as an example having a substantially circular shape in FIG. 1, the shape is not limited to this, and various shapes such as an elliptical shape are possible.

[0015] In the case of the SiC polycrystalline body 10SB, as shown in Fig. 1(a), there are depressions on the surface and voids inside, so even if the single crystal body and the polycrystalline body are directly bonded, it is difficult to reduce the surface roughness. Therefore, it is difficult to obtain an ideal semiconductor substrate structure as shown in Fig. 1(b), and the bonding strength is low.

[0016] In a method for manufacturing a semiconductor substrate structure according to an embodiment to which the present technology is applied, a schematic cross-sectional structure of a SiC polycrystalline body 10SB is shown in FIG.

[0017] FIG. 3 shows a schematic cross-sectional structure of one step for forming the surface roughness improving layer 16R on the SiC polycrystalline body 10SB.

[0018] FIG. 4 shows a schematic cross-sectional structure of one step of bonding the SiC epitaxial growth layer 12 onto the SiC polycrystalline body 10SB via the surface roughness improving layer 16R.

[0019] A schematic cross-sectional structure of a semiconductor substrate structure 1 according to an embodiment to which the present technology is applied is shown in FIG.

[0020] In a manufacturing method of a semiconductor substrate structure according to an embodiment of the present technology, the surface of the SiC sintered body 10SB is capped with a surface roughness improving layer 16R made of a CVD film formed by, for example, a chemical vapor deposition (CVD) method, and the surface roughness Ra of the bonding surface is set to, for example, 1 nm or less. As a technology for setting the surface roughness Ra to 1 nm or less, a chemical mechanical polishing (CMP) technology or a mechanical polishing (MP) technology can be applied.

[0021] As shown in Figure 3, by filling the recesses on the surface of the SiC sintered body 10SB with a surface roughness improvement layer 16R and further polishing the surface of the surface roughness improvement layer 16R, it is possible to form a surface in which the voids (holes) 13 inside the surface roughness improvement layer 16R are not exposed.

[0022] 5, a semiconductor substrate structure 1 according to an embodiment of the present technology includes a substrate 10SB, a surface roughness improving layer 16R disposed on the substrate 10SB, and a single crystal body 12 bonded to the substrate 10SB at room temperature via the surface roughness improving layer 16R. Here, the room temperature bonding includes at least one or more types selected from surface activated bonding, plasma activated bonding, and atomic diffusion bonding.

[0023] Furthermore, the substrate 10SB and the single crystal body 12 may be diffusion bonded.

[0024] When room temperature bonding is used, the surface roughness Ra of the substrate surface is set to about 1 nm or less, and as a result, the thickness of the surface roughness improving layer 16R having a different composition is set to about 1 nm to 10 μm.

[0025] When using diffusion bonding, the surface roughness of the substrate surface may be rough depending on the material and bonding temperature. The thickness of the surface roughness improvement layer 16R, which has a different composition gradient due to atomic diffusion in order to utilize atomic diffusion, is about 1 nm to 10 μm.

[0026] The single crystal body 12 may be a single crystal wafer or an epitaxially grown layer.

[0027] Furthermore, the single crystal body 12 may comprise at least one type or a plurality of types selected from the group consisting of Group IV element semiconductors, Group III-V compound semiconductors, and Group II-VI compound semiconductors.

[0028] Furthermore, the single crystal body 12 may include at least one type or a plurality of types selected from the group consisting of silicon carbide, gallium nitride, silicon, aluminum nitride, and gallium oxide.

[0029] The substrate 10SB may also include at least one or more types of sintered bodies selected from the group consisting of sintered bodies, BN, AlN, Al2O3, Ga2O3, diamond, carbon, and graphite. Here, the sintered bodies may include at least one or more types of sintered bodies selected from the group consisting of IV group element semiconductors, III-V group compound semiconductors, and II-VI group compound semiconductors. The sintered bodies may also include at least one or more types of sintered bodies selected from the group consisting of silicon carbide, gallium nitride, silicon, aluminum nitride, and gallium oxide.

[0030] The surface roughness improving layer 16R may include a CVD film formed by a CVD method.

[0031] The surface roughness improving layer 16R may be a film formed by a sol-gel method or a dip method.

[0032] Moreover, the surface roughness improving layer 16R may be made of the same material as the substrate 10SB.

[0033] Furthermore, the single crystal body 12 may be provided with the same type of material as the surface roughness improving layer 16R.

[0034] The surface roughness improving layer 16R may also include a metal layer.

[0035] Here, the metal layer may comprise at least one or more types selected from the group consisting of Al, Co, Ni, Nb, Mo, Ru, Rh, Pd, Ag, Ta, W, Re, Os, Ir, Pt, and Au.

[0036] The surface roughness improving layer 16R may include at least one type or a plurality of types of amorphous materials selected from the group consisting of Group IV element semiconductors, Group III-V compound semiconductors, and Group II-VI compound semiconductors.

[0037] The surface roughness improving layer 16R may include at least one type or a plurality of types of amorphous materials selected from the group consisting of silicon carbide, gallium nitride, silicon, aluminum nitride, and gallium oxide.

[0038] The surface roughness improving layer 16R may have a thickness of 1 nm or more.

[0039] In one embodiment of a semiconductor substrate structure to which the present technology is applied, a surface roughness improvement layer is formed by a chemical reaction without using an adhesive or molten material, making it possible to form the surface roughness improvement layer from the same type of material as the substrate material.

[0040] In the semiconductor substrate structure according to an embodiment to which the present technology is applied, a material that is stable at high temperatures can be used. For example, SiC can be used because it does not melt or decompose even in high-temperature semiconductor processes.

[0041] In a semiconductor substrate structure according to one embodiment to which the present technology is applied, it is possible to use the same material as the material to be joined, eliminating the need for differences or adjustments in thermal expansion coefficient, electrical conductivity, thermal conductivity, and mechanical properties, thereby enabling improved properties, shorter development time, and improved reliability.

[0042] A schematic cross-sectional structure of a semiconductor substrate structure according to one embodiment of the present technology is shown in FIG. 6(a), and another schematic cross-sectional structure of the semiconductor substrate structure is shown in FIG. 6(b).

[0043] 6(a) and 6(b) show an example in which the epitaxial growth layer 12 is a SiC epitaxial growth layer, and the substrate 10SB is a SiC sintered body 10SB. Furthermore, in the example of FIG. 6(a), the SiC sintered body 10SB is disposed on a support substrate 10SU.

[0044] The support substrate 10SU may include at least one or more types of sintered bodies selected from the group consisting of sintered bodies, BN, AlN, Al2O3, Ga2O3, diamond, carbon, and graphite. Here, the sintered bodies constituting the support substrate 10SU may include at least one or more types of sintered bodies selected from the group consisting of IV group element semiconductors, III-V group compound semiconductors, and II-VI group compound semiconductors. In addition, the sintered bodies may include at least one or more types of sintered bodies selected from the group consisting of silicon carbide, gallium nitride, silicon, aluminum nitride, and gallium oxide.

[0045] As shown in FIGS. 6(a) and 6(b), the substrate 10SB and the epitaxial growth layer 12 are bonded at room temperature or by diffusion bonding via a surface roughness improvement layer (SRI) 16R.

[0046] In a semiconductor substrate structure according to one embodiment to which the present technology is applied, a SiC polycrystalline body and a SiC epitaxial growth layer can be bonded via a surface roughness improvement layer, and a stable bond can be formed even in a high-temperature environment in which the adhesive decomposes.

[0047] Yet another schematic cross-sectional structure of a semiconductor substrate structure according to an embodiment of the present technology is shown in FIG. 7(a), and yet another schematic cross-sectional structure of the semiconductor substrate structure is shown in FIG. 7(b).

[0048] In the example of Fig. 7(a), the SiC sintered compact 10SB and the SiC epitaxial growth layer (SiC-epi) 12 are room-temperature bonded or diffusion bonded via an amorphous SiC 16RS as a surface roughness improving layer. In the example of Fig. 7(b), the SiC sintered compact 10SB and the SiC epitaxial growth layer 12 are room-temperature bonded or diffusion bonded via a metal layer 16RM as a surface roughness improving layer.

[0049] Here, the metal layer may comprise at least one or more types selected from the group consisting of Al, Co, Ni, Nb, Mo, Ru, Rh, Pd, Ag, Ta, W, Re, Os, Ir, Pt, and Au.

[0050] (Room temperature bonding technology) Room temperature bonding techniques include surface activated bonding, plasma activated bonding, atomic diffusion bonding, etc. Room temperature bonding is a technique in which oxides and adsorbed molecules on solid surfaces are removed by sputtering effect using high speed atomic beams in a vacuum to activate the surface, and then the activated surfaces are brought into contact with each other to form atomic bonds at room temperature. In room temperature bonding, the bonding surfaces are surface treated in a vacuum to activate the surface atoms so that they are more likely to form chemical bonds. Room temperature bonding removes the surface layer that hinders bonding, and directly bonds the bonds of the surface atoms to form strong bonds. Using room temperature bonding, many materials can be bonded at room temperature.

[0051] As semiconductor materials, for example, it is applicable to homojunctions of Si, SiC, GaAs, InP, GaP, InAs, etc., and heterojunctions between these materials. As single crystal oxides, it is applicable to Si / LiNbO3, Si / LiTaO3, Si / Gd3Ga5O 12 , Si / Al2O3 (sapphire), etc. As for metals, it can be applied to Au, Pt, Ag, Cu, Al, Sn, Pb, Zn, solder bulk materials, foils, bumps, etc. In addition, it can be applied to film materials made of Au, Pt, Cu, and Al on a substrate. As for metal / ceramic structures, it can be applied to Al dissimilar material joining such as Al / Al2O3, Al / silicon nitride, Al / SiC, and Al / AlN.

[0052] In room temperature bonding technology, it is necessary that the surfaces to be bonded are clean and atomically smooth. Therefore, it is desirable that the surface roughness Ra of the surfaces to be bonded is, for example, 1 nm or less. As a technology for achieving a surface roughness Ra of 1 nm or less, CMP technology and MP technology can be applied. In addition, a high-speed atomic beam irradiation technology of argon neutralized ion beams may also be applied.

[0053] To remove the surface layer, for example, sputter etching using an ion beam or plasma can be applied. After sputter etching, the surface is in a state where it easily reacts with surrounding gas molecules. An inert gas such as argon is used for the ion beam, and the process is carried out in a vacuum chamber evacuated to a high vacuum. After sputter etching, the surface where atoms with bonds are exposed is in an active state where they bond strongly with other atoms, and by bonding these atoms, strong bonds can be obtained at room temperature.

[0054] This is an explanation of room temperature bonding applicable to a manufacturing method of a semiconductor substrate structure according to one embodiment of the present technology, in which a first substrate 200 covered with a contaminant layer 200C is shown diagrammatically as in FIG. 8(a), and a second substrate 300 covered with a contaminant layer 300C is shown diagrammatically as in FIG. 8(b).

[0055] The etching process of the first substrate surface covered with the contaminant layer 200C is shown in schematic form in Fig. 8(c), and the etching process of the second substrate surface covered with the contaminant layer 300C is shown in schematic form in Fig. 8(d). Here, the etching process is performed by irradiating a fast atomic beam from a fast argon ion beam generator 400.

[0056] Furthermore, the state in which bonds BD are formed between the cleaned first substrate active surface and the cleaned second substrate active surface is shown in schematic form in Fig. 8(e), and the process in which the first substrate active surface and the second substrate active surface are bonded at room temperature is shown in schematic form in Fig. 8(f). All the processes in Fig. 8(c) to Fig. 8(f) are carried out in a high vacuum state.

[0057] Here, the first substrate may be, for example, an epitaxial growth layer 12 of a semiconductor substrate structure 1 according to an embodiment to which the present technology is applied, and the second substrate may be, for example, a substrate 10 of a semiconductor substrate structure 1 according to an embodiment to which the present technology is applied.

[0058] In addition, in the room temperature bonding technique, it is also possible to dispose a surface roughness improvement layer between the cleaned first substrate active surface and the cleaned second substrate active surface, and bond the first substrate active surface and the second substrate active surface at room temperature via the surface roughness improvement layer. The surface roughness improvement layer may comprise a CVD film formed by a CVD method. The surface roughness improvement layer may comprise the same type of material as the substrate. The bonded layer may comprise the same type of material as the surface roughness improvement layer. The surface roughness improvement layer may be made of amorphous SiC or a metal layer.

[0059] According to the method for manufacturing a semiconductor substrate structure according to an embodiment to which the present technology is applied, damage to the bonding interface is small, so that productivity due to high yield can be obtained.

[0060] (Diffusion bonding technology) Diffusion bonding is a technique in which base materials are bonded together, pressurized to a degree that minimizes plastic deformation at a temperature below the melting point of the base materials, and bonded using the diffusion of atoms that occurs at the bonding surface.

[0061] An explanatory diagram of a diffusion bonding method applicable to a manufacturing method of a semiconductor substrate structure according to an embodiment to which the present technology is applied is shown in FIG.

[0062] In diffusion bonding, the materials to be bonded are brought into close contact with each other and heated and pressurized in a controlled atmosphere such as a vacuum or an inert gas. The heating temperature TH is, for example, about 200° C. to 350° C., and the pressurizing pressure P is, for example, about 10 MPa to 80 MPa.

[0063] The example shown in Fig. 9 illustrates an example in which the SiC polycrystalline body 10SB and the SiC epitaxial growth layer 12 are diffusion-bonded by applying heat and pressure to each other. The example shown in Fig. 9 illustrates an example in which a void VD is present at the bonding interface.

[0064] In the description of a diffusion bonding method applicable to a method for manufacturing a semiconductor substrate structure according to an embodiment of the present technology, a SiC polycrystalline body 10SB is used as a substrate, and a SiC epitaxial growth layer 12 is disposed on the SiC polycrystalline body 10SB as a bonding material, as shown in FIG. 10(a). The SiC polycrystalline body 10SB includes a plurality of SiC polycrystalline grains 15.

[0065] The structure of Fig. 10(a) to which a pressure and heat process has been carried out is shown diagrammatically in Fig. 10(b), and the structure of Fig. 10(b) to which a pressure and heat process has been further carried out and diffusion bonding has progressed is shown diagrammatically in Fig. 10(c). Fig. 10(b) is an example in which voids are formed at the diffusion bonding interface, and Fig. 10(c) is an example in which a void-free diffusion bond has been formed. As shown in Figs. 10(a) to 10(c), in diffusion bonding, the voids in the bond disappear as bonding progresses.

[0066] In addition, in the diffusion bonding, it is also possible to bond the substrate and the bonding material via the surface roughness improving layer 16R. As the surface roughness improving layer 16R, amorphous SiC 16RS may be applied between the bonding surfaces to promote bonding as shown in Fig. 7(a), or a metal layer 16RM may be applied as shown in Fig. 7(b). This metal layer 16RM is called an insert metal layer.

[0067] In the solid-phase diffusion bonding method applicable to the manufacturing method of the semiconductor substrate structure according to the embodiment of the present technology, a structure in which a bonding material is disposed on a substrate via an insert metal layer 16RM is illustrated in schematic form as shown in Fig. 11(a). A SiC polycrystalline body 10SB is used as the substrate, and a SiC epitaxial growth layer 12 is used as the bonding material.

[0068] The structure in Fig. 11(a) where a pressure and heat step is performed to form solid-state diffusion bonding is shown typically in Fig. 11(b), and the structure in Fig. 11(b) where a pressure and heat step is further performed to advance solid-state diffusion bonding is shown typically in Fig. 11(c). In solid-state diffusion bonding, the insert metal layer 16RM is bonded in a solid state.

[0069] In diffusion bonding and solid-state diffusion bonding, the bonding process is promoted and the cleaning and bonding of the bonding surfaces proceed simultaneously. Both the cleaning and bonding processes in diffusion bonding are due to the diffusion phenomenon.

[0070] When amorphous SiC16RS is used as the surface roughness improving layer, amorphous SiC melts to form a bond, so liquid phase diffusion bonding or TLP (Transient Liquid Phase Diffusion Bonding) bonding is formed.

[0071] (Crystalline state of ceramics) An explanatory diagram of the crystalline state of ceramics, where an example of a polycrystalline body is represented typically as shown in Fig. 12(a) and an example of an amorphous non-crystalline solid is represented typically as shown in Fig. 12(b). Here, the crystalline state of a SiC polycrystalline body is a crystalline solid and is represented typically as in Fig. 12(a), while the crystalline state of amorphous SiC is an amorphous solid and is represented typically as in Fig. 12(b).

[0072] (SiC sintered body manufacturing equipment) A polycrystalline body (a SiC sintered body) manufacturing apparatus 500 for a semiconductor substrate structure according to an embodiment to which the present technology is applied is shown in schematic form in Fig. 13. An interior 500A of the polycrystalline body (a SiC sintered body) manufacturing apparatus 500 is in a vacuum atmosphere of about several Pa or is replaced with Ar / N2 gas.

[0073] The polycrystalline body (sintered SiC body) manufacturing apparatus 500 employs a solid compression sintering method using hot press sintering (HP). A graphite sintering mold (graphite die) 900 filled with powder or solid SiC polycrystalline body material 940 is heated while being pressurized. A thermocouple or radiation thermometer 920 is housed in the graphite die 900.

[0074] The graphite die 900 is connected to the pressure shafts 600A and 600B via the graphite bunches 800A and 800B and the graphite spacers 700A and 700B. The SiC polycrystalline material 940 is pressurized and heated by applying pressure between the pressure shafts 600A and 600B. The heating temperature is, for example, about 200° C. to 350° C., and the pressing pressure P is, for example, up to about 50 MPa. Note that spark plasma sintering (SPS) may be used instead of hot press sintering (HP).

[0075] According to the semiconductor substrate structure polycrystalline body (SiC sintered body) manufacturing apparatus 500 according to one embodiment to which the present technology is applied, the heating range is limited, so that it is possible to heat and cool more quickly (several minutes to several hours) than with atmospheric heating such as an electric furnace. By applying pressure and raising the temperature rapidly, it is possible to manufacture a dense SiC sintered body in which grain growth is suppressed. In addition to sintering, the present technology is also applicable to sinter bonding, porous body sintering, etc.

[0076] (Graphite substrate) 14, a semiconductor substrate structure 1 according to an embodiment to which the present technology is applied includes a graphite substrate 10GF, a surface roughness improving layer 16R disposed thereon, and a single crystal body 12 bonded to the graphite substrate 10GF at room temperature via the surface roughness improving layer 16R. Here, the room temperature bonding includes at least one or more types selected from surface activated bonding, plasma activated bonding, and atomic diffusion bonding.

[0077] Furthermore, the graphite substrate 10GF and the single crystal body 12 may be diffusion bonded.

[0078] When room temperature bonding is used, the surface roughness Ra of the graphite substrate 10GF surface is set to about 1 nm or less, and as a result, the thickness of the surface roughness improving layer 16R having a different composition is set to about 1 nm to 10 μm.

[0079] When using diffusion bonding, the surface roughness may be rough depending on the material and bonding temperature. The thickness of the surface roughness improvement layer 16R, which has a different composition gradient due to atomic diffusion in order to utilize atomic diffusion, is about 1 nm to 10 μm.

[0080] The single crystal body 12 may be a single crystal wafer or an epitaxially grown layer.

[0081] Furthermore, the single crystal body 12 may comprise at least one type or a plurality of types selected from the group consisting of Group IV element semiconductors, Group III-V compound semiconductors, and Group II-VI compound semiconductors.

[0082] Furthermore, the single crystal body 12 may include at least one type or a plurality of types selected from the group consisting of silicon carbide, gallium nitride, silicon, aluminum nitride, and gallium oxide.

[0083] The substrate 10SB may also include at least one or more types of sintered bodies selected from the group consisting of sintered bodies, BN, AlN, Al2O3, Ga2O3, diamond, carbon, and graphite. Here, the sintered bodies may include at least one or more types of sintered bodies selected from the group consisting of IV group element semiconductors, III-V group compound semiconductors, and II-VI group compound semiconductors. The sintered bodies may also include at least one or more types of sintered bodies selected from the group consisting of silicon carbide, gallium nitride, silicon, aluminum nitride, and gallium oxide.

[0084] The surface roughness improving layer 16R may include a CVD film formed by a CVD method.

[0085] The surface roughness improving layer 16R may be a film formed by a sol-gel method or a dip method.

[0086] Moreover, the surface roughness improving layer 16R may be made of the same type of material as the graphite substrate 10GF.

[0087] The single crystal body 12 may be made of the same material as the surface roughness improving layer 16R.

[0088] Here, the surface roughness improving layer 16R may include a metal layer.

[0089] The metal layer may comprise at least one or more layers selected from the group consisting of Al, Co, Ni, Nb, Mo, Ru, Rh, Pd, Ag, Ta, W, Re, Os, Ir, Pt, and Au.

[0090] The surface roughness improving layer 16R may include at least one type or a plurality of types of amorphous materials selected from the group consisting of Group IV element semiconductors, Group III-V compound semiconductors, and Group II-VI compound semiconductors.

[0091] The surface roughness improving layer 16R may include at least one type or a plurality of types of amorphous materials selected from the group consisting of silicon carbide, gallium nitride, silicon, aluminum nitride, and gallium oxide.

[0092] A graphite substrate 10GF applicable to a semiconductor substrate structure 1 according to an embodiment to which the present technology is applied has a laminated structure of graphite sheets GS1·GS2·GS3·...·GSn, as shown in Fig. 15. The graphite sheets GS1·GS2·GS3·...·GSn on each surface of the n-layer structure have a large number of hexagonal covalent bonds in one laminated crystal structure, and the graphite sheets GS1·GS2·GS3·...·GSn on each surface are bonded to each other by van der Waals forces.

[0093] Graphite substrate 10GF, which is a carbon-based anisotropic heat transfer material, is a layered crystal of a hexagonal mesh structure of carbon atoms and has anisotropic thermal conductivity. Graphite sheets GS1, GS2, GS3, ..., GSn shown in Figure 15 have greater thermal conductivity (higher thermal conductivity) in the crystal plane direction (XY plane) than in the thickness direction along the Z axis.

[0094] As an example of a graphite substrate 10GF applicable to a semiconductor substrate structure 1 according to an embodiment to which the present technology is applied, a schematic bird's-eye view of an XY-oriented graphite substrate 10GF(XY) is shown in FIG. 16(a), and a schematic bird's-eye view of an XZ-oriented graphite substrate 10GF(XZ) is shown in FIG. 16(b).

[0095] In the graphite substrate 10GF, two types of graphite substrates with different orientations, 10GF(XY) and 10GF(XZ), can be used.

[0096] Graphite substrate 10GF includes graphite substrate 10GF(XY) having XY orientation (first orientation) with higher thermal conductivity in the surface direction than in the thickness direction, and graphite substrate 10GF(XZ) having XZ orientation (second orientation) with higher thermal conductivity in the thickness direction than in the surface direction. As shown in Fig. 16(a), graphite substrate 10GF(XY) having XY orientation has thermal conductivity of, for example, X=1500 (W / mK), Y=1500 (W / mK), and Z=5 (W / mK). On the other hand, graphite substrate 10GF(XZ) having XZ orientation has thermal conductivity of, for example, X=1500 (W / mK), Y=5 (W / mK), and Z=1500 (W / mK), as shown in Fig. 16(b).

[0097] The semiconductor substrate structure 1 according to the embodiment to which the present technology is applied can be used, for example, in the manufacture of various SiC semiconductor elements. In the following, as examples of such elements, a SiC Schottky barrier diode (SBD), a SiC trench gate (T: Trench) type metal oxide semiconductor field effect transistor (MOSFET), and a SiC planar gate type MOSFET are shown.

[0098] (SiC-SBD) 17, a SiC-SBD 21 fabricated using a semiconductor substrate structure according to an embodiment of the present technology includes a semiconductor substrate structure 1 made of a SiC sintered body 10SB and a SiC epitaxial growth layer 12. A surface roughness improving layer 16R is provided between the SiC sintered body 10SB and the SiC epitaxial growth layer 12.

[0099] The SiC sintered body 10SB is + type (impurity density is, for example, about 1×10 18 cm -3 ~Approx. 1×10 21 cm -3 ) and the SiC epitaxial growth layer 12 is doped with n - type (impurity density is, for example, about 5×1014 cm -3 ~Approx. 5×10 16 cm -3 ) is doped.

[0100] Furthermore, the SiC epitaxial growth layer 12 may be made of any one of 4H-SiC, 6H-SiC, 2H-SiC, and 3C-SiC materials.

[0101] Moreover, instead of the SiC sintered body 10SB, any one of BN, AlN, Al2O3, Ga2O3, diamond, carbon, and graphite may be used.

[0102] As the n-type doping impurity, for example, N (nitrogen), P (phosphorus), As (arsenic), etc. can be used.

[0103] As the p-type doping impurity, for example, TMA or the like can be applied.

[0104] The back surface of the SiC sintered body 10SB is provided with a cathode electrode 22 so as to cover the entire back surface.

[0105] In addition, a surface 100 (e.g., a (0001) Si surface) of the SiC epitaxial growth layer 12 has a contact hole 24 that exposes a portion of the SiC epitaxial growth layer 12 as an active region 23, and a field insulating film 26 is formed in a field region 25 surrounding the active region 23.

[0106] The field insulating film 26 is made of SiO2 (silicon oxide), but may be made of other insulators such as silicon nitride (SiN). An anode electrode 27 is formed on the field insulating film 26, and the anode electrode 27 is connected to an anode terminal A.

[0107] A p-type JTE (Junction Termination Extension) structure 28 is formed in the vicinity of the surface 100 (surface layer portion) of the SiC epitaxial growth layer 12 so as to be in contact with the anode electrode 27. The JTE structure 28 is formed along the contour of the contact hole 24 so as to straddle the inside and outside of the contact hole 24 of the field insulating film 26.

[0108] (SiC-TMOSFET) A trench-gate MOSFET 31 fabricated using a semiconductor substrate structure according to an embodiment to which the present technology is applied includes a semiconductor substrate structure 1 made of a SiC sintered body 10SB and a SiC epitaxial growth layer 12, as shown in Fig. 18. A surface roughness improving layer 16R is provided between the SiC sintered body 10SB and the SiC epitaxial growth layer 12.

[0109] The SiC sintered body 10SB is + type (impurity density is, for example, about 1×10 18 cm -3 ~Approx. 1×10 21 cm -3 ) and the SiC epitaxial growth layer 12 is doped with n - type (impurity density is, for example, about 5×10 14 cm -3 ~Approx. 5×10 16 cm -3 ) is doped.

[0110] Furthermore, the SiC epitaxial growth layer 12 may be made of any one of 4H-SiC, 6H-SiC, 2H-SiC, and 3C-SiC materials.

[0111] Moreover, instead of the SiC sintered body 10SB, any one of BN, AlN, Al2O3, Ga2O3, diamond, carbon, and graphite may be used.

[0112] As the n-type doping impurity, for example, N (nitrogen), P (phosphorus), As (arsenic), etc. can be used.

[0113] As the p-type doping impurity, for example, TMA or the like can be applied.

[0114] The back surface ((000-1) C surface) of the SiC sintered body 10SB is provided with a drain electrode 32 so as to cover the entire area thereof.

[0115] In the vicinity (surface layer) of the surface 100 ((0001) Si surface) of the SiC epitaxial growth layer 12, p-type (impurity density is, for example, about 1×10 16 cm -3 ~Approx. 1×10 19 cm -3 In the SiC epitaxial growth layer 12, the portion on the SiC sintered compact 10SB side with respect to the body region 33 is maintained in the state of the SiC epitaxial growth layer, n - The drain region 34(12) is of the type.

[0116] A gate trench 35 is formed in the SiC epitaxial growth layer 12. The gate trench 35 penetrates the body region 33 from the surface 100 of the SiC epitaxial growth layer 12, and reaches the drain region 34 at its deepest portion.

[0117] A gate insulating film 36 is formed on the inner surface of the gate trench 35 and on the surface 100 of the SiC epitaxial growth layer 12 so as to cover the entire inner surface of the gate trench 35. The inside of the gate insulating film 36 is filled with, for example, polysilicon, so that a gate electrode 37 is embedded in the gate trench 35. A gate terminal G is connected to the gate electrode 37.

[0118] The surface layer of the body region 33 includes n-type GaN layers that form part of the side surface of the gate trench 35. + A source region 38 of the type is formed.

[0119] The SiC epitaxial growth layer 12 has p +type (impurity density is, for example, about 1×10 18 cm -3 ~Approx. 1×10 21 cm -3 ) a body contact region 39 is formed.

[0120] An interlayer insulating film 40 made of SiO2 is formed on the SiC epitaxial growth layer 12. A source electrode 42 is connected to the source region 38 and the body contact region 39 via a contact hole 41 formed in the interlayer insulating film 40. A source terminal S is connected to the source electrode 42.

[0121] By applying a predetermined voltage (a voltage equal to or higher than the gate threshold voltage) to the gate electrode 37 while a predetermined potential difference is generated between the source electrode 42 and the drain electrode 32 (between the source and drain), a channel can be formed in the body region 33 near the interface with the gate insulating film 36 by the electric field from the gate electrode 37. This allows a current to flow between the source electrode 42 and the drain electrode 32, turning the SiC-TMOSFET 31 on.

[0122] (SiC planar gate MOSFET) A planar gate MOSFET 51 fabricated using a semiconductor substrate structure 1 according to an embodiment to which the present technology is applied includes a semiconductor substrate structure 1 made of a SiC sintered body 10SB and a SiC epitaxial growth layer 12, as shown in Fig. 19. A surface roughness improving layer 16R is provided between the SiC sintered body 10SB and the SiC epitaxial growth layer 12.

[0123] The SiC sintered body 10SB is + type (impurity density is, for example, about 1×10 18 cm -3 ~Approx. 1×10 21 cm -3 ) and the SiC epitaxial growth layer 12 is doped with n - type (impurity density is, for example, about 5×10 14 cm -3 ~Approx. 5×10 16 cm-3 ) is doped.

[0124] Furthermore, the SiC epitaxial growth layer 12 may be made of any one of 4H-SiC, 6H-SiC, 2H-SiC, and 3C-SiC materials.

[0125] Moreover, instead of the SiC sintered body 10SB, any one of BN, AlN, Al2O3, Ga2O3, diamond, carbon, and graphite may be used.

[0126] As the n-type doping impurity, for example, N (nitrogen), P (phosphorus), As (arsenic), etc. can be used.

[0127] As the p-type doping impurity, for example, TMA or the like can be applied.

[0128] A drain electrode 52 is formed on the back surface ((000-1)C surface) of the SiC sintered body 10SB so as to cover the entire area, and a drain terminal D is connected to the drain electrode 52.

[0129] In the vicinity (surface layer) of the surface 100 ((0001) Si surface) of the SiC epitaxial growth layer 12, p-type (impurity density is, for example, about 1×10 16 cm -3 ~Approx. 1×10 19 cm -3 The body region 53 of the SiC epitaxial growth layer 12 is formed in a well shape. The portion of the SiC epitaxial growth layer 12 on the SiC substrate 2 side with respect to the body region 53 is maintained in the state after epitaxial growth, i.e., n - The drain region 54(12) is of the type.

[0130] The surface layer of the body region 53 is + A source region 55 of a type is formed in spaced relation to the periphery of the body region 53 .

[0131] Inside the source region 55, p + type (impurity density is, for example, about 1×10 18cm -3 ~Approx. 1×10 21 cm -3 ) is formed in the body contact region 56. The body contact region 56 penetrates the source region 55 in the depth direction and is connected to the body region 53.

[0132] A gate insulating film 57 is formed on a surface 100 of the SiC epitaxial growth layer 12. The gate insulating film 57 covers a portion of the body region 53 surrounding the source region 55 (the peripheral portion of the body region 53) and the outer periphery of the source region 55.

[0133] A gate electrode 58 made of, for example, polysilicon is formed on the gate insulating film 57. The gate electrode 58 faces the peripheral portion of the body region 53 with the gate insulating film 57 interposed therebetween. A gate terminal G is connected to the gate electrode 58.

[0134] An interlayer insulating film 59 made of SiO2 is formed on the SiC epitaxial growth layer 12. A source electrode 61 is connected to the source region 55 and the body contact region 56 via a contact hole 60 formed in the interlayer insulating film 59. A source terminal S is connected to the source electrode 61.

[0135] By applying a predetermined voltage (a voltage equal to or higher than the gate threshold voltage) to the gate electrode 58 while a predetermined potential difference is generated between the source electrode 61 and the drain electrode 52 (between the source and drain), a channel can be formed in the body region 53 near the interface with the gate insulating film 57 by the electric field from the gate electrode 58. This allows a current to flow between the source electrode 61 and the drain electrode 52, turning the planar gate MOSFET 51 on.

[0136] Although the present embodiment has been described above, the present invention can be embodied in other forms.

[0137] For example, although not shown, a vertical device structure can be manufactured using the semiconductor substrate structure 1 according to an embodiment to which the present technology is applied. That is, the vertical device structure includes a substrate, a surface roughness improving layer disposed on the substrate, a single crystal body that is room-temperature bonded or diffusion bonded to the substrate via the surface roughness improving layer, and a first metal electrode disposed on the substrate surface facing the bonding surface between the substrate and the single crystal body. A vertical power semiconductor device may be formed.

[0138] Also, a vertical power semiconductor device may be formed further comprising a second metal electrode disposed on the surface of the single crystal body opposite to the bonding surface between the substrate and the single crystal body.

[0139] Also, for example, a lateral device structure can be manufactured using the semiconductor substrate structure 1 according to an embodiment to which the present technology is applied. That is, a lateral power semiconductor device may be formed that includes a substrate, a surface roughness improving layer disposed on the substrate, a single crystal body that is room-temperature bonded or diffusion bonded to the substrate via the surface roughness improving layer, and a second metal electrode disposed on the surface of the single crystal body that faces the bonding surface between the substrate and the single crystal body.

[0140] In the above vertical or lateral power semiconductor device, the single crystal body may also include at least one or more types selected from the group consisting of Group IV element semiconductors, Group III-V compound semiconductors, and Group II-VI compound semiconductors, and may also include at least one or more types selected from the group consisting of silicon carbide, gallium nitride, silicon, aluminum nitride, and gallium oxide.

[0141] In the above vertical or lateral power semiconductor device, the substrate may also include at least one or more types of sintered body selected from the group consisting of sintered body, BN, AlN, Al2O3, Ga2O3, diamond, carbon, and graphite. The sintered body may also include at least one or more types of sintered body selected from the group consisting of IV group element semiconductor, III-V group compound semiconductor, and II-VI group compound semiconductor. The sintered body may also include at least one or more types of sintered body selected from the group consisting of silicon carbide, gallium nitride, silicon, aluminum nitride, and gallium oxide.

[0142] For example, although not shown, a MOS capacitor can be manufactured using the semiconductor substrate structure 1 according to an embodiment to which the present technology is applied. In the MOS capacitor, the yield and reliability can be improved.

[0143] Although not shown in the drawings, a bipolar transistor can be manufactured using the semiconductor substrate structure 1 according to an embodiment to which the present technology is applied. In addition, the semiconductor substrate structure 1 according to the embodiment can be used to manufacture SiC-pn diodes, SiC insulated gate bipolar transistors (IGBTs), SiC complementary MOSFETs, and the like.

[0144] A schematic bird's-eye view of a semiconductor substrate structure (wafer) according to a comparative example includes a substrate 10 and an epitaxial growth layer 12 bonded to the substrate 10, as shown in FIG. 20(a).

[0145] 20(b), a schematic bird's-eye view configuration of a semiconductor substrate structure (wafer) according to an embodiment to which the present technology is applied includes a substrate 10, a surface roughness improving layer 16R disposed on the substrate 10, and an epitaxial growth layer 12 bonded to the substrate 10 at room temperature via the surface roughness improving layer 16R. Here, the room temperature bonding includes at least one type or a plurality of types selected from surface activated bonding, plasma activated bonding, and atomic diffusion bonding.

[0146] Alternatively, the substrate 10 and the epitaxially grown layer 12 may be diffusion bonded.

[0147] When room temperature bonding is used, the surface roughness Ra of the substrate surface is set to about 1 nm or less, and as a result, the thickness of the surface roughness improving layer 16R having a different composition is set to about 1 nm to 10 μm.

[0148] When using diffusion bonding, the surface roughness may be rough depending on the material and bonding temperature. The thickness of the surface roughness improving layer 16R is about 1 nm to 10 μm.

[0149] The epitaxial growth layer 12 may comprise at least one type or a plurality of types selected from the group consisting of Group IV element semiconductors, Group III-V compound semiconductors, and Group II-VI compound semiconductors.

[0150] The epitaxial growth layer 12 may comprise at least one or more types selected from the group consisting of silicon carbide, gallium nitride, silicon, aluminum nitride, and gallium oxide.

[0151] The SiC epitaxial growth layer may be made of any one of 4H-SiC, 6H-SiC, 2H-SiC, and 3C-SiC materials.

[0152] The substrate 10 may comprise at least one or more types selected from the group consisting of sintered bodies, BN, AlN, Al2O3, Ga2O3, diamond, carbon, and graphite.

[0153] Here, the sintered body may include at least one type or a plurality of types of sintered bodies selected from the group consisting of Group IV element semiconductors, Group III-V compound semiconductors, and Group II-VI compound semiconductors.

[0154] The sintered body may include at least one type or a plurality of types of sintered bodies selected from the group consisting of silicon carbide, gallium nitride, silicon, aluminum nitride, and gallium oxide.

[0155] The surface roughness improving layer 16R may include a CVD film formed by a CVD method.

[0156] The surface roughness improving layer 16R may be a film formed by a sol-gel method or a dipping method.

[0157] Moreover, the surface roughness improving layer 16R may be made of the same material as the substrate 10SB.

[0158] The SiC epitaxial growth layer 12 may be made of the same material as the surface roughness improving layer 16R.

[0159] Here, the surface roughness improving layer 16R may include a metal layer.

[0160] The metal layer may comprise at least one or more layers selected from the group consisting of Al, Co, Ni, Nb, Mo, Ru, Rh, Pd, Ag, Ta, W, Re, Os, Ir, Pt, and Au.

[0161] The surface roughness improving layer 16R may include at least one type or a plurality of types of amorphous materials selected from the group consisting of Group IV element semiconductors, Group III-V compound semiconductors, and Group II-VI compound semiconductors.

[0162] The surface roughness improving layer 16R may include at least one type or a plurality of types of amorphous materials selected from the group consisting of silicon carbide, gallium nitride, silicon, aluminum nitride, and gallium oxide.

[0163] The SiC epitaxial growth layer 12 may be made of, for example, 4H—SiC and have an off angle of less than 4 degrees.

[0164] The substrate (SiC sintered body) 10 has a thickness of, for example, about 200 μm to about 500 μm, and the SiC epitaxial growth layer 12 has a thickness of, for example, about 4 μm to about 100 μm.

[0165] (Example of crystal structure) A schematic bird's-eye view of a unit cell of a 4H-SiC crystal applicable to SiC epitaxial growth layer 12 is shown in FIG. 21(a), a schematic structure of a two-layer portion of the 4H-SiC crystal is shown in FIG. 21(b), and a schematic structure of a four-layer portion of the 4H-SiC crystal is shown in FIG. 21(c).

[0166] Moreover, a schematic configuration of a unit cell of the crystal structure of 4H—SiC shown in FIG. 21(a) viewed from directly above the (0001) plane is expressed as shown in FIG.

[0167] As shown in Fig. 21(a) to Fig. 21(c), the crystal structure of 4H-SiC can be approximated by a hexagonal system, in which one Si atom is bonded to four C atoms. The four C atoms are located at the four vertices of a regular tetrahedron with a Si atom at the center. Of these four C atoms, one Si atom is located in the

[0001] axial direction relative to the C atom, and the other three C atoms are located on the [000-1] axial side relative to the Si atom. In Fig. 21(a), the off-angle θ is, for example, about 4 degrees or less.

[0168] The

[0001] and [000-1] axes are aligned along the axial direction of the hexagonal prism, and the surface normal to the

[0001] axis (top surface of the hexagonal prism) is the (0001) surface (Si surface). On the other hand, the surface normal to the [000-1] axis (bottom surface of the hexagonal prism) is the (000-1) surface (C surface).

[0169] In addition, the directions that are perpendicular to the

[0001] axis and pass through non-adjacent vertices of the hexagonal prism when viewed from directly above the (0001) face are the a1 axis [2-1-10], a2 axis [-12-10], and a3 axis [-1-120], respectively.

[0170] As shown in Figure 22, the direction passing through the vertex between the a1 axis and the a2 axis is the [11-20] axis, the direction passing through the vertex between the a2 axis and the a3 axis is the [-2110] axis, and the direction passing through the vertex between the a3 axis and the a1 axis is the [1-210] axis.

[0171] Between each of the six axes passing through each vertex of the hexagonal prism, the axes that are inclined at an angle of 30° to the axes on both sides and that are normal to each side of the hexagonal prism are, in order clockwise from between the a1 axis and the [11-20] axis, the [10-10] axis, the [1-100] axis, the [0-110] axis, the [-1010] axis, the [-1100] axis, and the [01-10] axis. Each face (side face of the hexagonal prism) with these axes as normals is a crystal plane perpendicular to the (0001) plane and the (000-1) plane.

[0172] A power semiconductor device including the semiconductor substrate structure according to this embodiment may include any of a SiC-based, Si-based, GaN-based, AlN-based, and gallium oxide-based IGBT, a diode, a MOSFET, and a thyristor.

[0173] A power semiconductor device including the semiconductor substrate structure of this embodiment may have any of the following configurations: a one-in-one module, a two-in-one module, a four-in-one module, a six-in-one module, a seven-in-one module, an eight-in-one module, a twelve-in-one module, or a fourteen-in-one module.

[0174] According to the present embodiment, it is possible to provide a semiconductor substrate structure having an interface structure that is stable even at high temperatures, and a power semiconductor device including this semiconductor substrate structure.

[0175] [Other embodiments] As described above, although several embodiments have been described, the descriptions and drawings forming a part of the disclosure are illustrative and should not be understood as limiting. From this disclosure, various alternative embodiments, examples and operating techniques will become apparent to those skilled in the art.

[0176] In this way, this embodiment includes various embodiments not described here. [Industrial Applicability]

[0177] The semiconductor substrate structure of this embodiment and the power semiconductor device including this semiconductor substrate structure can be used in various semiconductor module technologies such as IGBT modules, diode modules, and MOS modules (Si, SiC, GaN, AlN, gallium oxide), and can be applied to a wide range of application fields such as power modules for inverter circuits that drive electric motors used as power sources for electric vehicles (including hybrid vehicles), trains, industrial robots, etc., and power modules for inverter circuits that convert power generated by solar cells, wind turbines, and other power generation devices (particularly private power generation devices) into power from a commercial power source. [Explanation of symbols]

[0178] 1...semiconductor substrate structure, 10...substrate, 10GF...graphite substrate, 10SB...SiC sintered body (SiC polycrystalline body), 12...single crystal body (single crystal wafer, SiC epitaxial growth layer), 13, 16R...surface roughness improvement layer, 16RS...surface roughness improvement layer (amorphous SiC), 16RM...surface roughness improvement layer (metal layer), 21...power semiconductor device (SiC-SBD), 31...power semiconductor device (SiC-TMOSFET), 51...power semiconductor device (SiC-MOSFET), 500...polycrystalline body (SiC sintered body) manufacturing apparatus, 940...SiC polycrystalline body material, GS (GS1·GS2·GS3·...GSn)...graphite sheet, S...source terminal, D...drain terminal, G...gate terminal, A...anode terminal, K...cathode terminal

Claims

1. Providing a substrate and a single crystal body; forming a surface roughness improving layer having a thickness of 1 nm to 10 μm on the surface of the substrate; bringing the surfaces of the substrate and the single crystal body into close contact with each other via the surface roughness improving layer; the substrate and the single crystal body, which are in close contact with each other, are diffusion-bonded through the surface roughness improving layer by heating and pressurizing in a controlled atmosphere of vacuum or inert gas; having the surface roughness improving layer contains at least one or more types of amorphous material selected from the group consisting of silicon carbide, gallium nitride, silicon, aluminum nitride, and gallium oxide; one surface of the surface roughness improving layer is bonded to the substrate, and the other surface of the surface roughness improving layer is bonded to the single crystal body; A SiC polycrystalline body is used as the substrate, and a SiC epitaxial growth layer is used as the single crystal body; A method for manufacturing a semiconductor substrate structure, wherein the heating temperature is about 200° C. to 350° C., and the pressing pressure is about 10 MPa to 80 MPa.

2. A method for manufacturing a semiconductor substrate structure as described in claim 1, wherein the surface roughness improvement layer comprises a film formed by chemical vapor deposition.

3. The method for manufacturing a semiconductor substrate structure described in claim 1, wherein the surface roughness improvement layer comprises a film formed by a sol-gel method or a dip method.

4. A method for manufacturing a semiconductor substrate structure as described in claim 1, wherein the surface roughness improvement layer comprises the same type of material as the substrate.

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