Semiconductor Device

Abstract

To provide a technique capable of improving discharge performance or radiation performance of a protective element (protective circuit) with respect to surge of a long pulse width.SOLUTION: A semiconductor device comprises a protective element consisting of a MOSFET, and the protective element has a multi-layer metal wiring structure. The multi-layer metal wiring structure includes drain connection wiring connected to a drain region of the MOSFET and source connection wiring connected to a source region of the MOSFET. In the same layer of the multi-layer metal wiring structure, in a location where the drain connection wiring and the source connection wiring coexist, any one of the drain connection wiring and the source connection wiring is formed in a granular layout shape.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device, and is a technique that is effective when applied to a semiconductor device that includes a protection element (protection circuit) against surge pulses. [Background technology]

[0002] The semiconductor device includes a protection element against a surge pulse. For example, Japanese Patent Application Laid-Open No. 2020-161721 discloses a semiconductor device of this type. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2020-161721 A Summary of the Invention [Problem to be solved by the invention]

[0004] Semiconductor devices mounted on automotive electronic control units (ECUs) are tested with surge pulse widths that are longer in duration than ESD (Electro-Static Discharge) pulses. Consumer semiconductor devices are also being required to have stronger long pulse resistance.

[0005] An object of the present disclosure is to provide a technique capable of improving the discharge performance or heat dissipation performance of a protection element (protection circuit) against a surge with a long pulse width.

[0006] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0007] A brief summary of representative aspects of this disclosure is as follows.

[0008] A semiconductor device according to one embodiment has a protection element formed of a MOSFET, and the protection element has a multi-layer metal wiring structure. The multi-layer metal wiring structure includes a drain connection wiring connected to a drain region of the MOSFET and a source connection wiring connected to a source region of the MOSFET. In a location where the drain connection wiring and the source connection wiring coexist in the same layer of the multi-layer metal wiring structure, either the drain connection wiring or the source connection wiring is formed in a granular layout shape. Effect of the Invention

[0009] According to the semiconductor device of the above embodiment, it is possible to improve the discharge performance or heat dissipation performance of the protection circuit against a surge with a long pulse width. [Brief description of the drawings]

[0010] [Figure 1] FIG. 1 is a plan view illustrating the layout of a protection circuit according to a comparative example. [Diagram 2] FIG. 2 is a cross-sectional view of the protection circuit taken along line AA' in FIG. [Diagram 3] FIG. 3 is a plan view illustrating the layout of the protection circuit according to the first embodiment. [Figure 4] FIG. 4 is a cross-sectional view of the protection circuit taken along line AA' in FIG. [Diagram 5] FIG. 5 is a cross-sectional view of the protection circuit taken along line BB' in FIG. [Figure 6] FIG. 6 is a plan view illustrating the layout of a protection circuit according to the second embodiment. [Figure 7] FIG. 7 is a cross-sectional view of the protection circuit taken along line AA' in FIG. [Figure 8] FIG. 8 is a cross-sectional view of the protection circuit taken along line BB' in FIG. [Figure 9] FIG. 9 is a plan view illustrating an example of the arrangement of the second wiring layer M2 in the layout of the protection circuit according to the third embodiment. [Figure 10] FIG. 10 is a plan view illustrating an example of the arrangement of the third wiring layer M3 in the layout of the protection circuit according to the third embodiment. [Figure 11] FIG. 11 is a cross-sectional view of the protection circuit taken along line AA' in FIG. [Figure 12] FIG. 12 is a cross-sectional view of the protection circuit taken along line BB' in FIG. [Figure 13] FIG. 13 is a graph showing the results of measuring the breakdown power of protection elements with different silicon areas when the surge pulse width is within the surge test range for consumer semiconductor devices. [Figure 14] FIG. 14 is a graph showing the results of measuring the breakdown power of protective elements with different silicon areas when the surge pulse width is within the surge test range of an in-vehicle semiconductor device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Hereinafter, comparative examples, embodiments, and examples will be described with reference to the drawings. However, in the following description, the same components are given the same reference numerals and repeated description may be omitted. Note that the drawings may be shown more diagrammatically than the actual embodiment in order to clarify the description, but they are merely examples and do not limit the interpretation of the present invention.

[0012] Before describing the embodiment, a configuration example of the layout of a protection circuit according to a comparative example will be described with reference to Fig. 1 and Fig. 2. Fig. 1 is a plan view illustrating the layout of a protection circuit according to a comparative example. Fig. 2 is a cross-sectional view of the protection circuit along line A-A' in Fig. 1. Fig. 1 depicts a wiring M21 formed by the second wiring layer M2 and a wiring M31 formed by the third wiring layer M3 in the wiring layout of the protection circuit.

[0013] 1 and 2, a MOS protection element 3r constituting a protection circuit 2r has a gate electrode G, a source region S, and a drain region D. The source region S and the drain region D are formed in a silicon semiconductor substrate (SiSub) 1r, and the gate electrode G is formed on the upper side of a gate oxide film (not shown) formed on the surface of the semiconductor substrate 1r.

[0014] The source region S is electrically connected to a fourth wiring M41 formed from a fourth wiring layer M4 via a first via electrode V1, a first wiring M11 formed from a first wiring layer M1, a second via electrode V2, a second wiring M21 formed from a second wiring layer M2, a third via electrode V3, a third wiring M31 formed from a third wiring layer M3, and a fourth via electrode V4. The fourth wiring M41 can be referred to as a bus wiring.

[0015] The drain region D is electrically connected to the third wiring M31 through the first via electrode V1, the first wiring M11, the second via electrode V2, the second wiring M21, and the third via electrode V3. The second wiring M21 and the third wiring M31 to which the drain region D is connected are connected to a pad electrode PAD. The first via electrode V1 can also be referred to as a contact electrode.

[0016] The first to fourth wirings M11 to M41 and the first to fourth via electrodes V1 to V4 are made of metal such as copper (Cu), aluminum (Al), etc. The first to fourth wirings M11 to M41 and the first to fourth via electrodes V1 to V4 are covered with an insulating film 4r (e.g., a silicon oxide film SiO2, etc.) having a relatively low thermal conductivity.

[0017] As shown in Fig. 1, when a surge pulse is applied to the pad electrode PAD, a surge current Is indicated by a dotted arrow flows. When the MOS protection element 3r is an N-type MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), the fourth wiring M41 is at the ground potential (first reference potential) GND. On the other hand, when the MOS protection element 3r is a P-type MOSFET, the fourth wiring M41 is at the power supply potential (second reference potential) VDD (VDD>GND).

[0018] 13 and 14 are graphs showing the results of measuring the breakdown power of protection elements (N-type MOSFETs) with different silicon areas. FIG. 13 shows the measurement results when the surge pulse width is within the surge test range of a consumer semiconductor device, and FIG. 14 shows the measurement results when the surge pulse width is within the surge test range of an in-vehicle semiconductor device. In FIG. 13 and FIG. 14, the vertical axis shows the breakdown power Pf (W) per unit silicon area, and the horizontal axis shows the pulse width (sec) of the surge pulse. The silicon area is small (×1) for 5V-NA, medium (×2) for 5V-NB, and large (×3) for 5V-NC. The number of metal wirings on the drain (D) side is 28 for 5V-NA, 44 for 5V-NB, and 56 for 5V-NC. Here, surge testing of automotive semiconductor devices (also called ECU surge testing) includes tests with test voltage: -150V, pulse width: 2ms, energy: 250mJ, or test voltage: +112V, pulse width: 50μs, energy: 20mJ, etc. Surge testing of consumer semiconductor devices includes tests with test voltage: + / -2kV, pulse width: 150ns, energy: 800nJ, etc.

[0019] As shown in Figure 13, in the time domain TESD of a surge pulse in an ESD (Electro-Static Discharge) test of a consumer semiconductor device, the protection performance per unit Si area is almost the same for 5V-NA, 5V-NB, and 5V-NC.

[0020] On the other hand, in the time domain TECU of the surge pulse in the ECU surge test, when the pulse width of the surge pulse was 20μs or more, a difference in protection performance due to the number of metal wires on the drain side appeared, as shown in Fig. 14. In other words, when the pulse width was 20μs or more, the performance regarding the breakdown power Pf decreased as the number of metal wires on the drain (D) side increased, and it was found that the relationship of the breakdown power Pf values ​​was 5V-NA>5V-NB>5V-NC.

[0021] In summary, the following can be said: (1) As semiconductor devices formed in semiconductor devices become finer and the number of metal wiring layers increases, the performance of protection elements deteriorates significantly due to the heat generated by the metal wiring in response to surges with long pulse widths. (2) In the narrow-pitch metal wiring region, the metal wiring layers (M11-M41, V1-V4) are covered with an interlayer insulating film 4r such as silicon oxide film SiO2, which has low thermal conductivity, and this causes heat to accumulate between adjacent wiring, which is the main cause of the performance degradation of the protection element. Note that the thermal conductivity of copper (Cu) is 403 (W / m·K), and that of aluminum (Al) is 236 (W / m·K). On the other hand, the thermal conductivity of silicon (Si) is 160 (W / m·K), and that of silicon oxide film SiO2 is 1.3 (W / m·K). (3) If the wiring pitch (space between wirings) is increased, the effect of heat accumulation between metal wirings (M11 to M41, etc.) can be reduced, but this increases the Si area of ​​the protection element, resulting in a problem of increased chip cost for the semiconductor device.

[0022] (Embodiment) In order to solve the problems described above, the protection element 3 according to the embodiment of the present disclosure is configured as follows.

[0023] The protection element 3 formed on one main surface of the semiconductor substrate (SiSub) is In order to improve surge resistance against long surge pulse widths (e.g., tens of μs or more), (Here, the case where the protection element 3 is a MOSFET will be described.) In terms of the shape of the metal wiring (M1d to M4d, M1s to M3s) connected to the protection element 3, In the same layer in which a first multilayer connection wiring (for example, also referred to as a drain connection wiring) connected between the pad electrode PAD and the drain region D of the protection element 3 and a second multilayer connection wiring (for example, also referred to as a source connection wiring) connected between the source region S of the protection element 3 and a bus wiring (M41) to which a ground potential GND or a power supply potential VDD is supplied are adjacent, Either the connection wiring to the pad electrode PAD (first connection wiring) or the connection wiring to the bus wiring M41 (second connection wiring) is arranged in a granular layout.

[0024] According to the above layout arrangement, the density of the metal wiring can be reduced without increasing the Si area of ​​the protection element 3. Since the density of the metal wiring can be reduced, it is possible to avoid adverse effects due to heat accumulation in the interlayer insulating film caused by heat generation in the metal wiring region. This makes it possible to improve the discharge performance or heat dissipation performance of the protection element 3 against a surge with a long pulse width. For example, in a surge test with a pulse width of 50 μs, it is possible to improve the surge resistance per unit Si area by 1.5 to 2.0 times compared to the comparative example (see FIGS. 1 and 2).

[0025] When the protection element 3 is composed of a diode and a thyristor (SCR: Silicon Controlled Rectifier), the drain connection wiring and the source connection wiring can be rephrased as the anode connection wiring and the cathode connection wiring. The anode connection wiring is connected to the anode regions of the diode and the thyristor, and the cathode connection wiring is connected to the cathode regions of the diode and the thyristor.

[0026] Each embodiment will be described below with reference to the drawings. EXAMPLES

[0027] Next, a configuration example of the layout of the protection circuit 2 according to the first embodiment will be described with reference to Figs. 3 to 5. Fig. 3 is a plan view illustrating the layout of the protection circuit according to the first embodiment. Fig. 4 is a cross-sectional view of the protection circuit taken along line A-A' in Fig. 3. Fig. 5 is a cross-sectional view of the protection circuit taken along line B-B' in Fig. 3. Fig. 3 illustrates wirings M2s, M2d, and M2p formed by the second wiring layer M2 in the wiring layout of the protection circuit.

[0028] In the first embodiment, in the metal wiring structure of the protection element 3 formed of a MOSFET, only the second source wiring M2s formed of the second wiring layer M2 is granular. The second source wiring M2s is arranged in a granular layout. In other words, the second source wiring M2s is laid out in a dot-like (point-like) layout and is scattered.

[0029] 3, 4, and 5, the MOS protection element 3 constituting the protection circuit 2 has a gate electrode G, a source region S, and a drain region D. The source region S and the drain region D are formed in a silicon semiconductor substrate (SiSub) 1, and the gate electrode G is formed on the upper side of a gate oxide film (not shown) formed on one main surface (front surface) of the semiconductor substrate 1.

[0030] The drain region D is electrically connected to a third drain wiring M3d formed from a third wiring layer M3 through a first drain via electrode V1d, a first drain wiring M1d formed from a first wiring layer M1, a second drain via electrode V2d, a second drain wiring M2d formed from a second wiring layer M2, and a third drain via electrode V3d. The second drain wiring M2d and the third drain wiring M3d to which the drain region D is connected are connected to a pad electrode PAD. The pad electrode PAD is formed from a second pad wiring M2p formed from the second wiring layer M2. The first drain via electrode V1 can also be called a contact electrode. The first connection wiring (also called a drain connection wiring) of the multilayer connected between the pad electrode PAD and the drain region D of the protection element 3 is the first drain via electrode V1d, the first drain wiring M1d, the second drain via electrode V2d, the second drain wiring M2d, the third drain via electrode V3d, and the third drain wiring M3d.

[0031] The source region S is electrically connected to a fourth wiring M41 formed from a fourth wiring layer M4 via a first source via electrode V1s, a first source wiring M1s formed from a first wiring layer M1, a second source via electrode V2s, a second source wiring M2s formed from a second wiring layer M2, a third source via electrode V3s, a third source wiring M3s formed from a third wiring layer M3, and a fourth source via electrode V4s. The fourth wiring M41 can be called a bus wiring. The multi-layer second connection wiring (also called a source connection wiring) connected between the source region S of the protection element 3 and the bus wiring (M41) to which the ground potential GND or the power supply potential VDD is supplied is the first source via electrode V1s, the first source wiring M1s, the second source via electrode V2s, the second source wiring M2s, the third source via electrode V3s, the third source wiring M3s, and the fourth source via electrode V4s.

[0032] The first to fourth wirings (M1s, M1d to M3s, M3d, M41) and the first to fourth via electrodes (V1s, V1d to V4s) are made of metal such as copper (Cu) or aluminum (Al), and are covered with an insulating film 4 having a relatively low thermal conductivity and made of a silicon oxide film SiO2 or the like. The insulating film 4 is made of a first insulating film 41, a second insulating film 42, a third insulating film 43, a fourth insulating film 44, and a fifth insulating film 45.

[0033] The first insulating film 41 is formed on the main surface of the semiconductor substrate 1 so as to cover the source region S and drain region D formed on the main surface of the semiconductor substrate 1, and the gate electrode G on the gate oxide film formed on the main surface of the semiconductor substrate 1.

[0034] The first via electrodes (V1s, V1d) are embedded in through holes (also called contact holes) provided in the first insulating film 41, and are electrically connected to the source region S and the drain region D. The first wirings (M1s, M1d) are formed on the first insulating film 41 so as to be electrically connected to the first via electrodes (V1s, V1d). The second insulating film 42 is formed on the first insulating film 41 so as to cover the first wirings (M1s, M1d).

[0035] The second via electrodes (V2s, V2d) are embedded in through holes formed in the second insulating film 42, and are electrically connected to the first wirings (M1s, M1d). The second wirings (M2s, M2d) are formed on the second insulating film 42 so as to be electrically connected to the second via electrodes (V2s, V2d). The third insulating film 43 is formed on the second insulating film 42 so as to cover the second wirings (M2s, M2d).

[0036] The third via electrodes (V3s, V3d) are embedded in through holes formed in the third insulating film 43 and are electrically connected to the second wirings (M2s, M2d). The third wirings (M3s, M3d) are formed on the third insulating film 43 so as to be electrically connected to the third via electrodes (V3s, V3d). The fourth insulating film 44 is formed on the third insulating film 43 so as to cover the third wirings (M3s, M3d).

[0037] The fourth via electrode (V4s) is embedded in a through hole formed in the fourth insulating film 44, and is electrically connected to the third wiring (M3s). The fourth wiring (M41) is formed on the fourth insulating film 44 so as to be electrically connected to the fourth via electrode (V4s). The fifth insulating film 45 is formed on the fourth insulating film 44 so as to cover the fourth wiring (M41).

[0038] 3, in the metal wiring of the protection element 3, only the second source wiring M2s formed by the second wiring layer M2 is made granular. That is, the second source wiring M2s is arranged in a granular layout. Alternatively, the second source wiring M2s is laid out in a dot-like (point-like) layout and is scattered.

[0039] As a result, only the second source wiring M2s formed by the second wiring layer M2 is granulated without increasing the Si area of ​​the protection element 3, so that the density of the metal wiring of the protection element 3 can be reduced. Since the density of the metal wiring can be reduced, it is possible to avoid adverse effects of heat storage in the interlayer insulating film due to heat generation in the metal wiring region. This improves the discharge performance or heat dissipation performance of the protection element 3 against surges with long pulse widths. EXAMPLES

[0040] Next, a layout configuration example of the protection circuit 2 according to the second embodiment will be described with reference to Figs. 6 to 8. Fig. 6 is a plan view illustrating the layout of the protection circuit according to the second embodiment. Fig. 7 is a cross-sectional view of the protection circuit taken along line A-A' in Fig. 6. Fig. 8 is a cross-sectional view of the protection circuit taken along line B-B' in Fig. 6. Fig. 6 illustrates wirings M2s, M2d, and M2p formed by the second wiring layer M2 in the wiring layout of the protection circuit. To simplify the drawings, insulating films (41, 42, 43, 44, and 45) are omitted from the illustration.

[0041] In the second embodiment, as shown in Fig. 6, in the metal wiring of the protection element 3 formed of a MOSFET, only the second drain wiring M2d formed of the second wiring layer M2 is granular (the second drain wiring M2d is arranged in a granular layout). Alternatively, the second drain wiring M2d is laid out in a dot-like (point-like) layout and is scattered. Since the other configurations of the second embodiment are the same as those of the first embodiment, a duplicated description will be omitted.

[0042] In this way, since only the second drain wiring M2d formed by the second wiring layer M2 is granulated without increasing the Si area of ​​the protection element 3, it is possible to reduce the density of the metal wiring of the protection element 3. Since the density of the metal wiring can be reduced, it is possible to avoid adverse effects due to heat storage in the interlayer insulating film caused by heat generation in the metal wiring region. This improves the discharge performance or heat dissipation performance of the protection element 3 against surges with long pulse widths. EXAMPLES

[0043] Example 1 is a configuration example in which only the second source wiring M2s formed by the second wiring layer M2 is arranged in a granular shape, and Example 2 is a configuration example in which only the second drain wiring M2d formed by the second wiring layer M2 is arranged in a granular shape. Example 3 is a configuration example in which the second drain wiring M2d formed by the second wiring layer M2 is arranged in a granular shape, and further, the third source wiring M3s formed by the third wiring layer M3 is arranged in a granular shape.

[0044] A configuration example of the layout of the protection circuit 2 according to the third embodiment will be described with reference to FIGS. 9 to 12. FIG. 9 is a plan view illustrating an example of the arrangement of the second wiring layer M2 in the layout of the protection circuit according to the third embodiment. FIG. 10 is a plan view illustrating an example of the arrangement of the third wiring layer M3 in the layout of the protection circuit according to the third embodiment. FIG. 11 is a cross-sectional view of the protection circuit taken along line A-A' in FIG. 9. FIG. 12 is a cross-sectional view of the protection circuit taken along line B-B' in FIG. 10. FIG. 9 illustrates the wirings M2s, M2d, and M2p formed by the second wiring layer M2 in the wiring layout of the protection circuit 2. FIG. 10 illustrates the wirings M2s, M3d, and M3p formed by the third wiring layer M3 in the wiring layout of the protection circuit 2. To simplify the drawings, the insulating films (41, 42, 43, 44, 45, etc.) are omitted from the illustration.

[0045] Example 3 differs from Examples 1 and 2 in that a fifth wiring layer M5 is added as a wiring layer, and that the bus wiring to which the ground potential GND or the power supply potential VDD is supplied and to which the source region S of the protection element 3 is connected is a bus wiring M51 formed by the fifth wiring layer M5. For this reason, as shown in Fig. 11 and Fig. 12, a source wiring M4s, a fifth via electrode V5s, a fourth via electrode V4d, and a drain wiring M4d are added.

[0046] The multi-layer first connection wiring (also referred to as drain connection wiring) connected between the pad electrode PAD and the drain region D of the protection element 3 includes a first drain via electrode V1d, a first drain wiring M1d, a second drain via electrode V2d, a second drain wiring M2d, a third drain via electrode V3d, a third drain wiring M3d, a fourth drain via electrode V4d, and a fourth drain wiring M4d.

[0047] The multi-layer second connection wiring (also called source connection wiring) connected between the source region S of the protection element 3 and the bus wiring (M51) to which the ground potential GND or the power supply potential VDD is supplied includes the first source via electrode V1s, the first source wiring M1s, the second source via electrode V2s, the second source wiring M2s, the third source via electrode V3s, the third source wiring M3s, and the fourth source via electrode V4s, the fourth source wiring M4s, and the fifth source via electrode V5s. The other configurations of the third embodiment are similar to those of the first and second embodiments, so that the overlapping explanations will be omitted.

[0048] In the third embodiment, as shown in Fig. 9, in the metal wiring of the protection element 3 composed of MOSFET, the drain wiring M2d composed of the second wiring layer M2 is arranged in a granular manner, or as shown in Fig. 10, in the metal wiring of the protection element 3 composed of MOSFET, the source wiring M3s composed of the third wiring layer M3 is arranged in a granular manner. Also, the drain connection wiring (M2d) in the granular layout and the source connection wiring (M3s) in the granular layout are arranged diagonally alternately on a plan view.

[0049] In this way, the drain wiring M2d formed by the second wiring layer M2 is granular and the source wiring M3s formed by the third wiring layer M3 is granular, without increasing the Si area of ​​the protection element 3, so that the density of the metal wiring of the protection element 3 can be reduced. Since the density of the metal wiring can be reduced, it is possible to avoid adverse effects due to heat storage in the interlayer insulating film caused by heat generation in the metal wiring region. This improves the discharge performance or heat dissipation performance of the protection element 3 against surges with long pulse widths.

[0050] Furthermore, for surges with short pulse widths (several μs or less), it is important to reduce the impedance of the entire discharge path. However, by evenly thinning out the drain wiring and source wiring as in this embodiment 3, the protection performance is not deteriorated even for surges with short pulse widths.

[0051] (Modification) When the protective element 3 is a protective element formed of a diode or a thyristor (SCR: Silicon Controlled Rectifier), the drain connection wiring and the source connection wiring can be rephrased as an anode connection wiring and a cathode connection wiring.

[0052] The configuration of the protection element 3 of the present disclosure can be summarized as follows.

[0053] (1) The protection element 3 constituted by a MOSFET of a semiconductor device (or a semiconductor integrated circuit) has a multi-layer metal wiring structure, and in a location where the drain connection wiring (M2d, M3d) and the source connection wiring (M2s, M3s) coexist in the same layer (e.g., the second wiring layer M2 or the third wiring layer M3) of the multi-layer metal wiring structure, either the drain connection wiring (M2d, M3d) or the source connection wiring (M2s, M3s) has a granular layout shape.

[0054] (2) In (1) above, both the drain connection wiring (M2d) and the source connection wiring (M3s) have a granular layout, and the drain connection wiring (M2d) with a granular layout and the source connection wiring (M3s) with a granular layout are in different layers in a multi-layer metal wiring structure (see Example 3, Figures 9 and 10).

[0055] (3) In (2) above, the drain connection wiring (M2d) in a granular layout and the source connection wiring (M3s) in a granular layout are arranged diagonally alternately in a plan view (see FIGS. 9 and 10).

[0056] (4) The protection element 3 constituted by a diode of a semiconductor device (or a semiconductor integrated circuit) has a multilayer metal wiring structure, and at a location where the anode connection wiring (M2d, M3d) and the cathode connection wiring (M2s, M3s) coexist in the same layer (e.g., the second wiring layer M2 or the third wiring layer M3) of the multilayer metal wiring structure, either the anode connection wiring (M2d, M3d) or the cathode connection wiring (M2s, M3s) has a granular layout shape.

[0057] (5) The protection element 3 composed of a thyristor of a semiconductor device (or a semiconductor integrated circuit) has a multi-layer metal wiring structure, and at a location where the anode connection wiring (M2d, M3d) and the cathode connection wiring (M2s, M3s) coexist in the same layer (e.g., the second wiring layer M2 or the third wiring layer M3) of the multi-layer metal wiring structure, either the anode connection wiring (M2d, M3d) or the cathode connection wiring (M2s, M3s) has a granular layout shape.

[0058] The invention made by the inventor has been specifically described above based on examples. However, it goes without saying that the present invention is not limited to the above-mentioned embodiments and examples, and various modifications are possible. [Explanation of symbols]

[0059] 1: Semiconductor substrate 2: Protection circuit 3: Protection element 4: Insulating film M1~M5: 1st wiring layer ~ 5th wiring layer M41, M51: Bus wiring M1d, M2d, M3d, M4d: Drain wiring V1d to V5d: Drain via electrodes M1s, M2s, M3s, M4s: Source wiring V1s~V5s: Source via electrodes

Claims

1. A protection element is formed of a MOSFET, the protection element has a multi-layer metal wiring structure, the multi-layer metal wiring structure includes a drain connection wiring connected to a drain region of the MOSFET and a source connection wiring connected to a source region of the MOSFET; In a portion where the drain connection wiring and the source connection wiring coexist in the same layer of the multilayer metal wiring structure, both the drain connection wiring and the source connection wiring are formed in a granular layout shape; The drain connection wiring having a granular layout shape and the source connection wiring having a granular layout shape are in different layers in the multi-layer metal wiring structure.

2. In claim 1, the drain connection wirings in a granular layout shape and the source connection wirings in a granular layout shape are arranged diagonally opposite each other in a plan view.

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