NITRIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING NITRIDE SEMICONDUCTOR DEVICE - Patent application

Abstract

To provide a nitride semiconductor device and a method for manufacturing a nitride semiconductor device capable of suppressing the formation of trap levels.SOLUTION: A nitride semiconductor device has a gallium nitride layer, a gate insulating film on the gallium nitride layer, and a gate electrode on the gate insulating film. The gate insulating film has a first insulating film in contact with the gallium nitride layer and a second insulating film located between the first insulating film and the gate electrode. The first insulating film contains at least one of aluminum and gallium and oxygen, and includes corundum-type crystallized regions.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to a nitride semiconductor device and a method for manufacturing a nitride semiconductor device. [Background technology]

[0002] When an insulating film is formed on a gallium nitride (GaN) layer, a transition layer containing a natural oxide film (Ga oxide film) is formed at the interface between the GaN layer and the insulating film. In the region where the transition layer containing Ga oxide film is formed, spatially localized trap levels are formed in the band gap of the GaN layer, and become carrier trap sources. For example, if a trap source exists in the channel region of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), the carrier mobility decreases, and the electrical characteristics of the device may deteriorate.

[0003] It should be noted that a technique for reducing the thickness of the transition layer by improving the process for forming an insulating film is known (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2019-153627 A Summary of the Invention [Problem to be solved by the invention]

[0005] When forming an insulating film on a GaN layer, the surface of the GaN layer is cleaned in advance with a chemical solution or the like. When the cleaned GaN layer surface is exposed to an atmosphere containing oxygen or the like (for example, air passed through a filter), a natural oxide film (Ga oxide film) is formed in a short time. For this reason, in a general process, it is difficult to completely remove the natural oxide film from the interface between the GaN layer and the insulating film, and trap levels originating from the natural oxide film are likely to be formed in the band gap of GaN at this interface. When trap levels are formed, there is a possibility that the controllability by the field effect will be reduced, such as a decrease in carrier mobility or a change in threshold voltage.

[0006] The present invention has been made in view of the above circumstances, and has an object to provide a nitride semiconductor device capable of suppressing the formation of trap levels, and a method for manufacturing the nitride semiconductor device. [Means for solving the problem]

[0007] In order to solve the above problems, a nitride semiconductor device according to one aspect of the present invention includes a gallium nitride layer, a gate insulating film provided on the gallium nitride layer, and a gate electrode provided on the gate insulating film. The gate insulating film has a first insulating film in contact with the gallium nitride layer, and a second insulating film located between the first insulating film and the gate electrode. The first insulating film contains at least one of aluminum and gallium, and oxygen, and includes a region crystallized into a corundum type.

[0008] A method for manufacturing a nitride semiconductor device according to one aspect of the present invention includes forming a gate insulating film on a gallium nitride layer and forming a gate electrode on the gate insulating film. The gate insulating film forming step includes forming a first insulating film in contact with the gallium nitride layer, subjecting the first insulating film and the gallium nitride layer to a heat treatment to crystallize at least a portion of the first insulating film into a corundum type, and forming a second insulating film on the first insulating film that has been subjected to the heat treatment. The first insulating film before the heat treatment is an aluminum oxide film. Effect of the Invention

[0009] According to the present invention, it is possible to provide a nitride semiconductor device capable of suppressing the formation of trap levels and a method for manufacturing the nitride semiconductor device. [Brief description of the drawings]

[0010] [Figure 1] FIG. 1 is a plan view showing a configuration example of a GaN semiconductor device according to a first embodiment of the present invention. [Diagram 2] FIG. 2 is a cross-sectional view showing an example of the configuration of the GaN semiconductor device according to the first embodiment of the present invention. [Diagram 3] FIG. 3 is an enlarged cross-sectional view of the gate insulating film and its surrounding area. [Figure 4] FIG. 4 is a diagram illustrating a cross section of a portion of the first insulating film located near the interface between the GaN layer and the first insulating film, taken along a plane parallel to the surface of the GaN layer. [Diagram 5] FIG. 5 is a flowchart showing the process steps of a method for manufacturing a GaN semiconductor device according to the first embodiment of the present invention. [Figure 6A] FIG. 6A is a cross-sectional view showing a method for manufacturing a GaN semiconductor device according to embodiment 1 of the present invention in the order of steps. [Figure 6B] FIG. 6B is a cross-sectional view showing the process steps of a method for manufacturing the GaN semiconductor device according to the first embodiment of the present invention. [Figure 6C] 6A to 6C are cross-sectional views showing the process steps of a method for manufacturing the GaN semiconductor device according to the first embodiment of the present invention. [Figure 6D] 6A to 6D are cross-sectional views showing the process steps of a method for manufacturing the GaN semiconductor device according to the first embodiment of the present invention. [Figure 6E] FIG. 6E is a cross-sectional view showing the process steps of a method for manufacturing the GaN semiconductor device according to the first embodiment of the present invention. [Figure 7]FIG. 7 is a model diagram showing an atomic bonding state according to the first embodiment of the present invention, and is a model diagram showing an atomic bonding state near an interface between a well region provided in a GaN layer and a corundum-crystallized region of the first insulating film. [Figure 8] FIG. 8 is a diagram showing the energy band of GaN at the GaN / α-(Al0.9Ga0.1)2O3 interface shown in FIG. [Figure 9] FIG. 9 is a model diagram showing the atomic bonding state according to Reference Example 1, and is a model diagram showing the atomic bonding state in the vicinity of the interface where GaN and α-Ga2O3 are in contact with each other. [Figure 10] FIG. 10 is a diagram showing the energy band of GaN at the GaN / α-Ga2O3 interface shown in FIG. [Figure 11] FIG. 11 is a model diagram showing the atomic bonding state according to Reference Example 2, and is a model diagram showing the atomic bonding state in the vicinity of the interface where GaN and γ-Ga2O3 are in contact with each other. [Figure 12] FIG. 12 is a diagram showing the energy band of GaN at the GaN / γ-Ga2O3 interface shown in FIG. [Figure 13] FIG. 13 is a cross-sectional view showing an example of the configuration of a GaN semiconductor device 100A according to the second embodiment of the present invention. [Figure 14] FIG. 14 is a cross-sectional view showing an example of a configuration of a GaN semiconductor device 100B according to the third embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] The inventors have found from first-principles calculations that if the Ga oxide film has a corundum-type Ga2O3 (i.e., α-Ga2O3) structure at the interface between GaN and an insulating film (i.e., an interfacial transition layer including a Ga oxide film), the formation of trap levels in the band gap of GaN can be suppressed.

[0012] That is, when the Ga oxide film has a structure of, for example, γ-Ga2O3 at the interface, a trap level is formed in the gap of GaN. This trap level causes a decrease in controllability due to the field effect, such as a decrease in mobility and a change in threshold voltage in MOSFETs. The present inventor has found that by forming a layer containing corundum-type Al2O3 (α-Al2O3) as an insulating film on the surface of GaN, incorporating the Ga oxide film covering the surface of GaN into the corundum-type Al2O3 (α-Al2O3), and forming a density of states corresponding to α-Ga2O3, it is possible to suppress the formation of a trap level in the band gap of GaN. The present invention has been made based on such findings.

[0013] An embodiment of the present invention will be described below. In the following description of the drawings, the same or similar parts are given the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each device and each member, etc., differ from the actual ones. Therefore, the specific thickness and dimensions should be determined by taking into consideration the following description. In addition, it goes without saying that the drawings include parts whose dimensional relationships and ratios differ from each other.

[0014] In the following description, directions may be described using the terms X-axis, Y-axis, and Z-axis. For example, the X-axis or Y-axis direction is a direction parallel to the surface 12a of the GaN layer 12. The X-axis, Y-axis, or both the X-axis and Y-axis directions may be called horizontal directions. The Z-axis direction is a normal direction to the surface 12a. The Z-axis direction is also the thickness direction of the GaN layer 12. The X-axis, Y-axis, and Z-axis directions are mutually orthogonal.

[0015] In the following description, the direction of the Z-axis arrow may be referred to as "up" and the opposite direction of the Z-axis arrow may be referred to as "down". "Up" and "down" do not necessarily mean the vertical direction with respect to the ground. In other words, the directions of "up" and "down" are not limited to the direction of gravity. "Up" and "down" are merely convenient expressions for specifying the relative positional relationship in regions, layers, films, substrates, etc., and do not limit the technical idea of ​​the present invention. For example, if the paper is rotated 180 degrees, "up" will of course become "down" and "down" will become "up".

[0016] In the following explanation, p and n mean that holes and electrons are the majority carriers, respectively. Also, + and - attached to p and n mean that the semiconductor region has a relatively high or low impurity concentration, respectively, compared to a semiconductor region without + or -. However, even if the same p and p (or n and n) are attached to semiconductor regions, it does not mean that the impurity concentrations of the respective semiconductor regions are strictly the same.

[0017] <Embodiment 1> (Configuration example) Fig. 1 is a plan view showing a configuration example of a GaN semiconductor device 100 according to embodiment 1 of the present invention. Fig. 2 is a cross-sectional view showing a configuration example of a GaN semiconductor device 100 according to embodiment 1 of the present invention. Fig. 2 shows a cross section taken along line X1-X'1 of the plan view of Fig. 1.

[0018] 1 and 2 is, for example, a power semiconductor device, and includes a gallium nitride substrate (hereinafter, GaN substrate) 10 and a plurality of vertical MOSFETs 1 provided on the GaN substrate 10. In the GaN semiconductor device 100, the vertical MOSFETs 1 are repeatedly provided in one direction (for example, the X-axis direction). One vertical MOSFET 1 is a repeated unit structure, and this unit structure is arranged side by side in one direction (for example, the X-axis direction).

[0019] The region in which the multiple unit structures are provided is called the active region. Although not shown, an edge termination structure having a function of preventing electric field concentration in the active region is provided around the active region. The edge termination structure may include one or more of a guard ring structure, a field plate structure, and a JTE (Junction Termination Extension) structure.

[0020] As shown in Figures 1 and 2, the vertical MOSFET 1 has a gate insulating film 5 provided on a GaN substrate 10, a gate electrode 6 provided on the gate insulating film 5, and a source electrode 7 and a drain electrode 8 provided on the GaN substrate 10.

[0021] GaN substrate 10 has, for example, a GaN single crystal substrate 11 and a GaN layer 12 (an example of a "gallium nitride layer" of the present invention) provided on GaN single crystal substrate 11. As shown in Fig. 1, a front surface 12a of GaN layer 12 is also front surface 10a of GaN substrate 10. A back surface 12b located opposite front surface 12a of GaN layer 12 is in contact with GaN single crystal substrate 11. A back surface 11b of GaN single crystal substrate 11 is also back surface 10b of GaN substrate 10.

[0022] The conductivity type of the GaN single crystal substrate 11 is, for example, n+ type. The n-type dopant contained in the GaN single crystal substrate 11 is one or more elements selected from the group consisting of Si (silicon), O (oxygen) and Ge (germanium), and an example of this is O. The impurity concentration of O in the GaN single crystal substrate 11 is 2×10 18 / cm 3 That's all.

[0023] The GaN single crystal substrate 11 has a dislocation density of 1E+7 / cm 2The GaN single crystal substrate 11 may be a low dislocation freestanding substrate having a dislocation density of less than 100 nm. When the GaN single crystal substrate 11 is a low dislocation freestanding substrate, the dislocation density of the GaN layer 12 formed on the GaN single crystal substrate 11 is also low. Furthermore, by using a low dislocation freestanding substrate for the GaN single crystal substrate 11, it is possible to reduce leakage current in the power device even when a large-area power device is formed on the GaN single crystal substrate 11. This enables the manufacturing equipment to manufacture power devices with a high yield rate. Furthermore, it is possible to prevent ion-implanted impurities from diffusing deeply along the dislocations during heat treatment. Note that E+ is an exponential notation. For example, 1E+7 is 1×10 7 means...

[0024] GaN layer 12 is provided on GaN single crystal substrate 11. GaN layer 12 is an n-type GaN single crystal layer, and is a layer formed by epitaxial growth on GaN single crystal substrate 11. The n-type dopant (n-type impurity) contained in GaN layer 12 is one or more elements selected from Si (silicon), O (oxygen), and Ge (germanium), and one example is O.

[0025] A p-type well region 13, an n+ type source region 14, and a p+ type contact region 16 are provided on the surface 12a side of the GaN layer 12. A region of the GaN layer 12 where the well region 13, the source region 14, and the contact region 16 are not provided may be called a drift region. The drift region functions as a current path between the GaN single crystal substrate 11 and the well region 13.

[0026] The well region 13 is formed by ion-implanting a p-type dopant (p-type impurity) from the surface 12a side of the GaN layer 12 and activating the p-type dopant by heat treatment. The p-type dopant is, for example, magnesium (Mg). The well region 13 faces the surface 12a of the GaN layer 12. The well region 13 has a first side surface adjacent to the source region 14 in the horizontal direction and a second side surface in contact with the drift region directly below the gate insulating film 5. In the well region 13, a channel of the vertical MOSFET 1 is formed between the first side surface and the second side surface, at the contact interface with the gate insulating film 5 and in the vicinity thereof. Hereinafter, the region in the well region 13 where the channel is formed is referred to as a channel region CR.

[0027] For example, the channel region CR is located within a range of 20 nm from the front surface 12a in contact with the gate insulating film 5 toward the back surface 12b. The concentration of a p-type dopant (e.g., Mg) in the channel region CR is higher than the concentration of an n-type dopant contained in the channel region CR, and is, for example, 1E+16 / cm 3 That's all.

[0028] The source region 14 is formed by ion-implanting an n-type dopant from the surface 12a side of the GaN layer 12 and activating the n-type dopant by heat treatment. The n-type dopant is, for example, one or more elements selected from the group consisting of Si, O, and Ge. The source region 14 faces the surface 12a of the GaN layer 12 and is located inside the well region 13. The sides and bottom of the source region 14 are in contact with the well region 13. The source region 14 and the well region 13 are in contact with each other in the X-axis direction, the Y-axis direction, and the Z-axis direction.

[0029] The p+ type contact region 16 is formed by ion-implanting a p-type dopant from the surface 12a side of the GaN layer 12 and activating the p-type dopant by heat treatment. The p-type dopant is, for example, Mg. The contact region 16 faces the surface 12a of the GaN layer 12 and is located inside the well region 13. At least a bottom portion of the contact region 16 contacts the well region 13. In the Z-axis direction, the contact region 16 and the well region 13 contact each other.

[0030] 3 is an enlarged cross-sectional view of the gate insulating film 5 and its surrounding area. As shown in FIG. 2 and FIG. 3, the gate insulating film 5 has a first insulating film 51 in contact with the surface 12a of the GaN layer 12, and a second insulating film 52 located between the first insulating film 51 and the gate electrode 6.

[0031] The first insulating film 51 is a film formed by forming an amorphous aluminum oxide (Al2O3) film on the surface 12a of the GaN layer 12 and performing a high-temperature heat treatment. The natural oxide film (Ga oxide film) that covered the surface 12a of the GaN layer 12 before the first insulating film 51 was formed is incorporated into the Al2O3 film by the formation of the Al2O3 film and the high-temperature heat treatment, and is mixed with the Al2O3 film. As a result, the composition of the first insulating film 51 is, for example, (Al 0.9 Ga 0.1 )2O3. The total amount of Al contained in the first insulating film 51 is greater than the amount of Ga contained in the first insulating film 51. The film thickness of the first insulating film 51 is, for example, not less than 0.5 nm and not more than 100 nm, and one example is 2 nm.

[0032] Moreover, by the above-mentioned high-temperature heat treatment, at least a part (i.e., a part or the whole) of the first insulating film 51 becomes a region 511 crystallized into a corundum type. The region 511 crystallized into a corundum type is a region in which an Al2O3 film and a natural oxide film (Ga oxide film) are mixed and crystallized, and contains at least one of Al and Ga, and oxygen (O). FIG. 3 illustrates a state in which a part of the first insulating film 51 is crystallized into a corundum type.

[0033] 4 is a diagram illustrating a cross section of a portion 510 of first insulating film 51 located near the interface between GaN layer 12 and first insulating film 51 (hereinafter, referred to as the interface vicinity portion) cut along a plane (e.g., XY plane) parallel to surface 12a of GaN layer 12. As shown in FIG. 4, first insulating film 51 after heat treatment has a region 511 crystallized into a corundum type and a region 512 not crystallized into a corundum type. Region 512 not crystallized into a corundum type is, for example, an amorphous Al2O3 film.

[0034] In the first insulating film 51, the ratio of the region 511 crystallized in the corundum type is preferably 10% or more. For example, when the area of ​​the region 511 crystallized in the corundum type is S1 and the area of ​​the region 512 not crystallized in the corundum type is S2 in a plan view from the normal direction (e.g., Z-axis direction) of the surface 12a of the GaN layer 12, S1÷(S1+S2)×100 is preferably 10% or more. This makes it possible to suppress the formation of a trap level in the band gap of GaN at the interface between the GaN layer 12 and the first insulating film 51, as shown in FIG. 8 described later.

[0035] In particular, it is preferable that the ratio of the region 511 crystallized in the corundum type is high in the interface vicinity 510 of the first insulating film 51. For example, it is preferable that the ratio of the region 511 crystallized in the corundum type is 10% or more in the interface vicinity 510 of the first insulating film 51. It is preferable that S1÷(S1+S2)×100 is 10% or more in the interface vicinity 510. This can further suppress the formation of trap levels in the band gap of GaN, as shown in FIG. 8 described later. Note that the interface vicinity 510 is, for example, a portion located within 1 nm from the interface between the GaN layer 12 and the first insulating film 51 toward the first insulating film 51.

[0036] 2 and 3, a second insulating film 52 is provided on a first insulating film 51. The second insulating film 52 is, for example, a silicon oxide (SiO2) film. The film thickness of the second insulating film 52 is set arbitrarily according to, for example, a threshold value required for a MOSFET having the first insulating film 51 and the second insulating film 52 as the gate insulating film 5.

[0037] The second insulating film 52 is not limited to a SiO2 film. The second insulating film 52 may be an oxide or oxynitride containing one or more of boron (B), aluminum (Al), silicon (Si), gallium (Ga), titanium (Ti), yttrium (Y), zirconium (Zr), hafnium (Hf), tantalum (Ta), and tungsten (W). The second insulating film 52 is not limited to a single layer film. The second insulating film 52 may be a laminated film in which another film is laminated on an oxide or oxynitride containing one or more of the above.

[0038] The gate electrode 6 is provided on the gate insulating film 5. The gate electrode 6 is a planar electrode provided on the flat gate insulating film 5. The gate electrode 6 is made of, for example, polysilicon doped with impurities.

[0039] 2, the source electrode 7 is provided continuously from above the n+ type source region 14 to above the p+ type contact region 16, and is electrically connected to the source region 14 and the contact region 16. Although not shown, the source electrode 7 may be provided so as to cover the gate electrode 6 via an interlayer insulating film. The source electrode 7 is made of, for example, Al or an Al-Si alloy.

[0040] Drain electrode 8 is provided on the back surface 11b side of GaN single crystal substrate 11 and is electrically connected to GaN single crystal substrate 11. Drain electrode 8 is made of, for example, Al or an Al--Si ​​alloy.

[0041] (Manufacturing method) Next, a method for manufacturing GaN semiconductor device 100 will be described. FIG. 5 is a flow chart showing the process steps of a method for manufacturing GaN semiconductor device 100 according to embodiment 1 of the present invention. FIGS. 6A to 6E are cross-sectional views showing the process steps of a method for manufacturing GaN semiconductor device 100 according to embodiment 1 of the present invention. GaN semiconductor device 100 is manufactured using various types of equipment, such as a cleaning equipment, a film formation equipment, a heat treatment equipment, an exposure equipment, and an etching equipment. Hereinafter, these equipment will be collectively referred to as manufacturing equipment.

[0042] The manufacturing equipment uses a chemical solution to clean the entire GaN substrate including surface 12a of GaN layer 12 (step ST1 in FIG. 5). In this cleaning step, as shown in FIG. 6A, natural oxide films and the like are temporarily removed from surface 12a of GaN layer 12 together with particles and the like. However, after the cleaning step (e.g., during a drying step), surface 12a of GaN layer 12 is exposed to an atmosphere containing oxygen and the like (e.g., air that has been passed through a filter). For this reason, natural oxide film 121 is formed again on surface 12a of GaN layer 12, as shown in FIG. 6B.

[0043] Next, as shown in FIG. 6C, the manufacturing equipment forms a first insulating film 51' on the surface 12a of the GaN layer 12 (step ST2 in FIG. 5). For example, the manufacturing equipment forms an amorphous Al2O3 film as the first insulating film 51' by an ALD method. The amorphous Al2O3 film is formed so as to be in direct contact with the surface 12a of the GaN layer 12, or indirectly in contact with the surface 12a of the GaN layer 12 via a native oxide film 121. The thickness of the amorphous Al2O3 film is, for example, 0.5 nm to 100 nm, and is 2 nm as an example.

[0044] Next, the manufacturing equipment performs a heat treatment on the entire substrate including the first insulating film 51' and the GaN layer 12 to form the first insulating film 51 at least partially crystallized into a corundum type as shown in FIG. 6D (step ST3 in FIG. 5). For example, this heat treatment is performed in a nitrogen (N2) atmosphere or an oxygen (O2) atmosphere, or an atmosphere containing N2 and O2. The maximum temperature in the heat treatment step is, for example, 850° C. or higher. Through this heat treatment, the first insulating film 51' is mixed with the natural oxide film covering the surface 12a of the GaN layer 12 to form the first insulating film 51 at least partially crystallized into a corundum type. As described above, the composition of the first insulating film 51 is, for example, (Al 0.9 Ga 0.1 )2O3.

[0045] 6E, the manufacturing equipment forms a second insulating film 52 on the first insulating film 51 (step ST4 in FIG. 5). For example, the manufacturing equipment forms an amorphous SiO2 film as the second insulating film 52 by a CVD (Chemical Vapor Deposition) method.

[0046] Next, the manufacturing equipment forms the gate electrode 6 (see FIG. 2) on the second insulating film 52 (step ST5). For example, the manufacturing equipment deposits a gate electrode film on the second insulating film 52. The gate electrode film is polysilicon doped with impurities, and is deposited by a CVD method. Next, the manufacturing equipment forms the gate electrode 6 by patterning the gate electrode film.

[0047] Next, the manufacturing equipment uses the gate electrode 6 or a resist pattern (not shown) as a mask to ion-implant an n-type dopant or a p-type dopant into the front surface 12a of the GaN layer 12 to form an n+ type source region 14 (see FIG. 2) and a p+ type contact region 16 (see FIG. 2). Next, the manufacturing equipment forms a source electrode 7 (see FIG. 2) on the front surface 12a of the GaN layer 12. Next, the manufacturing equipment forms a drain electrode 8 (see FIG. 2) on the back surface 10b of the GaN substrate 10. Through the above steps, the GaN semiconductor device 100 shown in FIGS. 1 and 2 is completed.

[0048] (Levels in the gap) (1) Embodiment (GaN / α-(Al 0.9 Ga 0.1 )2O3 interface) 7 is a model diagram showing the atomic bonding state according to the first embodiment of the present invention, and shows the atomic bonding state near the interface between well region 13 provided in GaN layer 12 and corundum-crystallized region 511 of first insulating film 51. Well region 13 has a p-type GaN composition. Corundum-crystallized region 511 has a composition of (Al 0.9 Ga 0.1 The interface shown in Figure 7 is between the GaN GA atoms and the corundum-type (Al 0.9 Ga 0.1)2O3 and O atoms bond to each other, forming GaN / α-(Al 0.9 Ga 0.1 )2O3 interface.

[0049] FIG. 8 shows the GaN / α-(Al 0.9 Ga 0.1 8 is a diagram showing the energy bands of GaN at the GaN / α-(Al)2O3 interface. 0.9 Ga 0.1 At the GaN interface, no density of states due to trap levels is observed in the GaN gap. 0.9 Ga 0.1 )2O3 and controlling the Ga oxide film to be an α-Ga2O3 type, the formation of trap levels originating from the transition layer including the Ga oxide film is suppressed.

[0050] (2) Reference example 1 (GaN / α-Ga2O3 interface) Fig. 9 is a model diagram showing the atomic bonding state in the vicinity of the interface where GaN and α-Ga2O3 are in contact with each other according to Reference Example 1. Fig. 10 is a diagram showing the energy band of GaN at the GaN / α-Ga2O3 interface shown in Fig. 9. As shown in Fig. 10, the GaN / α-Ga2O3 interface is a At the α-Ga2O3 interface, no density of states due to trap levels is observed in the GaN gap. The inventors have confirmed through first-principles calculations that if the Ga oxide film has an α-Ga2O3 structure, no trap levels are formed in the GaN band gap.

[0051] (3) Reference example 2 (GaN / γ-Ga2O3 interface) Fig. 11 is a model diagram showing the atomic bonding state according to Reference Example 2, and is a model diagram showing the atomic bonding state near the interface where GaN and γ-Ga2O3 are in contact. Fig. 12 is a diagram showing the energy band of GaN at the GaN / γ-Ga2O3 interface shown in Fig. 11. As shown in Fig. 12, at the GaN / γ-Ga2O3 interface, density of states resulting from trap levels occurs in the GaN gap. The present inventors have confirmed through first-principles calculations that if a Ga oxide film has a γ-Ga2O3 structure, trap levels are formed in the band gap of GaN.

[0052] (Effects of the First Embodiment) As described above, the GaN semiconductor device according to the first embodiment of the present invention includes a GaN layer 12, a gate insulating film 5 provided on the GaN layer 12, and a gate electrode 6 provided on the gate insulating film 5. The gate insulating film 5 has a first insulating film 51 in contact with the GaN layer 12, and a second insulating film 52 located between the first insulating film 51 and the gate electrode 6. The first insulating film 51 includes at least one of aluminum (Al) and gallium (Ga), and oxygen (O), and includes a region 511 crystallized into a corundum type. For example, the region 511 crystallized into a corundum type is an α-(Al 0.9 Ga 0.1 )2O3.

[0053] According to this, the corundum-type crystallized region 511 can bring the density of states at the interface 40 between the GaN layer 12 and the first insulating film 51 (i.e., the interface transition layer including a Ga oxide film) close to the density of states corresponding to α-Ga2O3, and can suppress the formation of a trap level in the band gap of GaN at the interface 40. As a result, the GaN semiconductor device 100 can suppress a decrease in mobility and a fluctuation in threshold voltage, and can achieve good carrier control by the field effect.

[0054] Moreover, the ratio of the region 511 crystallized into a corundum type is preferably 10% or more in the first insulating film 51. As the ratio of the region 511 crystallized into a corundum type in the first insulating film 51 increases, the density of states at the interface 40 between the GaN layer 12 and the first insulating film 51 can be made closer to the density of states corresponding to α-Ga2O3, and the formation of trap levels can be further suppressed.

[0055] Moreover, in first insulating film 51, the closer to interface 40, the more the crystallization is preferably in the corundum type. For example, first insulating film 51 has interface vicinity portion 510 located within 1 nm toward first insulating film 51 from interface 40 between GaN layer 12 and first insulating film 51. In interface vicinity portion 510, the proportion of region 511 crystallized in the corundum type is preferably 10% or more. This makes it possible to further suppress the formation of trap levels.

[0056] The first insulating film 51 may be entirely crystallized in the corundum type, not just partially. For example, the first insulating film 51 may be entirely crystallized in the α-(Al 0.9 Ga 0.1 )2O3. In this case, too, the formation of trap levels is suppressed in the same manner as above.

[0057] A method for manufacturing a GaN semiconductor device 100 according to the first embodiment of the present invention includes the steps of forming a gate insulating film 5 on a GaN layer 12, and forming a gate electrode 6 on the gate insulating film 5. The step of forming the gate insulating film 5 includes the steps of forming a first insulating film 51' in contact with the GaN layer 12, subjecting the first insulating film 51' and the GaN layer to a heat treatment to crystallize at least a portion of the first insulating film 51' into a corundum type, and forming a second insulating film 52 on the heat-treated first insulating film 51. Before the heat treatment, the first insulating film 51' is an aluminum oxide film.

[0058] This makes it possible to form a region 511 containing at least one of Al and Ga, and O, and crystallized into a corundum type in the first insulating film 51. The region 511 crystallized into a corundum type can bring the density of states at the interface 40 between the GaN layer 12 and the first insulating film 51 close to the density of states corresponding to α-Ga2O3, and can suppress the formation of a trap level in the band gap of GaN at the interface 40.

[0059] <Embodiment 2> In the above-described first embodiment, the vertical MOSFET included in the GaN semiconductor device 100 is of the planar type. However, in the embodiments of the present invention, the vertical MOSFET included in the GaN semiconductor device is not limited to the planar type and may be of the trench gate type.

[0060] Fig. 13 is a cross-sectional view showing a configuration example of a GaN semiconductor device 100A according to embodiment 2 of the present invention. As shown in Fig. 13, the GaN semiconductor device 100A according to embodiment 2 has a trench H provided in a GaN substrate 10. The trench H opens on the front surface 10a side of the GaN substrate 10. The trench H is formed deeper than the p-type well region 13, and the bottom of the trench H reaches the n-type GaN layer 12 (drift region).

[0061] A gate insulating film 5 and a gate electrode 6 are disposed inside the trench H. The inner side and bottom surface of the trench H are covered with a first insulating film 51 of the gate insulating film 5. The gate electrode 6 is embedded in the trench H via the gate insulating film 5. In a trench-gate vertical MOSFET, a region of the well region 13 facing the gate electrode 6 via the gate insulating film 5 provided on the side surface of the trench H becomes a channel region CR.

[0062] Like the GaN semiconductor device 100 according to the first embodiment, the GaN semiconductor device 100A according to the second embodiment has, as the gate insulating film 5, a first insulating film 51 in contact with the GaN layer 12 and a second insulating film 52 located between the first insulating film 51 and the gate electrode 6. The first insulating film 51 contains at least one of Al and Ga, and O, and includes a region 511 crystallized into a corundum type.

[0063] Thus, like GaN semiconductor device 100, GaN semiconductor device 100A can suppress the formation of trap levels in the band gap of GaN at the interface between GaN layer 12 and first insulating film 51. GaN semiconductor device 100A can suppress the reduction in mobility and the fluctuation in threshold voltage, and enables good carrier control by the field effect.

[0064] Furthermore, in the GaN semiconductor device 100A, the vertical MOSFET employs a trench gate structure, which allows the channel regions CR to be arranged more densely, facilitating miniaturization of the element.

[0065] <Embodiment 3> In the above-mentioned first and second embodiments, the MOSFETs included in the GaN semiconductor devices 100 and 100A are vertical MOSFETs. However, in the embodiments of the present invention, the MOSFETs included in the GaN semiconductor device may be lateral MOSFETs instead of vertical MOSFETs.

[0066] Fig. 14 is a cross-sectional view showing a configuration example of a GaN semiconductor device 100B according to embodiment 3 of the present invention. As shown in Fig. 14, the GaN semiconductor device 100B according to embodiment 3 has an n+ type drain region 15 provided on the surface 12a side of the GaN layer 12. A drain electrode 8 is provided on the surface 12a of the GaN layer 12 and is electrically connected to the n+ type drain region 15. In the lateral MOSFET, the region sandwiched between the source region 14 and the drain region 15 and facing the gate electrode 6 via the gate insulating film 5 becomes a channel region CR.

[0067] Like the GaN semiconductor device 100 of the first embodiment, the GaN semiconductor device 100B of the third embodiment has, as the gate insulating film 5, a first insulating film 51 in contact with the GaN layer 12 and a second insulating film 52 located between the first insulating film 51 and the gate electrode 6. The first insulating film 51 contains at least one of Al and Ga, and O, and includes a region 511 crystallized into a corundum type.

[0068] Thus, like GaN semiconductor device 100, GaN semiconductor device 100B can suppress the formation of trap levels in the band gap of GaN at the interface between GaN layer 12 and first insulating film 51. GaN semiconductor device 100B can suppress the decrease in mobility and the fluctuation in threshold voltage, and enables good carrier control by the field effect.

[0069] <Other embodiments> As described above, the present invention has been described by the embodiments and modifications, but the descriptions and drawings forming a part of this disclosure should not be understood as limiting the present invention. Various alternative embodiments and modifications will become apparent to those skilled in the art from this disclosure.

[0070] For example, the p-type dopant used in the vertical MOSFET 1 is not limited to magnesium (Mg). The p-type dopant may be beryllium (Be), zinc (Zn), or cadmium (Cd). For example, the channel region CR may contain one or more of Mg, Be, Zn, and Cd as the p-type dopant at a concentration of 1E+16 / cm 3 It may be contained in a concentration of 10 or more.

[0071] 2, an n-type JFET region may be provided in the drift region immediately below the gate insulating film 5. The JFET region is a region having a higher concentration of n-type dopants and a lower electrical resistance than the other drift regions. The on-resistance of the vertical MOSFET 1 may be reduced by providing the JFET region.

[0072] In the above embodiment, the GaN layer 12 is exemplified as the "gallium nitride layer" of the present invention, but the "gallium nitride layer" is not limited to the GaN layer. For example, the "gallium nitride layer" may be a bulk GaN substrate. The "gallium nitride layer" may contain GaN as a main component, and may further contain one or more elements selected from the group consisting of aluminum (Al) and indium (In).

[0073] Thus, the present invention naturally includes various embodiments not described here. At least one of various omissions, substitutions, and modifications of components can be made without departing from the spirit of the above-mentioned embodiments and modifications. Furthermore, the effects described in this specification are merely examples and are not limited to the present invention, and other effects may also be present. The technical scope of the present invention is defined only by the invention-specific matters related to the scope of the claims that are appropriate from the above description. [Explanation of symbols]

[0074] 1 Vertical MOSFET 5 Gate insulating film 6 Gate electrode 7. Source Electrode 8 Drain electrode 10 GaN substrate 10a, 12a surface 10b, 11b, 12b back side 11 GaN single crystal substrate 12 GaN layers 13 Well Area 14 Source Area 15 Drain Region 16 Contact Area 40 Interface (interface transition layer including Ga oxide film) 51 First insulating film 52 Second insulating film 100, 100A, 100B GaN semiconductor device 121 Native oxide film 510 Near the interface 511 Corundum-type crystallized area 512 Areas not crystallized into corundum type H Trench

Claims

1. a gallium nitride layer; a gate insulating film provided on the gallium nitride layer; a gate electrode provided on the gate insulating film, The gate insulating film is a first insulating film in contact with the gallium nitride layer; a second insulating film located between the first insulating film and the gate electrode; The first insulating film is A nitride semiconductor device comprising a region that contains aluminum, gallium, and oxygen and is crystallized in a corundum type.

2. The nitride semiconductor device according to claim 1 , wherein a total amount of aluminum contained in said first insulating film is greater than a total amount of gallium contained in said first insulating film.

3. 3. The nitride semiconductor device according to claim 1, wherein the first insulating film has a thickness of 0.5 nm or more and 100 nm or less.

4. 4. The nitride semiconductor device according to claim 1, wherein the second insulating film is an oxide or an oxynitride containing one or more of boron, aluminum, silicon, gallium, titanium, yttrium, zirconium, hafnium, tantalum, and tungsten.

5. In the first insulating film, The nitride semiconductor device according to claim 1 , wherein the ratio of the region crystallized into a corundum type is 10% or more.

6. the first insulating film has an interface vicinity portion located within a range of 1 nm toward the first insulating film from the interface between the gallium nitride layer and the first insulating film, 5. The nitride semiconductor device according to claim 1, wherein the ratio of the region crystallized into a corundum type in the vicinity of the interface is 10% or more.

7. forming a gate insulating film on the gallium nitride layer; forming a gate electrode on the gate insulating film; The step of forming a gate insulating film includes: forming a first insulating film in contact with the gallium nitride layer; a step of subjecting the first insulating film and the gallium nitride layer to a heat treatment to crystallize at least a portion of the first insulating film into a corundum type; forming a second insulating film on the first insulating film that has been subjected to the heat treatment; the first insulating film before the heat treatment is an aluminum oxide film, The method for manufacturing a nitride semiconductor device, wherein the first insulating film after the heat treatment contains aluminum, gallium, and oxygen, and has a region crystallized into a corundum type.

8. 8. The method for manufacturing a nitride semiconductor device according to claim 7, wherein in the step of forming the first insulating film, the aluminum oxide film is formed in an amorphous state by atomic layer deposition (ALD).

9. 9. The method for manufacturing a nitride semiconductor device according to claim 7, wherein the heat treatment is a high-temperature heat treatment having a maximum temperature of 850[deg.] C. or higher.

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