Nitride Semiconductor Device

Abstract

To provide a nitride semiconductor device that can be suppressed from varying in threshold voltage while suppressing a gate insulation film from decreasing dielectric breakdown voltage.SOLUTION: A nitride semiconductor device comprises a gallium nitride layer, a gate insulation film provided on the gallium nitride layer, and a gate electrode provided on the gate insulation film. The gate insulation film has a first insulation film provided on the gallium nitride layer, a second insulation film provided on the first insulation film, and a third insulation film provided on the second insulation film. The first insulation film is an aluminum nitride film. The second insulation film is an AlxSiyO film (x>y≥0). The third insulation film is an Alx'Siy'O film (0≤x'<y').SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a nitride semiconductor device. [Background technology]

[0002] In order to realize GaN-MOSFET with excellent electrical characteristics, it is important to suppress the variation of the threshold voltage. However, with conventional methods, it is difficult to suppress the variation of the threshold voltage because of the large number of hole traps caused by the Ga-O bonds formed at the interface between gallium nitride (GaN) and the gate insulating film.

[0003] In addition, in HEMTs, a thin aluminum nitride (AlN) film is formed on GaN, and then aluminum oxide (Al 2 O 3 ) film or silicon oxide (SiO 2 However, a technique for forming an AlN film on an AlN film is known (for example, Patent Document 1). 2 O 3 In the case of forming a SiO film on AlN, the dielectric breakdown voltage of the gate insulating film may decrease. 2 When forming a film, AlN and SiO 2 Since interface states are formed at the interface with the silicon dioxide, the reduction in hole traps may be insufficient. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2016-143842 A Summary of the Invention [Problem to be solved by the invention]

[0005] In GaN-MOSFETs, a technology is desired that can suppress the variation in threshold voltage while suppressing the decrease in the dielectric breakdown voltage of the gate insulating film. The present invention has been made in consideration of the above circumstances, and has an object to provide a nitride semiconductor device that can suppress fluctuations in threshold voltage while suppressing a decrease in the dielectric breakdown voltage of the gate insulating film. [Means for solving the problem]

[0006] In order to solve the above problems, a nitride semiconductor device according to one aspect of the present invention includes a gallium nitride layer, a gate insulating film provided on the gallium nitride layer, and a gate electrode provided on the gate insulating film. The gate insulating film has a first insulating film provided on the gallium nitride layer, a second insulating film provided on the first insulating film, and a third insulating film provided on the second insulating film. The first insulating film is an aluminum nitride film. The second insulating film is an AlxSiyO film (x>y≧0). The third insulating film is an Alx′Siy′O film (0≦x′ <y´)である。 Effect of the Invention

[0007] According to the present invention, it is possible to provide a nitride semiconductor device capable of suppressing a decrease in the dielectric breakdown voltage of a gate insulating film and suppressing fluctuations in threshold voltage. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a plan view showing a configuration example of a GaN semiconductor device according to a first embodiment of the present invention. [Diagram 2] FIG. 2 is a cross-sectional view showing an example of the configuration of the GaN semiconductor device according to the first embodiment of the present invention. [Diagram 3] FIG. 3 is a flowchart showing the process steps of a method for manufacturing a GaN semiconductor device according to the first embodiment of the present invention. [Figure 4] FIG. 4 is a model diagram showing the atomic bonding state according to the first embodiment of the present invention, and is a model diagram showing the atomic bonding state between GaN, AlN, and Al2O3. [Diagram 5] FIG. 5 is a diagram showing the energy band at the AlN / Al2O3 interface shown in FIG. [Figure 6] FIG. 6 is a model diagram showing the atomic bonding state according to a comparative example of the present invention, and is a model diagram showing the atomic bonding state between GaN, AlN, and SiO 2 . [Figure 7] FIG. 7 is a diagram showing an energy band at the AlN / SiO2 interface shown in FIG. [Figure 8] FIG. 8 is a cross-sectional view showing a configuration example of a GaN semiconductor device according to the second embodiment of the present invention. [Figure 9] FIG. 9 is a cross-sectional view showing a configuration example of a GaN semiconductor device according to the third embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] An embodiment of the present invention will be described below. In the following description of the drawings, the same or similar parts are given the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each device and each member, etc., differ from the actual ones. Therefore, the specific thickness and dimensions should be determined by taking into consideration the following description. In addition, it goes without saying that the drawings include parts whose dimensional relationships and ratios differ from each other.

[0010] In the following description, directions may be described using the terms X-axis, Y-axis, and Z-axis. For example, the X-axis or Y-axis direction is a direction parallel to the surface 12a of the GaN layer 12. The X-axis, Y-axis, or both the X-axis and Y-axis directions may be called horizontal directions. The Z-axis direction is a normal direction to the surface 12a of the GaN layer 12. The Z-axis direction is also the thickness direction of the GaN layer 12. The X-axis, Y-axis, and Z-axis directions are mutually orthogonal.

[0011] In the following description, the direction of the Z-axis arrow may be referred to as "up" and the opposite direction of the Z-axis arrow may be referred to as "down". "Up" and "down" do not necessarily mean the vertical direction with respect to the ground. In other words, the directions of "up" and "down" are not limited to the direction of gravity. "Up" and "down" are merely convenient expressions for specifying the relative positional relationship in regions, layers, films, substrates, etc., and do not limit the technical idea of ​​the present invention. For example, if the paper is rotated 180 degrees, "up" will of course become "down" and "down" will become "up".

[0012] In the following explanation, p and n mean that holes and electrons are the majority carriers, respectively. Also, + and - attached to p and n mean that the semiconductor region has a relatively high or low impurity concentration, respectively, compared to a semiconductor region without + or -. However, even if the same p and p (or n and n) are attached to semiconductor regions, it does not mean that the impurity concentrations of the respective semiconductor regions are strictly the same.

[0013] <Embodiment 1> (Configuration example) Fig. 1 is a plan view showing a configuration example of a GaN semiconductor device 100 according to embodiment 1 of the present invention. Fig. 2 is a cross-sectional view showing a configuration example of a GaN semiconductor device 100 according to embodiment 1 of the present invention. Fig. 2 shows a cross section taken along line X1-X'1 of the plan view of Fig. 1. 1 and 2 is, for example, a power semiconductor device, and includes a gallium nitride substrate (hereinafter, GaN substrate) 10 and a plurality of vertical MOSFETs 1 provided on the GaN substrate 10. In the GaN semiconductor device 100, the vertical MOSFETs 1 are repeatedly provided in one direction (for example, the X-axis direction). One vertical MOSFET 1 is a repeated unit structure, and this unit structure is arranged side by side in one direction (for example, the X-axis direction).

[0014] A region in which a plurality of unit structures are provided is called an active region. Although not shown, an edge termination structure having a function of preventing electric field concentration in the active region is provided around the active region. The edge termination structure may include one or more of a guard ring structure, a field plate structure, and a JTE (JunctiOn TerminatiOn ExtenSiOn) structure. As shown in Figures 1 and 2, the vertical MOSFET 1 has a gate insulating film 5 provided on a GaN substrate 10, a gate electrode 6 provided on the gate insulating film 5, and a source electrode 7 and a drain electrode 8 provided on the GaN substrate 10.

[0015] GaN substrate 10 has, for example, a GaN single crystal substrate 11 and a GaN layer 12 (an example of a "gallium nitride layer" of the present invention) provided on GaN single crystal substrate 11. As shown in Fig. 1, a front surface 12a of GaN layer 12 is also front surface 10a of GaN substrate 10. A back surface 12b located opposite front surface 12a of GaN layer 12 is in contact with GaN single crystal substrate 11. A back surface 11b of GaN single crystal substrate 11 is also back surface 10b of GaN substrate 10. The conductivity type of the GaN single crystal substrate 11 is, for example, n+ type. The n-type dopant contained in the GaN single crystal substrate 11 is one or more elements selected from the group consisting of Si (silicon), O (oxygen) and Ge (germanium), and an example of this is O. The impurity concentration of O in the GaN single crystal substrate 11 is 2×10 18 / cm 3 That's all.

[0016] The GaN single crystal substrate 11 has a dislocation density of 1E+7 / cm 2The GaN single crystal substrate 11 may be a low dislocation freestanding substrate having a dislocation density of less than 100 nm. When the GaN single crystal substrate 11 is a low dislocation freestanding substrate, the dislocation density of the GaN layer 12 formed on the GaN single crystal substrate 11 is also low. Furthermore, by using a low dislocation freestanding substrate for the GaN single crystal substrate 11, it is possible to reduce leakage current in the power device even when a large-area power device is formed on the GaN single crystal substrate 11. This enables the manufacturing equipment to manufacture power devices with a high yield rate. Furthermore, it is possible to prevent ion-implanted impurities from diffusing deeply along the dislocations during heat treatment. Note that E+ is an exponential notation. For example, 1E+7 is 1×10 7 means...

[0017] GaN layer 12 is provided on GaN single crystal substrate 11. GaN layer 12 is an n-type GaN single crystal layer, and is a layer formed by epitaxial growth on GaN single crystal substrate 11. The n-type dopant (n-type impurity) contained in GaN layer 12 is one or more elements selected from Si (silicon), O (oxygen), and Ge (germanium), and one example is O. A p-type well region 13, an n+ type source region 14, and a p+ type contact region 16 are provided on the surface 12a side of the GaN layer 12. A region of the GaN layer 12 where the well region 13, the source region 14, and the contact region 16 are not provided may be called a drift region. The drift region functions as a current path between the GaN single crystal substrate 11 and the well region 13.

[0018] The well region 13 is formed by ion-implanting a p-type dopant (p-type impurity) from the surface 12a side of the GaN layer 12 and activating the p-type dopant by heat treatment. The p-type dopant is, for example, magnesium (Mg). The well region 13 faces the surface 12a of the GaN layer 12. The well region 13 has a first side surface adjacent to the source region 14 in the horizontal direction and a second side surface in contact with the drift region directly below the gate insulating film 5. In the well region 13, a channel of the vertical MOSFET 1 is formed between the first side surface and the second side surface, at the contact interface with the gate insulating film 5 and in the vicinity thereof. Hereinafter, the region in the well region 13 where the channel is formed is referred to as a channel region CR.

[0019] For example, the channel region CR is located within a range of 20 nm from the front surface 12a in contact with the gate insulating film 5 toward the back surface 12b. The concentration of a p-type dopant (e.g., Mg) in the channel region CR is higher than the concentration of an n-type dopant contained in the channel region CR, and is, for example, 1E+16 / cm 3 That's all.

[0020] The source region 14 is formed by ion-implanting an n-type dopant from the surface 12a side of the GaN layer 12 and activating the n-type dopant by heat treatment. The n-type dopant is, for example, one or more elements selected from the group consisting of Si, O, and Ge. The source region 14 faces the surface 12a of the GaN layer 12 and is located inside the well region 13. The sides and bottom of the source region 14 are in contact with the well region 13. The source region 14 and the well region 13 are in contact with each other in the X-axis direction, the Y-axis direction, and the Z-axis direction.

[0021] The p+ type contact region 16 is formed by ion-implanting a p-type dopant from the surface 12a side of the GaN layer 12 and activating the p-type dopant by heat treatment. The p-type dopant is, for example, Mg. The contact region 16 faces the surface 12a of the GaN layer 12 and is located inside the well region 13. At least a bottom portion of the contact region 16 contacts the well region 13. In the Z-axis direction, the contact region 16 and the well region 13 contact each other.

[0022] As shown in FIG. 2, the gate insulating film 5 includes a first insulating film 51 provided on the GaN layer 12, a second insulating film 52 provided on the first insulating film 51, and a third insulating film 53 provided on the second insulating film 52. That is, the first insulating film 51 is in contact with the surface 12a of the GaN layer 12 including the well region 13. The second insulating film 52 is located between the first insulating film 51 and the gate electrode 6 and is in contact with the surface of the first insulating film 51. The third insulating film 53 is located between the second insulating film 52 and the gate electrode 6 and is in contact with the surface of the second insulating film 52. The first insulating film 51, the second insulating film 52, and the third insulating film 53 are laminated in this order to form the gate insulating film 5.

[0023] The first insulating film 51 is an aluminum nitride (AlN) film. For example, the AlN film is formed to a thickness of 0.5 nm or more and 5 nm or less by the ALD (Atomic Layer Deposition) method, and is formed to a thickness of 2 nm as an example. Since cracks may occur if the AlN film is thick, it is preferably 5 nm or less in thickness.

[0024] The second insulating film 52 is an AlxSiyO film (x>y≧0), and for example, it is an aluminum oxide (Al 2 O 3 ) film. For example, the Al 2 O 3 film is formed to a thickness of 2 nm by the ALD method. The third insulating film 53 is an Alx´Siy´O film (0≦x´<y´), and for example, it is a silicon oxide (SiO 2 ) film. For example, the SiO 2 film is formed to a thickness of 100 nm by the CVD (Chemical Vapor Deposition) method.

[0025] The gate electrode 6 is provided on the gate insulating film 5. The gate electrode 6 is a planar electrode provided on the flat gate insulating film 5. The gate electrode 6 is made of, for example, Al or an Al-Si alloy. Alternatively, the gate electrode 6 may be made of polysilicon doped with impurities.

[0026] The source electrode 7 is provided continuously from above the n+ type source region 14 to above the p+ type contact region 16, and is electrically connected to the source region 14 and the contact region 16. Although not shown, the source electrode 7 may be provided so as to cover the gate electrode 6 via an interlayer insulating film. The source electrode 7 is made of, for example, Al or an Al-Si alloy. Drain electrode 8 is provided on the back surface 11b side of GaN single crystal substrate 11 and is electrically connected to GaN single crystal substrate 11. Drain electrode 8 is made of, for example, Al or an Al--Si ​​alloy.

[0027] (Manufacturing method) Next, a method for manufacturing the GaN semiconductor device 100 will be described. Fig. 3 is a flow chart showing the process steps of the method for manufacturing the GaN semiconductor device 100 according to the first embodiment of the present invention. The GaN semiconductor device 100 is manufactured using various types of equipment, such as a cleaning device, a film formation device, a heat treatment device, an exposure device, and an etching device. Hereinafter, these devices will be collectively referred to as the manufacturing equipment.

[0028] 3, the manufacturing equipment forms p-type well region 13 (see FIG. 2) on the surface 12a side of GaN layer 12. For example, p-type well region 13 is formed by partially ion-implanting magnesium (Mg) as a p-type impurity into the surface 12a side of GaN layer 12, and activating the Mg by performing a heat treatment on the entire substrate including GaN layer 12.

[0029] Next, in step ST2 of FIG. 3, the manufacturing equipment forms an n+ type source region 14 (see FIG. 2) and a p+ type contact region 16 (see FIG. 2) on the surface 12a side of the GaN layer 12. For example, the n+ type source region 14 is formed by partially ion-implanting silicon (Si) as an n-type impurity into the surface side of the well region 13, and activating Si by performing a heat treatment on the entire substrate including the well region 13. The p+ type contact region 16 is formed by partially ion-implanting Mg as a p-type impurity into the surface side of the well region 13, and activating Si by performing a heat treatment on the entire substrate including the well region 13. Note that the heat treatment for forming the n+ type source region 14 and the heat treatment for forming the p+ type contact region 16 are, for example, the same process.

[0030] 3, the manufacturing equipment forms a first insulating film 51 on the surface 12a of the GaN layer 12 on which the well region 13, the source region 14, and the contact region 16 are formed. The manufacturing equipment forms an AlN film as the first insulating film 51 to a thickness of 2 nm by, for example, the ALD method. 3, the manufacturing equipment forms a second insulating film 52 on the surface of the first insulating film 51. The manufacturing equipment forms an Al 2 O 3 The film is formed to a thickness of 2 nm.

[0031] The AlN film formation process shown in step ST3 of FIG. 3 and the AlN film formation process shown in step ST4 of FIG. 2 O 3 It is preferable to perform the film formation steps in separate chambers rather than consecutively in the same chamber. This is because the AlN film formation step in step ST3 and the AlN film formation step in step ST4 are preferably performed in separate chambers. 2 O 3 If the film formation process and the film formation process are performed in the same chamber, the film formation gas (containing oxygen) used in step ST4 may remain in the chamber and affect the next lot.

[0032] For example, assume that the oxygen-containing deposition gas used in step ST4 remains in the chamber even after step ST4 is completed. If the next lot of wafers is loaded into the chamber with remaining oxygen gas, the loaded wafers may be exposed to the remaining oxygen gas, and the surface 12a of the GaN layer 12 may be oxidized (i.e., Ga-O bonds may be formed on the surface 12a) before the AlN film is formed. To reduce this possibility, it is preferable to perform steps ST3 and ST4 in separate chambers.

[0033] 3, the manufacturing equipment forms a third insulating film 53 on the surface of the second insulating film 52. The manufacturing equipment forms the third insulating film 53 by, for example, a CVD method. 2 The film is formed to a thickness of 100 nm. Next, in step ST6 of FIG. 3, the manufacturing equipment forms a gate electrode 6 (see FIG. 2) on the third insulating film 53. For example, the manufacturing equipment forms a gate electrode film on the third insulating film 53. The gate electrode film is made of Al or an Al-Si alloy, and the method for forming the gate electrode film is a deposition method. Alternatively, the gate electrode film may be made of polysilicon doped with impurities, and the method for forming the gate electrode film may be a CVD method. Next, the manufacturing equipment forms the gate electrode 6 by patterning the gate electrode film.

[0034] 3, the manufacturing equipment forms a source electrode 7 (see FIG. 2) on the front surface 12a side of the GaN layer 12. The source electrode 7 is formed by depositing Al or an Al-Si alloy by a vapor deposition method and patterning the deposited Al or Al-Si alloy. 3, the manufacturing equipment forms a drain electrode 8 (see FIG. 2) on the back surface 10b side of the GaN substrate 10. The drain 8 is formed by depositing Al or an Al-Si alloy by vapor deposition and patterning it as necessary. Through the above steps, the GaN semiconductor device 100 shown in FIGS. 1 and 2 is completed.

[0035] It should be noted that the flowchart shown in FIG. 3 is merely an example of a manufacturing method. The manufacturing method of the GaN semiconductor device 100 is not limited to the flowchart shown in FIG. 3. For example, in the flowchart shown in FIG. 3, the order of the steps of forming the source electrode 7 (step ST7) and the step of forming the drain electrode 8 (step ST8) may be interchanged. In addition, the step of forming the n+ type source region 14 and the p+ type contact region 16 (step ST2) may be performed between steps ST6 and ST7, not between steps ST1 and ST3. The GaN semiconductor device 100 shown in FIG. 2 can be manufactured with such an order of steps.

[0036] (Interface states) (1) Implementation form FIG. 4 is a model diagram showing the atomic bonding state according to the first embodiment of the present invention, and is a schematic diagram of GaN, AlN, and Al. 2 O 3 This is a model diagram showing the atomic bonding state between GaN and AlN. As shown in Figure 4, AlN does not contain oxygen (O). Therefore, the surface of GaN is not easily oxidized, and Ga-O bonds are not easily formed. At the GaN / AlN interface, the formation of interface states due to Ga-O bonds is suppressed. FIG. 5 shows the AlN / Al 2 O 3 5 is a diagram showing an energy band at an interface. The vertical axis of FIG. 5 indicates energy (eV), and the horizontal axis of FIG. 5 indicates a symmetric point in wave number space. As shown in FIG. 5, the AlN / Al 2 O 3 At the interface, the formation of interface states is suppressed.

[0037] (2) Comparative Example FIG. 6 is a model diagram showing the atomic bonding state according to a comparative example of the present invention, and shows GaN, AlN, and SiO 2 A model diagram showing the bonding state of atoms between AlN / SiO 2 At the interface, Al-Si-O bonds are formed. FIG. 7 shows the AlN / SiO 2It is a diagram showing the energy band in the interface. The vertical axis of FIG. 7 indicates energy (eV), and the horizontal axis of FIG. 7 indicates symmetry points in the wave number space. As shown in FIG. 7, in the AlN / SiO 2 interface, interface levels are formed within the band gap due to oxygen (O) originating from the Al-O-Si bond. These interface levels can be the origin of hole traps.

[0038] (Effect of Embodiment 1) As described above, the GaN semiconductor device 100 according to Embodiment 1 of the present invention includes a GaN layer 12, a gate insulating film 5 provided on the GaN layer 12, and a gate electrode 6 provided on the gate insulating film 5. The gate insulating film 5 has a first insulating film 51 provided on the GaN layer 12, a second insulating film 52 provided on the first insulating film 51, and a third insulating film 53 provided on the second insulating film 52. The first insulating film 51 is an aluminum nitride film (AlN). The second insulating film 52 is an AlxSiyO film (x>y≧0). The third insulating film 53 is an Alx´Siy´O film (0≦x´<y´).

[0039] According to this, the first insulating film 51 is located between the GaN layer 12 and the second insulating film 52. Since the first insulating film 51 is AlN and does not contain oxygen (O), the formation of Ga-O bonds is suppressed at the interface between the first insulating film 51 and the GaN layer 12 (for example, the GaN / AlN interface). At the GaN / AlN interface, the formation of interface levels due to Ga-O bonds is suppressed.

[0040] Also, the second insulating film 52 is located between the first insulating film 51 and the third insulating film 53. The second insulating film 52 is an AlxSiyO film (x>y≧0), for example, an Al 2 O 3 film. The third insulating film 53 is an Alx´Siy´O film (0≦x´<y´), for example, an SiO 2 film. As shown in FIGS. 5 and 7, the AlN / Al 2 O 3 interface suppresses the formation of interface levels compared to the AlN / SiO 2 interface. Furthermore, AlN and SiO 2Between Al 2 O 3 By interposing SiO 2 The SiO 2 This reduces the effect of interface states formed by contact with the film on the GaN / AlN interface.

[0041] As a result, the GaN semiconductor device 100 can reduce hole traps due to interface states, and can suppress fluctuations in the threshold voltage of the vertical MOSFET 1. In addition, SiO 2 The film is AlN film, Al 2 O 3 The gate insulating film 5 has a larger dielectric breakdown field and can increase the dielectric breakdown voltage compared to a SiO 2 By providing the third insulating film 53, which is exemplified by the film, it is possible to suppress a decrease in the dielectric breakdown voltage.

[0042] (Evaluation Results) Table 1 shows the results of evaluating the shift amount of the threshold voltage and the dielectric breakdown voltage between the first embodiment of the present invention and the first to third comparative examples. As shown in FIG. 2, the vertical MOSFET 1 according to the first embodiment has a gate insulating film 5 made of an AlN film, an Al 2 O 3 membrane, SiO 2 In contrast, although not shown, the vertical MOSFET according to Comparative Example 1 has an insulating film in which Al 2 O 3 Membrane and SiO 2 The vertical MOSFET according to Comparative Example 2 has an insulating film in which an AlN film and a SiO 2 The vertical MOSFET according to Comparative Example 3 has an insulating film in which an AlN film and an AlN film are stacked in this order as a gate insulating film. 2 O 3 The insulating film has films laminated in this order.

[0043] [Table 1]

[0044] In Table 1, the threshold voltage shift amount is shown as a relative value of the threshold voltage shift amount after applying a negative bias to the gate electrode. The reference value of the shift amount is that of embodiment 1. In Table 1, the shift amount of embodiment 1 is set to 1, and the shift amounts of comparative examples 1 to 3 are shown as relative values ​​to embodiment 1. As shown in Table 1, the threshold voltage shift amount is 3 times that of embodiment 1 in comparative example 1, 2.5 times in comparative example 2, and 1 time in comparative example 3. From this result, it can be seen that the GaN layer and the SiO 2 Between the film, there is an AlN film and an Al 2 O 3 It was confirmed that the provision of the film suppresses the variation in threshold voltage. In addition, as shown in Table 1, the dielectric breakdown voltage of the gate insulating film was 100 V in the first embodiment and the first and second comparative examples, while it was 50 V in the third comparative example. 2 It was confirmed that the provision of the film can suppress a decrease in dielectric breakdown voltage.

[0045] <Embodiment 2> In the above-described first embodiment, the vertical MOSFET included in the GaN semiconductor device 100 is of the planar type. However, in the embodiments of the present invention, the vertical MOSFET included in the GaN semiconductor device is not limited to the planar type and may be of the trench gate type.

[0046] Fig. 8 is a cross-sectional view showing a configuration example of a GaN semiconductor device 100A according to embodiment 2 of the present invention. As shown in Fig. 8, the GaN semiconductor device 100A according to embodiment 2 has a trench H provided in a GaN substrate 10. The trench H opens on the front surface 10a side of the GaN substrate 10. The trench H is formed deeper than the p-type well region 13, and the bottom of the trench H reaches the n-type GaN layer 12 (drift region).

[0047] Inside the trench H, a gate insulating film 5 and a gate electrode 6 are arranged. The inner side surface and bottom surface of the trench H are covered with the first insulating film 51 of the gate insulating film 5. Further, the gate electrode 6 is embedded in the trench H via the gate insulating film 5. In the trench gate type vertical MOSFET, in the well region 13, the region facing the gate electrode 6 through the gate insulating film 5 provided on the side surface of the trench H becomes the channel region CR.

[0048] Similar to the GaN semiconductor device 100 according to the first embodiment, the GaN semiconductor device 100A according to the second embodiment has, as the gate insulating film 5, a first insulating film 51 provided on the GaN layer 12, a second insulating film 52 provided on the first insulating film 51, and a third insulating film 53 provided on the second insulating film 52. The first insulating film 51, the second insulating film 52, and the third insulating film 53 are laminated in this order to form the gate insulating film 5.

[0049] The first insulating film 51 is an AlN film formed to a thickness of 2 nm by, for example, the ALD method. The second insulating film 52 is an AlxSiyO film (x > y ≥ 0), for example, an Al 2 O 3 film formed to a thickness of 2 nm by the ALD method. The third insulating film 53 is an Alx´Siy´O film (0 ≤ x´ < y´), for example, a SiO 2 film formed to a thickness of 100 nm by the CVD method.

[0050] According to this, similar to the GaN semiconductor device 100, the GaN semiconductor device 100A can suppress fluctuations in the threshold voltage while suppressing a decrease in the breakdown voltage of the gate insulating film 5. Further, in the GaN semiconductor device 100A, by adopting a trench gate structure for the vertical MOSFET, it becomes possible to arrange the channel regions CR more densely, so that miniaturization of the element becomes easy.

[0051] <Embodiment 3> In the above-mentioned first and second embodiments, the MOSFETs included in the GaN semiconductor devices 100 and 100A are vertical MOSFETs. However, in the embodiments of the present invention, the MOSFETs included in the GaN semiconductor device may be lateral MOSFETs instead of vertical MOSFETs.

[0052] 9 is a cross-sectional view showing a configuration example of a GaN semiconductor device 100B according to embodiment 3 of the present invention. As shown in FIG. 9, the GaN semiconductor device 100B according to embodiment 3 has an n+ type drain region 15 provided on the surface 12a side of the GaN layer 12. A drain electrode 8 is provided on the surface 12a of the GaN layer 12 and is electrically connected to the n+ type drain region 15. In the lateral MOSFET, the region sandwiched between the source region 14 and the drain region 15 and facing the gate electrode 6 via the gate insulating film 5 becomes a channel region CR.

[0053] The GaN semiconductor device 100B of the third embodiment, like the GaN semiconductor device 100 of the first embodiment, has, as the gate insulating film 5, a first insulating film 51 provided on the GaN layer 12, a second insulating film 52 provided on the first insulating film 51, and a third insulating film 53 provided on the second insulating film 52. The first insulating film 51, the second insulating film 52, and the third insulating film 53 are laminated in this order to form the gate insulating film 5. The configurations of the first insulating film 51, the second insulating film 52, and the third insulating film 53 are similar to those of the GaN semiconductor device 100 of the first embodiment. According to this, GaN semiconductor device 100B, like GaN semiconductor device 100, can suppress a decrease in the dielectric breakdown voltage of gate insulating film 5 and suppress a fluctuation in the threshold voltage.

[0054] <Modification> In the above-mentioned first to third embodiments, the second insulating film 52 constituting the gate insulating film 5 is an AlxSiyO film (x>y≧0). As an example, 2 O 3It has been described that it is a film. However, in an embodiment of the present invention, the second insulating film 52 may be an AlxSiyO film (x > y > 0). That is, the second insulating film 52 may have a composition that necessarily contains Si. Thereby, since the composition of the second insulating film 52 and the bonding state between atoms can be made closer to the composition of the third insulating film 53 and the bonding state between atoms, it is possible to reduce the interface levels formed at the interface between the second insulating film 52 and the third insulating film 53.

[0055] Also, in the above-described Embodiments 1 to 3, the third insulating film 53 that constitutes the gate insulating film 5 is an Alx'Siy'O film (0 ≤ x' < y'), and as an example, it is a SiO 2 film. However, in an embodiment of the present invention, the third insulating film 53 may be an Alx'Siy'O film (0 < x' < y'). That is, the third insulating film 53 may have a composition that necessarily contains Al. Thereby, since the composition of the third insulating film 53 can be made closer to the composition of the second insulating film 52, it is possible to reduce the interface levels formed at the interface between the second insulating film 52 and the third insulating film 53.

[0056] <Other Embodiments> As described above, the present invention has been described by way of embodiments and variations, but it should not be understood that the descriptions and drawings that form a part of this disclosure limit the present invention. Various alternative embodiments and variations will be apparent to those skilled in the art from this disclosure. For example, the p-type dopant used in the vertical MOSFET 1 is not limited to magnesium (Mg). The p-type dopant may be beryllium (Be), zinc (Zn), or cadmium (Cd). For example, the channel region CR may contain any one or more of Mg, Be, Zn, and Cd as a p-type dopant at a concentration of 1E+16 / cm 3 or higher.

[0057] 2, an n-type JFET region may be provided in the drift region immediately below the gate insulating film 5. The JFET region is a region having a higher concentration of n-type dopants and a lower electric resistance than the other drift regions. The on-resistance of the vertical MOSFET 1 may be reduced by providing the JFET region.

[0058] In the above embodiment, the GaN layer 12 is exemplified as the "gallium nitride layer" of the present invention, but the "gallium nitride layer" is not limited to the GaN layer. For example, the "gallium nitride layer" may be a bulk GaN substrate. The "gallium nitride layer" may contain GaN as a main component, and may further contain one or more elements selected from the group consisting of aluminum (Al) and indium (In).

[0059] Thus, the present invention naturally includes various embodiments not described here. At least one of various omissions, substitutions, and modifications of components can be made without departing from the spirit of the above-mentioned embodiments and modifications. Furthermore, the effects described in this specification are merely examples and are not limited to the present invention, and other effects may also be present. The technical scope of the present invention is defined only by the invention-specific matters related to the scope of the claims that are appropriate from the above description. [Explanation of symbols]

[0060] 1 Vertical MOSFET 5 Gate insulating film 6 Gate electrode 7. Source Electrode 8 Drain electrode 10 GaN substrate 10a, 12a surface 10b, 11b, 12b back side 11 GaN single crystal substrate 12 GaN layers 13 Well Area 14 Source Area 15 Drain Region 16 Contact Area 51 First insulating film 52 Second insulating film 53 Third insulating film 100, 100A, 100B GaN semiconductor device H Trench

Claims

1. a gallium nitride layer; a gate insulating film provided on the gallium nitride layer; a gate electrode provided on the gate insulating film, The gate insulating film is a first insulating film provided on the gallium nitride layer; A second insulating film provided on the first insulating film; A third insulating film provided on the second insulating film, the first insulating film is an aluminum nitride film, the second insulating film is an AlxSiyO film (x>y>0), The third insulating film is an Alx'Siy'O film (0≦x'<y').

2. A gallium nitride layer, a gate insulating film provided on the gallium nitride layer; a gate electrode provided on the gate insulating film, The gate insulating film is a first insulating film provided on the gallium nitride layer; A second insulating film provided on the first insulating film; A third insulating film provided on the second insulating film, the first insulating film is an aluminum nitride film, the second insulating film is an AlxSiyO film (x>y≧0), The third insulating film is an Alx'Siy'O film (0<x'<y').

3. The AlxSiyO film (x>y≧0) is Al ２ O ３ The nitride semiconductor device according to claim 2 , which is a film.

4. The Alx'Siy'O film (0≦x'<y') is made of SiO ２ The nitride semiconductor device according to claim 1 , which is a film.

5. The nitride semiconductor device according to claim 1 , wherein the first insulating film has a thickness of 0.5 nm or more and 5 nm or less.

6. a MOSFET provided on the gallium nitride layer, The nitride semiconductor device according to claim 1 , wherein said gate insulating film and said gate electrode are included in a MOSFET.

7. The nitride semiconductor device according to claim 6, wherein said MOSFET is a vertical MOSFET.

8. A gallium nitride layer, a gate insulating film provided on the gallium nitride layer; a gate electrode provided on the gate insulating film, The gate insulating film is a first insulating film provided on the gallium nitride layer; A second insulating film provided on the first insulating film; A third insulating film provided on the second insulating film, the first insulating film is an aluminum nitride film, the second insulating film is an AlxSiyO film (x>y≧0), the third insulating film is an Alx'Siy'O film (0≦x'<y'), a thickness of the third insulating film is greater than a total thickness of the first insulating film and the second insulating film.

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