Silicon carbide semiconductor device

Abstract

To provide a silicon carbide semiconductor device in which the number of times of forming epitaxial layers can be reduced.SOLUTION: A silicon carbide semiconductor device comprises a silicon carbide substrate that has a first principal surface and a second principal surface at an opposite side of the first principal surface, the silicon carbide substrate has a drift region, a body region and a source region, a gate trench that is defined by a side surface which penetrates through the source region and the body region to reach to the drift region and a bottom surface connected to the side surface is provided on the first principal surface, the silicon carbide substrate further has a first electric field relaxation region that is provided between the gate trench and the second principal surface and has a second conductivity type, the first electric field relaxation region has a first region that is positioned at a second principal surface side compared to a bottom surface of the gate trench and a second region that projects to a first principal surface side from the first region, a portion of the drift region exists between the second region and the body region, and peak depth of effective concentration of second conductivity type impurity of the first electric field relaxation region is less than or equal to 1.0 μm based on the first principal surface.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to silicon carbide semiconductor devices. [Background technology]

[0002] 2. Description of the Related Art As one type of silicon carbide semiconductor device, a MOS type field effect transistor (Metal Oxide Semiconductor Field Effect Transistor: MOSFET) having a gate trench penetrating a source region and a body region has been disclosed (for example, Patent Documents 1 and 2). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2014-41990 A [Patent Document 2] JP 2017-139441 A Summary of the Invention [Problem to be solved by the invention]

[0004] In order to manufacture a conventional silicon carbide semiconductor device, it is necessary to form an epitaxial layer multiple times on a silicon carbide single crystal substrate. In order to reduce costs, it is desirable to reduce the number of times that the epitaxial layer is formed.

[0005] An object of the present disclosure is to provide a silicon carbide semiconductor device that can reduce the number of times an epitaxial layer is formed. [Means for solving the problem]

[0006] A silicon carbide semiconductor device according to the present disclosure comprises a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface, the silicon carbide substrate having a drift region having a first conductivity type, a body region provided on the drift region and having a second conductivity type different from the first conductivity type, and a source region provided on the body region so as to be separated from the drift region and having the first conductivity type, the first main surface having a side surface defined by a side surface passing through the source region and the body region to reach the drift region, and a bottom surface continuous with the side surface. a gate trench is provided through the bottom surface of the silicon carbide substrate, the silicon carbide substrate further having a first electric field relaxation region having the second conductivity type and provided between the gate trench and the second main surface, the first electric field relaxation region having a first region located closer to the second main surface than the bottom surface and a second region protruding from the first region towards the first main surface, a portion of the drift region is between the second region and the body region, and a peak depth of an effective concentration of the second conductivity type impurity in the first electric field relaxation region with respect to the first main surface is 1.0 μm or less. Effect of the Invention

[0007] According to the present disclosure, the number of times epitaxial layers are formed can be reduced. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a cross-sectional view (part 1) showing the configuration of a silicon carbide semiconductor device according to an embodiment. [Diagram 2] FIG. 2 is a cross-sectional view (part 2) showing the configuration of the silicon carbide semiconductor device according to the embodiment. [Diagram 3] FIG. 3 is a diagram showing a configuration of an interlayer insulating film and a first main surface in the silicon carbide semiconductor device according to the embodiment. [Figure 4] 4A to 4C are cross-sectional views (part 1) illustrating the method for manufacturing a silicon carbide semiconductor device according to the embodiment. [Diagram 5] FIG. 5 is a cross-sectional view (part 2) illustrating the method for manufacturing a silicon carbide semiconductor device according to the embodiment. [Figure 6]6A to 6C are cross-sectional views (part 3) illustrating the method for manufacturing a silicon carbide semiconductor device according to the embodiment. [Figure 7] 7A to 7C are cross-sectional views (part 4) illustrating the method for manufacturing a silicon carbide semiconductor device according to the embodiment. [Figure 8] 8A to 8C are cross-sectional views (part 5) illustrating the method for manufacturing a silicon carbide semiconductor device according to the embodiment. [Figure 9] FIG. 9 is a cross-sectional view (part 6) illustrating the method for manufacturing a silicon carbide semiconductor device according to the embodiment. [Figure 10] FIG. 10 is a cross-sectional view (part 7) illustrating the method for manufacturing a silicon carbide semiconductor device according to the embodiment. [Figure 11] FIG. 11 is a cross-sectional view (part 8) illustrating the method for manufacturing a silicon carbide semiconductor device according to the embodiment. [Figure 12] FIG. 12 is a ninth cross-sectional view illustrating the method for manufacturing a silicon carbide semiconductor device according to the embodiment. [Figure 13] FIG. 13 is a cross-sectional view (part 10) illustrating the method for manufacturing a silicon carbide semiconductor device according to the embodiment. [Figure 14] FIG. 14 is a cross-sectional view (part 11) illustrating the method for manufacturing a silicon carbide semiconductor device according to the embodiment. [Figure 15] FIG. 15 is a twelfth cross-sectional view illustrating the method for manufacturing a silicon carbide semiconductor device according to the embodiment. [Figure 16] FIG. 16 is a thirteenth cross-sectional view illustrating the method for manufacturing a silicon carbide semiconductor device according to an embodiment. [Figure 17] FIG. 17 is a fourteenth cross-sectional view illustrating the method for manufacturing a silicon carbide semiconductor device according to an embodiment. [Figure 18] FIG. 18 is a fifteenth cross-sectional view illustrating the method for manufacturing a silicon carbide semiconductor device according to the embodiment. [Figure 19] FIG. 19 is a cross-sectional view (part 16) illustrating the method for manufacturing a silicon carbide semiconductor device according to the embodiment. [Figure 20] FIG. 20 is a cross-sectional view (part 17) illustrating the method for manufacturing a silicon carbide semiconductor device according to the embodiment. [Figure 21] FIG. 21 is a cross-sectional view showing a configuration of a silicon carbide semiconductor device according to a modified example of the embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] The embodiments for carrying out the invention are described below.

[0010] [Description of the embodiments of the present disclosure] First, the embodiments of the present disclosure will be listed and described. In the following description, the same or corresponding elements are given the same symbols, and the same description will not be repeated. In the crystallographic description in this specification, individual orientations are indicated by [], collective orientations by <>, individual planes by (), and collective planes by {}. In addition, when a crystallographic index is negative, it is usually expressed by placing a "-" (bar) above the number, but in this specification, a negative sign is placed before the number.

[0011] [1] A silicon carbide semiconductor device according to one aspect of the present disclosure includes a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface, the silicon carbide substrate having a drift region having a first conductivity type, a body region provided on the drift region and having a second conductivity type different from the first conductivity type, and a source region provided on the body region to be separated from the drift region and having the first conductivity type, the first main surface having a side surface penetrating the source region and the body region to reach the drift region, and a bottom surface continuous with the side surface. the silicon carbide substrate further has a first electric field relief region having the second conductivity type and provided between the gate trench and the second main surface, the first electric field relief region having a first region located closer to the second main surface than the bottom surface and a second region protruding from the first region toward the first main surface, a part of the drift region is between the second region and the body region, and a peak depth of an effective concentration of an impurity of the second conductivity type in the first electric field relief region with respect to the first main surface is 1.0 μm or less.

[0012] The peak depth of the effective concentration of the second conductivity type impurity in the first electric field buffer region is 1.0 μm or less with respect to the first main surface. Therefore, the source region, the body region, the drift region, and the first electric field buffer region can be appropriately formed without forming the epitaxial layer multiple times. In addition, since the first electric field buffer region includes the second region, even if a high drain voltage is applied during off-state, the penetration of the electric field into the body region can be suppressed, and drain leakage can be suppressed.

[0013] [2] In the above [1], the silicon carbide substrate may have a first connection region that electrically connects the first electric field relief region and the body region and has the second conductivity type. In this case, the first electric field relief region and the body region can be controlled to the same potential, making it easy to suppress drain leakage.

[0014] [3] In the structure [2], the first connection regions may be periodically disposed in a longitudinal direction of the gate trench. In this case, a current path for an on-current can be sufficiently secured while suppressing a drain leakage.

[0015] [4] In any one of [1] to [3], the silicon carbide substrate may have a second electric field relief region that is connected to the body region and has the second conductivity type, sandwiching the body region between the side surface and the silicon carbide substrate, and a lower end surface of the second electric field relief region may be located closer to the first main surface than an upper end surface of the first region. In this case, a part of the drift region is sandwiched between the second region of the first electric field relief region and the second electric field relief region, which makes it easier to suppress drain leakage.

[0016] [5] In the above [4], the silicon carbide substrate may have a second connection region that electrically connects the first electric field relaxation region and the second electric field relaxation region and has the second conductivity type. In this case, the first electric field relaxation region and the second electric field relaxation region can be controlled to the same potential, making it easy to suppress drain leakage.

[0017] [6] In the structure of [5], the second connection regions may be periodically disposed in a longitudinal direction of the gate trench. In this case, a current path for an on-current can be sufficiently secured while suppressing a drain leakage.

[0018] [7] In any one of [1] to [6], the silicon carbide substrate may have a contact region having the first conductivity type, connected to the source region, and sandwiching the source region between the side surface and the silicon carbide substrate, the contact region being thicker than the source region, which makes it easier to form an ohmic contact between a source electrode and the contact region.

[0019] [8] In any of [1] to [7], the side surface of the gate trench may include a {0-33-8} plane. By including the {0-33-8} plane on the side surface, good mobility can be obtained on the side surface of the gate trench, and channel resistance can be reduced.

[0020] [Embodiments of the present disclosure] An embodiment of the present disclosure relates to a so-called vertical MOSFET (silicon carbide semiconductor device). Fig. 1 and Fig. 2 are cross-sectional views showing a configuration of a silicon carbide semiconductor device according to an embodiment. Fig. 3 is a diagram showing a configuration of an interlayer insulating film and a first main surface in a silicon carbide semiconductor device according to an embodiment. Fig. 1 corresponds to a cross-sectional view taken along line II in Fig. 3. Fig. 2 corresponds to a cross-sectional view taken along line II-II in Fig. 3.

[0021] As shown in FIGS. 1 to 3, the MOSFET 100 according to this embodiment mainly includes a silicon carbide substrate 10, a gate insulating film 81, a gate electrode 82, an interlayer insulating film 83, a source electrode 60, a drain electrode 70, a barrier metal film 84, and a passivation film 85. The silicon carbide substrate 10 includes a silicon carbide single crystal substrate 50 and a silicon carbide epitaxial layer 40 on the silicon carbide single crystal substrate 50. The silicon carbide substrate 10 has a first main surface 1 and a second main surface 2 opposite to the first main surface 1. The silicon carbide epitaxial layer 40 constitutes the first main surface 1, and the silicon carbide single crystal substrate 50 constitutes the second main surface 2. The silicon carbide single crystal substrate 50 and the silicon carbide epitaxial layer 40 are made of, for example, hexagonal silicon carbide of polytype 4H. Silicon carbide single crystal substrate 50 contains n-type impurities such as nitrogen (N) and has n-type conductivity (first conductivity type).

[0022] The first main surface 1 is a {0001} plane or a plane inclined at an off angle of 8° or less in the off direction. Preferably, the first main surface 1 is a (000-1) plane or a plane inclined at an off angle of 8° or less in the off direction. The off direction may be, for example, the <11-20> direction or the <1-100> direction. The off angle may be, for example, 1° or more, or 2° or more. The off angle may be 6° or less, or 4° or less.

[0023] The silicon carbide epitaxial layer 40 mainly has a drift region 11, a body region 12, a source region 13, a current spreading region 14, a lower electric field relaxation region 16, an upper electric field relaxation region 17, a first contact region 19, a second contact region 18, a lower connection region 31, and an upper connection region 32.

[0024] The drift region 11 contains n-type impurities such as nitrogen or phosphorus (P) and has an n-type conductivity. The drift region 11 mainly includes, for example, a third region 11C, a fourth region 11D, and a fifth region 11E.

[0025] The current diffusion region 14 is provided on the drift region 11. The current diffusion region 14 contains an n-type impurity such as phosphorus and has an n-type conductivity. The current diffusion region 14 is between the body region 12 and the third region 11C in a direction perpendicular to the second main surface 2. The current diffusion region 14 contacts the body region 12 and the third region 11C. The current diffusion region 14 is closer to the second main surface 2 than the body region 12. The current diffusion region 14 is closer to the first main surface 1 than the third region 11C. The current diffusion region 14 also contacts the side surface 3. The peak value of the effective concentration of the n-type impurity in the current diffusion region 14 is preferably 5×10 17 cm -3 The peak value of the effective concentration of the n-type impurity in the current spreading region 14 is preferably 2×10 17 cm -3 The current spreading region 14 constitutes a part of the drift region.

[0026] The body region 12 is provided on the current diffusion region 14. The body region 12 contains p-type impurities such as aluminum (Al) and has a p-type conductivity (second conductivity type). The body region 12 is between the source region 13 and the current diffusion region 14 in a direction perpendicular to the second main surface 2. The body region 12 is in contact with the source region 13 and the current diffusion region 14. The body region 12 is closer to the second main surface 2 than the source region 13. The body region 12 is closer to the first main surface 1 than the current diffusion region 14. The body region 12 is also in contact with the side surface 3. The body region 12 has a lower end surface 94 that is connected to the side surface 3. The lower end surface 94 is in contact with an upper end surface of the current diffusion region 14. A depth D2 of the lower end surface 94 with respect to the first main surface 1 is, for example, 0.2 μm or more and 0.5 μm or less. An effective concentration of the p-type impurity in the body region 12 is, for example, 5×10 17 cm -3 5×10 or more 18 cm -3 The peak value of the effective concentration of the p-type impurity in the body region 12 is preferably 2×10 18 cm -3That is all. The short channel effect (punch-through) can occur when the depletion layer spreads from the pn junction region into the channel region, causing the entire channel region to become a depletion layer. By increasing the effective concentration of the p-type impurity in the body region 12, the spread of the depletion layer formed in the channel region can be reduced.

[0027] The source region 13 is on the body region 12 in a direction perpendicular to the second main surface 2. The source region 13 is in contact with the body region 12. The source region 13 is provided on the body region 12 so as to be separated from the current spreading region 14 by the body region 12. The source region 13 is closer to the first main surface 1 than the body region 12. The source region 13 is also in contact with the side surface 3. The source region 13 has a lower end surface 97 connected to the side surface 3. The lower end surface 97 is in contact with the upper end surface of the body region 12. The source region 13 has a first thickness T1. The first thickness T1 is, for example, not less than 0.1 μm and not more than 0.3 μm. The source region 13 is covered with a gate insulating film 81. The source region 13 is in direct contact with the gate insulating film 81. The source region 13 contains n-type impurities such as nitrogen or phosphorus, and has n-type conductivity. The source region 13 constitutes the first main surface 1. The effective concentration of the n-type impurity in the source region 13 is, for example, 5×10 18 cm -3 5×10 or more 19 cm -3 The effective concentration of the n-type impurity in the first main surface 1 of the source region 13 is preferably 1×10 19 cm -3 That's all.

[0028] The first contact region 19 contains an n-type impurity such as nitrogen or phosphorus and has an n-type conductivity. The first contact region 19 sandwiches the source region 13 between itself and the side surface 3. That is, the source region 13 is between the side surface 3 and the first contact region 19 in a direction parallel to the first main surface 1. The first contact region 19 is located on the side farther away from the gate trench 5 than the source region 13. The first contact region 19 is connected to the source region 13. The first contact region 19 constitutes the first main surface 1. A lower end surface 96 of the first contact region 19 is located closer to the second main surface 2 than a lower end surface 97 of the source region 13. The first contact region 19 is thicker than the source region 13. The first contact region 19 has a second thickness T2 that is greater than the first thickness T1. The second thickness T2 may be 1.1 times or more and 5.0 times or less than the first thickness T1. The second thickness T2 is, for example, 0.2 μm or more. The second thickness T2 may be 0.2 μm or more and 0.5 μm or less. The effective concentration of n-type impurities in the first contact region 19 may be approximately the same as the effective concentration of n-type impurities in the source region 13. The effective concentration of n-type impurities in the first contact region 19 may be, for example, 5×10 18 cm -3 5×10 or more 19 cm -3 The first contact region 19 is an example of a contact region having a first conductivity type.

[0029] The second contact region 18 contains p-type impurities such as aluminum and has p-type conductivity. The effective concentration of the p-type impurities in the second contact region 18 is higher than the effective concentration of the p-type impurities in the body region 12. The second contact region 18 penetrates the first contact region 19 and contacts the body region 12. The second contact region 18 constitutes the first main surface 1. The effective concentration of the p-type impurities in the second contact region 18 is, for example, 1×10 18 cm -3 More than 1×10 20 cm -3 The following is the result.

[0030] The first main surface 1 is provided with a gate trench 5 defined by a side surface 3 and a bottom surface 4. The side surface 3 penetrates the source region 13, the body region 12, the current diffusion region 14, and the drift region 11 to reach the lower electric field relaxation region 16. The bottom surface 4 is continuous with the side surface 3. The bottom surface 4 is located in the lower electric field relaxation region 16. The bottom surface 4 is, for example, a plane parallel to the second main surface 2. An angle θ1 of the side surface 3 with respect to a plane including the bottom surface 4 is, for example, 45° or more and 65° or less. The angle θ1 may be, for example, 50° or more. The angle θ1 may be, for example, 60° or less. The side surface 3 preferably has a {0-33-8} plane. The {0-33-8} plane is a crystal plane that provides excellent mobility. The gate trench 5 extends in a stripe shape along a first direction parallel to the first main surface 1, for example. When viewed in a plan view from a direction perpendicular to the first main surface 1, a plurality of gate trenches 5 are provided at regular intervals in a second direction perpendicular to the first direction. The plurality of gate trenches 5 may be provided, for example, in an array.

[0031] The lower electric field relaxation region 16 includes p-type impurities such as aluminum and has a p-type conductivity. The lower electric field relaxation region 16 is between the current diffusion region 14 and the second main surface 2. When viewed in a plan view from a direction perpendicular to the first main surface 1, the lower electric field relaxation region 16 includes a portion overlapping with the gate trench 5. For example, the lower electric field relaxation region 16 is between the bottom surface 4 of the gate trench 5 and the second main surface 2, and the upper end surface of the lower electric field relaxation region 16 includes, for example, the bottom surface 4 of the gate trench 5. A part of the upper end surface of the lower electric field relaxation region 16 faces a part of the lower end surface of the current diffusion region 14. When viewed in a plan view from a direction perpendicular to the first main surface 1, the lower electric field relaxation region 16 has a side end surface 92 on a side farther away from the gate trench 5 than a first position 91 where the current diffusion region 14, the body region 12, and the side surface 3 contact each other. The lower electric field relaxation region 16 may be electrically connected to a source electrode 60. The effective concentration of the p-type impurity in the lower electric field relaxation region 16 is, for example, 5×10 17 cm -3 5×10 or more 18 cm -3or less. With respect to the first main surface 1, a peak depth D1 of the effective concentration of the p-type impurity in the lower electric field relief region 16 is, for example, 1.0 μm or less. The peak depth D1 may be 0.8 μm or more and 1.0 μm or less. The thickness of the lower electric field relief region 16 in a direction perpendicular to the first main surface 1 may be 0.4 μm or more and 0.6 μm or less. The lower electric field relief region 16 is an example of a first electric field relief region.

[0032] The lower electric field reduction region 16 has a first region 16A and a second region 16B. The first region 16A is located closer to the second main surface 2 than the bottom surface 4 of the gate trench 5. The second region 16B protrudes from the first region 16A toward the first main surface 1. The second region 16B is located between the first position 91 and the side end surface 92 when viewed in a plan view from a direction perpendicular to the first main surface 1. The lower end surface of the current diffusion region 14 includes a portion that is recessed toward the first main surface 1 in a concave shape following the second region 16B.

[0033] The upper electric field relief region 17 contains p-type impurities such as aluminum and has p-type conductivity. The upper electric field relief region 17 sandwiches the body region 12 between itself and the side surface 3. That is, the body region 12 is between the side surface 3 and the upper electric field relief region 17 in a direction parallel to the first main surface 1. The upper electric field relief region 17 is located on a side farther away from the gate trench 5 than the body region 12. The upper electric field relief region 17 is connected to the body region 12. The upper electric field relief region 17 is located closer to the second main surface 2 than the first contact region 19 and the second contact region 18. The upper electric field relief region 17 may overlap the first contact region 19 and the second contact region 18 when viewed in a plan view from a direction perpendicular to the first main surface 1.

[0034] A lower end surface 93 of the upper electric field relief region 17 is located closer to the second main surface 2 than a lower end surface 94 of the body region 12. In other words, a depth D3 of the lower end surface 93 with respect to the first main surface 1 is greater than a depth D2 of the lower end surface 94. The lower end surface 93 of the upper electric field relief region 17 is located closer to the first main surface 1 than an upper end surface 95 of the first region 16A of the lower electric field relief region 16. In other words, the lower end surface 93 of the upper electric field relief region 17 is located closer to the first main surface 1 than the bottom surface 4 of the gate trench 5. The upper electric field relief region 17 may penetrate the current spreading region 14. The effective concentration of p-type impurities in the upper electric field relief region 17 is preferably 1×10 18 cm -3 More than 2×10 19 cm -3 This is to obtain a good breakdown voltage and short circuit resistance. In addition, the effective concentration of the p-type impurity in the upper electric field relaxation region 17 is 1×10 18 cm -3 More than 2×10 19 cm -3 If it is equal to or less than this, it is easy to ensure the current spreading region 14. The upper electric field buffer region 17 is an example of the second electric field buffer region.

[0035] The third region 11C of the drift region 11 is between the current diffusion region 14 and the lower electric field reduction region 16. The third region 11C is in contact with the current diffusion region 14 and the lower electric field reduction region 16. The third region 11C is located closer to the second main surface 2 than the current diffusion region 14. The third region 11C is located closer to the first main surface 1 than the lower electric field reduction region 16. The effective concentration of n-type impurities in the third region 11C is, for example, 5×10 15 cm -3 5×10 or more 16 cm -3 The following is the result.

[0036] The fourth region 11D is located closer to the second major surface 2 than the third region 11C. The fourth region 11D is continuous with the third region 11C. The fourth region 11D is in contact with the lower electric field reduction region 16 in a direction parallel to the second major surface 2. The fourth region 11D and the lower electric field reduction region 16 may be located in the same plane parallel to the second major surface 2. The effective concentration of n-type impurities in the fourth region 11D may be higher than the effective concentration of n-type impurities in the third region 11C. The effective concentration of n-type impurities in the fourth region 11D is, for example, 5×10 16 cm -3 5×10 or more 17 cm -3 The following is the result.

[0037] The fifth region 11E is located closer to the second main surface 2 than the fourth region 11D. The fifth region 11E is continuous with the fourth region 11D. The fifth region 11E is in contact with the lower electric field relaxation region 16. The fifth region 11E is located closer to the second main surface 2 than the lower electric field relaxation region 16. The fifth region 11E may be between the fourth region 11D and the silicon carbide single crystal substrate 50. The fifth region 11E may be continuous with the silicon carbide single crystal substrate 50. The effective concentration of n-type impurities in the fifth region 11E may be lower than the effective concentration of n-type impurities in the fourth region 11D. The effective concentration of n-type impurities in the fifth region 11E may be, for example, 5×10 15 cm -3 5×10 or more 16 cm -3 The following is the result.

[0038] The gate insulating film 81 is, for example, an oxide film. The gate insulating film 81 is made of, for example, a material containing silicon dioxide. The gate insulating film 81 contacts the side surface 3 and the bottom surface 4. The gate insulating film 81 contacts the lower electric field reduction region 16 at the bottom surface 4. The gate insulating film 81 contacts each of the source region 13, the body region 12, the current diffusion region 14, and the third region 11C at the side surface 3. The gate insulating film 81 may be in contact with the source region 13 at the first main surface 1.

[0039] The gate electrode 82 is provided on the gate insulating film 81. The gate electrode 82 is made of, for example, polysilicon (poly-Si) containing conductive impurities. The gate electrode 82 is disposed inside the gate trench 5. A part of the gate electrode 82 may be disposed on the first main surface 1.

[0040] The interlayer insulating film 83 is provided in contact with the gate electrode 82 and the gate insulating film 81. The interlayer insulating film 83 is made of a material containing, for example, silicon dioxide. The interlayer insulating film 83 electrically insulates the gate electrode 82 from the source electrode 60. A part of the interlayer insulating film 83 may be provided inside the gate trench 5.

[0041] In the interlayer insulating film 83 and the gate insulating film 81, contact holes 86 are formed at regular intervals in the second direction. The contact holes 86 are provided such that the gate trench 5 is located between the contact holes 86 adjacent to each other in the second direction when viewed in a plan view from a direction perpendicular to the first main surface 1. The contact holes 86 extend in the first direction. Through the contact holes 86, the source region 13, the first contact region 19, and the second contact region 18 are exposed from the interlayer insulating film 83 and the gate insulating film 81. The second contact regions 18 do not need to be arranged over the entire area in the first direction (the longitudinal direction of the gate trench 5), and may be arranged periodically, for example, as shown in FIG. 3.

[0042] The lower connection region 31 contains p-type impurities such as aluminum and has p-type conductivity. The lower connection region 31 is between the lower electric field relief regions 16 adjacent in the second direction and is in contact with both of these lower electric field relief regions 16 adjacent in the second direction. The lower connection region 31 and the lower electric field relief region 16 may be located on the same plane parallel to the second main surface 2. The lower connection region 31 is periodically arranged in the first direction. The lower connection region 31 is, for example, arranged with the same period as the second contact regions 18 in the first direction. The effective concentration of the p-type impurity in the lower connection region 31 may be approximately the same as the effective concentration of the p-type impurity in the lower electric field relief region 16. The effective concentration of the p-type impurity in the lower connection region 31 may be, for example, 1×10 17 cm -3 5×10 or more 18 cm -3 The following is the result.

[0043] The upper connection region 32 contains p-type impurities such as aluminum and has p-type conductivity. The upper connection region 32 is between the lower connection region 31 and the upper electric field relief region 17 in a direction perpendicular to the second main surface 2, and is in contact with the lower connection region 31 and the upper electric field relief region 17. The upper connection region 32 is on the second main surface 2 side of the upper electric field relief region 17. The upper connection region 32 is on the first main surface 1 side of the lower connection region 31. The upper connection region 32 is periodically arranged in the first direction, similar to the lower connection region 31. The upper connection region 32 is periodically arranged in the first direction as the upper connection region 32. The effective concentration of the p-type impurity in the upper connection region 32 is, for example, 1×10 17 cm -3 5×10 or more 18 cm -3 The following is the result.

[0044] The second contact region 18 contacts the body region 12, the body region 12 contacts the upper electric field relief region 17, the upper electric field relief region 17 contacts the upper connection region 32, the upper connection region 32 contacts the lower connection region 31, and the upper connection region 32 contacts the lower electric field relief region 16. In this manner, the lower electric field relief region 16 is electrically connected to the second contact region 18. The upper electric field relief region 17, the lower connection region 31, and the upper connection region 32 function as a first connection region 33 that electrically connects the lower electric field relief region 16 and the body region 12. The lower connection region 31 and the upper connection region 32 function as a second connection region 34 that electrically connects the lower electric field relief region 16 and the upper electric field relief region 17.

[0045] The barrier metal film 84 covers the upper surface and side surfaces of the interlayer insulating film 83 and the side surfaces of the gate insulating film 81. The barrier metal film 84 is in contact with each of the interlayer insulating film 83 and the gate insulating film 81. The barrier metal film 84 is made of a material containing, for example, titanium nitride (TiN).

[0046] The source electrode 60 is in contact with the first main surface 1. The source electrode 60 has a contact electrode 61 and a source wiring 62. The contact electrode 61 may be in contact with the source region 13, the second contact region 18, and the first contact region 19 on the first main surface 1. The contact electrode 61 is made of a material containing, for example, nickel silicide (NiSi). The contact electrode 61 may be made of a material containing titanium, aluminum, and silicon. The contact electrode 61 is in ohmic junction with the first contact region 19. The contact electrode 61 may be in ohmic junction with the second contact region 18. The source wiring 62 covers the upper surface and side surfaces of the barrier metal film 84 and the upper surface of the contact electrode 61. The source wiring 62 is in contact with each of the barrier metal film 84 and the contact electrode 61. The source wiring 62 is made of a material containing, for example, aluminum.

[0047] The passivation film 85 covers the upper surface of the source wiring 62. The passivation film 85 is in contact with the source wiring 62. The passivation film 85 is made of a material containing, for example, polyimide.

[0048] The drain electrode 70 is in contact with the second main surface 2. The drain electrode 70 is in contact with the silicon carbide single crystal substrate 50 at the second main surface 2. The drain electrode 70 is electrically connected to the drift region 11. The drain electrode 70 is made of a material containing nickel silicide, for example. The drain electrode 70 may be made of a material containing titanium, aluminum, and silicon. The drain electrode 70 is in ohmic junction with the silicon carbide single crystal substrate 50.

[0049] In a direction perpendicular to the second main surface 2, the upper end surface of the lower electric field relief region 16 may be spaced from the bottom surface 4. In this case, for example, the bottom surface 4 may be located in the drift region 11, and the side surface 3 may reach the drift region 11 through the source region 13, the body region 12, and the current spreading region 14. For example, a third region 11C may be present between the upper end surface of the lower electric field relief region 16 and the bottom surface 4.

[0050] A buffer layer containing an n-type impurity such as nitrogen and having n-type conductivity may be provided between silicon carbide single crystal substrate 50 and fifth region 11E. The effective concentration of the n-type impurity in the buffer layer may be higher than the effective concentration of the n-type impurity in fifth region 11E.

[0051] In the present disclosure, the effective concentration of p-type impurities is the difference between the concentration of p-type impurities and the concentration of n-type impurities, and the effective concentration of n-type impurities is the difference between the concentration of n-type impurities and the concentration of p-type impurities. The effective concentrations can be measured, for example, by the following steps 1 to 4.

[0052] (Step 1) The surface of the semiconductor device is observed to identify an element region.

[0053] (Step 2) The semiconductor device is processed so that a cross section of the semiconductor region appears as shown in Fig. 2. For example, a focused ion beam (FIB) device is used to process the cross section of the semiconductor device.

[0054] (Step 3) Using a scanning electron microscope (SEM), determine whether the conductivity type of the region where the impurities were implanted is p-type or n-type. For example, when SEM observation is performed under conditions of an acceleration voltage of 3 kV and a magnification of 10,000 times, the bright regions are p-type regions and the dark regions are n-type regions.

[0055] (Step 4) The impurity concentrations of the p-type and n-type regions in the above cross section are measured using a scanning spreading resistance microscope (SSRM). The concentration in the p-type region is the effective concentration of the p-type impurity, and the concentration in the n-type region is the effective concentration of the n-type impurity.

[0056] Next, a method for manufacturing the MOSFET 100 according to the embodiment will be described. Figs. 4 to 20 are cross-sectional views showing the method for manufacturing the MOSFET 100 according to the embodiment. Figs. 4 to 6, 8 to 10, and 12 to 20 correspond to cross-sectional views taken along line II in Fig. 3, similar to Fig. 1. Figs. 7, 11, and 14 correspond to cross-sectional views taken along line II-II in Fig. 3, similar to Fig. 2.

[0057] First, as shown in Fig. 4, a silicon carbide single crystal substrate 50 is prepared. For example, a silicon carbide ingot (not shown) manufactured by sublimation is sliced ​​to prepare the silicon carbide single crystal substrate 50. A buffer layer (not shown) may be formed on the silicon carbide single crystal substrate 50. The buffer layer may be formed by a chemical vapor deposition (CVD) method using, for example, a mixed gas of silane (SiH4) and propane (C3H8) as a source gas and, for example, hydrogen (H2) as a carrier gas. During epitaxial growth of the buffer layer, an n-type impurity such as nitrogen may be introduced into the buffer layer.

[0058] Next, as also shown in Fig. 4, epitaxial layer 21 is formed. For example, epitaxial layer 21 is formed on silicon carbide single crystal substrate 50 by a CVD method using a mixed gas of silane and propane as a source gas and hydrogen as a carrier gas. During epitaxial growth, n-type impurities such as nitrogen are introduced into epitaxial layer 21. Epitaxial layer 21 has n-type conductivity. The effective concentration of n-type impurities in epitaxial layer 21 may be lower than the effective concentration of n-type impurities in the buffer layer.

[0059] 5, a mask layer 150 having an opening 151 is formed on the region where the lower electric field reduction region 16 and the lower connection region 31 are to be formed. The mask layer 150 is made of a material containing silicon dioxide, for example. In forming the mask layer 150, after forming a silicon dioxide film, the silicon dioxide film is etched using a photoresist mask. This etching is performed under conditions such that the opening area at the bottom of the opening 151 is smaller than that at the top.

[0060] Next, as shown in Fig. 6 and Fig. 7, p-type impurity ions capable of imparting p-type, such as aluminum ions, are implanted into the epitaxial layer 21. This forms the lower electric field relaxation region 16 and the lower connection region 31. The lower electric field relaxation region 16 and the lower connection region 31 are each formed inside the epitaxial layer 21 so as not to be exposed on the surface of the epitaxial layer 21. The lower electric field relaxation region 16 and the lower connection region 31 may be formed simultaneously or separately. The implantation energy of the p-type impurity ions when forming the lower electric field relaxation region 16 and the lower connection region 31 may be 700 keV or more and 1200 keV or less. The peak depth of the effective concentration of the p-type impurity in the lower electric field relaxation region 16 and the lower connection region 31 based on the first main surface 1 may be, for example, 0.8 µm or more and 1.0 µm or less.

[0061] The opening area of ​​the opening 151 of the mask layer 150 used for forming the lower electric field relief region 16 and the lower connection region 31 is smaller at the lower end than at the upper end. Therefore, the lower electric field relief region 16 is likely to be formed shallower on the side wall surface of the opening 151 on the second main surface 2 side than in the center of the opening 151, and is formed to include a first region 16A and a second region 16B.

[0062] 8, the body region 12 is formed. For example, p-type impurity ions capable of imparting p-type, such as aluminum ions, are implanted into the entire surface of the epitaxial layer 21. This forms the body region 12. The implantation energy of the p-type impurity ions when forming the body region 12 may be 200 keV or more and 400 keV or less. The thickness of the body region 12 is, for example, 0.2 μm or more and 0.5 μm or less.

[0063] 9, the current spreading region 14 is formed. For example, n-type impurity ions capable of imparting n-type, such as phosphorus ions, are implanted into the entire surface of the epitaxial layer 21. This forms the current spreading region 14. The implantation energy of the n-type impurity ions when forming the current spreading region 14 may be set to be equal to or higher than 300 keV and equal to or lower than 800 keV.

[0064] 10, the source region 13 is formed. For example, n-type impurity ions capable of imparting n-type, such as phosphorus ions, are implanted into the entire surface of the epitaxial layer 21. This forms the source region 13. The implantation energy of the n-type impurity ions when forming the source region 13 may be 50 keV or more and 150 keV or less. The thickness of the source region 13 is, for example, 0.1 μm or more and 0.3 μm or less.

[0065] 11, the upper connection region 32 is formed. For example, a mask layer (not shown) having an opening on a region where the upper connection region 32 is to be formed is formed. Next, p-type impurity ions capable of imparting p-type, such as aluminum ions, are implanted into the drift region 11. This forms the upper connection region 32. The implantation energy of the p-type impurity ions when forming the upper connection region 32 may be set to be not less than 400 keV and not more than 900 keV.

[0066] 12, the upper electric field relaxation region 17 is formed. For example, a mask layer (not shown) having an opening on a region where the upper electric field relaxation region 17 is to be formed is formed. Next, p-type impurity ions capable of imparting p-type, such as aluminum ions, are implanted into the epitaxial layer 21. This forms the upper electric field relaxation region 17. The implantation energy of the p-type impurity ions when forming the upper electric field relaxation region 17 may be set to be not less than 300 keV and not more than 800 keV.

[0067] 13, the first contact region 19 is formed. For example, a mask layer (not shown) having an opening on the region where the first contact region 19 is to be formed is formed. Next, n-type impurity ions capable of imparting n-type, such as phosphorus ions, are implanted into the epitaxial layer 21. This forms the first contact region 19. The implantation energy of the n-type impurity ions when forming the first contact region 19 may be 100 keV or more and 300 keV or less. The mask layer used for forming the upper electric field reduction region 17 may be used as it is for forming the first contact region 19.

[0068] Next, as shown in FIG. 14, the second contact region 18 is formed. For example, a mask layer (not shown) having an opening on a region where the second contact region 18 is to be formed is formed. Next, p-type impurity ions capable of imparting p-type, such as aluminum ions, are implanted into the first contact region 19 and the body region 12. This forms the second contact region 18 in contact with the body region 12. The implantation energy of the p-type impurity ions when forming the second contact region 18 may be 50 keV or more and 300 keV or less. The drift region 11 is formed from a portion of the epitaxial layer 21 into which the impurity ions have not been implanted after the formation of the epitaxial layer 21.

[0069] Next, activation annealing is performed to activate the impurity ions implanted into the silicon carbide substrate 10. The temperature of the activation annealing is preferably 1500° C. or higher and 1900° C. or lower, for example, about 1700° C. The time of the activation annealing is, for example, about 30 minutes. The atmosphere of the activation annealing is preferably an inert gas atmosphere, for example, an argon (Ar) atmosphere.

[0070] Next, as shown in FIG. 15, a gate trench 5 is formed. For example, a mask layer (not shown) having an opening at a position where the gate trench 5 is to be formed is formed on the first main surface 1. Using the mask layer, a part of the source region 13, a part of the body region 12, a part of the current diffusion region 14, and a part of the drift region 11 are removed by etching. For example, reactive ion etching, particularly inductively coupled plasma reactive ion etching, can be used as the etching method. Specifically, for example, inductively coupled plasma reactive ion etching using sulfur hexafluoride (SF6) or a mixed gas of SF6 and oxygen (O2) as a reactive gas can be used. By etching, a recess (not shown) having a side portion substantially perpendicular to the first main surface 1 and a bottom portion that is continuous with the side portion and is substantially parallel to the first main surface 1 is formed in the region where the gate trench 5 is to be formed.

[0071] Next, thermal etching is performed in the recess. The thermal etching can be performed, for example, by heating in an atmosphere containing a reactive gas having at least one or more types of halogen atoms, with the mask layer formed on the first main surface 1. The at least one or more types of halogen atoms include at least one of chlorine (Cl) atoms and fluorine (F) atoms. The atmosphere includes, for example, chlorine (Cl2), boron trichloride (BCl3), SF6, or carbon tetrafluoride (CF4). For example, a mixed gas of chlorine gas and oxygen gas is used as the reactive gas, and the thermal etching is performed at a heat treatment temperature of, for example, 800°C or more and 900°C or less. The reactive gas may contain a carrier gas in addition to the above-mentioned chlorine gas and oxygen gas. For example, nitrogen gas, argon gas, helium gas, or the like can be used as the carrier gas.

[0072] By the above thermal etching, a gate trench 5 is formed in the first main surface 1 of the silicon carbide substrate 10. The gate trench 5 is defined by a side surface 3 and a bottom surface 4. The side surface 3 is composed of a source region 13, a body region 12, a current diffusion region 14, and a drift region 11. The bottom surface 4 is composed of a lower electric field reduction region 16. An angle θ1 between the side surface 3 and a plane including the bottom surface 4 is, for example, not less than 45° and not more than 65°. Next, the mask layer is removed from the first main surface 1.

[0073] Next, as shown in FIG. 16, a gate insulating film 81 is formed. For example, the silicon carbide substrate 10 is thermally oxidized to form the gate insulating film 81 in contact with the source region 13, the body region 12, the current diffusion region 14, the drift region 11, the lower electric field relaxation region 16, the first contact region 19, and the second contact region 18. Specifically, the silicon carbide substrate 10 is heated in an atmosphere containing oxygen at a temperature of, for example, 1300° C. or higher and 1400° C. or lower. As a result, the gate insulating film 81 in contact with the first main surface 1, the side surface 3, and the bottom surface 4 is formed. Note that, when the gate insulating film 81 is formed by thermal oxidation, strictly speaking, a part of the silicon carbide substrate 10 is taken into the gate insulating film 81. For this reason, in the subsequent processing, it is assumed that the first main surface 1, the side surface 3, and the bottom surface 4 have moved slightly to the interface between the gate insulating film 81 and the silicon carbide substrate 10 after thermal oxidation.

[0074] Next, the silicon carbide substrate 10 may be subjected to a heat treatment (NO annealing) in a nitric oxide (NO) gas atmosphere. In the NO annealing, the silicon carbide substrate 10 is held, for example, for about one hour under conditions of 1100° C. or higher and 1400° C. or lower. This introduces nitrogen atoms into the interface region between the gate insulating film 81 and the body region 12. As a result, the formation of an interface state in the interface region is suppressed, and channel mobility can be improved.

[0075] After the NO annealing, Ar annealing may be performed using argon (Ar) as the atmospheric gas. The heating temperature of the Ar annealing is, for example, equal to or higher than the heating temperature of the NO annealing. The time of the Ar annealing is, for example, about one hour. This further suppresses the formation of an interface state in the interface region between the gate insulating film 81 and the body region 12. Note that, instead of Ar gas, other inert gases such as nitrogen gas may be used as the atmospheric gas.

[0076] 17, a gate electrode 82 is formed. The gate electrode 82 is formed on the gate insulating film 81. The gate electrode 82 is formed by, for example, a low pressure chemical vapor deposition (LP-CVD) method. The gate electrode 82 is formed so as to face each of the source region 13, the body region 12, the current diffusion region 14, and the drift region 11.

[0077] 18, an interlayer insulating film 83 is formed. Specifically, the interlayer insulating film 83 is formed so as to cover the gate electrode 82 and to be in contact with the gate insulating film 81. The interlayer insulating film 83 is formed by, for example, a CVD method. The interlayer insulating film 83 is made of, for example, a material containing silicon dioxide. A part of the interlayer insulating film 83 may be formed inside the gate trench 5.

[0078] 19, a contact hole 86 is formed in the interlayer insulating film 83 and the gate insulating film 81. The first contact region 19 and the second contact region 18 are exposed from the interlayer insulating film 83 and the gate insulating film 81 in the contact hole 86. The source region 13 is preferably left covered with the gate insulating film 81 and the interlayer insulating film 83.

[0079] Next, as shown in FIG. 20, a barrier metal film 84, a contact electrode 61, and a drain electrode 70 are formed. For example, a barrier metal film 84 is formed to cover the upper surface and side surface of the interlayer insulating film 83 and the side surface of the gate insulating film 81. When viewed in a plan view from a direction perpendicular to the first main surface 1, it is preferable that the source region 13 is located inside the side end surface of the barrier metal film 84. The barrier metal film 84 is made of a material containing, for example, titanium nitride. The barrier metal film 84 is formed by, for example, film formation by a sputtering method and reactive ion etching (RIE). Next, a metal film (not shown) for the contact electrode 61 that contacts the first contact region 19 and the second contact region 18 on the first main surface 1 is formed. The metal film for the contact electrode 61 is formed by, for example, a sputtering method. The metal film for the contact electrode 61 is made of a material containing, for example, nickel. Next, a metal film (not shown) for the drain electrode 70 that contacts the silicon carbide single crystal substrate 50 on the second main surface 2 is formed. The metal film for the drain electrode 70 is formed by, for example, a sputtering method. The metal film for the drain electrode 70 is made of, for example, a material containing nickel.

[0080] Next, alloying annealing is performed. The metal film for the contact electrode 61 and the metal film for the drain electrode 70 are held at a temperature of, for example, 900° C. or higher and 1100° C. or lower for about 5 minutes. As a result, at least a part of the metal film for the contact electrode 61 and at least a part of the metal film for the drain electrode 70 react with silicon contained in the silicon carbide substrate 10 to be silicided. As a result, the contact electrode 61 in ohmic contact with the first contact region 19 and the drain electrode 70 in ohmic contact with the silicon carbide single crystal substrate 50 are formed. When viewed in a plan view from a direction perpendicular to the first main surface 1, if the source region 13 is located inside the side end surface of the barrier metal film 84, the contact electrode 61 is formed so that the side end surface of the contact electrode 61 is farther away from the gate trench 5 than the boundary surface between the source region 13 and the first contact region 19. Although a part of the first contact region 19 is consumed by the silicidation, the source region 13 is not consumed because the source region 13 is covered with the gate insulating film 81 and the interlayer insulating film 83. The contact electrode 61 may form an ohmic junction with the second contact region 18. The contact electrode 61 may be made of a material containing titanium, aluminum, and silicon. The drain electrode 70 may be made of a material containing titanium, aluminum, and silicon.

[0081] Next, the source wiring 62 is formed. Specifically, the source wiring 62 is formed to cover the contact electrode 61 and the barrier metal film 84. The source wiring 62 is formed by, for example, film formation using a sputtering method and RIE. The source wiring 62 is made of, for example, a material containing aluminum. In this manner, the source electrode 60 having the contact electrode 61 and the source wiring 62 is formed.

[0082] Next, the passivation film 85 is formed. Specifically, the passivation film 85 is formed to cover the source wiring 62. The passivation film 85 is made of a material including, for example, polyimide. The passivation film 85 is formed by, for example, a coating method.

[0083] In this manner, the MOSFET 100 according to the embodiment is completed.

[0084] Next, the effects of the MOSFET according to this embodiment will be described.

[0085] In the MOSFET 100 according to this embodiment, the peak depth of the effective concentration of the p-type impurity in the lower electric field relaxation region 16 is 1.0 μm or less with respect to the first main surface 1. Therefore, the source region 13, the body region 12, the current diffusion region 14, the drift region 11, and the lower electric field relaxation region 16 can be appropriately formed by ion implantation without forming epitaxial layers multiple times. In addition, since the lower electric field relaxation region 16 includes the second region 16B, even if a high drain voltage is applied during off-state, penetration of an electric field into the body region 12 can be suppressed, thereby suppressing drain leakage.

[0086] When the peak depth D1 is small, unlike the above-mentioned manufacturing method, regrowth of the epitaxial layer is not required after the formation of the lower electric field relaxation region 16. Therefore, the cost associated with the regrowth of the epitaxial layer can be reduced. Moreover, high-energy ion implantation is not required when forming the lower electric field relaxation region 16. Therefore, the increase in cost associated with high-energy ion implantation can be avoided.

[0087] Furthermore, the smaller the first thickness T1 of the source region 13, the more the drain current during a short circuit is reduced, and the more the short circuit resistance can be improved. On the other hand, since the second thickness T2 of the first contact region 19 is greater than the first thickness T1, even if a part of the first contact region 19 is consumed when the contact electrode 61 is formed, the source electrode 60 including the contact electrode 61 can be easily ohmic-contacted to the first contact region 19.

[0088] The lower electric field relief region 16 and the body region 12 are electrically connected to each other via the lower connection region 31, the upper connection region 32, and the upper electric field relief region 17. Therefore, the lower electric field relief region 16 and the body region 12 are controlled to the same potential, making it easy to suppress drain leakage. In addition, the lower connection region 31 and the upper connection region 32 are periodically arranged in the first direction. Therefore, it is easy to suppress drain leakage while sufficiently securing a current path for the on-current.

[0089] The lower end surface 93 of the upper electric field relief region 17 is located closer to the first main surface 1 than the upper end surface 95 of the first region 16A of the lower electric field relief region 16. Therefore, the current spreading region 14 and the third region 11C of the drift region 11 are sandwiched between the second region 16B of the lower electric field relief region 16 and the upper electric field relief region 17, making it easier to suppress drain leakage.

[0090] The lower electric field relaxation region 16 and the upper electric field relaxation region 17 are electrically connected to each other via the lower connection region 31 and the upper connection region 32. Therefore, the lower electric field relaxation region 16 and the upper electric field relaxation region 17 can be controlled to the same potential, making it easy to suppress drain leakage.

[0091] Furthermore, by increasing the effective concentration of the n-type impurity in the current diffusion region 14, an increase in the on-resistance can be suppressed even if the second region 16B is provided.

[0092] [Variations] Next, a modified example of the embodiment will be described. The modified example differs from the embodiment mainly in the shape of the gate trench. Fig. 21 is a cross-sectional view showing a configuration of a MOSFET (silicon carbide semiconductor device) according to the modified example of the embodiment. Fig. 21 shows a cross section similar to the cross section taken along line II in Fig. 3.

[0093] 21, in a MOSFET 200 according to the modification, a gate trench 5 is a vertical trench. That is, an angle θ1 of a side surface 3 with respect to a plane including a bottom surface 4 may be 90°. The other configurations are the same as those of the embodiment.

[0094] Even with such a modification, the same effects as those of the embodiment can be obtained.

[0095] In the above embodiment and reference example, n type is the first conductivity type and p type is the second conductivity type, but p type may be the first conductivity type and n type may be the second conductivity type. In the above embodiment and reference example, MOSFET is exemplified as the silicon carbide semiconductor device, but the silicon carbide semiconductor device may be, for example, an insulated gate bipolar transistor (IGBT). The effective concentration of p-type impurities and the effective concentration of n-type impurities in each of the impurity regions can be measured by, for example, a scanning capacitance microscope (SCM) method or a secondary ion mass spectrometry (SIMS) method. The position of the boundary surface (i.e., pn junction interface) between the p-type region and the n-type region can be identified by, for example, the SCM method or the SIMS method. The distribution of the effective concentration of majority carriers in the current spreading region can be determined based on, for example, the distribution of the thickness of the depletion layer generated by the pn junction between the current spreading region and the body region, without measuring the effective concentration. The thickness of the depletion layer can be determined by, for example, the SCM method or the SIMS method.

[0096] The gate trenches may extend in a honeycomb shape or may be scattered in an island shape.

[0097] Although the embodiments have been described in detail above, the present invention is not limited to the specific embodiments, and various modifications and changes are possible within the scope of the claims. [Explanation of symbols]

[0098] 1 First main surface 2 Second main surface 3. Aspects 4 Bottom 5. Gate trench 10 Silicon carbide substrate 11 Drift Region 11C Third area 11D 4th area 11E 5th area 12 Body Region 13 Source Area 14 Current spreading region 16 Lower electric field relaxation region 16A 1st area 16B 2nd area 17 Upper electric field relaxation region 18 Second Contact Area 19 First Contact Area 21 Epitaxial layer 31 Lower connection area 32 Upper connection area 33 First Connection Area 34 Second Connection Area 40 Silicon carbide epitaxial layer 50 Silicon carbide single crystal substrate 60 Source electrode 61 Contact electrode 62 Source wiring 70 Drain electrode 81 Gate insulating film 82 Gate electrode 83 Interlayer insulating film 84 Barrier metal film 85 Passivation Film 86 Contact Hole 91 1st position 92 Side end face 93, 94, 96, 97 Lower end surface 95 Upper end surface 100, 200 MOSFETs 150 Mask Layers 151 Opening

Claims

1. a silicon carbide substrate having a first main surface and a second main surface opposite the first main surface; The silicon carbide substrate is a drift region having a first conductivity type; a body region provided on the drift region and having a second conductivity type different from the first conductivity type; a source region having the first conductivity type and provided on the body region to be separated from the drift region; having a gate trench is provided in the first main surface, the gate trench being defined by a side surface that penetrates the source region and the body region to reach the drift region and a bottom surface that is continuous with the side surface; The silicon carbide substrate is a first electric field relief region having the second conductivity type, the first electric field relief region being provided between the gate trench and the second main surface; a second electric field relief region having the second conductivity type, the second electric field relief region being connected to the body region and sandwiching the body region between the side surface and the second electric field relief region; Further comprising: The first electric field relief region is A first region located closer to the second main surface than the bottom surface; A second region protruding from the first region toward the first main surface; having a portion of the drift region is between the second region and the body region; a lower end surface of the second electric field relief region is located closer to the first main surface than an upper end surface of the first region, a peak depth of an effective concentration of the second conductivity type impurity in the first electric field relaxation region with respect to the first main surface is 1.0 μm or less.

2. The silicon carbide semiconductor device according to claim 1 , wherein the silicon carbide substrate has a first connection region electrically connecting the first electric field relief region and the body region and having the second conductivity type.

3. The silicon carbide semiconductor device according to claim 2 , wherein the first connection regions are periodically arranged in a longitudinal direction of the gate trench.

4. 4 . The silicon carbide semiconductor device according to claim 1 , wherein the silicon carbide substrate has a second connection region that electrically connects the first electric field relaxation region and the second electric field relaxation region and has the second conductivity type. 5 .

5. The silicon carbide semiconductor device according to claim 4 , wherein the second connection regions are periodically arranged in a longitudinal direction of the gate trench.

6. the silicon carbide substrate has a contact region that is connected to the source region and has the first conductivity type, the contact region sandwiching the source region between the side surface and the silicon carbide substrate; The silicon carbide semiconductor device according to claim 1 , wherein the contact region is thicker than the source region.

7. 7. The silicon carbide semiconductor device according to claim 1, wherein the side surface of the gate trench includes a {0-33-8} plane.

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