Silicon carbide semiconductor device

Abstract

To provide a silicon carbide semiconductor device and a method for manufacturing the silicon carbide semiconductor device that can suppress peeling and cracking of barrier metal.SOLUTION: A first recess portion 10a reflecting a recess 7a on an upper surface of a gate electrode 7 inside a trench 5 is provided on an upper surface of an interlayer insulating film 10. A second recess portion 10b obtained by removing an upper end of a side surface of the interlayer insulating film 10 in a fan shape is provided at a boundary between the upper surface and the side surface of the interlayer insulating film 10. Convex portions 10e and 10f based on the first and second concave portions 10a and 10b are formed on a surface of the interlayer insulating film 10, and three or more concave and convex portions are repeatedly formed by these first and second concave portions 10a and 10b and convex portions 10e and 10f. Angles θ1 and θ2 of vertices of the convex portions 10e and 10f on the surface of the interlayer insulating film 10 are obtuse angles of about 100° or more. Barrier metal 12 covering the interlayer insulating film 10 has unevenness reflecting the concave and convex portions of the surface of interlayer insulating film 10.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] This invention relates to a silicon carbide semiconductor device. Place Regarding. [Background technology]

[0002] In trench-gate MOSFETs (Metal Oxide Semiconductor Field Effect Transistors: MOS-type field effect transistors with an insulated gate consisting of a three-layer structure of metal-oxide-semiconductor), the finer the trench pitch, the higher the current density and the smaller the chip size can be. However, the unevenness formed by the upper surface of the interlayer insulating film and the portion exposed in the contact hole on the front surface of the semiconductor substrate becomes larger, and this deteriorates the step coverage of the top layer, a metal electrode layer containing aluminum (Al) (hereinafter referred to as the Al metal electrode layer).

[0003] Conventionally, in trench-gate MOSFETs using silicon (Si) as a semiconductor material, in order to planarize the Al metal electrode layer, it has been common to soften and deform the interlayer insulating film after forming a contact hole, and make the upper surface of the interlayer insulating film a curved surface that is convexly curved in a direction away from the semiconductor substrate, thereby reducing the unevenness formed by the upper surface of the interlayer insulating film and the portion exposed through the contact hole on the front surface of the semiconductor substrate. Even when silicon carbide (SiC) is used as the semiconductor material, the Al metal electrode layer is smoothed by making the upper surface of the interlayer insulating film the same curved surface as when silicon is used as the semiconductor material (for example, see Patent Document 1 below).

[0004] The structure of a conventional trench-gate MOSFET will be described. FIG. 10 is a cross-sectional view showing the structure of a conventional silicon carbide semiconductor device. FIG. 10 is FIG. 1 of Patent Document 1 below. A conventional silicon carbide semiconductor device 130 shown in FIG. 10 is a vertical MOSFET equipped with a general trench gate on the front surface side of a semiconductor substrate 120 made of silicon carbide, and an upper surface of an interlayer insulating film 110 covering a gate electrode 107 is a curved surface that is convexly curved in a direction away from the semiconductor substrate 120. The interlayer insulating film 110 has a two-layer structure of first and second insulating layers 108 and 109 stacked in order on the front surface of the semiconductor substrate 120, and covers the gate electrode 107.

[0005] The first insulating layer 108 is a non-doped silicate glass (NSG) film. The upper surface of the first insulating layer 108 is flat. The second insulating layer 109 is a boron phosphorus silicate glass (BPSG) film. The thickness of the second insulating layer 109 is thicker at the center of the trench 105 and thinner toward the contact hole 115. The upper surface of the second insulating layer 109 is a curved surface that is convex in a direction away from the semiconductor substrate 120. By making the upper surface of the second insulating layer 109 a curved surface, unevenness formed between the upper surface of the interlayer insulating film 110 and the portion of the front surface of the semiconductor substrate 120 exposed to the contact hole 115 is reduced.

[0006] This also smooths the surfaces of the metal electrode layers 112 and 113 that are laminated in sequence on the interlayer insulating film 110 that covers the entire front surface of the semiconductor substrate 120. Reference numerals 111 to 113 form a source electrode 114. Reference numeral 112 is a laminated film of a titanium (Ti) film and an aluminum silicon (AlSi) film. Reference numeral 113 is a laminated film of a nickel (Ni) plating film and a gold (Au) plating film. Reference numerals 101 to 107, 116, and 117 each represent n - p-type drift region, p-type base region, n + Type source region, p + Type contact region, trench, gate insulating film, source electrode, n + a drain region and a drain electrode.

[0007] In a MOSFET using silicon carbide as a semiconductor material (hereinafter referred to as SiC-MOSFET), a nickel silicide (NiSi) film 111 is required as the bottom layer of the source electrode 114 in order to form an ohmic contact between the source electrode 114 and the semiconductor substrate 120. The nickel silicide film 111 makes ohmic contact with a portion exposed in a contact hole 115 on the front surface of the semiconductor substrate 120. A Ti film or a TiN film, or a metal laminate film combining these, is required on the nickel silicide film 111 as a barrier metal for preventing diffusion of aluminum atoms from the Al metal electrode layer 112 to the semiconductor substrate 120.

[0008] As a conventional SiC-MOSFET with a trench gate structure, a device has been proposed in which the upper surface of the interlayer insulating film is curved convexly in a direction away from the semiconductor substrate, and a barrier metal is provided over the entire front surface of the semiconductor substrate so as to cover the upper surface of the interlayer insulating film (see, for example, Patent Documents 2 to 4 below). In Patent Documents 2 and 3 below, a tungsten alloy film containing titanium is provided as the barrier metal. In Patent Document 4 below, a single layer titanium nitride (TiN) film or a laminated film in which a titanium (Ti) film and a titanium nitride film are laminated in order is provided as the barrier metal.

[0009] Also, as a conventional SiC-MOSFET with a trench gate structure, a device has been disclosed in which a recess that is deepest on the drain side at approximately the center of the trench is formed on the top surface of the gate electrode, and a recess that is recessed on the drain side at approximately the center of the trench reflecting the recess on the top surface of the gate electrode remains on the top surface of the interlayer insulating film (for example, see Patent Document 5 (Figure 28) below). In Patent Document 5 below, both sides of the recess on the top surface of the interlayer insulating film protrude with sharp tips in a convex shape in the direction away from the semiconductor substrate due to the recess, and unevenness that reflects the unevenness on the top surface of the interlayer insulating film is also formed on the top surface of the barrier metal. [Prior art documents] [Patent documents]

[0010] [Patent Document 1] Patent No. 6475142 [Patent Document 2] JP 2010-272676 A [Patent Document 3] JP 2010-267899 A [Patent Document 4] International Publication No. 2016 / 039074 [Patent Document 5] Japanese Patent Application Publication No. 7-235676 Summary of the Invention [Problem to be solved by the invention]

[0011] However, when a laminated film of a titanium film and a titanium nitride film is provided as a barrier metal in a conventional silicon carbide semiconductor device 130 (see FIG. 10), the following problem occurs. FIG. 11 is a cross-sectional view showing a schematic observation of an interlayer insulating film and a barrier metal of a conventional silicon carbide semiconductor device. Conventional silicon carbide semiconductor device 140 shown in FIG. 11 differs from conventional silicon carbide semiconductor device 130 shown in FIG. 10 in that it includes a barrier metal 141 between nickel silicide film 111 and Al metal electrode layer 112.

[0012] Fig. 11 shows a schematic diagram of an interlayer insulating film 110 and a barrier metal 141 of a conventional silicon carbide semiconductor device 140 observed with a scanning electron microscope (SEM). In Fig. 11, parts other than a trench 105, a gate insulating film 106, and a gate electrode 107 inside a semiconductor substrate 120 are omitted. The Al metal electrode layer 112 is, for example, an aluminum silicon film.

[0013] The barrier metal 141 is provided from the surface of the nickel silicide film 111 to the surface of the interlayer insulating film 110. The barrier metal 141 is, for example, a laminated film in which a titanium nitride film, a titanium film, and a titanium nitride film are laminated in this order. The titanium film and titanium nitride film constituting the barrier metal 141 have high stress. For this reason, if the upper surface of the interlayer insulating film 110 is a curved surface that is convex in the direction away from the semiconductor substrate 120, the step coverage of the barrier metal 141 on the interlayer insulating film 110 will be poor.

[0014] The barrier metal 141 has a high rate of discontinuity in areas with poor step coverage, resulting in large surface irregularities. The barrier metal 141 shrinks due to tensile stress in areas with large surface irregularities, making these areas vulnerable to stress. A specific example of the area with large surface irregularities of the barrier metal 141 is a portion 141a of the barrier metal 141 directly above the trench 105. The portion of the barrier metal 141 above the nickel silicide film 111 has good step coverage and does not shrink.

[0015] The deformation of the barrier metal 141 due to the difference in stress applied to the barrier metal 141 causes peeling and cracking of the barrier metal 141. Through intensive research by the present inventor, the following points have been confirmed regarding peeling and cracking of the barrier metal 141. The main starting point of cracks in the barrier metal 141 is the boundary 141b between the sidewall of the contact hole 115 and the front surface of the semiconductor substrate 120. Cracks in the barrier metal 141 occur randomly with no regularity and are not dependent on the layout of the gate electrode 107. The barrier metal 141 peels off from the cracks in the barrier metal 141.

[0016] In order to solve the above-mentioned problems of the prior art, the present invention provides a silicon carbide semiconductor device capable of suppressing peeling and cracking of a barrier metal. Place The purpose is to provide. [Means for solving the problem]

[0017] In order to solve the above-mentioned problems and achieve the object of the present invention, the silicon carbide semiconductor device according to the present invention has the following features: A trench-gate type silicon carbide semiconductor device having trenches, each having a polysilicon layer with a recess on its upper surface, embedded therein, arranged side by side in a lateral direction parallel to the front surface of the semiconductor substrate on the front surface side of the semiconductor substrate, comprising an interlayer insulating film laminated on the front surface of the semiconductor substrate and covering the polysilicon layer, and a barrier metal, at least a portion of which is provided along a surface of the interlayer insulating film. In a YZ cross section in the lateral direction and in the depth direction of the semiconductor substrate, a first recess facing the recess in the depth direction and having a height difference of 0.1 μm or more, and a second recess arranged side by side with the first recess in the lateral direction and having a height difference of 0.1 μm or more are provided on the front surface side of the semiconductor substrate. The height difference between the projections and recesses caused by the first recesses and the second recesses on the front surface side of the semiconductor substrate is not less than 0.1 μm and less than 0.5 μm. The barrier metal is provided along the surfaces of the first recess and the second recess. In order to solve the above-mentioned problems and achieve the object of the present invention, the silicon carbide semiconductor device according to the present invention has the following features. A trench-gate type silicon carbide semiconductor device in which trenches, each having a polysilicon layer with a recess on its upper surface, are provided on the front surface side of a semiconductor substrate in a lateral direction parallel to the front surface of the semiconductor substrate, and an interlayer insulating film is provided on the front surface of the semiconductor substrate to cover the polysilicon layer, and a barrier metal is provided at least partially along the surface of the interlayer insulating film. In a YZ cross section in the lateral direction and in the depth direction of the semiconductor substrate, the barrier metal has a first apex that is the deepest part facing the recess in the depth direction, a second apex that is located outside the polysilicon layer in the lateral direction and where an inner wall of a first recess is located between the first apex and the second apex, and another apex that is located farther from the polysilicon layer in the lateral direction than the second apex and forms a flat surface between the first apex and the second apex. The height difference of the unevenness between the first apex and the second apex is 0.1 μm or more and less than 0.5 μm. In order to solve the above-mentioned problems and achieve the object of the present invention, the silicon carbide semiconductor device according to the present invention has the following features. A first semiconductor region of a first conductivity type is provided inside a semiconductor substrate. A second semiconductor region of a second conductivity type is provided between a first main surface of the semiconductor substrate and the first semiconductor region, in contact with the first semiconductor region. A third semiconductor region of a first conductivity type is selectively provided between the first main surface of the semiconductor substrate and the second semiconductor region, in contact with the second semiconductor region. A trench extends from the first main surface of the semiconductor substrate through the third semiconductor region and the second semiconductor region to reach the first semiconductor region. A gate electrode is provided inside the trench via a gate insulating film. An interlayer insulating film covers the gate electrode. A contact hole extends through the interlayer insulating film in a depth direction to reach the semiconductor substrate.

[0018] A first electrode is provided on the surface of the interlayer insulating film, and is connected to the second semiconductor region and the third semiconductor region inside the contact hole. A second electrode is electrically connected to the first semiconductor region. Three or more recesses are provided on the surface of the interlayer insulating film, spaced apart from one another. The surface of the interlayer insulating film has a shape in which three or more recesses and protrusions each having an apex at a boundary between an inner wall of the recess and the surface between the recesses are repeated. The first electrode has first to third electrode films. The first electrode film is in ohmic contact with the second semiconductor region and the third semiconductor region inside the contact hole. A second electrode film containing titanium is provided along the surface of the first electrode film and the surface of the interlayer insulating film. A third electrode film containing aluminum is provided on the surface of the second electrode film. The second electrode film has an uneven shape that reflects the unevenness caused by the recesses on the surface of the interlayer insulating film. The height difference of the concave portions on the surface of the interlayer insulating film is 0.1 μm or more and less than 0.5 μm.

[0019] In order to solve the above-mentioned problems and achieve the object of the present invention, a silicon carbide semiconductor device according to the present invention has the following features. A first semiconductor region of a first conductivity type is provided inside a semiconductor substrate. A second semiconductor region of a second conductivity type is provided between a first main surface of the semiconductor substrate and the first semiconductor region, in contact with the first semiconductor region. A third semiconductor region of a first conductivity type is selectively provided between the first main surface of the semiconductor substrate and the second semiconductor region, in contact with the second semiconductor region. A trench extends from the first main surface of the semiconductor substrate through the third semiconductor region and the second semiconductor region to reach the first semiconductor region. A gate electrode is provided inside the trench via a gate insulating film.

[0020] An interlayer insulating film covers the gate electrode. A contact hole penetrates the interlayer insulating film in the depth direction to reach the semiconductor substrate. A first electrode is provided on the surface of the interlayer insulating film and is connected to the second semiconductor region and the third semiconductor region inside the contact hole. A second electrode is electrically connected to the first semiconductor region. Three or more recesses are provided on the surface of the interlayer insulating film, and the surface of the interlayer insulating film has a shape in which three or more projections and recesses caused by the recesses are repeated. A contact hole closest to the contact hole is provided on the surface of the interlayer insulating film. The above The recess has a predetermined depth less than the thickness of the interlayer insulating film and is continuous with the contact hole.

[0021] The opening width of the contact hole is The above Due to the recesses, the area is wider at a location away from the semiconductor substrate than at a location closer to the semiconductor substrate. The first electrode has first to third electrode films. The first electrode film is in ohmic contact with the second semiconductor region and the third semiconductor region inside the contact hole. A second electrode film containing titanium is provided along a surface of the first electrode film and a surface of the interlayer insulating film. A third electrode film containing aluminum is provided on a surface of the second electrode film. The second electrode film has an uneven shape that reflects the unevenness caused by the recesses on the surface of the interlayer insulating film. The height difference of the concave portions on the surface of the interlayer insulating film is 0.1 μm or more and less than 0.5 μm.

[0023] In the silicon carbide semiconductor device according to the present invention, in the above-mentioned invention, the height difference between the projections and recesses on the surface of the interlayer insulating film is 0.3 μm or less.

[0024] In the silicon carbide semiconductor device according to the present invention, in the above-mentioned invention, the multiple recesses in the surface of the interlayer insulating film include first and second recesses. The first recess is provided in the upper surface of the interlayer insulating film so as to reflect a recess generated in a contact surface of the gate electrode with the interlayer insulating film. The second recess is provided in the boundary between the upper surface of the interlayer insulating film and a side surface of the interlayer insulating film, is recessed in an arc shape, and is continuous with the contact hole.

[0025] Moreover, in the silicon carbide semiconductor device according to the present invention, in the above-mentioned invention, the first recess and the second recess are provided apart from each other. A surface of the interlayer insulating film between the first recess and the second recess is a first flat surface. A depth of the second recess is 20% or more and 50% or less of a thickness from the first flat surface of the interlayer insulating film to an upper surface of the gate insulating film on the first main surface of the semiconductor substrate.

[0026] In addition, in the silicon carbide semiconductor device according to the present invention, in the above-mentioned invention, a surface of the interlayer insulating film has first protrusions having a triangular cross-sectional shape with a vertex defined by a boundary between an inner wall of the recess and the first flat surface, and all of the vertices of the first protrusions have an obtuse angle of approximately 100° or more.

[0027] In the silicon carbide semiconductor device according to the present invention, in the above-mentioned invention, the first convex portion closer to the trench has an apex angle greater.

[0028] In addition, in the silicon carbide semiconductor device according to the present invention, in the above-mentioned invention, the angle of the first protrusion arranged in a position close to the trench is an obtuse angle of approximately 110° or more.

[0029] In addition, in the silicon carbide semiconductor device according to the present invention, in the above-mentioned invention, a side surface of the interlayer insulating film is a second flat surface having an inclination with respect to the first main surface of the semiconductor substrate. A second protrusion having a triangular cross-sectional shape with an apex at a boundary between an inner wall of the second recess and the second flat surface is provided on a surface of the interlayer insulating film. The angle of the apex of the second protrusion is an obtuse angle of approximately 100° or more.

[0030] In addition, in the silicon carbide semiconductor device according to the present invention, in the above-mentioned invention, an angle of an apex of the second protrusion is smaller than an angle of an apex of the first protrusion.

[0031] Furthermore, in order to solve the above-mentioned problems and achieve the object of the present invention, a method for manufacturing a silicon carbide semiconductor device according to the present invention has the following features: A first step is performed to form a trench reaching a predetermined depth from a first main surface of a semiconductor substrate. A second step is performed to form a gate insulating film along the first main surface of the semiconductor substrate and an inner wall of the trench. A third step is performed to deposit a polysilicon layer on the first main surface of the semiconductor substrate and fill the inside of the trench with the polysilicon layer. The above A fourth step is performed in which the polysilicon layer is etched back until the gate insulating film is exposed, leaving the polysilicon layer that becomes the gate electrode only inside the trench.

[0032] A fifth step is performed in which an interlayer insulating film covering the gate electrode is formed on a first main surface of the semiconductor substrate. A sixth step is performed in which a contact hole is formed by penetrating the interlayer insulating film in the depth direction to reach the semiconductor substrate. A seventh step is performed in which the interlayer insulating film is planarized by heat treatment. An eighth step is performed in which a first electrode film making ohmic contact with the semiconductor substrate inside the contact hole is formed. A ninth step is performed in which a second electrode film containing titanium is formed along a surface of the first electrode film and a surface of the interlayer insulating film. A tenth step is performed in which a third electrode film containing aluminum is formed on a surface of the second electrode film. In the fourth step, Depth of 0.1μm to less than 0.5μm causes a dent.

[0033] In the fifth step, a first recess reflecting the recess in the surface of the gate electrode is left on the surface of the interlayer insulating film. The sixth step includes a mask forming step, a first and second groove forming step, and the removing step. In the mask forming step, an etching mask having an opening in a portion corresponding to a region where the contact hole is to be formed is formed on the surface of the interlayer insulating film. In the first groove forming step, isotropic etching is performed using the etching mask to form a first groove of a predetermined depth from the surface of the interlayer insulating film. In the second groove forming step, anisotropic etching is performed using the etching mask to form a second groove penetrating the interlayer insulating film in the depth direction from the bottom surface of the first groove. In the removing step, the etching mask is removed.

[0035] Furthermore, in the method for manufacturing a silicon carbide semiconductor device according to the present invention, in the above-mentioned invention, in the first groove formation step, the specified depth of the first groove is set to be 20% or more and 50% or less of a thickness from a surface of the interlayer insulating film other than the first recess to an upper surface of the gate insulating film on the first main surface of the semiconductor substrate.

[0036] Moreover, in the method for manufacturing a silicon carbide semiconductor device according to the present invention, in the above-mentioned invention, in the fifth step, a first insulating layer and a second insulating layer having a higher boron concentration and phosphorus concentration than the first insulating layer, a boron concentration of 1 wt% or more and 3 wt% or less, and a phosphorus concentration of 1 wt% or more and 3 wt% or less are sequentially stacked as the interlayer insulating film. In the first groove forming step, the first groove is formed in the second insulating layer. In the second groove forming step, the second groove is formed so as to penetrate the second insulating layer and the first insulating layer in a depth direction from a bottom surface of the first groove. In the seventh step, the temperature of the heat treatment is set to 1000° C. or less. Effect of the Invention

[0038] Silicon carbide semiconductor device according to the present invention Place This brings about an effect of suppressing peeling and cracking of the barrier metal. [Brief description of the drawings]

[0039] [Figure 1] 1 is a cross-sectional view showing a structure of a silicon carbide semiconductor device according to an embodiment. [Diagram 2] FIG. 2 is an enlarged cross-sectional view showing a part of FIG. [Diagram 3] 1A to 1C are cross-sectional views showing a state during the manufacture of a silicon carbide semiconductor device according to an embodiment. [Figure 4] 1A to 1C are cross-sectional views showing a state during the manufacture of a silicon carbide semiconductor device according to an embodiment. [Diagram 5] 1A to 1C are cross-sectional views showing a state during the manufacture of a silicon carbide semiconductor device according to an embodiment. [Figure 6] 1A to 1C are cross-sectional views showing a state during the manufacture of a silicon carbide semiconductor device according to an embodiment. [Figure 7] 1A to 1C are cross-sectional views showing a state during the manufacture of a silicon carbide semiconductor device according to an embodiment. [Figure 8] 1A to 1C are cross-sectional views showing a state during the manufacture of a silicon carbide semiconductor device according to an embodiment. [Figure 9] 1A to 1C are cross-sectional views showing a state during the manufacture of a silicon carbide semiconductor device according to an embodiment. [Figure 10] FIG. 1 is a cross-sectional view showing a structure of a conventional silicon carbide semiconductor device. [Figure 11] FIG. 1 is a cross-sectional view showing a schematic observation of an interlayer insulating film and a barrier metal of a conventional silicon carbide semiconductor device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0040] A silicon carbide semiconductor device according to the present invention will be described below with reference to the accompanying drawings. PlaceA preferred embodiment will be described in detail. In this specification and the accompanying drawings, in a layer or region prefixed with n or p, electrons or holes are the majority carriers, respectively. In addition, + and - attached to n or p respectively mean that the impurity concentration is higher and lower than that of a layer or region not prefixed with that. In the following description of the embodiment and the accompanying drawings, the same reference numerals are attached to similar configurations, and duplicated explanations are omitted.

[0041] (Embodiment) The structure of a silicon carbide semiconductor device according to an embodiment will be described. (YZ cross section) Fig. 2 is an enlarged cross-sectional view of a portion of Fig. 1. Fig. 2 shows a schematic view of an interlayer insulating film 10 and a barrier metal 12 on a semiconductor substrate (semiconductor chip) 20 of Fig. 1, as observed with a scanning electron microscope. In Fig. 2, parts other than a trench gate inside the semiconductor substrate 20 are omitted.

[0042] 1 and 2 is a vertical trench-gate type SiC-MOSFET having a typical trench gate on the front surface side of a semiconductor substrate 20 made of silicon carbide, and has three recesses (one first recess 10a and two second recesses 10b described later) on the surface of an interlayer insulating film 10 covering a gate electrode 7. The trench gate is composed of a trench 5, a gate insulating film 6, and a gate electrode 7 described later.

[0043] Inside the semiconductor substrate 20, - A first semiconductor region (1) is provided on the front surface of the semiconductor substrate (20). - Between the n-type drift region 1, - A p-type base region (second semiconductor region) 2 is provided in contact with the p-type drift region 1. An n-type + type source region (third semiconductor region) 3 and p + Mold contact regions 4 are selectively provided respectively.

[0044] n + Type source region 3 and p + The contact region 4 is exposed on the front surface of the semiconductor substrate 20. + The contact region 4 may not be provided. + When the contact region 4 is not provided, + Instead of the p-type contact region 4, the p-type base region 2 is exposed on the front surface of the semiconductor substrate 20. + The depth of the type source region 3 from the front surface of the semiconductor substrate 20 is, for example, about 0.5 μm.

[0045] The semiconductor substrate 20 is made of silicon carbide. + On the starting substrate 21 - Alternatively, the epitaxial substrate may be fabricated by sequentially stacking epitaxial layers 22 and 23 that will become the n-type drift region 1 and the p-type base region 2. In this case, + Type source region 3 and p + The contact regions 4 are provided in the surface region of the p-type epitaxial layer 23 , and the portions of the p-type epitaxial layer 23 excluding the surface regions become the p-type base region 2 .

[0046] The trench 5 is formed from the front surface of the semiconductor substrate 20 to the n + The n-type source region 3 and the p-type base region 2 are connected through - The trench 5 is formed so as to extend from the first surface of the semiconductor substrate 20 to the first drift region 1. The upper corners and the bottom corners of the trench 5 may be rounded with a predetermined curvature. The upper corners of the trench 5 are the boundaries between the front surface of the semiconductor substrate 20 and the side walls of the trench 5. The bottom corners of the trench 5 are the boundaries between the bottom surface of the trench 5 and the side walls.

[0047] A gate insulating film 6 is provided inside the trench 5 along the inner wall of the trench 5. The gate insulating film 6 extends from the side wall of the trench 5 onto the front surface of the semiconductor substrate 20. A gate electrode 7 made of, for example, polysilicon (poly-Si) is provided on the gate insulating film 6 inside the trench 5. A recess 7a is formed on the upper surface of the gate electrode 7 (contact surface with the interlayer insulating film 10) at approximately the center of the trench 5, the recess 7a being deepest on the drain side (the bottom side of the trench 5).

[0048] The recess 7a on the upper surface of the gate electrode 7 is generated by etching back the polysilicon layer 41 (see FIG. 3) described later for forming the gate electrode 7. The depth d1 of the recess 7a on the upper surface of the gate electrode 7 is the depth d1 of the gate electrode 7 at the portion along the side wall of the trench 5 through the gate insulating film 6. + It is sufficient that the trench 5 faces the source region 3, and for example, the depth at the deepest portion (approximately the center of the trench 5) is about 0.1 μm or more and less than 0.5 μm, and preferably about 0.3 μm or less.

[0049] The interlayer insulating film 10 has a two-layer structure of first and second insulating layers 8 and 9 laminated in this order on the front surface of the semiconductor substrate 20. The first insulating layer 8 is made of an insulating material that does not contain boron (B) or phosphorus (P) or has a very low boron and phosphorus concentration compared to the second insulating layer 9. The second insulating layer 9 is made of an insulating material that contains boron and phosphorus at a predetermined concentration described below. The softening point of the second insulating layer 9 is lower than that of the first insulating layer 8.

[0050] Specifically, the first insulating layer 8 is, for example, a non-doped silicate glass (NSG) film. The first insulating layer 8 has a function of preventing the diffusion of boron and phosphorus in the second insulating layer 9 into the gate electrode 7. The first insulating layer 8 may contain boron and phosphorus diffused from the second insulating layer 9. The first insulating layer 8 covers the gate insulating film 6 on the front surface of the semiconductor substrate 20 and the upper surface of the gate electrode 7.

[0051] When the upper surface of the gate electrode 7 is located deeper on the drain side than the upper corners of the trench 5, the first insulating layer 8 also covers the gate insulating film 6 on the surfaces of the upper corners of the trench 5. The thickness d11 of the first insulating layer 8 is substantially uniform over the entire front surface of the semiconductor substrate 20, and is, for example, about 100 nm or more and 300 nm or less. "Substantially uniform" means that the thickness is the same within a range that includes an allowable error due to process variations.

[0052] The second insulating layer 9 is provided on the first insulating layer 8. The second insulating layer 9 is not in contact with the gate insulating film 6 and the gate electrode 7. The second insulating layer 9 is, for example, a BPSG film, and has a higher boron concentration and phosphorus concentration than the second insulating layer 109 (see FIGS. 10 and 11) constituting the interlayer insulating film 110 of the conventional structure. By disposing the first insulating layer 8 between the second insulating layer 9 and the gate electrode 7, it is possible to suppress the variation in conductivity of the gate electrode 7 caused by boron and phosphorus in the second insulating layer 9.

[0053] The boron concentration of the second insulating layer 9 is, for example, about 1 wt% to 3 wt%, and preferably about 1.6 wt% to 2.6 wt%. The phosphorus concentration of the second insulating layer 9 is, for example, about 1 wt% to 3 wt%, and preferably about 1.5 wt% to 2.5 wt%. The reason for this is that by setting the boron concentration and phosphorus concentration of the second insulating layer 9 in the above ranges, the second insulating layer 9 is more likely to flow even if the reflow temperature of the interlayer insulating film 10 is lower than in the conventional method.

[0054] When the boron concentration and phosphorus concentration of the second insulating layer 9 are less than the above lower limit, the reflow temperature of the interlayer insulating film 10 cannot be lowered as compared to the conventional method. The reason is that when the boron concentration and phosphorus concentration of the second insulating layer 9 are less than the above lower limit, the reflow temperature of the interlayer insulating film 10 is lower than the conventional method, and the second insulating layer 9 does not flow easily, and the first and second recesses 10a, 10b and the first and second flat surfaces 10c, 10d described below cannot be formed on the surface of the second insulating layer 9. When the boron concentration and phosphorus concentration of the second insulating layer 9 exceed the above upper limit, this causes peeling of the second insulating layer 9.

[0055] The thickness d12 of the second insulating layer 9 is thicker than the thickness d11 of the first insulating layer 8, and is, for example, about 400 nm to 800 nm. The total thickness d10 of the interlayer insulating film 10 is a thickness that can electrically insulate the gate electrode 7 and the source electrode (first electrode) 14, and is, for example, about 800 nm (for example, the thickness d11 of the first insulating layer 8 is about 200 nm, and the thickness d12 of the second insulating layer 9 is about 600 nm). Since the surface of the interlayer insulating film 10 is uneven due to the first and second recesses 10a, 10b and the protrusions 10e to 10g described later, the total thickness d10 of the interlayer insulating film 10 for electrically insulating the gate electrode 7 and the source electrode 14 can be easily ensured.

[0056] The upper surface of the interlayer insulating film 10 has a recess that is recessed in a portion (i.e., approximately at the center of the trench 5) facing the recess 7a in the upper surface of the gate electrode 7 in the depth direction Z, the recess 7a reflecting the recess 7a in the upper surface of the gate electrode 7. (First vertex) The upper surface of the interlayer insulating film 10 refers to a contact surface (surface) of the interlayer insulating film 10 with the barrier metal 12, excluding the surface that becomes the side wall of the contact hole 15 (the side surface of the interlayer insulating film 10).

[0057] 1, at the boundary between the upper surface of the interlayer insulating film 10 and the side surface of the interlayer insulating film 10 (hereinafter referred to as the upper end of the side surface of the interlayer insulating film 10), a second recess 10b is formed in the surface of the second insulating layer 9, which is recessed in a downwardly convex arc shape by removing the upper end of the side surface of the interlayer insulating film 10 in a sector shape in cross section. The second recess 10b is formed by leaving the side wall and bottom corner portion of a first groove 15a (see FIG. 8) formed in the second insulating layer 9 by isotropic etching, which will be described later. The bottom corner portion of the first groove 15a is the boundary between the bottom surface and the side wall of the first groove 15a.

[0058] 2, the second recess 10b at the upper end of the side surface of the interlayer insulating film 10 may be chamfered by a depth d3 described below. The chamfered upper end of the side surface of the interlayer insulating film 10 is, for example, a flat surface having a greater inclination with respect to the front surface of the semiconductor substrate 20 than the side surface of the interlayer insulating film 10, or a curved surface that is close to a flat surface and has a greater inclination with respect to the front surface of the semiconductor substrate 20 than the side surface of the interlayer insulating film 10, and is slightly curved downwardly convex.

[0059] The depth d2 of the first recess 10a in the upper surface of the interlayer insulating film 10 is approximately the same as the depth d1 of the recess 7a in the upper surface of the gate electrode 7. "Approximately the same depth" means that the depth is the same within a range that includes an allowable error due to process variations. The depth d3 of the second recess 10b at the upper end of the side surface of the interlayer insulating film 10 is the radius of the arc-shaped second recess 10b, and is a depth that is approximately 0.1 μm or more from the upper surface of the interlayer insulating film 10 and is approximately 20% to 50% of the maximum value of the total thickness d10 of the interlayer insulating film 10.

[0060] Between the first recess 10a and the second recess 10b on the upper surface of the interlayer insulating film 10 is a first flat surface 10c that smoothly continues to the inner walls of the first and second recesses 10a, 10b. The side surface of the interlayer insulating film 10 is a second flat surface 10d that smoothly continues to the inner wall of the second recess 10b at the upper end of the side surface of the interlayer insulating film 10. The first recess 10a is approximately parallel to the front surface of the semiconductor substrate 20. The second flat surface 10d may have an inclination with respect to the front surface of the semiconductor substrate 20.

[0061] On the surface of the interlayer insulating film 10, protrusions 10e-10g are formed, each having a substantially triangular cross section with the inner walls of the first and second recesses 10a, 10b and the first and second flat surfaces 10c, 10d as one side and the boundary between these two sides as a vertex. The angles θ1-θ3 of the vertices of these protrusions 10e-10g are, for example, obtuse angles of about 100° or more. The first and second recesses 10a, 10b can increase the number of protrusions 10e-10g with obtuse vertices on the surface of the interlayer insulating film 10 compared to the conventional structure (see FIG. 11).

[0062] Specifically, in the embodiment, three convex portions (indicated by reference characters 10e to 10g) are formed between each of the first concave portion 10a on the upper surface of the interlayer insulating film 10 and both side surfaces (second flat surfaces 10d) of the interlayer insulating film 10, resulting in a total of six convex portions being formed on the surface of the interlayer insulating film 10. On the other hand, in the conventional structure (see FIGS. 10 and 11), the surface of the interlayer insulating film 110 smoothly continues from the side surfaces to the upper surface of the interlayer insulating film 110, so no convex portions exist on the surface of the interlayer insulating film 110.

[0063] The apex angles θ1 to θ3 of the protrusions 10e to 10g disposed closer to the trench 5 are larger. That is, the apex of the protrusion 10e formed by the inner wall of the first recess 10a and the first flat surface 10c has a larger angle θ1 to θ3. (Second vertex) The angle θ1 is the largest, and may be an obtuse angle of, for example, about 110° or more. (4th vertex, other vertices) and the apex of the protrusion 10g formed by the inner wall of the second recess 10b and the second flat surface 10d. (Third vertex) The angle θ3 is smaller than the angle θ1 of the apex of the protrusion 10e (θ1>θ2, θ1>θ3).

[0064] In this manner, the first and second recesses 10a, 10b are provided at a distance from each other on the surface of the interlayer insulating film 10, so that three or more projections and recesses are repeatedly formed on the surface of the interlayer insulating film 10, each projection having an apex at the boundary between the inner wall of the first and second recesses 10a, 10b and the first and second flat surfaces 10c, 10d. The height difference of the projections and recesses formed by the first and second recesses 10a, 10b and the projections 10e-10g on the surface of the interlayer insulating film 10 corresponds to the depths d2, d3 of the first and second recesses 10a, 10b on the surface of the interlayer insulating film 10, and is approximately the same as the depth d1 of the recess 7a on the upper surface of the gate electrode 7.

[0065] A contact hole 15 is provided through the interlayer insulating film 10 in the depth direction to reach the semiconductor substrate 20. + Type source region 3 and p + The contact region 4 is exposed. In the YZ sectionThe opening width in the lateral direction Y is one step wider on the upper end side away from the semiconductor substrate 20 than on the semiconductor substrate 20 side due to a second recess 10b that is continuous with the contact hole 15 at the upper end of the side surface of the interlayer insulating film 10 (w1>w2).

[0066] The source electrode 14 is composed of a nickel silicide film (first electrode film) 11, a barrier metal (second electrode film) 12, and a metal electrode layer (Al metal electrode layer: third electrode film) 13 containing aluminum (Al). The nickel silicide film 11 in the bottom layer is a portion (n + Type source region 3 and p + Type contact region 4, or p + The source electrode 14 is in ohmic contact with the semiconductor substrate 20 (only the contact region 4 ) to form an ohmic contact between the source electrode 14 and the semiconductor substrate 20 .

[0067] The barrier metal 12 is provided with a substantially uniform thickness from the surface of the nickel silicide film 11 along the surface of the interlayer insulating film 10, and has an uneven shape reflecting the unevenness caused by the first and second recesses 10a, 10b and the protrusions 10e to 10g on the surface of the interlayer insulating film 10. The barrier metal 12 has a function of preventing diffusion of aluminum atoms from the Al metal electrode layer 13 to the semiconductor substrate 20. The barrier metal 12 has a function of preventing mutual reaction between the Al metal electrode layer 13 and the semiconductor substrate 20 during the manufacturing process.

[0068] The barrier metal 12 has a single layer of titanium (Ti) film or titanium nitride (TiN) film, or a laminated structure in which a plurality of these films are laminated, for example, a three-layered laminated film in which a titanium nitride film, a titanium film, and a titanium nitride film are laminated in this order. The topmost Al metal electrode layer 13 is, for example, an aluminum silicon (AlSi) film. The thickness d13 of the Al metal electrode layer 13 is, for example, about 5 μm.

[0069] The surface region of the back surface of the semiconductor substrate 20 is n + A n-type drain region 16 is provided. When the semiconductor substrate 20 is an epitaxial substrate as described above,+ The starting substrate 21 is n + This forms an n-type drain region 16. A drain electrode (second electrode) 17 is provided on the entire back surface of the semiconductor substrate 20. The drain electrode 17 is an n-type + The semiconductor layer 12 is in ohmic contact with the drain region 16 .

[0070] Next, a method for manufacturing a silicon carbide semiconductor device according to an embodiment will be described. Figures 3 to 9 are cross-sectional views showing states during the manufacturing process of a silicon carbide semiconductor device according to an embodiment. First, a n + A semiconductor substrate (semiconductor wafer) 20 is fabricated by sequentially stacking epitaxial layers 22 and 23 (see FIG. 1) on the front surface of a starting substrate 21. The main surface of the semiconductor substrate 20 on the side of the p-type epitaxial layer 23 is the front surface, and + The main surface facing the starting mold substrate 21 is referred to as the back surface.

[0071] Next, as shown in FIG. 3, a set of steps of photolithography and ion implantation is repeatedly performed under different conditions to form n - The inside of the n-type epitaxial layer 22 + Type source region 3 and p + The n-type contact region 4 is selectively formed in the p-type epitaxial layer 23. + Type source region 3 and p + The portion excluding the contact region 4 becomes the p-type base region 2 .

[0072] Next, n + The n-type source region 3 and the p-type base region 2 are connected through - n type drift region 1 - A trench 5 is formed so as to reach the type epitaxial layer 22 (first step). Next, a gate insulating film 6 is formed along the front surface of the semiconductor substrate 20 and the inner wall of the trench 5 (second step). Next, a polysilicon layer 41 is deposited on the front surface of the semiconductor substrate 20 to completely fill the inside of the trench 5 with the polysilicon layer 41 (third step).

[0073] 4, the gate insulating film 6 on the front surface of the semiconductor substrate 20 is used as an etching stop layer, and the polysilicon layer 41 is etched back until the gate insulating film 6 on the front surface of the semiconductor substrate 20 is exposed. Furthermore, the polysilicon layer 41 is over-etched by a predetermined etching amount to make the surface of the polysilicon layer 41 inside the trench 5 sink to a position that is lower by a depth d1 than the upper surface of the gate insulating film 6 on the front surface of the semiconductor substrate 20 (fourth step).

[0074] As a result, the polysilicon layer 41 that will become the gate electrode 7 remains only inside the trench 5, and a recess 7a is formed on the upper surface of the gate electrode 7. The polysilicon layer 41 is etched back using, for example, carbon tetrafluoride (CF 4 ) to oxygen (O 2 Alternatively, chemical dry etching (CDE) may be used, in which silicon (polysilicon layer 41) is etched with highly reactive fluorine radicals generated by plasma of a mixed gas to which fluorine has been added.

[0075] 5, for example, NSG and BPSG are deposited in order as first and second insulating layers 8 and 9 of interlayer insulating film 10 on the surface of gate insulating film 6 on the front surface of semiconductor substrate 20 and on the upper surface of gate electrode 7 (fifth step). A recess is generated on the surface (upper surface) of interlayer insulating film 10, as the upper surface of second insulating layer 9 is recessed, reflecting recess 7a in the upper surface of gate electrode 7. This recess in the surface of interlayer insulating film 10 is left as first recess 10a. Depth d2 of first recess 10a is approximately the same as depth d1 of recess 7a in the upper surface of gate electrode 7.

[0076] 6, a resist film 42 having an opening corresponding to a region where the contact hole 15 is to be formed is formed on the surface of the interlayer insulating film 10 (mask formation step). The resist film 42 is formed so as to cover the first recess 10a on the upper surface of the second insulating layer 9. Next, as shown in FIG. 7, the interlayer insulating film 10 is selectively removed by isotropic etching, for example, by CDE, using the resist film 42 as an etching mask, to form a first groove 15a having a predetermined depth d3 on the upper surface of the second insulating layer 9 (first groove formation step).

[0077] At this time, isotropic etching is performed for a preset time to form a first groove 15a of a preset depth d3 (e.g., about 0.3 μm) in the upper surface of the second insulating layer 9. The isotropic etching of the interlayer insulating film 10 progresses in the depth direction Z as well as in the lateral directions X and Y. As a result, the interlayer insulating film 10 is etched (side etched) to just below the resist film 42, and the width of the first groove 15a in the lateral direction Y (opening width w1) becomes wider than the opening width w11 of the resist film 42 in the lateral direction Y.

[0078] 8, the interlayer insulating film 10 is selectively removed by anisotropic etching using the resist film 42 as an etching mask to form a second groove 15b penetrating the interlayer insulating film 10 in the depth direction Z from the bottom surface of the first groove 15a (second groove formation step). Since the anisotropic etching does not progress in the lateral directions X and Y, the width in the lateral direction Y of the second groove 15b (opening width w2) is approximately the same as the opening width w11 in the lateral direction Y of the resist film 42 and is narrower than the width in the lateral direction Y of the first groove 15a (opening width w1).

[0079] The first and second trenches 15a, 15b continuing in the depth direction Z form a contact hole 15 (sixth step). The opening width in the lateral direction Y of the contact hole 15 is wider on the opening side away from the semiconductor substrate 20 than on the semiconductor substrate 20 side due to the difference in the widths in the lateral direction Y of the first and second trenches 15a, 15b. The sidewall and bottom corners of the first trench 15a remaining in the upper corners of the contact hole 15 become second recesses 10b at the upper end of the side surface of the interlayer insulating film 10.

[0080] 9, after removing the resist film 42 (removal step), the second insulating layer 9 is softened and fluidized by heat treatment at a low temperature (reflow temperature) of, for example, about 1000° C. or less, thereby planarizing (reflowing) the interlayer insulating film 10 (seventh step). By setting the reflow temperature of the interlayer insulating film 10 within the above range, the first and second recesses 10a, 10b and the first and second flat surfaces 10c, 10d can be left on the surface of the second insulating layer 9 after the interlayer insulating film 10 is reflowed.

[0081] Furthermore, by setting the upper limit of the reflow temperature of the interlayer insulating film 10 within the above range, the gate electrode 7 is not heated to a temperature exceeding 1000° C., thereby preventing deterioration of the gate characteristics. Next, the nickel (Ni) film deposited on the portion exposed in the contact hole 15 on the front surface of the semiconductor substrate 20 is reacted with the semiconductor substrate 20 by heat treatment to form a silicide, thereby forming a nickel silicide film 11 in ohmic contact with the semiconductor substrate 20 (step 8).

[0082] Next, barrier metal 12 is formed along the surface of the portion of the front surface of semiconductor substrate 20 exposed in contact hole 15 and the surface of interlayer insulating film 10 (ninth step). First and second recesses 10a, 10b are formed on the surface of interlayer insulating film 10, thereby forming first and second flat surfaces 10c, 10d, and the first and second recesses 10a, 10b and the first and second flat surfaces 10c, 10d generate protrusions (first and second protrusions) 10e-10g, thereby forming multiple (six in total) irregularities.

[0083] The unevenness of the surface of the interlayer insulating film 10, which is formed by the first and second recesses 10a, 10b and the protrusions 10e-10g, increases the contact area between the interlayer insulating film 10 and the barrier metal 12. Therefore, the unevenness of the surface of the interlayer insulating film 10 acts as an anchor, improving the adhesion between the interlayer insulating film 10 and the barrier metal 12 compared to the conventional structure. In addition, the protrusions 10e-10g on the surface of the interlayer insulating film 10 make it easier to ensure that the total thickness d10 of the interlayer insulating film 10 is thick enough to electrically insulate the barrier metal 12 from the gate electrode 7.

[0084] Next, an Al metal electrode layer 13 is deposited on the surface of the barrier metal 12 (tenth step), thereby forming a source electrode 14 composed of the nickel silicide film 11, the barrier metal 12 and the Al metal electrode layer 13. Next, the rear surface (n + The n-type drain region 16 +A drain electrode 17 is formed on the back surface of the starting mold substrate 21. Thereafter, the semiconductor substrate (semiconductor wafer) 20 is diced (cut) into individual chips (semiconductor chips), thereby completing the SiC-MOSFET shown in FIG.

[0085] As described above, according to the embodiment, the upper surface of the interlayer insulating film has a first recess that is recessed according to the recess of the upper surface of the gate electrode. At the boundary between the upper surface and the side surface of the interlayer insulating film 10, a second recess is formed by removing the upper end of the side surface of the interlayer insulating film in a fan shape. The surface between the first and second recesses of the interlayer insulating film and the surface between the second recess and the semiconductor substrate are flat. Three or more projections and recesses formed by the first and second recesses and the projections having apexes at the boundaries between the inner walls of the first and second recesses and the first and second flat surfaces are repeatedly formed on the surface of the interlayer insulating film.

[0086] The apexes of the convex portions on the surface of the interlayer insulating film are obtuse angles, and compared to a conventional structure having only a first concave portion on the upper surface of the interlayer insulating film (see, for example, FIG. 28 of Reference 5), the interlayer insulating film is flattened. The barrier metal has an uneven shape that reflects the unevenness of the surface of the underlying interlayer insulating film. The uneven shape of the barrier metal distributes the stress applied to the barrier metal. In addition, the anchor effect of the unevenness formed on the surface of the interlayer insulating film improves the adhesion between the interlayer insulating film and the barrier metal. This makes it possible to suppress peeling and cracking of the barrier metal.

[0087] The present invention is not limited to the above-mentioned embodiment, and various modifications can be made without departing from the spirit of the present invention. For example, in the above-mentioned embodiment, the surface of the interlayer insulating film is described as having three repeated irregularities, namely, the first and second recesses and the protrusions whose apexes are the boundaries between the inner walls of the first and second recesses and the first and second flat surfaces, but the present invention is not limited to this, and it is sufficient that the irregularities on the surface of the interlayer insulating film have a height difference within the above-mentioned range, and a plurality of recesses may be formed on the surface of the interlayer insulating film so that the surface of the interlayer insulating film has a repeated irregularity of four or more.

[0088] In addition, for example, although the above-mentioned embodiment has been described taking a MOSFET as an example, the present invention is not limited thereto, and can be applied to various semiconductor devices that can have a trench gate structure, such as an IGBT (Insulated Gate Bipolar Transistor) or a diode. In addition, the present invention is similarly applicable even if the conductivity type (n-type, p-type) is reversed. [Industrial Applicability]

[0089] As described above, the silicon carbide semiconductor device according to the present invention Place The present invention is useful for power semiconductor devices used in power conversion devices and power supply devices for various industrial machines. [Explanation of symbols]

[0090] 1n - Mold Drift Region 2 p-type base region 3n + Type Source Area 4 p + Mold Contact Area 5. Trench 6 Gate insulating film 7 Gate electrode 7a Recess on top of gate electrode 8 First insulating layer 9 Second insulating layer 10 Interlayer insulating film 10a: First recess in the upper surface of the interlayer insulating film 10b: a second recess at the upper end of the side surface of the interlayer insulating film 10c: a first flat surface of the upper surface of the interlayer insulating film 10d Side surface of interlayer insulating film (second flat surface) 10e to 10g: Convex portions on the surface of the interlayer insulating film 10 11 Nickel silicide film 12 Barrier metal 13 Al metal electrode layer 14 Source electrode 15 Contact Hole 15a: First groove formed in interlayer insulating film 15b A second groove formed in the interlayer insulating film 16n + Type drain region 17 Drain electrode 20 Semiconductor substrate 21 n + Starting substrate 22n - Type epitaxial layer 23 p-type epitaxial layer 30 Silicon carbide semiconductor device 41 Polysilicon layer 42 Resist film d1 Depth of the recess on the top surface of the gate electrode d2 Depth of the first recess in the upper surface of the interlayer insulating film d3 Depth of the second recess in the upper surface of the interlayer insulating film d10 Total thickness of interlayer insulating film d11 Thickness of the first insulating layer d12 Thickness of the second insulating layer d13 Thickness of Al metal electrode layer w1, w2 The width of the contact hole opening in the lateral direction where the trenches are aligned w11: The width of the opening in the resist film (etching mask) in the lateral direction where the trenches are lined up X: A lateral direction parallel to the front surface of the semiconductor substrate and perpendicular to the direction in which the trenches are arranged. Horizontal direction with Y-trench Z depth direction θ1 to θ3: Angles of the apexes of the protrusions on the surface of the interlayer insulating film

Claims

1. A trench-gate type silicon carbide semiconductor device, in which trenches having a polysilicon layer with a recess on an upper surface thereof embedded therein are provided on a front surface side of a semiconductor substrate in a lateral direction parallel to the front surface of the semiconductor substrate, an interlayer insulating film laminated on a front surface of the semiconductor substrate and covering the polysilicon layer; a barrier metal, at least a portion of which is provided along a surface of the interlayer insulating film; Equipped with In a Y-Z cross section in the lateral direction and the depth direction of the semiconductor substrate, a first recess facing the recess in the depth direction and having a height difference of 0.1 μm or more; and a second recess arranged side by side with the first recess in the lateral direction and having a height difference of 0.1 μm or more, a height difference between the first recess and the second recess on the front surface side of the semiconductor substrate is 0.1 μm or more and less than 0.5 μm; the barrier metal is provided along surfaces of the first recess and the second recess, the silicon carbide semiconductor device comprising: a first insulating layer;

2. 2. The silicon carbide semiconductor device according to claim 1, wherein, in the Y-Z cross section, the deepest portions of the first recess and the second recess are located at a position higher than the front surface of the semiconductor substrate on the opposite side in the depth direction.

3. A silicon carbide semiconductor device as described in claim 1 or 2, characterized in that in the Y-Z cross section, the difference in height of the unevenness caused by the first recess and the second recess on the front surface side of the semiconductor substrate is 0.3 μm or less.

4. A trench gate in which the polysilicon layer is a gate electrode, In the Y-Z cross section, the first recess faces the gate electrode in the depth direction, 4 . The silicon carbide semiconductor device according to claim 1 , wherein the second recess faces, in the depth direction, a region between the trench gates adjacent to each other in the lateral direction. 5 .

5. In the Y-Z cross section, The barrier metal is a first apex which is the deepest portion facing the recess in the depth direction; a second apex located outside the polysilicon layer in the lateral direction, the second apex being between the first apex and an inner wall of the first recess; 5 . The silicon carbide semiconductor device according to claim 1 , wherein a height difference between the first apex and the second apex is equal to or greater than 0.1 μm and less than 0.5 μm. 6 .

6. In the Y-Z cross section, The barrier metal is a third apex which is the deepest portion of the second recess; a fourth vertex located closer to the recess than the third vertex in the lateral direction, with an inner wall of the second recess being located between the fourth vertex and the third vertex, 6. The silicon carbide semiconductor device according to claim 5, wherein a height difference between the third apex and the fourth apex is 0.1 μm or more and 50% or less of a maximum value of a total thickness of the interlayer insulating film.

7. In the Y-Z cross section, The barrier metal is a third apex which is the deepest portion of the second recess; a fourth vertex located closer to the recess than the third vertex in the lateral direction, with an inner wall of the second recess being located between the fourth vertex and the third vertex, 6. The silicon carbide semiconductor device according to claim 5, wherein a difference in height between the third apex and the fourth apex is not less than 0.1 μm and not more than 0.4 μm.

8. The silicon carbide semiconductor device of claim 6, wherein a flat surface is provided between the second vertex and the fourth vertex in the YZ cross section.

9. A trench-gate type silicon carbide semiconductor device having trenches embedded with a polysilicon layer having a recess on an upper surface thereof, the trenches being arranged side by side in a lateral direction parallel to the front surface of a semiconductor substrate on a front surface side of the semiconductor substrate, an interlayer insulating film laminated on a front surface of the semiconductor substrate and covering the polysilicon layer; a barrier metal, at least a portion of which is provided along a surface of the interlayer insulating film; Equipped with In a Y-Z cross section in the lateral direction and the depth direction of the semiconductor substrate, The barrier metal is a first apex which is the deepest portion facing the recess in the depth direction; a second apex located outside the polysilicon layer in the lateral direction, the second apex being between the first apex and an inner wall of the first recess; a second vertex that is located farther from the polysilicon layer in the lateral direction than the second vertex and that forms a flat surface between the second vertex and the other vertex, a height difference between the first apex and the second apex being 0.1 μm or more and less than 0.5 μm.

10. A semiconductor device comprising: a first conductivity type source region provided within the semiconductor substrate and exposed on a front surface of the semiconductor substrate; 10. The silicon carbide semiconductor device according to claim 5, wherein, in the YZ cross section, the second apex faces the source region in the depth direction.

11. A silicon carbide semiconductor device according to claim 1, wherein the barrier metal is an electrode film containing titanium.

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