Semiconductor Device

Abstract

To solve a problem that current passing from an undersurface to a top face of a chip concentrates on part of a P+ type contact region in the case where the P+ type contact region is provided on the top face side of the chip in a diode part and an N+ type cathode region is provided in an entire region under the P+ type contact region.SOLUTION: A semiconductor device comprises a semiconductor substrate, a transistor part provided on the substrate and a diode part provided on the substrate and adjacent to the transistor part. The diode part has: a second conductivity type anode region; a first conductivity type drift region; a first conductivity type cathode region; a plurality of dummy trench parts arranged along a predetermined arrangement direction; contact parts provided in an extension direction of the plurality of dummy trench parts different from the arrangement direction; and an undersurface side semiconductor region provided just under the outside ends of the contact parts in the extension direction.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device.

[0002] Conventionally, there is known a semiconductor device in which a transistor section such as an IGBT (Insulated Gate Bipolar Transistor) and a diode section such as an FWD (Free Wheeling Diode) are formed on the same chip. In this semiconductor device, an N+ type cathode region is provided in a region on the underside of the chip where the diode section is provided (for example, see Patent Document 1). [Prior art document] [Patent documents] [Patent Document 1] JP 2015-135954 A Summary of the Invention [Problem to be solved by the invention]

[0003] In the diode section, for example, a contact section is provided along the longitudinal direction of the trench. If an N+ type cathode region is provided in the entire lower part of the diode section, there is a problem that the current flowing from the lower surface to the upper surface of the chip is concentrated at the end of the diode section, i.e., the end of the contact section. [Means for solving the problem]

[0004] In order to solve the above problem, a first aspect of the present invention provides a semiconductor device in which a transistor portion and a diode portion are provided on a semiconductor substrate having an upper surface and a lower surface parallel to a first axis direction and a second axis direction. The semiconductor device may include a first trench portion provided on the upper surface and having a straight portion extending in the first axis direction, a cathode region of a first conductivity type provided on the lower surface, and a second trench portion provided on the upper surface and having an outer portion that is continuously provided from the outside of an end of the cathode region in the first axis direction to the outside of an end of the cathode region in the second axis direction. In any of the above semiconductor devices, the transistor portion may include the first trench portion.

[0005] In any of the above semiconductor devices, the second trench portion may have a plurality of inner portions extending in the first axis direction or the second axis direction and connected to the outer portion.

[0006] In any of the above semiconductor devices, the outer portion may have a portion extending in the first axis direction, a portion extending in the second axis direction, and a connection portion between the portion extending in the first axis direction and the portion extending in the second axis direction.

[0007] In any of the above semiconductor devices, the portion of the outer portion extending in the first axis direction may be located outward from an end of the cathode region in the second direction. In any of the above semiconductor devices, the portion of the outer portion extending in the second axis direction may be located outward from an end of the cathode region in the first direction.

[0008] In any of the above semiconductor devices, the portion of the outer portion extending in the first axis direction and the portion extending in the second axis direction may be connected outside the cathode region.

[0009] In any of the semiconductor devices described above, the first trench portion may have a first portion which is the straight portion, and a second portion which extends in the second axis direction.

[0010] In any of the above semiconductor devices, the first trench portion of the transistor portion may have a first portion which is the straight portion and a second portion extending in the second axis direction. In any of the above semiconductor devices, the outer portion may have a connection portion between the portion extending in the first axis direction and the portion extending in the second axis direction. In any of the above semiconductor devices, the connection portion may be surrounded by the first portion and the second portion.

[0011] In any of the semiconductor devices described above, the straight portion in the first trench portion of the transistor portion may be provided over a wider range in the first axial direction than the outer portion.

[0012] Any of the above semiconductor devices may include a metal electrode made of a metal material provided above the upper surface, and an interlayer insulating film provided between the upper surface and the metal electrode. In any of the above semiconductor devices, a plurality of contact holes provided in the interlayer insulating film along the first axis direction may be connected to the semiconductor substrate on the inside of the outer portion.

[0013] In a second aspect of the present invention, there is provided a semiconductor device having a transistor portion and a diode portion provided on a semiconductor substrate having an upper surface and a lower surface parallel to a first axis direction and a second axis direction. The semiconductor device may include a first trench portion provided on the upper surface and having a first portion that is a straight portion extending in the first axis direction and a second portion extending in the second axis direction, and a second trench portion provided on the upper surface and having a connection portion between the portion extending in the first axis direction and the portion extending in the second axis direction.

[0014] In any of the semiconductor devices described above, the transistor portion may include the first trench portion.

[0015] In any of the semiconductor devices described above, the connection portion may be surrounded by the first portion and the second portion.

[0016] In any one of the above semiconductor devices, the diode portion may include the second trench portion. In any one of the above semiconductor devices, the second trench portion may be a dummy trench portion.

[0017] In any of the above semiconductor devices, a plurality of the diode sections may be provided, and at least a corner of each of the diode sections and two sides that define the corner may be surrounded by the transistor section.

[0018] In any of the above semiconductor devices, the first trench portion may be a gate trench portion.

[0019] In any of the above semiconductor devices, the cathode region and the outer portion may not overlap each other in a top view. At least a part of the outer portion may be located at a boundary between the transistor portion and the diode portion.

[0020] In any of the above semiconductor devices, an end of the contact hole in the first axial direction may be positioned outside an end of the cathode region in the first axial direction.

[0021] The above summary of the invention does not list all of the necessary features of the present invention. Also, subcombinations of these features may also be inventions. [Brief description of the drawings]

[0022] [Figure 1] 1 is a top view of a semiconductor device 100 according to a first embodiment. [Diagram 2] 2 is a cross-sectional view taken along line AA' of FIG. [Diagram 3] 2 is a cross-sectional view taken along the line B-B' of FIG. [Figure 4] This is a modified example of the first embodiment. [Diagram 5] 5 is a cross-sectional view taken along the line AA' of FIG. [Figure 6] FIG. 11 is a top view of a semiconductor device 200 according to a second embodiment. [Figure 7] 7 is a cross-sectional view taken along line AA' of FIG. 6. [Figure 8] 7 is a cross-sectional view taken along the line B-B' of FIG. 6. [Figure 9] 9 is a partial enlarged view of the accumulation region 16 in the vicinity of the contact region 15 in FIG. 8. [Figure 10] 13A and 13B are diagrams illustrating mask sagging when forming a storage region 16. FIG. [Figure 11] FIG. 11 is a top view of a semiconductor device 300 according to a third embodiment. [Figure 12] 12 is a cross-sectional view taken along the line AA' of FIG. [Figure 13] FIG. 11 is a top view of a semiconductor device 400 according to a fourth embodiment. [Figure 14] 14 is a cross-sectional view taken along line AA' of FIG. 13. [Figure 15A] FIG. 2 is a cross-sectional view taken along line AA' in the first comparative example. [Figure 15B] FIG. 11 is a cross-sectional view taken along line AA' in the second comparative example. [Figure 16] 1 is a top view showing a corner of a diode portion 80 adjacent to a transistor portion 70. FIG. [Figure 17] This is a cross-sectional view taken along line aa' of Figure 16. [Figure 18] 1 is a diagram showing the concentration distribution of recombination centers in a lifetime killer region 19. FIG. [Figure 19] This is a cross-sectional view taken along line b-b' of Figure 16. [Figure 20] FIG. 17 is a diagram showing a modification of FIG. 16. [Figure 21] This is a cross-sectional view taken along line c-c' of Figure 20. [Figure 22] This is a cross-sectional view taken along line dd' of Figure 20. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0023] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention according to the claims. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0024] FIG. 1 is a top view of a semiconductor device 100 in the first embodiment. The semiconductor device 100 of this example has a semiconductor substrate including a transistor section 70 including a transistor such as an IGBT, and a diode section 80 including a diode such as an FWD. The diode section 80 is provided adjacent to the transistor section 70 on the top surface of the semiconductor substrate. The top surface of the semiconductor substrate refers to one of two opposing main surfaces of the semiconductor substrate. FIG. 1 shows the top surface around the end of the semiconductor substrate, and other regions are omitted. Note that the collector region 22 and the cathode region 82 indicated by the arrows in FIG. 1 are provided on the back surface side of the semiconductor substrate.

[0025] In this example, the transistor section 70 and the diode section 80 are provided in an active region of a semiconductor substrate. In this example, the transistor section 70 refers to a projection area when the collector region 22 is projected from the back surface of the semiconductor substrate toward the front surface side in a direction perpendicular to the back surface of the semiconductor substrate, and includes an area where predetermined unit configurations including both the emitter region 12 and the contact region 15 are regularly arranged. In this example, the diode section 80 refers to an area on the back surface that coincides with the cathode region 82, or includes a projection area when the cathode region 82 is projected from the back surface of the semiconductor substrate toward the front surface side in a direction perpendicular to the back surface of the semiconductor substrate.

[0026] In this specification, the terms "upper", "lower", "upper side", "lower", "upper surface" and "lower surface" are not limited to the up and down directions in the direction of gravity. These terms refer to relative directions on a specific axis.

[0027] FIG. 1 shows an active region around an edge of a semiconductor substrate. However, the semiconductor device 100 may have an edge termination surrounding the active region in a top view. The active region refers to a region through which current flows when the semiconductor device 100 is controlled to be in an on-state. The edge termination relieves electric field concentration on the top side of the semiconductor substrate. The edge termination has a structure such as a guard ring, a field plate, a resurf, or a combination of these.

[0028] The semiconductor device 100 of this example includes a dummy trench portion 30, a gate trench portion 40, an emitter region 12, a base region 14, a contact region 15, and a well region 17 formed on the upper surface side of a semiconductor substrate. In this specification, the gate trench portion 40 and the dummy trench portion 30 may be collectively referred to as a trench portion. The semiconductor device 100 of this example also includes an emitter electrode 52 and a gate metal layer 50 provided above the upper surface of the semiconductor substrate. The emitter electrode 52 and the gate metal layer 50 are provided separately from each other.

[0029] The semiconductor device 100 has an interlayer insulating film between the emitter electrode 52 and the gate metal layer 50 and the upper surface of the semiconductor substrate. However, the interlayer insulating film is omitted in Fig. 1. The interlayer insulating film in this example has contact holes 54, 55, and 56. The contact holes 54, 55, and 56 are formed to penetrate the interlayer insulating film.

[0030] The emitter electrode 52 is in contact with the emitter region 12, the contact region 15, and the base region 14 through a contact hole 54. The emitter electrode 52 is also electrically connected to a dummy conductive portion in the dummy trench portion 30 through a contact hole 56. A conductive connection portion 57 may be provided between the emitter electrode 52 and the dummy conductive portion. The connection portion 57 may be formed of polysilicon doped with impurities, or the like.

[0031] The gate metal layer 50 contacts the gate wiring 51 through the contact hole 55. The gate wiring 51 may be formed of polysilicon doped with impurities or the like. A conductive gate wiring 51 is provided between the gate metal layer 50 and a gate conductive portion in the gate trench portion 40. The gate wiring 51 is provided on the upper surface of the semiconductor substrate, spanning at least a portion of the gate trench portion 40 and the contact hole 55. The gate wiring 51 is electrically connected to the gate conductive portion in the gate trench portion 40.

[0032] The emitter electrode 52 and the gate metal layer 50 are formed of a material containing metal. For example, at least a portion of each electrode is formed of aluminum or an aluminum-silicon alloy. Each electrode may have a barrier metal made of titanium or a titanium compound under the region made of aluminum, and may have plugs made of tungsten in the contact holes 54, 55, and 56.

[0033] The multiple gate trench portions 40 and the multiple dummy trench portions 30 are arranged at predetermined intervals along a predetermined arrangement direction in the region of the transistor portion 70. In the transistor portion 70, one or more gate trench portions 40 and one or more dummy trench portions 30 may be alternately provided along the arrangement direction. Also, in the diode portion 80, the multiple dummy trench portions 30 are arranged at predetermined intervals along the arrangement direction.

[0034] In this example, two types of shapes of dummy trench portions 30 are provided on the upper surface of the semiconductor substrate. The first shape is a linear shape extending in a predetermined extension direction. The second shape is a U-shape in which a linear portion extending in the extension direction and a linear portion extending in the arrangement direction are connected by curved portions at each end.

[0035] In FIG. 1, the X-axis direction is the arrangement direction of the trench portions. The Y-axis direction is the extension direction of the trench portions. The X-axis and Y-axis are axes that are perpendicular to each other in a plane parallel to the upper surface of the semiconductor substrate. The axis that is perpendicular to the X-axis and Y-axis is the Z-axis. In this specification, the Z-axis direction may be referred to as the depth direction.

[0036] In the transistor section 70, a plurality of dummy trench sections 30 may be arranged at a predetermined interval at the boundary with the diode section 80. The number of dummy trench sections 30 arranged in the X-axis direction near the boundary between the transistor section 70 and the diode section 80 may be greater than the number of dummy trench sections 30 arranged inside the transistor section 70 away from the diode section 80.

[0037] In the example of FIG. 1, in the transistor section 70 at the boundary between the transistor section 70 and the diode section 80, a total of three dummy trench sections 30, two connected in a U-shape and one linear dummy trench section 30, are arranged at a predetermined interval. The dummy trench section 30 that overlaps the boundary between the transistor section 70 and the diode section 80 is not counted as one of the three. In contrast, in the transistor section 70 away from the boundary between the transistor section 70 and the diode section 80, the gate trench section 40 and the dummy trench section 30 are arranged alternately one by one. In FIG. 1, the diode section 80 has two dummy trench sections 30 connected in a U-shape. However, the diode section 80 may further have a plurality of dummy trench sections 30 in the positive direction of the X-axis.

[0038] In this example, one type of shape of gate trench portion 40 is provided on the upper surface of the semiconductor substrate. The shape is a U-shape in which a straight portion extending in a predetermined extension direction and a straight portion extending in the arrangement direction are connected at each end by a curved portion.

[0039] The gate trench portion 40 has an opposing portion 41 and a protruding portion 43. The opposing portion 41 is a portion that faces the dummy trench portion 30 in the transistor portion 70. The opposing portion 41 is provided in parallel with the dummy trench portion 30. The protruding portion 43 is provided outside the opposing portion 41 in the Y-axis direction. In this example, the outside in the Y-axis direction means the end side of the semiconductor substrate in the vicinity of the gate metal layer 50. The inside in the Y-axis direction means the side opposite to the outside. In this example, the two opposing portions 41 of the gate trench portion 40 provided on both sides of the dummy trench portion 30 are connected to one protruding portion 43. At least a part of the protruding portion 43 may have a curved shape.

[0040] At the protruding portion 43, the gate conductive portion in the gate trench portion 40 and the gate wiring 51 are electrically connected. The gate wiring 51 may be electrically connected to the gate conductive portion in a region of the protruding portion 43 that is farthest from the opposing portion 41. The protruding portion 43 in this example has a portion that extends in the arrangement direction in a region farthest from the opposing portion 41. The gate wiring 51 may be connected to the gate conductive portion in that portion of the protruding portion 43.

[0041] The dummy trench portion 30 in the diode portion 80 may have a shape similar to that of the dummy trench portion 30 in the transistor portion 70, and may have a shape similar to that of the gate trench portion 40 in the transistor portion 70. However, the dummy trench portion 30 in the diode portion 80 has the same length as the dummy trench portion 30 in the transistor portion 70.

[0042] The emitter electrode 52 is provided above the gate trench portion 40, the dummy trench portion 30, the well region 17, the emitter region 12, the base region 14, and the contact region 15. The well region 17 is formed from the end of the active region where the gate metal layer 50 is provided to a predetermined range in the positive direction of the Y axis. The diffusion depth of the well region 17 may be deeper than the depth of the dummy trench portion 30 and the gate trench portion 40. Part of the regions of the dummy trench portion 30 and the gate trench portion 40 located on the gate metal layer 50 side are formed in the well region 17. The bottoms of the ends of the dummy trench portion 30 and the gate trench portion 40 in the extension direction may be provided in the well region 17.

[0043] The protruding portion 43 of the gate trench portion 40 may be entirely provided within the well region 17. The semiconductor substrate is of a first conductivity type, and the well region 17 is of a second conductivity type different from the semiconductor substrate. In this example, the semiconductor substrate is of N- type, and the well region 17 is of P+ type. In this example, the first conductivity type is described as N type, and the second conductivity type is described as P type. However, in other examples, the first conductivity type may be P type, and the second conductivity type may be N type.

[0044] In this example, the mesa portion 94 is a part of the semiconductor substrate located on the surface of the semiconductor substrate below the bottom surfaces of the dummy trench portion 30 and the gate trench portion 40. The mesa portion 94 is also a region sandwiched between the trench portions. A base region 14 is provided in the mesa portion 94. The base region 14 is of a second conductivity type having a lower doping concentration than the well region 17. In this example, the base region 14 is of P-type. At least a portion of the base region 14 is provided below the emitter region 12 and the contact region 15.

[0045] In the mesa portion 94, a contact region 15 of a second conductivity type having a higher doping concentration than the base region 14 is provided on the base region 14. In this example, the contact region 15 is of P+ type. In the transistor portion 70, an emitter region 12 of a first conductivity type having a higher doping concentration than the semiconductor substrate is selectively formed in an area other than the contact region 15. In this example, the emitter region 12 is of N+ type.

[0046] Each of the contact region 15 and the emitter region 12 is formed from one trench portion adjacent to the other trench portion in the X-axis direction. One or more contact regions 15 and one or more emitter regions 12 of the transistor portion 70 are exposed on the upper surface of the mesa portion 94 alternately along the extension direction of the trench portion.

[0047] The mesa portion 94 of the diode portion 80 has a contact region 15 at the same position in the Y-axis direction as at least one contact region 15 in the transistor portion 70. In the example of Fig. 1, the mesa portion 94 of the diode portion 80 has a contact region 15 at the same position in the Y-axis direction as the contact region 15 that is closest to the gate metal layer 50 in the transistor portion 70. The mesa portion 94 of the diode portion 80 has a base region 14 in a region other than the contact region 15.

[0048] The contact hole 54 of the transistor section 70 is provided above the contact region 15 and the emitter region 12 arranged side by side in the Y-axis direction. The contact hole 54 of the transistor section 70 is not provided above the base region 14 and the well region 17. The contact hole 54 of the diode section 80 is provided above the base region 14 and the contact region 15. The contact hole 54 of the diode section 80 is also not provided above the well region 17 and above the base region 14 closest to the gate metal layer 50. In this example, the contact hole 54 of the transistor section 70 and the contact hole 54 of the diode section 80 have the same length in the extension direction of each trench section. The contact structure provided in the contact hole 54 of this example is an example of a contact section provided along the Y-axis direction. The contact structure may be the emitter electrode 52 that is in direct contact with the semiconductor substrate, or may be the above-mentioned plug.

[0049] Among the multiple mesas 94, at least one boundary mesa 94-1 in the vicinity of the boundary between the transistor section 70 and the diode section 80 has a contact region 15. The area of ​​the contact region 15 exposed on the upper surface of the semiconductor substrate in the boundary mesa 94-1 in this example is larger than the area of ​​the contact region 15 exposed on the upper surface of the semiconductor substrate in the other mesas 94. In this example, the boundary mesa 94-1 refers to the mesa 94 on the transistor section 70 side among the mesas 94 adjacent to the dummy trench section 30 overlapping the boundary between the transistor section 70 and the diode section 80.

[0050] 1, the boundary mesa portion 94-1 is adjacent to the boundary between the transistor portion 70 and the diode portion 80. In the boundary mesa portion 94-1, a contact region 15 is provided even in a region where an emitter region 12 is provided in another mesa portion 94 of the transistor portion 70. In other words, the boundary mesa portion 94-1 in this example does not have an emitter region 12 on the upper surface of the semiconductor substrate.

[0051] At least a portion of the mesa portion 94 of the diode portion 80 has a base region 14 exposed on the upper surface of the semiconductor substrate. The mesa portion 94 also has the base region 14 at the same position in the Y-axis direction as the contact region 15 in the boundary mesa portion 94-1. The base region 14 in this example functions as an anode region in the diode portion 80. That is, in this example, the base region 14 of the diode portion 80 may be read as an anode region.

[0052] Further, in a portion of the region of the diode section 80, a cathode region 82 is provided below the base region 14 in the Z-axis direction. The cathode region 82 is of a first conductivity type. In this example, the cathode region 82 is of an N+ type. The cathode region 82 in this example is provided in a portion directly below the base region 14. In FIG. 1, the region where the cathode region 82 is provided is indicated by a thick dashed line.

[0053] The diode section 80 of this example has a collector region 22 in a region other than the cathode region 82 at the same depth position as the cathode region 82. The collector region 22 is of the second conductivity type, and the collector region 22 of this example is of P+ type. In FIG. 1, the region in which the collector region 22 is provided is indicated by a thick dashed line, similar to the cathode region 82. The collector region 22 of this example is an example of a lower surface side semiconductor region of the second conductivity type. The lower surface side semiconductor region is of the second conductivity type, and the lower surface side semiconductor region of this example is of P+ type. The lower surface side semiconductor region may have the same P-type doping concentration as the collector region 22, may have a higher P-type doping concentration than the collector region 22, or may have a lower P-type doping concentration than the collector region 22 and a higher P-type doping concentration than the base region 14. In this example, the collector region 22 is provided in the region where the transistor portion 70 is projected onto the lower surface side of the semiconductor substrate. The collector region 22 may be provided in the region where the boundary mesa portion 94-1 is projected onto the lower surface side of the semiconductor substrate, or the collector region 22 of the transistor portion 70 may be extended. In this case, the boundary mesa portion 94-1 may be a part of the transistor portion 70.

[0054] The cathode region 82 and the collector region 22 are not limited to the regions surrounded by thick dashed lines. For example, the thick dashed line of the cathode region 82 that is not the boundary with the collector region 22 simply indicates the edge on the drawing, and the cathode region 82 may be formed beyond the thick dashed line. The same is true for the collector region 22. On the other hand, the cathode region 82 is not formed beyond the dashed line indicating the boundary with the collector region 22.

[0055] The collector region 22 may be provided continuously across the transistor section 70 and the diode section 80. In the transistor section 70 of this example, the collector region 22 is provided on the entire lower surface side of the semiconductor substrate. In contrast, in the diode section 80 of this example, the collector region 22 is provided on a part of the lower surface side of the semiconductor substrate. In the diode section 80, the collector region 22 may be provided directly below the well region 17, directly below the end of the contact region 15 in the Y-axis direction, or directly below the base region 14 adjacent to the contact region 15 in the positive direction of the Y-axis. In the diode section 80 of this example, the collector region 22 is provided continuously from the end of the semiconductor substrate in the Y-axis direction to a position directly below the base region 14.

[0056] In this way, in this example, the cathode region 82 is not provided directly below the contact region 15 of the diode section 80. In this example, the cathode region 82 is reduced in the positive direction of the Y-axis, and the collector region 22 is expanded in the positive direction of the Y-axis accordingly. As a result, the collector region 22 is provided at least directly below the outer end 53 of the contact hole 54 in the Y-axis direction. The collector region 22 is provided further in the positive direction of the Y-axis than the end 53. As described above, a contact portion is provided in the contact hole 54, and the end of the contact portion coincides with the end 53 of the contact hole 54. In this example, it is possible to prevent the current flowing from the lower surface to the upper surface of the semiconductor substrate from concentrating at the end 53 of the contact portion.

[0057] 2 is a cross-sectional view taken along the line A-A' in FIG. 1. The A-A' cross-section is parallel to the X-Z plane. The A-A' cross-section passes through the emitter region 12 of the transistor section 70 and the base region 14 of the diode section 80. In the A-A' cross-section, the semiconductor device 100 of this example has a semiconductor substrate 10, an interlayer insulating film 26, an emitter electrode 52, and a collector electrode 24. The emitter electrode 52 is formed on the upper surfaces of the semiconductor substrate 10 and the interlayer insulating film 26.

[0058] In contrast, the collector electrode 24 is formed on the bottom surface of the semiconductor substrate 10. The bottom surface refers to the surface opposite to the top surface. The emitter electrode 52 and the collector electrode 24 are formed of a conductive material such as metal. In this specification, the surface or end of each member such as a substrate, layer, or region on the emitter electrode 52 side is referred to as the top surface or top end, and the surface or end on the collector electrode 24 side is referred to as the bottom surface or bottom end. The direction connecting the emitter electrode 52 and the collector electrode 24 is referred to as the depth direction.

[0059] The semiconductor substrate 10 may be a silicon substrate, a silicon carbide substrate, a nitride semiconductor substrate such as gallium nitride, or the like. In the A-A' cross section, an N+ type emitter region 12 and a P- type base region 14 are provided in this order from the upper surface side of the semiconductor substrate 10 on the upper surface side of each mesa portion 94 of the transistor portion 70. In addition, in the A-A' cross section, a P- type base region 14 is provided on the upper surface side of each mesa portion 94 of the diode portion 80.

[0060] In the transistor section 70 and the diode section 80, a drift region 18 of a first conductivity type is provided below the base region 14. In this example, the drift region 18 is an N-type. In the transistor section 70 and the diode section 80, an N-type buffer region 20 is provided below the drift region 18. The doping concentration of the buffer region 20 may be higher than the doping concentration of the drift region 18. The buffer region 20 may function as a field stop layer that prevents a depletion layer extending from the lower surface side of the base region 14 from reaching the P+ type collector region 22 and the N+ type cathode region 82.

[0061] In the transistor section 70, a P+ type collector region 22 is provided below the buffer region 20. In the diode section 80, an N+ type cathode region 82 is provided below the buffer region 20. In addition, a collector electrode 24 is provided on the lower surfaces of the collector region 22 and the cathode region 82.

[0062] In this specification, a plane that passes through the boundary between the collector region 22 and the cathode region 82 and is parallel to the YZ plane is defined as the boundary between the transistor section 70 and the diode section 80. The boundary P1 between the collector region 22 and the cathode region 82 may be a position where the distribution of the net doping concentration of the dopant in the X-axis direction is a minimum value. One dummy trench section 30 may be formed on a region including the boundary P1 between the transistor section 70 and the diode section 80. In addition, the position of the dummy trench section 30 that is closest to the position where the net doping concentration is a minimum value in the X-axis direction may be defined as the position of the boundary P1 between the transistor section 70 and the diode section 80.

[0063] One or more gate trench portions 40 and one or more dummy trench portions 30 are provided on the upper surface side of the semiconductor substrate 10. Each trench portion may reach the drift region 18 from the upper surface of the semiconductor substrate 10, penetrating the base region 14. The trench portion may reach the drift region 18 by penetrating one or more of the emitter region 12, the base region 14, and the contact region 15. The shape of the bottom of the trench portion in the A-A' cross section may be U-shaped.

[0064] The gate trench portion 40 of this example has a gate insulating film 42, a gate conductive portion 44, and a gate trench 46. The gate insulating film 42 may be provided to cover the inner wall of the gate trench 46. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench 46. The gate conductive portion 44 of this example is provided inside the gate insulating film 42 inside the gate trench. The gate insulating film 42 may insulate the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 may be formed of a conductive material such as polysilicon.

[0065] The gate trench portion 40 in this example is covered with an interlayer insulating film 26 on the upper surface of the semiconductor substrate 10. In this example, the gate conductive portion 44 in the protruding portion 43 is electrically connected to the gate metal layer 50 via the gate wiring 51 as shown in Fig. 1. When a predetermined voltage is applied to the gate conductive portion 44, a channel is formed in a region of the base region 14 near the interface with the gate trench 46.

[0066] The dummy trench portion 30 may have the same structure as the gate trench portion 40 in the A-A' cross section. The dummy trench portion 30 has a dummy insulating film 32, a dummy conductive portion 34, and a dummy trench 36 formed on the upper surface side of the semiconductor substrate 10. The dummy insulating film 32 is formed to cover the inner wall of the dummy trench 36. The dummy conductive portion 34 is provided inside the dummy trench 36 relative to the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy conductive portion 34 may be formed of the same material as the gate conductive portion 44. For example, the dummy conductive portion 34 is formed of a conductive material such as polysilicon. The dummy conductive portion 34 may have the same length as the gate conductive portion 44 in the depth direction.

[0067] The dummy trench portion 30 of this example is also covered with the interlayer insulating film 26 on the upper surface of the semiconductor substrate 10. In this example, the dummy conductive portion 34 is electrically connected to the emitter electrode 52 through a contact hole 56 as shown in FIG.

[0068] In this example, in a boundary mesa portion 94-1 at the boundary between the transistor portion 70 and the diode portion 80 among the multiple mesas 94, the emitter region 12 exposed on the upper surface of the semiconductor substrate 10 is not provided, but a contact region 15 exposed on the upper surface of the semiconductor substrate 10 is provided. Since the boundary mesa portion 94-1 in this example is a region that does not allow electrons to be injected from the gate, i.e., does not function as an IGBT, it is preferable that the emitter region 12 exposed on the upper surface of the semiconductor substrate 10 is not provided in the entire boundary mesa portion 94-1 as shown in FIG. 1. The contact region 15 of the boundary mesa portion 94-1 in this example is connected to the emitter electrode 52 via a contact hole 54.

[0069] In this example, by providing the boundary mesa portion 94-1 described above, holes near the boundary between the transistor portion 70 and the diode portion 80 can be efficiently extracted when the semiconductor device 100 is turned off. This efficiently reduces the tail current when the semiconductor device 100 is turned off, thereby reducing losses when the semiconductor device 100 is turned off. In addition, a decrease in the breakdown resistance of the semiconductor device 100 can be suppressed. Furthermore, holes accumulated in the transistor portion 70 can be prevented from flowing to the diode portion 80, thereby reducing the effect of interference from the transistor portion 70 to the diode portion 80.

[0070] FIG. 3 is a cross-sectional view taken along the line B-B' in FIG. 1. The B-B' cross section is a plane parallel to the Y-Z plane. The B-B' cross section passes through the connection portion 57 in the mesa portion 94 of the diode portion 80. As described above, the collector region 22 is provided as a lower surface semiconductor region on the lower surface side of the diode portion 80 in this example. The collector region 22 in this example extends in the positive direction of the Y axis further than the well region 17 and the contact region 15. In this example, the end P1 in the positive direction of the Y axis of the collector region 22 is located in the positive direction of the Y axis further than the end 53 of the contact hole 54 (see the dashed arrow). The length A from the position where the end P1 in the positive Y-axis direction of collector region 22 is projected onto the upper surface to contact region 15 may be longer than the depth of base region 14 and may be longer than the length in the depth direction from base region 14 to collector region 22. In this example, it is 100 μm.

[0071] Length B from a virtual position where end P1 in the positive Y-axis direction of collector region 22 is projected onto the upper surface to end 53 in the positive Y-axis direction of contact hole 54 may be longer than the depth of base region 14 and may be longer than the length in the direction from the bottom of base region 14 to the top of collector region 22. In this example, length B is 120 μm. Note that the depth of base region 14 is the length parallel to the Z-axis direction and means the length from the upper surface to the bottom of base region 14.

[0072] The length C from a virtual position where end P1 of collector region 22 in the positive Y-axis direction is projected onto the upper surface to the boundary between base region 14 and well region 17 may be longer than the depth of base region 14 and may be longer than the length in the depth direction from the bottom of base region 14 to the top of collector region 22. In this example, length C is 140 μm.

[0073] The connection portion 57 may be electrically connected to the dummy conductive portion 34 of the dummy trench portion 30. In this example, the connection portion 57 and the dummy conductive portion 34 come into contact with each other at a position where the connection portion 57 and the dummy conductive portion 34 overlap in the Z-axis direction. Also, in this example, an insulating film 58 is provided between the upper surface of the semiconductor substrate 10 and the connection portion 57 at a position where the connection portion 57 and the dummy conductive portion 34 do not overlap in the Z-axis direction. The insulating film 58 may be the same insulating film as the dummy insulating film 32. The insulating film 58 may be a silicon oxide film or a silicon nitride film.

[0074] The gate metal layer 50 is electrically connected to the gate wiring 51 through a contact hole 55. As described above, the gate wiring 51 extends in the X-axis direction and is electrically connected to the gate conductive portion 44 of the transistor section 70. In this example, an insulating film 58 is also provided between the gate wiring 51 and the upper surface of the semiconductor substrate 10. However, as described above, the insulating film 58 is not provided at a position where the gate wiring 51 and the gate conductive portion 44 overlap in the Z direction, and the gate wiring 51 contacts the gate conductive portion 44 at that position.

[0075] 3, if cathode region 82 is also provided at a position directly below well region 17, the current flowing from cathode region 82 directly below well region 17 to the upper surface of semiconductor substrate 10 cannot flow to well region 17 because there is no contact region 15 in well region 17. Therefore, the current flowing from directly below well region 17 to the upper surface is concentrated at end 53 of the contact portion. In contrast, in this example, by forming at least the area directly below end 53 as collector region 22, it is possible to avoid current concentration at end 53.

[0076] FIG. 4 is a modified example of the first embodiment. The difference from FIG. 1 is that a new boundary portion 90 is provided between the boundary mesa portion 94-1 and the diode portion 80. The boundary mesa portion 94-1 in this example means the mesa portion 94 on the transistor portion 70 side among the mesa portions 94 adjacent to the dummy trench portion 30 overlapping the boundary between the transistor portion 70 and the boundary portion 90. The boundary portion 90 in this example includes a plurality of boundary mesa portions 94-2 having contact regions 15 only at both ends in the extension direction of the contact hole 54. In addition, the base region 14 is exposed on the upper surface of the semiconductor substrate 10 between the contact regions 15 at both ends in the extension direction. The area of ​​the base region 14 exposed on the upper surface of the boundary mesa portion 94-2 may be 5 times or more, 10 times or more, or 20 times or more, as compared to the area of ​​the contact region 15.

[0077] The number of mesa portions 94 in the boundary portion 90 may be greater than or equal to the number of mesa portions 94 in the boundary mesa portion 94-1. Here, the number of mesa portions 94 refers to the number of mesa portions 94 sandwiched between the trench portions in the arrangement direction. In this example, the number of mesa portions 94 in the boundary mesa portion 94-1 is one, and the number of mesa portions 94 in the boundary mesa portion 94-2 in the boundary portion 90 is two.

[0078] A lifetime killer region 19 may be formed from the dummy trench portion 30 located in the positive direction of the X-axis from the gate trench portion 40 closest to the boundary portion 90, throughout the boundary portion 90 and the diode portion 80. The lifetime killer region 19 may be a point defect (such as a vacancy, a divacancy, or a dangling bond) formed inside the semiconductor substrate 10 by introducing light ions such as helium or a metal such as platinum. Furthermore, the lifetime killer region 19 may be a carrier recombination center formed by a point defect.

[0079] FIG. 5 is a cross-sectional view taken along the line A-A' in FIG. 4. The collector region 22 below the boundary mesa portion 94-1 may be extended and formed on the lower surface of the semiconductor substrate 10 directly below the boundary mesa portion 94-2. When the diode portion 80 is conductive in the forward direction, holes flow from the boundary mesa portion 94-1 of the transistor portion 70 toward the cathode region 82 of the diode portion 80. The contact region 15 is formed almost entirely on the surface of the boundary mesa portion 94-1, so that the amount of holes injected is large. In this example, the boundary mesa portion 94-2, which has a reduced area of ​​the contact region 15 compared to the boundary mesa portion 94-1, is provided in the boundary portion 90, so that the distance between the boundary mesa portion 94-1 and the cathode region 82 is increased, and the amount of holes injected from the boundary mesa portion 94-1 can be suppressed.

[0080] The lifetime killer region 19 shown in Fig. 5 may include a position where the concentration of the introduced helium, point defect carrier recombination centers is maximum (peak). The width in the depth direction of the lifetime killer region 19 shown in Fig. 5 may be the full width at half maximum of the peak concentration of the introduced helium, point defects, or recombination centers. In the lifetime killer region 19, the concentration distribution of the introduced helium, point defects, or recombination centers may have a mountain-shaped distribution shape including a peak.

[0081] By providing the lifetime killer region 19, when the diode portion 80 operates, the reverse recovery time can be shortened and the reverse recovery charge and reverse recovery peak current can be reduced. Also, the minority carriers (holes in this example) can be prevented from flowing excessively from the mesa portion 94-1 into the diode portion 80, improving the reverse recovery withstand capability.

[0082] 6 is a top view of a semiconductor device 200 in the second embodiment. The semiconductor device 200 of this example has an accumulation region 16 of the first conductivity type having a higher doping concentration of the first conductivity type than the drift region 18. This point differs from the first embodiment. The region in which the accumulation region 16 is provided is shown with diagonal lines. The accumulation region 16 in this example is of N+ type. In FIG. 6, the outer end of the range in which the accumulation region 16 is provided is shown with a dashed line that is thinner than the dashed line of the collector region 22.

[0083] The semiconductor device 200 of this example has an accumulation region 16 in both the transistor section 70 and the diode section 80. The dopant (donor in this example) in the accumulation region 16 is accumulated at a higher concentration than in the drift region 18. The outer end of the accumulation region 16 may be provided further outside than the emitter region 12 located at the outermost position in the Y-axis direction. In this example, the outer end of the accumulation region 16 in the Y-axis direction is provided inside the outer end 53 in the Y-axis direction of the contact hole 54 located at the outermost position in the Y-axis direction. The accumulation region 16 may be provided in a region other than that shown in FIG. 6 in the positive and negative X-axis directions and the positive Y-axis direction. In the transistor section 70, the accumulation region 16 is provided to enhance the carrier injection enhancement effect (IE effect) and reduce the on-voltage.

[0084] In order to obtain the IE effect, it is also possible to provide the accumulation region 16 only in the transistor section 70. However, if an attempt is made to provide the accumulation region 16 only in the transistor section 70 without providing the accumulation region 16 in the diode section 80, the depth position of the accumulation region 16 may vary at the boundary between the transistor section 70 and the diode section 80. The variation in the depth position of the accumulation region 16 occurs, for example, due to resist sagging, which will be described later.

[0085] Therefore, in this example, the accumulation region 16 is provided in both the transistor section 70 and the diode section 80. This makes it possible to prevent variation in the depth position of the accumulation region 16. Therefore, it is possible to suppress variation in the threshold voltage and saturation current of the IGBT or the like in the transistor section 70, and a decrease in the forward voltage of the FWD in the diode section 80, which are caused by variation in the depth position of the accumulation region 16.

[0086] In this example, the cathode region 82 provided on the lower surface side of the diode section 80 is provided inward by a length L from the outer end in the Y-axis direction of the accumulation region 16 provided in the transistor section 70. In other words, the collector region 22 provided on the lower surface side of the diode section 80 partially overlaps with the accumulation region 16. For example, the collector region 22 is also provided directly below the end in the Y-axis direction of the accumulation region 16 in the diode section 80.

[0087] The collector region 22 in the diode section 80 may be provided continuously at least from just below the outer end 53 of the contact hole 54 in the Y-axis direction to just below the end of the accumulation region 16 in the Y-axis direction. The collector region 22 in this example is provided continuously from the outer end in the Y-axis direction to the boundary between the collector region 22 and the cathode region 82. In the upper surface of the semiconductor substrate 10 in this example, the length from the outer end of the accumulation region 16 in the Y-axis direction to the boundary between the collector region 22 and the cathode region 82 is referred to as L. The value of the length L may be variable with respect to the outer end of the accumulation region 16 in the Y-axis direction. The length L may be several μm or more, several tens of μm or more, 100 μm or more, or 200 μm or more. However, in order to allow the diode section 80 to function properly, it is preferable that the length L is 400 μm or less. This makes it possible to avoid current concentration at the end 53 of the contact section while ensuring the function of the diode section 80.

[0088] In the transistor portion 70 having the mesa portion 94-1, the lifetime killer region 19 may be formed from the dummy trench portion 30 located in the positive direction of the X-axis relative to the gate trench portion 40 that is closest to the diode portion 80, throughout the entire diode portion 80. In this example, the outer circumferential end portion in the Y-axis direction of the lifetime killer region 19 may be located on the outer circumferential side (negative direction of the Y-axis) relative to the contact hole 55 of the gate wiring 51. In addition, the outer circumferential end portion in the Y-axis direction of the lifetime killer region 19 may be located on the outer circumferential side of the outer circumferential end portion of the gate wiring 51.

[0089] 7 is a cross-sectional view taken along line A-A' in FIG. 6. The semiconductor substrate 10 of this example has an accumulation region 16 between the base region 14 and the drift region 18 in the transistor section 70. The semiconductor substrate 10 of this example also has an accumulation region 16 between the base region 14 (i.e., the anode region) and the drift region 18 in the diode section 80. As described above, in this example, the accumulation region 16 is provided in both the transistor section 70 and the diode section 80, so that the depth at which the accumulation region 16 is provided can be made the same in the transistor section 70 and the diode section 80.

[0090] The lifetime killer region 19 of this example may be formed on the upper surface side of the center of the semiconductor substrate 10 in the depth direction (Z-axis direction) of the semiconductor substrate 10. That is, the depth from the upper surface of the semiconductor substrate 10 to the lifetime killer region 19 may be smaller than the depth from the lifetime killer region 19 to the lower surface of the semiconductor substrate 10. The lifetime killer region 19 may be formed from a dummy trench portion 30 located in the X-axis positive direction of the gate trench portion 40 closest to the diode portion 80 in the transistor portion 70 having the mesa portion 94-1, over the entire diode portion 80.

[0091] FIG. 8 is a cross-sectional view taken along the line B-B' in FIG. 6. FIG. 8 is the same as FIG. 3 of the first embodiment except that the accumulation region 16 is between the base region 14 and the drift region 18, so a duplicated description will be omitted. The accumulation region 16 extends in the positive direction of the Y axis from directly below the contact region 15. As described above, in the diode section 80 of this example, the outer end of the accumulation region 16 in the Y axis direction is provided inside the end 53 of the contact hole 54 located on the outermost side in the Y axis direction (see the arrow). In this example, the length from the outer end of the accumulation region 16 in the Y axis direction to the boundary between the collector region 22 and the cathode region 82 on the upper surface of the semiconductor substrate 10 is referred to as W. In this example, the collector region 22 in the diode section 80 is provided continuously at least from directly below the end 53 of the contact hole 54 to directly below the end of the accumulation region 16 in the Y axis direction.

[0092] The outer end of the accumulation region 16 in the Y-axis direction may be provided outside the boundary between the collector region 22 and the cathode region 82. In this case, the length L from the outer end of the accumulation region 16 in the Y-axis direction to the boundary between the collector region 22 and the cathode region 82 may be longer than the length W from the end 53 of the contact hole 54 as the contact portion located on the outermost side in the Y-axis direction to the outer end of the accumulation region 16 in the Y-axis direction. When the diode portion 80 is conductive, holes injected from the base region 14, which is the anode region, flow toward the cathode region 82. The accumulation region 16 suppresses the injection of holes from the base region 14, while in this example, there is no accumulation region 16 in the region of length W outside the end of the accumulation region 16, so that holes are easily injected. However, since the boundary between the collector region 22 and the cathode region 82 is located inside the end 53 of the contact hole 54, even if the position of the outer end of the accumulation region 16 in the Y-axis direction is inside the end 53, the injection of holes outside the end 53 is suppressed. Furthermore, since the length L is longer than the length W, excessive injection of holes into the region of length W is almost eliminated. This is an advantage of this example.

[0093] In other examples of this embodiment, the length W may be longer than the length L. In general, when the diode section 80 is conductive, holes leak outward from the end 53 to a certain extent. Therefore, the current of the diode section 80 is concentrated at the end 53 of the contact hole 54, and the current density at the end 53 increases. On the other hand, when the diode section 80 performs reverse recovery operation, the electric field near the pn junction between the base region 14 and the accumulation region 16 is likely to concentrate particularly at the outer end of the accumulation region 16 in the Y-axis direction. Therefore, the electric field strength increases at the outer end of the accumulation region 16 in the Y-axis direction. By making the length W longer than the length L, the position where the current density increases due to current concentration (end 53) and the position where the electric field strength increases due to electric field concentration (the outer end of the accumulation region 16 in the Y-axis direction) can be sufficiently separated. This makes it possible to avoid avalanche breakdown due to mutual amplification of current concentration and electric field concentration, and to increase the reverse recovery withstand capability of the diode section 80.

[0094] In still another example of this embodiment, the outer end of the accumulation region 16 in the Y-axis direction may be provided inside the boundary between the collector region 22 and the cathode region 82. In other words, the boundary between the collector region 22 and the cathode region 82 may be located outside the outer end of the accumulation region 16 in the Y-axis direction. However, in this case as well, the boundary between the collector region 22 and the cathode region 82 is located inside the end 53 of the contact hole 54 in the Y-axis direction.

[0095] In the present example, the outer circumferential end in the Y-axis direction of the lifetime killer region 19 may be located on the outer circumferential side (negative Y-axis direction) of the contact hole 55 of the gate wiring 51. In addition, the outer circumferential end in the Y-axis direction of the lifetime killer region 19 may be located on the outer circumferential side of the outer circumferential end of the gate wiring 51. The length L2 from the outer end of the accumulation region 16 in the Y-axis direction to the outer end of the gate wiring 51 in the Y-axis direction may be longer than the length L3 from the outer end of the gate wiring 51 in the Y-axis direction to the outer end of the lifetime killer region 19 in the Y-axis direction.

[0096] In this example, the outer peripheral end of the lifetime killer region 19 in the Y-axis direction may be located outside (outer peripheral side) of the outer (outer peripheral side) end of the contact hole 54 of the diode section 80 in the Y-axis direction. The outer peripheral end of the lifetime killer region 19 in the Y-axis direction may be located outside the outer end of the contact region 15 including the outer (outer peripheral side) end of the contact hole 54 in the Y-axis direction. The outer peripheral end of the lifetime killer region 19 in the Y-axis direction may be located outside the boundary between the base region 14 and the well region 17. The outer peripheral end of the lifetime killer region 19 in the Y-axis direction may be located on the outer peripheral side (Y-axis negative direction) of the contact hole of the gate wiring 51. Also, the outer peripheral end of the lifetime killer region 19 in the Y-axis direction may be located on the outer peripheral side of the outer peripheral end of the gate wiring 51.

[0097] The outer circumferential end of the lifetime killer region 19 in the Y-axis direction may be located inside the outer circumferential end (not shown) of the well region 17. As a result, the accumulated charge stored outside the contact hole 54 of the diode section 80 can be reduced, and the reverse recovery withstand capability of the semiconductor device 200 can be improved.

[0098] FIG. 9 is a partial enlarged view of the accumulation region 16 near the contact region 15 in FIG. 8. The accumulation region 16 in this example has a flat region 62 and an end region 64. The flat region 62 is located at least above the cathode region 82 and has a predetermined depth. In contrast, the end region 64 is located above the collector region 22 and becomes shallower toward the outside in the Y-axis direction. The end region 64 is located outside the flat region 62. The end region 64 in this example is provided at the same position as the flat region 62 or shallower than the flat region 62. The tip of the end region 64 does not need to contact the drift region 18. The tip of the end region 64 may be provided at a position shallower than the middle of the base region 14 in the Z-axis direction. The shape of the end region 64 is caused by, for example, resist sagging, which will be described later.

[0099] The accumulation region 16 of this example can be formed by using a mask described later. The shape of the end region 64 of the accumulation region 16 can be controlled by adjusting the shape of the mask. For example, the baking temperature, baking time, mask thickness, or mask material may be adjusted. Since the channel of the IGBT in the transistor section 70 is formed directly below the emitter region 12, no problem occurs in the operation of the semiconductor device 200 even if the end region 64 of this example is formed directly below the contact region 15 located at the outermost position in the Y-axis direction.

[0100] Fig. 10 is a diagram for explaining mask sagging when forming the accumulation region 16. Fig. 10 is a diagram in which a mask 110 having an excess portion 112 is added to Fig. 8. Since the parts other than the mask 110 are the same as Fig. 8, a duplicated description will be omitted.

[0101] The mask 110 is used in a step of implanting impurities into regions corresponding to the accumulation regions 16. The mask 110 is arranged so as to cover regions where the accumulation regions 16 are not to be formed. When the impurities are ion-implanted, the accumulation regions 16 are not formed in the regions covered by the mask 110, and the accumulation regions 16 are formed in the regions not covered by the mask 110. The mask 110 may be formed by applying a resist or the like and patterning it into a predetermined shape.

[0102] It is preferable that the end of the mask 110 is formed perpendicular to the upper surface of the semiconductor substrate 10. However, in reality, resist sagging may occur on the mask 110, forming an excess portion 112. When the excess portion 112 is formed, the accumulation region 16 is not formed at a predetermined depth in the mesa portion 94 covered with the excess portion 112. For example, in the mesa portion 94 covered with the excess portion 112, the accumulation region 16 is not formed at all, or is formed shallower than the predetermined depth. Note that, although the flat region 62 and the end region 64 in this example are provided continuously, the flat region 62 and the end region 64 may be provided discontinuously in the depth direction.

[0103] 11 is a top view of a semiconductor device 300 according to the third embodiment. The mesa portion 94 of the diode portion 80 in this example has a high-concentration first-conductivity-type region 84 and a high-concentration second-conductivity-type region 86 between the multiple dummy trench portions 30. The third embodiment differs from the second embodiment in this respect, but may be the same as the second embodiment in other respects.

[0104] The high concentration first conductivity type region 84 may have a doping concentration of the first conductivity type higher than that of the drift region 18. The high concentration first conductivity type region 84 may have an N-type doping concentration similar to that of the emitter region 12. Also, the high concentration first conductivity type region 84 may have a depth similar to that of the emitter region 12. The high concentration first conductivity type region 84 in this example is an N+ type. Also, the high concentration second conductivity type region 86 may have a second conductivity type doping concentration higher than that of the base region 14 of the diode section 80. The high concentration second conductivity type region 86 may have a P-type doping concentration similar to that of the contact region 15. Also, the high concentration second conductivity type region 86 may have a depth similar to that of the contact region 15. The high concentration second conductivity type region 86 in this example is a P+ type.

[0105] In this example, the high concentration first conductivity type region 84 and the high concentration second conductivity type region 86 extend in the extension direction of the trench portion (i.e., the Y-axis direction). In this example, the high concentration first conductivity type region 84 and the high concentration second conductivity type region 86 are located inside the contact region 15 in the extension direction. When base regions 14 are provided at both ends in the Y-axis direction of the diode portion 80 and two contact regions 15 are provided between the base regions 14 at both ends in contact with the base regions 14 at both ends, the high concentration first conductivity type region 84 and the high concentration second conductivity type region 86 may extend continuously between the two contact regions 15.

[0106] In addition, the high concentration first conductivity type region 84 and the high concentration second conductivity type region 86 in this example are adjacent to each other in the arrangement direction of the trench portions (i.e., the X-axis direction). The high concentration first conductivity type region 84 and the high concentration second conductivity type region 86 in this example contact each other directly below the contact hole 54.

[0107] FIG. 12 is a cross-sectional view taken along the line A-A' of FIG. 11. FIG. 12 is a cross-section parallel to the X-Z plane passing through the high-concentration first-conductivity-type region 84 and the high-concentration second-conductivity-type region 86. The upper surfaces of the high-concentration first-conductivity-type region 84 and the high-concentration second-conductivity-type region 86 may coincide with the surface of the semiconductor substrate 10. The high-concentration first-conductivity-type region 84 and the high-concentration second-conductivity-type region 86 are connected to the emitter electrode 52 via the contact hole 54. The bottom of the high-concentration first-conductivity-type region 84 may coincide with the bottoms of the emitter region 12 and the contact region 15 of the transistor section 70. The bottom of the high-concentration second-conductivity-type region 86 may be deeper than the bottom of the high-concentration first-conductivity-type region 84. However, the bottom of the high-concentration second-conductivity-type region 86 may be shallower than the accumulation region 16.

[0108] In this example, the accumulation region 16 is provided in both the transistor section 70 and the diode section 80. This makes it possible to solve the problems that arise when the accumulation region 16 is provided only in the transistor section 70, that is, the following problems (1) to (3) caused by mask sagging: (1) fluctuations in the threshold voltage (Vth) of the transistor section 70, (2) variations in the saturation current of the transistor section 70, and (3) current flowing from the transistor section 70 into the diode section 80, which causes the forward voltage (Vf) of the diode section 80 to steadily decrease.

[0109] Additionally, in this example, by providing the high-concentration first-conductivity-type region 84 and the high-concentration second-conductivity-type region 86, the forward voltage (Vf) can be reduced compared to the second embodiment when a large current flows through the diode section 80. In other words, when a large current flows through the diode section 80, the high-concentration holes derived from the high-concentration second-conductivity-type region 86 contribute to the conduction of the diode, so that the forward voltage (Vf) can be reduced only when a large current is conducted.

[0110] 13 is a top view of a semiconductor device 400 in the fourth embodiment. The fourth embodiment differs from the third embodiment in the arrangement of the high-concentration first-conductivity type region 84 and the high-concentration second-conductivity type region 86. The high-concentration first-conductivity type region 84 and the high-concentration second-conductivity type region 86 in this example extend in the arrangement direction and are adjacent to each other in the extension direction. In this example, the high-concentration first-conductivity type region 84 and the high-concentration second-conductivity type region 86 are alternately provided in the extension direction. Note that, in this example as well, the upper surfaces of the high-concentration first-conductivity type region 84 and the high-concentration second-conductivity type region 86 coincide with the surface of the semiconductor substrate 10, and the bottom of the high-concentration second-conductivity type region 86 is deeper than the bottom of the high-concentration first-conductivity type region 84.

[0111] Fig. 14 is a cross-sectional view taken along line AA' of Fig. 13. Fig. 14 is a cross-section parallel to the XZ plane, passing through the high-concentration first conductivity type region 84. In this example as well, the same advantageous effects as in the third embodiment can be obtained.

[0112] Fig. 15A is a cross-sectional view taken along line A-A' in the first comparative example. The first comparative example is an example in which an accumulation region 16 is provided only in a portion of the transistor section 70. Fig. 15A shows an ideal shape of a mask 210 used when an accumulation region 16 is provided only in a portion of the transistor section 70. However, in reality, the steep edge of the mask 210 located above the transistor section 70 may droop.

[0113] FIG. 15B is a cross-sectional view taken along line A-A' in the second comparative example. The second comparative example is also an example in which an accumulation region 16 is provided only in a part of the transistor section 70. However, the mask 210 in FIG. 15B has an excess portion 212 that occurs after a certain time has passed in addition to the ideal shape immediately after formation. The above-mentioned mask sagging corresponds to the excess portion 212. When the thickness of the mask 210 in the Z-axis direction is, for example, 5 μm, the length of the excess portion 212 in the X-axis direction is, for example, 5.8 μm.

[0114] Due to the mask sagging, the above problems (1) to (3) occur. For example, in region C, the accumulation region 16 near the gate trench portion 40 is not provided at a predetermined depth position, which causes the above problems (1) and (2). Also, for example, in region D, the accumulation region 16 is not formed, which causes the above problem (3). In contrast, according to the second to fourth embodiments, the accumulation region 16 is provided in both the transistor portion 70 and the diode portion 80, so that the above problems (1) to (3) can be solved.

[0115] Fig. 16 is a top view showing a corner of the diode portion 80 adjacent to the transistor portion 70. Note that Fig. 16 is not a top view of the periphery of the end of the semiconductor substrate 10, but a top view of a region closer to the center of the semiconductor substrate 10 than the end. The structure shown in this example may be applied to the semiconductor devices 100 to 400.

[0116] The semiconductor device may have a plurality of transistor sections 70 and a plurality of diode sections 80. Ends of the diode section 80 in the X-axis direction and the Y-axis direction may be adjacent to the transistor section 70, and a corner of the diode section 80 may also be adjacent to the transistor section 70. In this example, at least the corner of the diode section 80 and two sides of the diode section 80 that constitute the corner are surrounded by the plurality of transistor sections 70.

[0117] When the semiconductor substrate 10 is viewed from above, the gate trench portion 40 may be provided in a lattice pattern. The gate trench portion 40 may be continuous across multiple transistor portions 70. The gate trench portion 40 of this example has a first portion 47 extending in the Y-axis direction and a second portion 48 extending in the X-axis direction. The second portion 48 in the gate trench portion 40 may be connected to multiple first portions 47. A mesa portion 94 is located between the first portion 47 of the gate trench portion 40 extending in the Y-axis direction and the dummy trench portion 30 in the transistor portion 70.

[0118] The diode section 80 of the present example includes a comb-tooth dummy trench section 30. The comb-tooth dummy trench section 30 may have a first portion 37 extending in the Y-axis direction and a second portion 38 extending in the X-axis direction. In the diode section 80, the first portions 37 may be provided spaced apart from each other in the X-axis direction. In the diode section 80, the second portions 38 may be connected to the ends of the first portions 37 in the positive direction of the Y-axis. In the diode section 80 of the present example, a P+ type contact region 15 is provided near the connection portion between the first portion 37 and the second portion 38 of the dummy trench section 30.

[0119] A connection portion between the first portion 37 and the second portion 38 of the dummy trench portion 30 in the diode portion 80 may be surrounded by the base region 14 in the XY plane on the upper surface of the semiconductor substrate 10. Furthermore, the connection portion may be surrounded by an intersection portion between the first portion 47 and the second portion 48 of the gate trench portion 40. This makes it possible to reduce the electric field strength at the connection portion.

[0120] The diode section 80 may be adjacent to the transistor section 70-3 in the positive direction of the Y axis with the gate metal layer 50 sandwiched therebetween. The diode section 80 may be adjacent to the transistor section 70-3 in the positive direction of the Y axis with the second portion 48 of the gate trench section 40 sandwiched therebetween. The second portion 48 of the gate trench section 40 may be surrounded by a P+ type well region 17. The boundary between the diode section 80 and the transistor section 70-3 in the Y axis direction may be located in the well region 17 surrounding the second portion 48 of the gate trench section 40.

[0121] The boundary between the diode portion 80 and the transistor portion 70-1 may be located in the first portion 37 of the dummy trench portion 30. In this example, the boundary between the diode portion 80 and the transistor portion 70-1 may extend parallel to the Y-axis direction in the first portion 37 of the dummy trench portion 30. The boundary between the diode portion 80 and the transistor portion 70-1 may be located in the X-axis direction coincident with the boundary between the transistor portion 70-2 and the transistor portion 70-3 in the X-axis direction.

[0122] The mesa portion 94 between the transistor portion 70-1 and the diode portion 80, in which the contact region 15 is formed so as to entirely surround the contact hole 54, may be defined as the first boundary portion 72. The region including the second portion 48 of the gate trench portion 40 from the end of the contact region 15 of the transistor portion 70-1 adjacent to the second portion 48 of the gate trench portion 40 to the end of the contact region 15 of the transistor portion 70-2 adjacent to the second portion 48 of the gate trench portion 40 may be defined as the second boundary portion 74. Of the contact region 15 of the transistor section 70-3, the region including the second portion 48 of the gate trench portion 40 from the end adjacent to the second portion 48 of the gate trench portion 40 to the second portion 38 of the dummy trench portion 30 of the diode section 80 may be defined as the third boundary portion 76.

[0123] The second boundary 74 and the third boundary 76 may be in contact with each other in the X-axis direction. The first boundary 72 may intersect with the second boundary 74 or the third boundary 76. The range in which the first portion 37 and the second portion 38 of the dummy trench portion 30 are provided may be at least the diode portion 80. The second boundary 74 and the third boundary 76 may be the second portion 48 of the gate trench portion 40 itself. In this case, the transistor portion 70-3 and the diode portion 80 may each extend up to the sidewall of the second portion 48 of the gate trench portion 40.

[0124] The width in the X-axis direction of the first portion 47 of the gate trench portion 40 of the transistor portion 70 and the width in the X-axis direction of the dummy trench portion 30 may be the same as the width in the Y-axis direction of the second portion 48 of the gate trench portion 40. The width in the X-axis direction of the first portion 37 of the dummy trench portion 30 of the diode portion 80 may be the same as the width in the Y-axis direction of the second portion 38 of the dummy trench portion 30.

[0125] In the transistor portion 70, the width in the X-axis direction of the first portion 47 of the gate trench portion 40, the width in the X-axis direction of the dummy trench portion 30, and the width in the Y-axis direction of the second portion 48 of the gate trench portion 40 may be the same as the width in the X-axis direction of the first portion 37 of the dummy trench portion 30 and the width in the Y-axis direction of the second portion 38 of the dummy trench portion 30 in the diode portion 80. The width in the X-axis direction of the mesa portion 94 of the transistor portion 70 may be the same as the width in the X-axis direction of the mesa portion 94 of the diode portion 80.

[0126] The length from the Y-axis end of the dummy trench portion 30 of the transistor portion 70-2 to the second portion 48 of the gate trench portion 40 may be the same as the length from the Y-axis end of the dummy trench portion 30 to the second portion 48 of the gate trench portion 40 of the transistor portion 70-1 adjacent to the transistor portion 70-2 across the gate trench portion 40. The length from the Y-axis end of the dummy trench portion 30 of the transistor portion 70 to the second portion 48 of the gate trench portion 40 may be the same as or smaller than the width of the mesa portion 94 of the transistor portion 70 in the X-axis direction.

[0127] The width in the Y-axis direction of the mesa portion between the second portion 48 of the gate trench portion 40 and the second portion 38 of the dummy trench portion 30 of the diode portion 80 may be equal to or smaller than the width in the X-axis direction of the mesa portion 94 of the transistor portion 70 or the diode portion 80. As a result, when the gate voltage is off and a power supply voltage is applied between the collector electrode 24 and the emitter electrode 52, the potential distribution at the bottom of the trench portion becomes uniform, and a local increase in the electric field strength at the bottom of the trench portion is suppressed.

[0128] The gate metal layer 50 may be located on the second portion 48 of the gate trench portion 40. The gate metal layer 50 may be in direct contact with the gate conductive portion 44 provided in the second portion 48 of the gate trench portion 40, or may be in contact with the gate conductive portion 44 via a plug. The gate metal layer 50 may have a lower resistance than the gate wiring 51 such as polysilicon doped with impurities. By electrically connecting the low-resistance gate metal layer 50 and the gate conductive portion 44 without the gate wiring 51 such as polysilicon, the delay of the gate signal can be suppressed. Similarly, in this example, the dummy conductive portion 34 of the dummy trench portion 30 is directly connected to the emitter electrode 52 via a contact hole. However, the dummy conductive portion 34 may be in contact with the emitter electrode 52 via a plug provided in the contact hole.

[0129] In another example, the second portion 48 of the gate trench portion 40 and the gate metal layer 50 may be omitted in a portion where the transistor portions 70 are adjacent to each other in the Y-axis direction. For example, a cell structure having an emitter region 12 and a contact region 15 is provided in the boundary region between the transistor portions 70-1 and 70-2. More specifically, in the boundary region between the transistor portions 70-1 and 70-2, the dummy trench portions 30 may be continuously provided in the Y-axis direction, and the emitter regions 12 and the contact regions 15 may be repeatedly provided in the Y-axis direction according to the continuously provided dummy trench portions 30.

[0130] The cathode region 82 may be located more inward than the first portion 37 of the dummy trench portion 30 that is closest to the transistor portion 70-1. The X-axis end of the cathode region 82 in this example is located below the first portion 37 of the dummy trench portion 30 that is second closest to the transistor portion 70-1. The cathode region 82 may be located more inward than the second portion 48 of the gate trench portion 40. The Y-axis end of the cathode region 82 in this example is located in the negative Y-axis direction more than the second portion 38 of the dummy trench portion 30 in the diode portion 80.

[0131] The semiconductor substrate 10 may have a lifetime killer region 19. The lifetime killer region 19 may be provided in the transistor portion 70 in addition to the diode portion 80. In this example, the lifetime killer region 19 is provided in parts of the transistor portions 70-1, 70-2, and 70-3 adjacent to the diode portion 80.

[0132] The length of the lifetime killer region 19 extending beyond the third boundary 76 to the transistor portion 70-3 may be equal to or longer than the length of the lifetime killer region 19 extending beyond the first boundary 72 to the transistor portion 70-1. This makes it possible to prevent the accumulated charge that accumulates in the depth direction of the semiconductor substrate 10 at the third boundary 76 from concentrating on the side end of the third boundary 76 in the contact hole 54 of the diode portion 80 when the diode portion 80 performs reverse recovery operation.

[0133] The length of the lifetime killer region 19 extending beyond the first boundary 72 to the transistor portion 70-1 may be equal to or longer than the length of the lifetime killer region 19 extending beyond the third boundary 76 to the transistor portion 70-3. When the diode portion 80 performs a reverse recovery operation, the accumulated charge parasitically injected and accumulated from the transistor portion 70-1 can be prevented from concentrating on the contact hole 54 of the mesa portion 94 having the cathode region 82 on its lower surface and located closest to the first boundary 72 among the contact holes 54 of the diode portion 80. The semiconductor substrate 10 may have an accumulation region 16. The accumulation region 16 in this example is provided in the transistor portions 70-1, 70-2, 70-3 and the diode portion 80.

[0134] 17 is a cross-sectional view taken along the line a-a' in FIG. 16. The a-a' cross-sectional view is parallel to the Y-Z plane. The line a-a' passes through the contact hole 54 provided on the mesa portion 94 of the transistor portion 70-3 and the contact hole 54 provided on the mesa portion 94 of the diode portion 80. The line a-a' also passes through the second portion 48 of the gate trench portion 40 and the second portion 38 of the dummy trench portion 30.

[0135] The accumulation region 16 in this example is provided discontinuously in the second portion 48 of the gate trench portion 40. However, in other examples, the accumulation region 16 may be continuous in the second portion 48 of the gate trench portion 40, as shown by the dashed line in Fig. 17. In other words, the accumulation region 16 may be provided in the form of one surface in the entire transistor portion 70 and the diode portion 80.

[0136] The accumulation region 16 of the diode section 80 may extend beyond the dummy trench section 30 toward the transistor section 70-3 in the Y-axis direction. Even if the accumulation region 16 is extended, it may be considered that there is no effect on the gate threshold voltage of the transistor section 70 compared to the case where the accumulation region 16 is not extended. In this example, the accumulation region 16 of the diode section 80 extends beyond the dummy trench section 30 in the Y-axis direction and terminates just before the gate trench section 40.

[0137] In the transistor section 70-3 of this example, the length from the end 119 of the lifetime killer region 19 in the positive Y-axis direction to the end of the accumulation region 16 in the negative Y-axis direction is defined as Ly. In addition, in the transistor section 70-3, the length from the end 53 of the contact hole 54 located at the outermost position in the Y-axis direction to the outer end of the accumulation region 16 in the Y-axis direction is defined as W. In this example, the length Ly is greater than the length W. However, the length W may be greater than the length Ly.

[0138] In this example, the gate conductive portion 44 of the gate trench portion 40 and the gate metal layer 50 are connected via a contact hole 154 provided in the interlayer insulating film 26. Also, in this example, the dummy conductive portion 34 of the dummy trench portion 30 and the emitter electrode 52 are connected via a contact hole 156 provided in the interlayer insulating film 26.

[0139] In this example, the length from the end of the contact hole 156 of the diode section 80 in the positive direction of the Y axis to the boundary between the cathode region 82 and the collector region 22 is set to Lc2ny. That is, in this example, the boundary between the cathode region 82 and the collector region 22 is set back by Lc2ny from the end of the contact hole 156 of the diode section 80 in the positive direction of the Y axis. The length Lc2ny may be greater than the thickness of the semiconductor substrate 10 in the Z axis direction (the length from the upper surface to the lower surface). In this example, the length Lc2ny is 50 μm. Note that the lengths A and B are the same as those described in FIG. 3.

[0140] The lifetime killer region 19 may be provided in at least the diode portion 80. The lifetime killer region 19 may be provided in the diode portion 80 and a part of the transistor portion 70. The lifetime killer region 19 in this example extends in the positive direction of the Y-axis further than the end in the negative direction of the Y-axis of the contact hole 54 of the transistor portion 70-3. An end 119-1 in the positive direction of the Y-axis of the lifetime killer region 19 in this example is located below the emitter region 12 located furthest in the negative direction of the Y-axis in the transistor portion 70-3.

[0141] In another example, the end 119-2 in the positive direction of the Y-axis of the lifetime killer region 19 may be located below a region located between the end in the negative direction of the Y-axis of the contact hole 54 of the transistor portion 70-3 and the second portion 48 of the gate trench portion 40. In yet another example, the end 119-3 in the positive direction of the Y-axis of the lifetime killer region 19 may be located below a region located between the second portion 48 of the gate trench portion 40 and the second portion 38 of the dummy trench portion 30.

[0142] In this example, the length between the end 119 of the lifetime killer region 19 in the positive direction of the Y axis and the end of the contact hole 54 of the transistor portion 70-3 in the negative direction of the Y axis is designated as Lc1k. The length Lc1k-1 may correspond to the end 119-1. Similarly, the length Lc1k-2 may correspond to the end 119-2, and the length Lc1k-3 may correspond to the end 119-3.

[0143] The length Lc1k-1 may be longer than the length Lc1c2 from the end in the negative Y-axis direction of the contact hole 54 of the transistor section 70-3 to the end in the positive Y-axis direction of the contact hole 156 of the diode section 80. Due to this configuration, the lifetime killer region 19 can prevent excess holes from flowing toward the cathode region 82 when the diode section 80 operates.

[0144] The length Lc1k-1 may be shorter than the length Ly. Even in this case, the lifetime killer region 19 can prevent excess holes from flowing toward the cathode region 82 through a region where the accumulation region 16 is not provided when the diode section 80 operates. The length Lc1k-1 may be shorter than the length Lc2ny. Even in this case, the lifetime killer region 19 can achieve the same effect.

[0145] In this example, Lkny is the length in the Y-axis direction from end 119 of lifetime killer region 19 in the Y-axis positive direction to the boundary between cathode region 82 and collector region 22. In this example, the length corresponding to end 119-1 is Lkny-1, the length corresponding to end 119-2 is Lkny-2, and the length corresponding to end 119-3 is Lkny-3.

[0146] Lkny-1, Lkny-2, and Lkny-3 may be longer than the Z-axis direction thickness of the semiconductor substrate 10. The lifetime killer region 19 having this configuration can prevent excess holes from flowing toward the cathode region 82 when the diode section 80 is in operation.

[0147] In addition, as shown by the dashed line, in another example, a P+ type well region 17 may be provided to surround the second portion 48 of the gate trench portion 40. In this case, the well region 17 may cover the sides and bottom of the second portion 48 of the gate trench portion 40. The well region 17 may extend in the X-axis direction to cover the entire second portion 48 of the gate trench portion 40. This makes it possible to prevent an increase in the electric field strength at the bottom of the second portion 48 of the gate trench portion 40.

[0148] The end of the well region 17 in the positive direction along the Y axis may be spaced apart from the end 53 of the contact hole 54 of the transistor portion 70-3. Also, the end of the well region 17 in the negative direction along the Y axis may be located closer to the transistor portion 70-3 than the contact hole 156 that is closest to the transistor portion 70-3 in the diode portion 80. The end of the well region 17 in the negative direction along the Y axis may be located between the second portion 48 of the gate trench portion 40 and the second portion 38 of the dummy trench portion 30 of the diode portion 80.

[0149] 18 is a diagram showing the concentration distribution of recombination centers in the lifetime killer region 19. The lifetime killer region 19 of this example has a peak of the concentration distribution of recombination centers in the depth direction. The concentration distribution of recombination centers in the lifetime killer region 19 of this example has a tail region that reaches the upper surface of the semiconductor substrate 10. The concentration distribution of recombination centers in the lifetime killer region 19 may have a tail region that reaches the lower surface of the semiconductor substrate 10 instead of the tail region that reaches the upper surface.

[0150] The recombination centers may be formed by point defects (vacancies, divacancies, dangling bonds, etc.) formed inside the semiconductor substrate 10 by the introduction of light ions such as helium or metals such as platinum, as described above. Furthermore, the concentration of the recombination centers may be the concentration of point defects, or may be the concentration of helium or metal. 18 may include a position where the concentration of recombination centers is maximum (peak). The width of the lifetime killer region 19 in the depth direction may be the full width at half maximum of the peak concentration of the introduced helium, point defects, or recombination centers. The concentration distribution of the recombination centers may have a mountain-shaped distribution shape including a peak.

[0151] 19 is a cross-sectional view taken along the line b-b' in FIG. 16. The cross-sectional view taken along the line b-b' is parallel to the XZ plane. The line b-b' passes through the emitter regions 12 in the transistor section 70-1 and the diode section 80. In this example, the length in the X-axis direction from the end 120 in the positive X-axis direction of the lifetime killer region 19 to the boundary between the cathode region 82 and the collector region 22 is defined as Lknx. The length Lknx may be longer than the thickness of the semiconductor substrate 10.

[0152] 19, the mesa portion 94 between the dummy trench portions 30 of the diode portion 80 is provided with the base region 14, but is not provided with the emitter region 12 and the contact region 15. The collector region 22 may extend from a region below the emitter region 12 located at the end in the negative direction of the X-axis toward the diode portion 80. The collector region 22 in this example extends to a region below the mesa portion 94 where the base region 14 is provided, but is not provided with the emitter region 12 and the contact region 15. The collector region 22 may extend across a plurality of mesa portions in the diode portion 80.

[0153] In this example, the length from the end in the positive direction of the X-axis of the contact hole 156 on the dummy trench portion 30 located at the end in the positive direction of the X-axis of the diode portion 80 to the boundary between the cathode region 82 and the collector region 22 is defined as Lc2nx. The length Lc2nx may be greater than the thickness in the Z-axis direction of the semiconductor substrate 10 and may be shorter than the length Lknx. In this example, the length Lc2nx is 50 μm.

[0154] FIG. 20 is a diagram showing a modified example of FIG. 16. In this example, the comb-shaped dummy trench portion 30 may have a first portion 37 extending in the X-axis direction and a second portion 38 extending in the Y-axis direction. That is, in the diode portion 80 of this example, a plurality of first portions 37 are provided spaced apart in the Y-axis direction. In addition, in the diode portion 80, the second portion 38 is connected to the ends of the plurality of first portions 37 in the X-axis positive direction. In this example, the first portion 47 of the gate trench portion 40 and the first portion 37 of the dummy trench portion 30 are perpendicular to each other. This point is different from the example of FIG. 16. The cathode region 82 may be located inside (in the X-axis negative direction) the second portion 38 of the dummy trench portion 30 of the diode portion 80. In addition, the cathode region 82 may be located inside (in the X-axis negative direction) the end of the contact hole 54 in the X-axis positive direction.

[0155] The mesa portion 94 between the transistor portion 70-1 and the second portion 38 of the dummy trench portion 30 of the diode portion 80, in which the contact region 15 is formed so as to surround the entire contact hole 54, may be the first boundary portion 72. The region including the second portion 48 of the gate trench portion 40 from the end of the contact region 15 of the transistor portion 70-1 adjacent to the second portion 48 of the gate trench portion 40 to the end of the contact region 15 of the transistor portion 70-2 adjacent to the second portion 48 of the gate trench portion 40 may be the second boundary portion 74. The region including the second portion 48 of the gate trench portion 40 from the end of the contact region 15 of the transistor portion 70-3 adjacent to the second portion 48 of the gate trench portion 40 to the first portion 37 located furthest in the Y-axis positive direction in the dummy trench portion 30 of the diode portion 80 may be the third boundary portion 76.

[0156] The second boundary 74 and the third boundary 76 may be in contact with each other in the X-axis direction. The first boundary 72 may intersect with the second boundary 74 or the third boundary 76. The width in the Y-axis direction of the mesa portion 94 between the second portion 48 of the gate trench portion 40 and the first portion 37 of the dummy trench portion 30 of the diode portion 80 adjacent to the second portion 48 and located furthest in the Y-axis positive direction may be equal to or smaller than the width in the X-axis direction of the mesa portion 94 of the transistor portion 70 or the diode portion 80. This makes the potential distribution at the bottom of the trench portion uniform when the gate voltage is off and a power supply voltage is applied between the collector electrode 24 and the emitter electrode 52, thereby suppressing a local increase in the electric field strength at the bottom of the trench portion.

[0157] FIG. 21 is a cross-sectional view taken along the line c-c' in FIG. 20. The cross-sectional view taken along the line c-c' is parallel to the X-Z plane. The line c-c' passes through the emitter regions 12 in the transistor section 70-1, the second portion 38 of the dummy trench portion 30 in contact with the first boundary portion 72, and the contact hole 54 on the mesa portion 94 located between the two first portions 37 of the dummy trench portion 30 in the diode section 80. In this example, the length in the Y-axis direction from the end 120 in the X-axis positive direction of the lifetime killer region 19 to the boundary between the cathode region 82 and the collector region 22 is defined as Lknx. The length Lknx may be longer than the thickness of the semiconductor substrate 10.

[0158] The collector region 22 may extend from a region below the emitter region 12 located at the end in the negative direction of the X-axis toward the diode section 80. The collector region 22 in this example extends beyond the second portion 38 of the dummy trench portion 30 in the diode section 80 to below a region in the diode section 80 where the base region 14 is provided but the emitter region 12 and the contact region 15 are not provided.

[0159] In this example, the length from the end in the positive direction of the X-axis of the contact hole 156 on the dummy trench portion 30 located at the end in the positive direction of the X-axis of the diode portion 80 to the boundary between the cathode region 82 and the collector region 22 is defined as Lc2nx. The length Lc2nx may be greater than the thickness in the Z-axis direction of the semiconductor substrate 10 and may be shorter than the length Lknx. In this example, the length Lc2nx is 50 μm.

[0160] Fig. 22 is a d-d' cross-sectional view of Fig. 20. The d-d' cross-sectional view is parallel to the YZ plane. The d-d' cross-sectional view passes through the contact hole 54 and the second portion 48 of the gate trench portion 40 provided on the mesa portion 94 of the transistor portion 70-3, and the first portions 37 of the contact holes 54 and the first portions 37 of the dummy trench portions 30 provided on the mesa portion 94 of the diode portion 80.

[0161] The accumulation region 16, the lengths Ly, W, and Lc2ny, and the lifetime killer region 19 may be the same as the accumulation region 16 in the description of FIG. 17. As in the description of FIG. 17, the lengths Lc1k-1, Lc1k-2, and Lc1k-3 allow the lifetime killer region 19 to prevent excess holes from flowing toward the cathode region 82 during operation of the diode portion 80. Note that, as described in FIG. 17, in another example, a P+ type well region 17 may be provided to surround the second portion 48 of the gate trench portion 40.

[0162] Although the present invention has been described above using the embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It is clear to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the description of the claims that such modifications and improvements can also be included in the technical scope of the present invention. [Explanation of symbols]

[0163] 10 ·· semiconductor substrate, 12 ·· emitter region, 14 ·· base region, 15 ·· contact region, 16 ·· accumulation region, 17 ·· well region, 18 ·· drift region, 19 ·· lifetime killer region, 20 ·· buffer region, 22 ·· collector region, 24 ·· collector electrode, 26 ·· interlayer insulating film, 30 ·· dummy trench portion, 32 ·· dummy insulating film, 34 ·· dummy conductive portion, 36 ·· dummy trench, 37 ·· first portion, 38 ·· second portion, 40 ·· gate trench portion, 41 ·· opposing portion, 42 ·· gate insulating film, 43 ·· protruding portion, 44 ·· gate conductive portion, 46 ·· gate trench, 47 ·· first portion, 48 ·· second portion, 50 ·· gate metal layer, 51 · 5. A semiconductor device comprising: a gate wiring, a first electrode, a first boundary portion, a second boundary portion, a third boundary portion, a diode portion, a cathode portion, a first conductive type region, a second conductive type region ...

Claims

1. A semiconductor device including a transistor portion and a diode portion provided on a semiconductor substrate having an upper surface and a lower surface parallel to a first axial direction and a second axial direction, a first trench portion provided on the upper surface and having a straight portion extending in the first axial direction; a cathode region of a first conductivity type provided on the lower surface; a second trench portion provided on the upper surface and having an outer portion continuously provided from an outer side of an end portion of the cathode region in the first axial direction to an outer side of an end portion of the cathode region in the second axial direction; Equipped with the transistor portion includes the first trench portion, The second trench portion has a plurality of inner portions extending in the first axial direction or the second axial direction and connected to the outer portion. Semiconductor device.

2. A semiconductor device including a transistor portion and a diode portion provided on a semiconductor substrate having an upper surface and a lower surface parallel to a first axial direction and a second axial direction, a first trench portion provided on the upper surface and having a straight portion extending in the first axial direction; a cathode region of a first conductivity type provided on the lower surface; a second trench portion provided on the upper surface and having an outer portion continuously provided from an outer side of an end portion of the cathode region in the first axial direction to an outer side of an end portion of the cathode region in the second axial direction; Equipped with the transistor portion includes the first trench portion, The outer portion is a portion extending in the first axial direction; a portion extending in the second axial direction; a connection portion between a portion extending in the first axial direction and a portion extending in the second axial direction; have Semiconductor device.

3. the portion of the outer portion extending in the first axial direction is disposed outwardly of an end of the cathode region in the second axial direction; The portion of the outer portion extending in the second axial direction is disposed outboard of an end of the cathode region in the first axial direction. The semiconductor device according to claim 2 .

4. The portion of the outer portion extending in the first axial direction and the portion of the outer portion extending in the second axial direction are connected outside the cathode region. The semiconductor device according to claim 3 .

5. A semiconductor device including a transistor portion and a diode portion provided on a semiconductor substrate having an upper surface and a lower surface parallel to a first axial direction and a second axial direction, a first trench portion provided on the upper surface and having a straight portion extending in the first axial direction; a cathode region of a first conductivity type provided on the lower surface; a second trench portion provided on the upper surface and having an outer portion continuously provided from an outer side of an end portion of the cathode region in the first axial direction to an outer side of an end portion of the cathode region in the second axial direction; Equipped with the transistor portion includes the first trench portion, The first trench portion has a first portion which is the linear portion and a second portion which extends in the second axial direction. Semiconductor device.

6. A semiconductor device including a transistor portion and a diode portion provided on a semiconductor substrate having an upper surface and a lower surface parallel to a first axial direction and a second axial direction, a first trench portion provided on the upper surface and having a straight portion extending in the first axial direction; a cathode region of a first conductivity type provided on the lower surface; a second trench portion provided on the upper surface and having an outer portion continuously provided from an outer side of an end portion of the cathode region in the first axial direction to an outer side of an end portion of the cathode region in the second axial direction; Equipped with the transistor portion includes the first trench portion, the first trench portion of the transistor portion has a first portion which is the straight portion and a second portion which extends in the second axial direction, the outer portion has a connection portion between a portion extending in the first axial direction and a portion extending in the second axial direction, The connection portion is surrounded by the first portion and the second portion. Semiconductor device.

7. A semiconductor device including a transistor portion and a diode portion provided on a semiconductor substrate having an upper surface and a lower surface parallel to a first axial direction and a second axial direction, a first trench portion provided on the upper surface and having a straight portion extending in the first axial direction; a cathode region of a first conductivity type provided on the lower surface; a second trench portion provided on the upper surface and having an outer portion continuously provided from an outer side of an end portion of the cathode region in the first axial direction to an outer side of an end portion of the cathode region in the second axial direction; Equipped with the transistor portion includes the first trench portion, The straight portion of the first trench portion of the transistor portion is provided in a range wider than the outer portion in the first axial direction. Semiconductor device.

8. A semiconductor device including a transistor portion and a diode portion provided on a semiconductor substrate having an upper surface and a lower surface parallel to a first axial direction and a second axial direction, a first trench portion provided on the upper surface and having a straight portion extending in the first axial direction; a cathode region of a first conductivity type provided on the lower surface; a second trench portion provided on the upper surface and having an outer portion continuously provided from an outer side of an end portion of the cathode region in the first axial direction to an outer side of an end portion of the cathode region in the second axial direction; a metal electrode formed of a metal material and disposed above the upper surface; an interlayer insulating film provided between the upper surface and the metal electrode; Equipped with the transistor portion includes the first trench portion, a plurality of contact holes provided in the interlayer insulating film along the first axis direction are connected to the semiconductor substrate on the inner side of the outer portion; An end of the contact hole in the first axial direction is located outside an end of the cathode region in the first axial direction. Semiconductor device.

9. A semiconductor device including a transistor portion and a diode portion provided on a semiconductor substrate having an upper surface and a lower surface parallel to a first axial direction and a second axial direction, a first trench portion provided on the upper surface and having a straight portion extending in the first axial direction; a cathode region of a first conductivity type provided on the lower surface; a second trench portion provided on the upper surface and having an outer portion continuously extending from a position outside an end portion of the cathode region in the first axial direction and facing the cathode region in the first axial direction to a position outside an end portion of the cathode region in the second axial direction and facing the cathode region in the second axial direction; Equipped with The transistor portion includes the first trench portion. Semiconductor device.

10. A semiconductor device including a transistor portion and a diode portion provided on a semiconductor substrate having an upper surface and a lower surface parallel to a first axis direction and a second axis direction, a first trench portion provided on the upper surface and having a first portion that is a straight portion extending in the first axis direction and a second portion that extends in the second axis direction; a second trench portion provided on the upper surface and having a connection portion between a portion extending in the first axial direction and a portion extending in the second axial direction; a well region of a second conductivity type covering a sidewall and a bottom of the second portion; Equipped with the transistor portion includes the first trench portion, the connection portion is surrounded by the first portion and the second portion, The well region is not in contact with the second trench portion. Semiconductor device.

11. A semiconductor device including a transistor portion and a diode portion provided on a semiconductor substrate having an upper surface and a lower surface parallel to a first axial direction and a second axial direction, a first trench portion provided on the upper surface and having a first portion that is a straight portion extending in the first axis direction and a second portion that extends in the second axis direction; a second trench portion provided on the upper surface and having a connection portion between a portion extending in the first axial direction and a portion extending in the second axial direction; Equipped with the transistor portion includes the first trench portion, the connection portion is surrounded by the first portion and the second portion, a cathode region of a first conductivity type provided on the lower surface and located inside the first trench portion; The cathode region does not overlap the first trench portion in a top view. Semiconductor device.

12. The cathode region is surrounded by the second trench portion having the connection portion. The semiconductor device according to claim 11.

13. The cathode region is provided on the inside of the connection portion. The semiconductor device according to claim 12.

14. the diode portion includes the second trench portion, The second trench portion is a dummy trench portion. The semiconductor device according to claim 1 .

15. A plurality of the diode sections are provided, and at least a corner of each of the diode sections and two sides that define the corner are surrounded by the transistor section. The semiconductor device according to claim 1 .

16. The first trench portion is a gate trench portion. The semiconductor device according to claim 1 .

17. When viewed from above, the cathode region and the outer portion do not overlap. The semiconductor device according to claim 1 .

18. At least a part of the outer portion is located at the boundary between the transistor portion and the diode portion. The semiconductor device according to claim 1 .

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