Asymmetrical voltage-resistant TVS diodes and assemblies

Abstract

To provide overvoltage protection devices and resettable fuses.SOLUTION: A protective device 100 of a double sided transient voltage suppression (TVS) diode device includes: a semiconductor substrate 102 having an inner region 104 that has a first polarity; and a first surface region 106 disposed on a first surface 108 of the semiconductor substrate and having a second polarity, opposite the first polarity. The TVS device also include a second surface region 110 having the second polarity and disposed on a second surface 112 of the semiconductor substrate, opposite the first surface. The first surface region has a first dopant concentration, and the second surface region has a second dopant concentration, greater than the first dopant concentration.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] FIELD OF THE DISCLOSURE Embodiments relate to the field of surge protection devices, and more particularly, to overvoltage protection devices and resettable fuses. [Background technology]

[0002] [Description of Related Art] Surge protection devices include overvoltage protection devices used to protect components, equipment or systems from damage caused by overvoltage fault conditions and fuses used to protect components, equipment or systems from excessive current flow. In the field of overvoltage protection devices, diodes such as transient voltage suppressor (TVS) diodes can be used in unidirectional TVS. Unidirectional TVS are best suited to protect circuit nodes where the signal is one-way or always above or below a reference voltage, usually ground voltage.

[0003] In the field of automotive circuits, protection requirements may include different withstand voltage requirements: for example, jump initiation requirements may require that the voltage be maintained below a certain voltage threshold, while reverse polarity protection may require that the voltage not exceed a different voltage threshold.

[0004] It is with respect to these and other considerations that the present disclosure is provided. Summary of the Invention

[0005] Exemplary embodiments are directed to improvements in protection devices. In one embodiment, an asymmetric transient voltage suppression (TVS) device is provided. The asymmetric TVS device may include a semiconductor substrate having an inner region including a first polarity and a first surface region disposed on a first surface of the semiconductor substrate and having a second polarity opposite the first polarity. The asymmetric TVS device may also include a second surface region having a second polarity and disposed on a second surface of the semiconductor substrate opposite the first surface. The first surface region has a first dopant concentration and the second surface region has a second dopant concentration greater than the first dopant concentration.

[0006] In a further embodiment, a method of forming an asymmetric transient voltage suppression (TVS) device is provided. The method may include providing a semiconductor substrate including a first dopant of a first polarity and defining a first surface and a second surface opposite the first surface. The method may also include performing a first oxidation process of the semiconductor substrate, where a first oxide layer occurs on the first surface and a second oxide layer occurs on the second surface. The method may further include removing the first oxide layer from at least a first region of the first surface of the semiconductor substrate and performing a first doping process, where the first doping process produces a first surface region on the first surface including a first concentration of a second dopant of a second polarity opposite the first polarity. The method may additionally include performing a second oxidation process of the semiconductor substrate, where a third oxide layer occurs above the first region on the first surface, and removing the second oxide layer from at least a second region of the second surface. The method may additionally comprise performing a second doping process, the second doping process producing a second surface region on the second surface including a second concentration of a second dopant of a second polarity that is greater than the first concentration.

[0007] In an additional embodiment, an asymmetric transient voltage suppression (TVS) device may include a semiconductor substrate having an inner region including a first polarity. The semiconductor substrate may include a first surface region having a second polarity disposed on a first surface of the semiconductor substrate, and a second surface region having the second polarity disposed on a second surface of the semiconductor substrate opposite the first surface. Thus, the first surface region and the inner region define a first TVS diode including the first polarity and a first breakdown voltage, and the second surface region and the inner region define a second TVS diode including the second polarity and a second breakdown voltage greater than the first breakdown voltage. [Brief description of the drawings]

[0008] [Figure 1] 1 illustrates a side cross-sectional view of a protection device according to various embodiments of the present disclosure.

[0009] [Figure 2A] 4 illustrates exemplary stages in the synthesis of a protection device according to an embodiment of the present disclosure. [Figure 2B] 4 illustrates exemplary stages in the synthesis of a protection device according to an embodiment of the present disclosure. [Figure 2C] 4 illustrates exemplary stages in the synthesis of a protection device according to an embodiment of the present disclosure. [Figure 2D] 4 illustrates exemplary stages in the synthesis of a protection device according to an embodiment of the present disclosure. [Figure 2E] 4 illustrates exemplary stages in the synthesis of a protection device according to an embodiment of the present disclosure. [Figure 2F] 4 illustrates exemplary stages in the synthesis of a protection device according to an embodiment of the present disclosure. [Figure 2G] 4 illustrates exemplary stages in the synthesis of a protection device according to an embodiment of the present disclosure. [Figure 2H] 4 illustrates exemplary stages in the synthesis of a protection device according to an embodiment of the present disclosure. [Figure 2I] 4 illustrates exemplary stages in the synthesis of a protection device according to an embodiment of the present disclosure.

[0010] [Diagram 3]Exemplary pressure resistance data is provided.

[0011] [Figure 4] 1 shows an exemplary process flow.

[0012] [Diagram 5] 1 illustrates the overall structure of an embodiment of a mesa TVS.

[0013] [Figure 6] 1 shows the overall structure of a planar TVS embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] The present embodiments will now be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments are shown. These embodiments should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the embodiments to those skilled in the art. In the drawings, the same reference numerals refer to the same elements throughout.

[0015] In the following description and / or claims, the terms "on", "overlying", "disposed on" and "over" may be used in the following description and claims. "On", "overlying", "disposed on" and "over" may be used to indicate that two or more elements are in direct physical contact with each other. Also, the terms "on", "overlying", "disposed on" and "over" may mean that two or more elements are not in direct contact with each other. For example, "over" may mean that one element is on another element but is not in contact with each other, and may have another element or elements between the two elements. Additionally, the term "and / or" can mean "and," "or," "exclusive or," "one," "some but not all," "either," and / or "both," although the scope of the claimed subject matter is not limited in this respect.

[0016] In various embodiments, protection devices and assemblies are presented for protecting electrical components, systems, or electrical lines, such as communication lines. Various embodiments may include a protection device arranged as a double-sided transient voltage suppression (TVS) diode.

[0017] 5 and 6, according to the present embodiment, a double-sided transient voltage suppression (TVS) diode device may be arranged as a mesa device 500 or a planar device 600. Generally, in either device, a single crystal substrate such as silicon may be used. As shown in FIG. 5, the inner region 502 of the mesa device 500 may be doped as an N-type region, while the surface region 504 on the first side may be a P-type region, and the surface region 506 on the second side may also be a P-type region. As shown in FIG. 6, the inner region 602 of the planar device 600 may be doped with a first dopant, such as an N-type region, while the surface region 604 on the first side may be doped with a second dopant to form a P-type region, for example, the surface region 606 on the second side may also be a P-type region. As is known in the art, the isolation structures 508 in the mesa device 500 may be formed differently than the isolation structures 608 in the planar device 600. As described below, in either a double-sided mesa TVS device or a planar TVS device, the breakdown voltage may be designed to be different on different sides, for example, by adjusting the dopant concentration in the surface region.

[0018] FIG. 1 illustrates a cross-sectional side view of a protection device 100 according to various embodiments of the present disclosure. The protection device 100 may be formed in a substrate 102, such as monocrystalline silicon or a similar suitable semiconductor material. The protection device 100 may include a first TVS diode 140 and a second TVS diode 142. The first TVS diode 140 and the second TVS diode 142 are integrated into a common die, i.e., the substrate 102. According to various embodiments of the present disclosure, the first TVS diode 140 may be characterized by a first breakdown voltage, while the second TVS diode is characterized by a second breakdown voltage that is different from the first breakdown voltage. Thus, the protection device 100 may form an asymmetric TVS device characterized by two different breakdown voltages for voltage surges of opposite polarity.

[0019] According to various embodiments of the present disclosure, the protection device 100 includes an inner region 104. The inner region 104 has a first polarity, such as N-type polarity. The protection device 100 may further include a first surface region 106 disposed on a first surface 108 of the substrate 102. The first surface region 106 has a second polarity, such as P-type polarity. The protection device 100 may also include a second surface region 110. The second surface region 110 has a second polarity and is disposed on a second surface 112 of the substrate 102 opposite to the first surface 108. In particular, as shown in FIG. 1 , the inner region 104 and the first surface region 106 include a first TVS diode 140 having a first breakdown voltage, while the inner region 104 and the second surface region 110 include a second TVS diode 142 having a second breakdown voltage of opposite polarity to the first TVS diode 140 and different from the first breakdown voltage.

[0020] According to some non-limiting embodiments, the first voltage tolerance may be in a range of 15V to 20V, and the second voltage tolerance may be in a range of 30V to 35V. In a particular embodiment, the first voltage tolerance may be approximately 18V, and the second voltage tolerance may be approximately 33V.

[0021] Of course, other voltage ranges may be used depending on the application. To generate different breakdown voltages for the first TVS diode 140 and the second TVS diode 142, the first surface region 106 may have a first dopant concentration, while the second surface region 110 may have a second dopant concentration greater than the first dopant concentration. In various embodiments, the first dopant concentration may be within a suitable concentration range for generating a breakdown voltage of approximately 15V to 20V, the concentration range depending on the doping level of the inner region of the substrate. Similarly, the second dopant concentration may be within a suitable concentration range for generating a breakdown voltage of approximately 30V to 35V, the concentration range depending on the doping level of the inner region of the substrate. In one non-limiting example, the concentration of one P-type layer may be within a suitable concentration range for generating a breakdown voltage of approximately 30V to 35V, the concentration range depending on the doping level of the inner region of the substrate. 3and may exhibit a relatively deep junction depth producing a relatively high breakdown voltage, while the other P-type layer may exhibit a maximum dopant concentration of 8E19 / cm 3 and may exhibit a relatively shallow junction depth which produces a relatively low breakdown voltage.

[0022] In general, as will be appreciated by those skilled in the art, the first dopant concentration and the second dopant concentration may be adjusted to produce a target breakdown voltage for the first and second TVS diodes, taking into account the dopant concentration of the inner region 104.

[0023] In a given substrate, such as substrate 102, a given diode may be defined as a planar diode. The area of ​​the planar diode may be defined by electrically insulating components, such as an isolation trench 120 disposed on the first surface 108 and an isolation trench 122 disposed on the second surface 112. According to various embodiments of the present disclosure, the first surface region 106 may have a first surface area. The second surface region 110 has a second surface area that is the same as the first surface area.

[0024] 2A-2I show exemplary stages in the synthesis of a protection device according to an embodiment of the present disclosure. In FIG. 2A, a substrate 102, such as a single crystal silicon substrate, is provided. However, the embodiments are not limited in this context. The substrate 102 may be doped according to a target dopant polarity, such as an N-type dopant, and a target dopant concentration level. In FIG. 2B, the substrate 102 is shown after an oxidation process is performed to form an oxide layer 150. In various embodiments, the oxide layer 150 may be formed on the first surface 108 and the second surface 112.

[0025] In Figure 2C, a subsequent step is shown in which oxide layer 150 is removed from first surface 108. In different embodiments, oxide layer 150 may be removed from the entire first surface 108 or only a portion of first surface 108. In Figure 2D, a subsequent step is shown in which dopant layer 152 is formed on first surface 108. Dopant layer 152 may generally have a polarity opposite to that of substrate 102.

[0026] 2E shows a subsequent example in which a first surface region 154 is formed. The first surface region 154 may be formed with a dopant of opposite polarity to that of the substrate 102, such as P-type polarity. The first surface region 154 may be formed by performing a drive-in anneal to drive the dopant of the dopant layer 152 into the substrate 102. Thus, the layer thickness of the first surface region 154 (see D1 in FIG. 1) may be determined in part by the layer thickness of the dopant layer 152 and the annealing protocol (annealing temperature, annealing time) of the drive-in annealing. In addition, the dopant concentration of the first surface region 154 may be determined by the layer thickness of the dopant layer 152 or the total amount of dopant in the dopant layer 152 and the annealing protocol of the drive-in annealing.

[0027] 2D and 2E do not explicitly show the formation of a dopant layer on second surface 112, in some embodiments, the formation of dopant layer 152 may use a process that may deposit at least a portion of the dopant on the bottom side. However, the bottom side is protected by oxide layer 150 to prevent the dopant from being driven in from second surface 112 into substrate 102.

[0028] In Figure 2F, a second oxide layer 156 is formed on the substrate 102. As shown, the second oxide layer 156 may cover the first surface region 154. In Figure 2G, a subsequent operation is shown in which oxides such as oxide layer 150 and second oxide layer 156 are removed from the second surface 112.

[0029] In FIG. 2H, a subsequent example is shown in which a second dopant layer 158 is deposited on the second surface 112.

[0030] In FIG. 2I, a subsequent example is shown in which a second surface region 160 is formed. The second surface region 160 may be formed with a dopant of opposite polarity to that of the substrate 102, such as P-type polarity. The second surface region 160 may be formed by performing a drive-in anneal to drive the dopant of the dopant layer 158 into the substrate 102. Thus, the layer thickness of the second surface region 160 (see D2 in FIG. 1) may be determined in part by the thickness of the dopant layer 158 and the annealing protocol (annealing temperature, annealing time) of the drive-in anneal. In addition, the dopant concentration of the second surface region 160 may be determined by the thickness of the dopant layer 158 or the total amount of dopant in the dopant layer 158 and the annealing protocol of the drive-in anneal. In the example of FIG. 2I, the second oxide layer 156 is also removed from the first surface 108 to form a device 180 with an asymmetric breakdown voltage. One non-limiting example of a suitable annealing procedure for forming a P-type polarity surface region (either on the relatively high voltage layer or the relatively low voltage layer) involves annealing at 1150° C. for 4 hours in a gas atmosphere. The nitrogen flow may be 28 SLPM (standard liters per minute) with 70 standard cubic centimeters per degree (sccm) of O2. A BBr3 material may be used as the doping source, flowing at 380 sccm. In particular, the higher voltage layer may need to be created first. In addition, the basic annealing procedure described above may be slightly modified to create different dopant concentrations. For example, the volumes of N2, O2 source gases may be adjusted to be different to create different dopant concentrations and therefore different breakdown voltages.

[0031] In a particular embodiment, an asymmetric TVS diode device may be arranged with a breakdown voltage suitable for automotive applications. As an example, a first diode may be arranged with a breakdown voltage in the range of 32.8V formed on a first surface of a silicon die, while a second diode is arranged with a breakdown voltage of 18V arranged on a second surface of the silicon die. FIG. 3 shows the breakdown voltage behavior of a semiconductor die arranged according to the above embodiment, with opposing diodes having nominal breakdown voltages of 32.8V and 18V. As shown, measurements of multiple dies show uniform breakdown voltage values ​​for both diodes. Furthermore, it can be seen that the surge capability meets the product specifications for this set of dies.

[0032] In this example, one of the P-type layers is approximately 8E19 / cm 3 and extends to a thickness of less than 30 mm, while the other P-type layer has a peak dopant concentration of approximately 2E19 / cm 3 4 and extends to a greater thickness (depth).

[0033] 4 illustrates a process flow 400 according to an embodiment of the present disclosure. At block 410, a semiconductor substrate, such as a silicon substrate, is provided. The semiconductor substrate may be doped with a doping concentration appropriate to form a breakdown diode. As an example, the semiconductor substrate may be doped to have an N-type polarity. In one example, the doping levels may be such that both polarity doping ranges result in a sheet resistance of 1.0 ohm / sq to 1.5 ohm / sq.

[0034] A first oxidation process is performed to form an oxide layer on the semiconductor substrate at block 420. The first oxidation process may be performed by any suitable method and, in some examples, may form an oxide layer on the first surface and the second surface of the semiconductor substrate.

[0035] The first oxide layer, if present, is removed from the first surface of the semiconductor substrate in block 430. In some instances where the entire first surface is initially coated with the first oxide layer, the first oxide layer is removed from all or at least a portion of the first surface.

[0036] At block 440, a first doping process is performed to create a first surface region on the first surface, thus forming a first surface region having a second polarity opposite to the first polarity of the substrate. In some embodiments, a suitable dopant concentration for the P-type surface region is 2E20 / cm 3 in the range of 0.1 to 0.5 mm or somewhat less.

[0037] A second oxidation process is performed to form a third oxide layer on the first surface of the semiconductor substrate at block 450. The second oxidation process may be performed by any suitable method, and in some examples may form an oxide layer on a second oxide layer already present on the second surface of the semiconductor substrate.

[0038] The second oxide layer is removed from the second surface of the semiconductor substrate in block 460. To the extent a third oxide layer is present on the second oxide layer, the third oxide layer is also removed from the second surface.

[0039] At block 470, a second doping process is performed to create a second surface region on the second surface having a second polarity. According to various embodiments, the second doping process differs from the first doping process in that the concentration of the dopant species of the second polarity in the first surface region differs from the second surface region. The depth of the first surface region may also differ from the depth of the second surface region according to some embodiments. Thus, the first surface region and the second surface region may cooperate with the semiconductor substrate to create two different TVS diodes characterized by different breakdown voltages.

[0040] Although the present embodiments have been disclosed with reference to specific embodiments, numerous modifications, variations and variations and changes to the described embodiments are possible without departing from the sphere and scope of the present disclosure as defined in the appended claims. Accordingly, it is intended that the present embodiments not be limited to the described embodiments, but rather have their full scope as defined by the language of the following claims and their equivalents.

Claims

1. providing a semiconductor substrate, the semiconductor substrate including a first dopant of a first polarity and defining a first surface and a second surface opposite the first surface; performing a first oxidation treatment of the semiconductor substrate, where a first oxide layer forms on the first surface and a second oxide layer forms on the second surface; removing the first oxide layer from at least a first region of the first surface of the semiconductor substrate and not removing the second oxide layer from the second surface; performing a first doping process that produces a first surface region on the first surface including a first concentration of a second dopant of a second polarity opposite to the first polarity; performing a second oxidation process of the semiconductor substrate, where a third oxide layer forms over the first region on the first surface and a fourth oxide layer forms over the second oxide layer; removing the second oxide layer and the fourth oxide layer from at least a second region of the second surface, and not removing the third oxide layer from the first surface; performing a second doping process, the second doping process producing a second surface region on the second surface including a second concentration of a second dopant of a second polarity that is greater than the first concentration; 16. A method for forming an asymmetric transient voltage suppression (TVS) device comprising:

2. The method of claim 1 , wherein the semiconductor substrate comprises an N-type polarity and the first surface region and the second surface region comprise a P-type polarity.

3. 3. The method of claim 2, wherein the semiconductor substrate includes an N-type inner region characterized by the N-type polarity after the steps of performing the first doping process and performing the second doping process.

4. 4. The method of claim 3, wherein the N-type inner region and the first surface region comprise a first TVS diode including a first breakdown voltage, and the N-type inner region and the second surface region comprise a second TVS diode of opposite polarity to the first TVS diode and including a second breakdown voltage different from the first breakdown voltage.

5. 5. The method of claim 4, wherein the first withstand voltage is in a range of 15V to 20V and the second withstand voltage is in a range of 30V to 35V.

6. 6. The method of claim 1, wherein the first dopant concentration comprises a range of 2E19 / cm3 and the second dopant concentration comprises a range of 8E19 / cm3.

7. The method of claim 1 , wherein the first surface region comprises a first surface area and the second surface region comprises a second surface area.

8. performing the first doping process includes depositing a first dopant layer having a first layer thickness and performing a first drive-in anneal; performing the second doping process includes depositing a second dopant layer having a second layer thickness and performing a second drive-in anneal.

8. The method according to any one of claims 1 to 7.

9. The method of claim 8 , wherein the first layer thickness is different from the second layer thickness.

10. 10. The method of claim 8 or 9, wherein the first drive-in anneal differs in procedure from the second drive-in anneal to produce different dopant concentrations.

11. The method of claim 10, wherein during the step of performing the first doping process, the first dopant layer is formed on the second oxide layer; 9. The method of claim 8, wherein the step of removing the second oxide layer and the fourth oxide layer further comprises removing the first dopant layer from at least the second region of the second surface.

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