Semiconductor device manufacturing method

Abstract

To provide a technique capable of improving the film quality of a gate insulating film while suppressing a shift in threshold voltage in a semiconductor device in which the gate insulating film is formed on a compound semiconductor layer containing gallium.SOLUTION: A manufacturing method of a semiconductor device includes the steps of forming a diffusion suppression film 16 containing no gallium and oxygen on a compound semiconductor layer 14 containing gallium, forming a gate insulating film 42 on the diffusion suppressing film, and performing heat treatment at 1000°C or higher after forming the gate insulating film.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The technology disclosed in this specification relates to a method for manufacturing a semiconductor device. [Background technology]

[0002] Gallium nitride (GaN), gallium oxide (Ga 2 O 3 When a gate insulating film is formed on a compound semiconductor layer containing gallium, such as gallium arsenide (GaAs) or gallium arsenide (GaP), and a heat treatment is performed to improve the quality of the gate insulating film, gallium diffuses into the gate insulating film, causing a shift in the threshold voltage. Patent Document 1 proposes a technology to limit the temperature of the heat treatment to less than 600°C in order to suppress such a shift in the threshold voltage. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2016-54250 A Summary of the Invention [Problem to be solved by the invention]

[0004] However, in order to improve the quality of the gate insulating film, a heat treatment at 1000° C. or higher is required. This specification provides a technique that can improve the quality of the gate insulating film while suppressing the shift in threshold voltage. [Means for solving the problem]

[0005] The method for manufacturing a semiconductor device disclosed in this specification can include the steps of forming a diffusion-inhibiting film (16) containing neither gallium nor oxygen on a compound semiconductor layer (14) containing gallium, forming a gate insulating film (42) on the diffusion-inhibiting film, and performing a heat treatment at 1000° C. or higher after forming the gate insulating film.

[0006] The reason why gallium diffuses into the gate insulating film in the conventional manufacturing method is that a gallium oxide layer is formed between the compound semiconductor layer containing gallium and the gate insulating film, and gallium diffuses from the oxide layer into the gate insulating film. In the manufacturing method disclosed in this specification, a diffusion suppression film that does not contain gallium and oxygen is interposed between the compound semiconductor layer and the gate insulating film. Therefore, since a gallium oxide layer is not formed, the diffusion of gallium into the gate insulating film is suppressed. Since the diffusion of gallium is suppressed, a heat treatment of 1000°C or more can be performed. In this way, the manufacturing method disclosed in this specification can improve the film quality of the gate insulating film while suppressing the shift of the threshold voltage. [Brief description of the drawings]

[0007] [Figure 1] 1 is a schematic cross-sectional view of a main portion of an embodiment of a semiconductor device; [Diagram 2] 2 shows a flow chart of a part of a method for manufacturing the semiconductor device of FIG. [Diagram 3] 2 is a schematic cross-sectional view of a main part in one manufacturing process of the manufacturing method of the semiconductor device of FIG. [Figure 4] 2 is a schematic cross-sectional view of a main part in one manufacturing process of the manufacturing method of the semiconductor device of FIG. [Diagram 5] 2 is a schematic cross-sectional view of a main part in one manufacturing process of the manufacturing method of the semiconductor device of FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Hereinafter, a semiconductor device and a manufacturing method thereof disclosed in this specification will be described with reference to the drawings. In each drawing, for the purpose of clarity, common components may be denoted by reference characters only for one of the components.

[0009] 1, the semiconductor device 1 includes a compound semiconductor substrate 12, a compound semiconductor layer 14, a diffusion suppression film 16, a drain electrode 32 provided to cover the lower surface of the compound semiconductor substrate 12, a source electrode 34 provided to cover part of the upper surface of the diffusion suppression film 16, and a planar type insulated gate 40 provided to cover part of the upper surface of the diffusion suppression film 16. The insulated gate 40 has a gate insulating film 42 and a gate electrode 44.

[0010] The compound semiconductor substrate 12 is not particularly limited, and may be, for example, a gallium nitride substrate (GaN substrate). As described later, the compound semiconductor substrate 12 is a base substrate for crystal growth of the compound semiconductor layer 14. The compound semiconductor substrate 12 also contains a high concentration of n-type dopant, and serves as the drain region 21. The n-type dopant is not particularly limited, and may be, for example, silicon. The drain region 21 is in ohmic contact with the drain electrode 32.

[0011] The compound semiconductor layer 14 and the diffusion suppression film 16 are laminated together. The dashed line in the figure indicates the interface between the compound semiconductor layer 14 and the diffusion suppression film 16. The compound semiconductor layer 14 is provided so as to be in contact with the upper surface of the compound semiconductor substrate 12, and is disposed between the compound semiconductor substrate 12 and the diffusion suppression film 16. The compound semiconductor layer 14 is made of a material that contains gallium in the atoms that make up the compound, and is, although not limited to, gallium nitride (GaN) in this example. Alternatively, the compound semiconductor layer 14 may be made of gallium oxide (Ga 2 O 3 ) or gallium arsenide (GaAs).

[0012] The diffusion suppression film 16 is provided so as to be in contact with the upper surface of the compound semiconductor layer 14. The diffusion suppression film 16 is made of a material that does not contain gallium and oxygen in the atoms that constitute the compound, and is not particularly limited, but is aluminum nitride (AlN) in this example. Alternatively, the diffusion suppression film 16 may be silicon nitride (SiN). As will be described later in the manufacturing method, the diffusion suppression film 16 is provided to suppress the diffusion of gallium into the gate insulating film 42 during heat treatment for improving the film quality of the gate insulating film 42.

[0013] The compound semiconductor layer 14 and the diffusion suppression film 16 are stacked together to form an n-type drift region 22 and a p - a body region 24 of the type; + A source region 25 of p + A mold body contact region 26 is formed.

[0014] The drift region 22 is provided so as to be in contact with the upper surface of the drain region 21, and is disposed between the drain region 21 and the body region 24. The drift region 22 also has a JFET region 23 provided so as to be sandwiched between the body region 24 in the surface direction (left-right direction of the paper) of the stack of the compound semiconductor layer 14 and the diffusion suppression film 16. In other words, the JFET region 23 is a part of the drift region 22 provided so as to penetrate the body region 24 from the upper surface of the diffusion suppression film 16. The JFET region 23 is provided at a position exposed on the upper surface of the diffusion suppression film 16, and is in contact with the insulating gate 40. The JFET region 23 is disposed across both the compound semiconductor layer 14 and the diffusion suppression film 16. The drift region 22 contains an n-type dopant at a lower concentration than the drain region 21. The n-type dopant is not particularly limited, and may be, for example, silicon.

[0015] The body region 24 is provided in contact with the upper surface of the drift region 22, and is disposed adjacent to the side surface of the JFET region 23. A portion of the body region 24 is provided at a position exposed on the upper surface of the diffusion suppression film 16, and is in contact with the insulating gate 40. A portion of the body region 24 is disposed across both the compound semiconductor layer 14 and the diffusion suppression film 16. The body region 24 contains a p-type dopant. The p-type dopant is not particularly limited, and may be, for example, magnesium.

[0016] The source region 25 is provided so as to contact the upper surface of the body region 24, and is separated from the drift region 22 by the body region 24. The source region 25 is provided at a position exposed on the upper surface of the diffusion suppression film 16, and contacts the insulating gate 40. The source region 25 is disposed across both the compound semiconductor layer 14 and the diffusion suppression film 16. The source region 25 contains an n-type dopant at a higher concentration than the drift region 22. The n-type dopant is not particularly limited, and may be, for example, silicon. The source region 25 is in ohmic contact with the source electrode 34.

[0017] The body contact region 26 is provided in contact with the upper surface of the body region 24. The body contact region 26 is provided at a position exposed on the upper surface of the diffusion suppression film 16, and is arranged across both the compound semiconductor layer 14 and the diffusion suppression film 16. The body contact region 26 contains a p-type dopant at a higher concentration than the body region 24. The p-type dopant is not particularly limited, and may be, for example, magnesium. The body contact region 26 is in ohmic contact with the source electrode 34.

[0018] The insulating gate 40 is provided so as to be in contact with a part of the upper surface of the diffusion suppression film 16 and is made of silicon oxide (SiO 2 The gate insulating film 42 is made of aluminum oxide (Al 2 O 3) The gate insulating film 42 is disposed between the diffusion suppression film 16 and the gate electrode 44, and is in contact with both the diffusion suppression film 16 and the gate electrode 44. The gate electrode 44 faces the body region 24 at a position separating the JFET region 23, which is a part of the drift region 22, from the source region 25, and the JFET region 23 via the gate insulating film 42.

[0019] Next, the operation of the semiconductor device 1 will be described. During use, a positive voltage is applied to the drain electrode 32, and the source electrode 34 is grounded. When a positive voltage higher than the gate threshold voltage is applied to the gate electrode 44, an inversion layer is formed in the body region 24, i.e., the channel region, at a portion separating the JFET region 23 and the source region 25. Electrons flow from the source region 25 to the JFET region 23 through the inversion layer formed in the channel region. The electrons that flow into the JFET region 23 flow vertically through the JFET region 23 and the drift region 22 toward the drain electrode 32. This brings the drain electrode 32 and the source electrode 34 into conduction, and the semiconductor device 1 is turned on. When the gate electrode 44 is grounded, the inversion layer disappears, and the semiconductor device 1 is turned off. In this way, the semiconductor device 1 can perform a switching operation that switches between on and off between the drain electrode 32 and the source electrode 34 based on the voltage applied to the gate electrode 44.

[0020] (Method of Manufacturing Semiconductor Device 1) 2 is a manufacturing flow showing a flow of some steps among those for manufacturing the semiconductor device 1. FIGS. 3 to 5 are cross-sectional views of the main part in the manufacturing process corresponding to the manufacturing flow of FIG.

[0021] First, as shown in FIG. 3, a crystal growth technique is used to crystal grow the compound semiconductor layer 14 from the upper surface of the compound semiconductor substrate 12, and further, a diffusion suppression film 16 is crystal grown from the upper surface of the compound semiconductor layer 14 to form a laminate of the compound semiconductor layer 14 and the diffusion suppression film 16 (step S1 in FIG. 2). The compound semiconductor layer 14 is formed by crystal growth so as to include an n-type dopant. The diffusion suppression film 16 may be formed by crystal growth so as to include an n-type dopant, or may be formed by crystal growth without doping. The thickness of the diffusion suppression film 16 is 15 nm or less. When the thickness of the diffusion suppression film 16 is 15 nm or less, cracks in the diffusion suppression film 16 due to the influence of the lattice constant difference between the compound semiconductor layer 14 (in this example, a GaN layer) and the diffusion suppression film 16 (in this example, an AlN layer) are suppressed, and a good quality diffusion suppression film 16 can be formed.

[0022] Next, as shown in Fig. 4, a p-type dopant or an n-type dopant is implanted into a predetermined region of the upper layer of the stack of the compound semiconductor layer 14 and the diffusion suppression film 16 by using an ion implantation technique to form a body region 24, a source region 25, and a body contact region 26 (step S2 in Fig. 2). The order in which these semiconductor regions 24, 25, and 26 are formed is not particularly limited. The dopants for forming these semiconductor regions 24, 25, and 26 are implanted so as to straddle both the compound semiconductor layer 14 and the diffusion suppression film 16. When the diffusion suppression film 16 is an i-type, an n-type dopant may be implanted into a portion of the diffusion suppression film 16 corresponding to the JFET region 23.

[0023] Next, a heat treatment is performed to activate these semiconductor regions 24, 25, and 26 (step S3 in FIG. 2). The temperature of the heat treatment is not particularly limited, but may be, for example, 1200° C. or higher. Such a high-temperature heat treatment can satisfactorily activate the implanted dopants, particularly magnesium, which is a p-type dopant. In addition, the diffusion suppression film 16 (in this example, the AlN layer) is made of a material having a higher melting point than the compound semiconductor layer 14 (in this example, the GaN layer). Therefore, the diffusion suppression film 16 can function as a cap layer, and can suppress nitrogen loss from the upper surface of the compound semiconductor layer 14 and suppress the formation of pits on the upper surface of the compound semiconductor layer 14.

[0024] 5, a gate insulating film 42 is formed on the diffusion suppression film 16 (step S4 in FIG. 2). Specifically, a deposition technique is used to deposit the gate insulating film 42 so as to cover the upper surface of the diffusion suppression film 16. The deposition technique is not particularly limited, but may be an atomic layer deposition method or a plasma CVD method.

[0025] Next, a heat treatment is performed to improve the film quality of the gate insulating film 42 (step S5 in FIG. 2). This heat treatment is also called PDA (Post Deposition Annealing). The heat treatment temperature is 1000° C. or higher and 1400° C. or lower. Heat treatment at 1000° C. or higher reduces defects at the interface between the gate insulating film 42 and the diffusion suppression film 16, and also reduces impurities (hydrogen, carbon, etc.) in the gate insulating film 42. Heat treatment at 1400° C. or lower can prevent the gate insulating film 42 from melting. The upper limit of the heat treatment temperature is appropriately adjusted depending on the material of the gate insulating film 42.

[0026] Next, the drain electrode 32, the source electrode 34, and the gate electrode 44 are formed using a known manufacturing technique (Step S6 in FIG. 2), thereby completing the manufacture of the semiconductor device 1 shown in FIG.

[0027] In the semiconductor device 1, the diffusion suppression film 16 is provided between the compound semiconductor layer 14 and the gate insulating film 42. If such a diffusion suppression film 16 is not provided, a gallium oxide layer is formed between the compound semiconductor layer 14 and the gate insulating film 42, and gallium diffuses from the oxide layer into the gate insulating film 42 during heat treatment to improve the film quality of the gate insulating film 42, causing a shift in the threshold voltage. In particular, when a heat treatment at 1000° C. or higher is performed, such a shift in the threshold voltage becomes apparent. In the above manufacturing method, since the diffusion suppression film 16 that does not contain gallium and oxygen is interposed between the compound semiconductor layer 14 and the gate insulating film 42, a gallium oxide layer is not formed, and as a result, the diffusion of gallium into the gate insulating film 42 is suppressed. Since the diffusion of gallium is suppressed, a heat treatment at 1000° C. or higher can be performed. In this way, the above manufacturing method can improve the film quality of the gate insulating film 42 while suppressing the shift in the threshold voltage.

[0028] In the semiconductor device 1, the material of the diffusion suppression film 16 is selected so that the band gap of the material of the diffusion suppression film 16 is wider than the band gap of the material of the compound semiconductor layer 14. Therefore, the diffusion suppression film 16 can also function as a gate insulating film. As a result, in the semiconductor device 1, dielectric breakdown of the gate insulating film 42 is suppressed.

[0029] In the above, the technology disclosed in this specification has been explained using a semiconductor device 1 having a planar type insulated gate 40, but the technology disclosed in this specification can also be applied to a semiconductor device having a trench type insulated gate.

[0030] The features of the technology disclosed in this specification are summarized below. Note that the technical elements described below are independent technical elements that exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing.

[0031] The method for manufacturing a semiconductor device disclosed in this specification can include the steps of forming a diffusion-inhibiting film that does not contain gallium and oxygen on a compound semiconductor layer that contains gallium, forming a gate insulating film on the diffusion-inhibiting film, and performing a heat treatment at 1000° C. or higher after forming the gate insulating film.

[0032] In the method for manufacturing a semiconductor device, the band gap of the material of the diffusion suppression film may be wider than the band gap of the material of the compound semiconductor layer. For example, the material of the compound semiconductor layer may be gallium nitride (GaN), and the material of the diffusion suppression film may be aluminum nitride (AlN) or silicon nitride (SiN). The insulating property of the diffusion suppression film suppresses dielectric breakdown of the gate insulating film.

[0033] In the above-mentioned method for manufacturing a semiconductor device, the material of the gate insulating film is silicon oxide (SiO 2 ) or aluminum oxide (Al 2 O 3 ) may also be used.

[0034] Although specific examples of the present invention have been described above in detail, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and variations of the specific examples exemplified above. Furthermore, the technical elements described in this specification or drawings exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technology exemplified in this specification or drawings can achieve multiple objectives simultaneously, and achieving one of these objectives is itself technically useful. [Explanation of symbols]

[0035] 12: compound semiconductor substrate, 14: compound semiconductor layer, 16: diffusion suppression film, 21: drain region, 22: drift region, 23: JFET region, 24: body region, 25: source region, 26: body contact region, 32: drain electrode, 34: source electrode, 42: gate insulating film, 44: gate electrode, 40: insulated gate

Claims

1. A method for manufacturing a semiconductor device, comprising: forming a diffusion suppression film (16) containing neither gallium nor oxygen on a compound semiconductor layer (14) containing gallium; Injecting dopants into predetermined regions of the compound semiconductor layer and the diffusion suppression film using an ion implantation technique; performing a first heat treatment to activate the implanted dopants; forming a gate insulating film (42) on the diffusion suppression film after the first heat treatment; and performing a second heat treatment at 1000° C. or more after forming the gate insulating film; A method for manufacturing a semiconductor device, wherein the specific region of the diffusion suppression film into which the dopant is implanted is provided at a position exposed on an upper surface of the diffusion suppression film and is in contact with an electrode provided on the upper surface of the diffusion suppression film.

2. The method for manufacturing a semiconductor device according to claim 1 , wherein a band gap of the material of said diffusion suppression film is wider than a band gap of the material of said compound semiconductor layer.

3. the material of the compound semiconductor layer is gallium nitride (GaN); 3. The method of claim 2, wherein the material of the diffusion suppression film is aluminum nitride (AlN) or silicon nitride (SiN).

4. The material of the gate insulating film is silicon oxide (SiO 2 ) or aluminum oxide (Al 2 O 3 4. The method for manufacturing a semiconductor device according to claim 1, wherein

Images