Power silicon carbide MOSFET devices and related methods

Abstract

To provide a novel power MOSFET provided with a silicon carbide drift region having a first conductivity type.SOLUTION: A unit cell transistor 400 of a power MOSFET includes: a silicon carbide drift region 420 having a first conductivity type; well regions 430 which are located in an upper portion of the silicon carbide drift region and each include a major well 432 and side wells 434 on both sides of the major well 432 that are doped with second conductivity dopants; and a channel region 436 in a side portion of the well region, an upper portion of the channel region having the first conductivity type. Therein, a depth D of the well region is at least 1.5 micrometers, and the depth of the well region exceeds width W of a JFET region 422 between the well regions.SELECTED DRAWING: Figure 5B

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to U.S. Patent Application No. 15 / 849,975, filed December 21, 2017, the entire contents of which are incorporated by reference herein.

[0002] Statement of U.S. Government Interests This invention was made with Government support funded by the Army Research Laboratory under Contract No. W911NF-12-2-0064. The Government has certain rights in this invention.

[0003] The present invention relates to conductor devices, and more particularly to power semiconductor transistors. [Background technology]

[0004] Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) are a well-known type of semiconductor transistor that can be used as a switching device. A MOSFET is a three-terminal device that includes source and drain regions separated by a channel region, and a gate electrode disposed adjacent to the channel region. A MOSFET can be turned on or off by applying a gate bias voltage to the gate electrode. When a MOSFET is turned on by applying a gate bias voltage equal to or greater than the threshold voltage, current is conducted through the channel region of the MOSFET between the source and drain regions. When the bias voltage is removed from the gate electrode (or reduced below the threshold voltage level), current no longer conducts through the channel region. As an example, an n-type MOSFET includes n-type source and drain regions and a p-type channel. An n-type MOSFET can be designed to turn on when a gate bias voltage sufficient to create a conductive n-type inversion layer in the p-type channel region that electrically connects the n-type source and drain regions is applied to the gate electrode, thereby allowing majority carrier conduction between them. A MOSFET may also be designed as a "normally on" device, which is turned off by applying a gate bias voltage to the gate electrode.

[0005] The gate electrode of a MOSFET is usually separated from the channel region by a thin gate insulation pattern, such as a silicon oxide pattern. Because the gate electrode of a MOSFET is insulated from the channel region by the gate insulation pattern, a minimal gate current is required to maintain the MOSFET in its on state or to switch the MOSFET between on and off states. The gate current is kept low during switching because the gate forms a capacitor with the channel region. Therefore, only minimal charging and discharging currents are required during switching, allowing for a simpler gate drive circuit.

[0006] There is an increasing demand for high power MOSFETs that can pass large currents (tens of amps or more) in their "on" state and block high voltages (hundreds or even thousands of volts) in their reverse blocking state. To support high current densities and block such high voltages, power MOSFETs typically have a vertical structure with a source and drain on either side of a thick semiconductor layer structure. For very high power applications, power MOSFETs are typically formed in wide bandgap semiconductor material systems (as used herein, the term "wide bandgap semiconductor" encompasses any semiconductor with a bandgap of at least 1.4 eV), such as silicon carbide ("SiC"), which has many beneficial properties including, for example, high electric field dielectric strength, high thermal conductivity, high electron mobility, high melting point, and high saturated electron drift velocity. Relative to devices formed in other semiconductor materials, such as silicon, electronic devices formed in silicon carbide may be capable of operation at higher temperatures, higher power densities, higher speeds, higher power levels, and / or higher radiation densities. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] U.S. Patent Application Serial No. 15 / 168,310 Summary of the Invention [Means for solving the problem]

[0008] According to some embodiments of the present invention, a power MOSFET is provided that includes a silicon carbide drift region having a first conductivity type. A first well region is disposed within an upper portion of the silicon carbide drift region and extends to an upper surface of the silicon carbide drift region. The first well region is doped with a dopant of a second conductivity type, and at least a lower portion of the first well region has a second conductivity type different from the first conductivity type. A second well region is disposed within an upper portion of the silicon carbide drift region and extends to an upper surface of the silicon carbide drift region. The second well region is spaced from the first well region by a JFET region of the silicon carbide drift layer. The second well region is doped with a dopant of a second conductivity type, and at least a lower portion of the second well region has the second conductivity type. A channel region is disposed at a side portion of the first well region, and an upper portion of the channel region has the first conductivity type. The depth of the first well region is at least 1.5 micrometers, and the depth of the first well region exceeds the distance between the first and second well regions.

[0009] In some embodiments, the power MOSFET further comprises a first source / drain contact facing a lower surface of the silicon carbide drift region, a first conductivity type region within an upper portion of the first well region and extending to an upper surface of the first well region, a second source / drain contact on an upper surface of the first conductivity type region, a gate insulating layer on the first well region, and a gate electrode on the gate insulating layer.

[0010] In some embodiments, the first and second well regions may be implanted regions that are implanted with a second conductivity type dopant.

[0011] In some embodiments, the doping concentration of the JFET region is greater than 1×10 16 cm 3 ~5×10 17 / cm 3 It is.

[0012] In some embodiments, at least the top 0.2 micrometers of the first well region have the first conductivity type. In other embodiments, at least the top 0.4 micrometers of the first well region have the first conductivity type.

[0013] In some embodiments, the first and second well regions can each have a depth of at least 2.5 micrometers.

[0014] In some embodiments, the channel region and the central portion of the first well region can have substantially the same doping profile of the second conductivity type dopant as a function of depth from the top surface of the silicon carbide drift region.

[0015] In some embodiments, the second conductivity type dopant concentration in the first well region may vary by less than a factor of 3 from a depth of 1.0 to 2.0 micrometers from a top surface of the silicon carbide drift region.

[0016] In some embodiments, the lower portion of the channel region may then have the second conductivity type.

[0017] In some embodiments, the power MOSFET may exhibit a negative temperature coefficient of drain current over a temperature range of at least 25 to 150° C. at a drain-source current of less than 40 amps.

[0018] According to a further embodiment of the present invention, there is provided a power MOSFET comprising: a silicon carbide drift region having a first conductivity type; a first well region disposed within an upper portion of the silicon carbide drift region and extending to an upper surface of the silicon carbide drift region, the first well region being doped with a dopant of a second conductivity type, at least a lower portion of the first well region having the second conductivity type, the second conductivity type being different from the first conductivity type; a gate insulating layer on the upper surface of the first well region; and a channel region below the gate insulating layer in a lateral portion of the first well region, the upper portion of the channel region having the first conductivity type. These power MOSFETs may exhibit a negative temperature coefficient of drain current at least at temperatures in the range of 25 to 150° C. at a drain-source current of less than 40 amps.

[0019] In some embodiments, the depth of the first well region can be at least 1.5 micrometers, and the depth of the first well region can exceed the distance between the first well region and a second well region adjacent to the first well region. The first and second well regions can be formed using channeling ion implantation.

[0020] According to a further embodiment of the present invention, there is provided a method of forming a power MOSFET in which a silicon carbide drift region having a first conductivity type is formed on a substrate. First and second well regions are formed in an upper portion of the silicon carbide drift region by implanting a second conductivity type dopant into the upper portion of the silicon carbide drift region using channeled ion implantation. An upper portion of each of the first and second well regions has the first conductivity type, while a lower portion of each of the first and second well regions has a second conductivity type, the second conductivity type being different from the first conductivity type.

[0021] In some embodiments, channeling ion implantation is used to inject dopant impurities into the silicon carbide drift region. <0001> , <11-23>, <-1-123>, <1-213>, <-12-13>, <2-1-13> or <-2113> crystal axes within ±1.5°.

[0022] In some embodiments, the first and second well regions may have a depth of 1.5 micrometers (or at least 2.5 micrometers), and at least the top 0.2 micrometers (or 0.4 micrometers) of the first well region may have the first conductivity type.

[0023] In some embodiments, the depth of the first well region may exceed the distance between the first and second well regions.

[0024] In some embodiments, a lateral portion of the first well region underlying the gate electrode of the MOSFET may include a channel region, at least a portion of the channel region having the first conductivity type.

[0025] In some embodiments, the channel region and the central portion of the first well region can have substantially the same doping profile of the second conductivity type dopant as a function of depth from the top surface of the silicon carbide drift region. [Brief description of the drawings]

[0026] [Figure 1A] FIG. 1 is a schematic cross-sectional view of a unit cell of a conventional power MOSFET. [Figure 1B] 1B is a graph showing the doping profile as a function of depth in the channel region of the unit cell of FIG. 1A. [Figure 2A] FIG. 1 is a schematic cross-sectional view of a unit cell of another conventional power MOSFET. [Figure 2B] FIG. 2B is a graph showing the doping profile as a function of depth in the channel region of the unit cell of FIG. 2A. [Diagram 3]1 is a schematic plan view of a semiconductor wafer including a plurality of power MOSFETs, in accordance with an embodiment of the present invention. [Figure 4A] FIG. 4 is a schematic plan view of one of the power MOSFETs included on the semiconductor wafer of FIG. 3. [Figure 4B] FIG. 4B is a schematic plan view of the power MOSFET of FIG. 4A with the source metallization removed. [Figure 5A] FIG. 5 is a schematic plan view of a portion of a unit cell of the power MOSFET of FIGS. 4A to 4B. [Figure 5B] 5B is a schematic cross-sectional view taken along line 5B-5B in FIG. 5A. [Figure 5C] FIG. 6 is a graph showing the doping profile as a function of depth in the channel region of the unit cell of FIGS. 5A-5B. [Figure 6] 5C is a graph illustrating exemplary doping profiles into the well region of the unit cell of FIGS. 5A-5B that can be achieved using channeling ion implantation at various implant energies. FIG. [Figure 7] 1 is a graph of a gain characteristic curve of a silicon carbide MOSFET according to an embodiment of the present invention. [Figure 8] 5 is a graph showing the voltage blocking characteristics of the power MOSFETs of FIGS. 4A and 4B. [Figure 9A] 1 is a graph showing output characteristics of a conventional MOSFET. [Figure 9B] 4 is a graph showing output characteristics of a MOSFET according to an embodiment of the present invention. [Figure 10] 4 is a flow chart of a method of forming a power MOSFET in accordance with an embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0027] Power silicon carbide MOSFETs are currently used in applications requiring high voltage blocking, such as blocking voltages of 1,000 volts or more. As an example, 2Silicon carbide MOSFETs are commercially available that are rated for current densities of at least 10 kV and will block voltages of at least 10 kV. To form such devices, multiple "unit cell" MOSFET transistors are typically formed, electrically connected in parallel. For high power applications, a large number of these unit cells (e.g., hundreds or thousands) are typically provided on a single semiconductor substrate, and a gate electrode pattern is formed on the top surface of the semiconductor substrate to serve as the gate electrode for all the unit cells. The opposite (bottom) side of the semiconductor substrate serves as a common drain for all the unit cells of the device. Multiple source contacts are formed on source regions in the semiconductor layer structure and exposed within openings in the gate electrode pattern. These source contacts are also electrically connected to each other to serve as a common source. The resulting device has three terminals, a common source terminal, a common drain terminal, and a common gate electrode that serve as terminals for hundreds or thousands of individual unit cell transistors. It will be understood that the above description is for an n-type MOSFET, and that for a p-type MOSFET the positions of the drain and source would be reversed.

[0028] There is a continuing demand to reduce both the cost and size of power MOSFET devices, while providing equivalent or improved performance. Some of the key performance parameters are the mobility of carriers in the channel region of the MOSFET, the threshold voltage of the device, and the "short circuit capability" of the device.

[0029] Figure 1A is a schematic cross-sectional view of a conventional silicon carbide power MOSFET unit cell transistor 100 (Figure 1A also shows portions of two adjacent unit cells 100). Figure 1B is a graph showing the doping profile of the lateral p-well of the unit cell transistor 100 as a function of depth from the top surface of the device's semiconductor layer structure.

[0030] As shown in FIG. 1A, the unit cell transistor 100 may be formed on an n-type silicon carbide semiconductor substrate 110. The substrate 110 may be, for example, heavily doped with n-type impurities (i.e., n + The silicon carbide substrate may include a single crystal 4H silicon carbide semiconductor substrate.

[0031] Lightly doped n-type (n - 1.) A silicon carbide drift region 120 is provided on the substrate 110. An upper portion of the n-type silicon carbide drift region 120 may be doped p-type by ion implantation to form p-wells 130. Each p-well 130 may include a pair of a main p-well 132 and a side p-well 134. The main p-well 132 may be, for example, 5×10 18 / cm 3 ~5×10 19 / cm 3 The dopant concentration is typically higher the deeper the p-well 132 extends into the silicon carbide drift region 120. The lateral p-wells 134 are lightly doped with p-type dopants than the main p-well 132. The doping concentration profile of each lateral p-well 134 is shown in FIG. 1B and discussed below. Each p-well 130 is formed by ion implantation using two ion implantation steps. As known to those skilled in the art, ions such as n-type or p-type dopants can be implanted into a semiconductor layer or region by ionizing a desired ion species and accelerating the ions at a predetermined kinetic energy as an ion beam toward the surface of the semiconductor layer in an ion implantation target chamber. Based on the predetermined kinetic energy, the desired ion species can penetrate into the semiconductor layer. The ions will be implanted at different depths into the semiconductor layer, so that a given kinetic energy will provide an implantation "profile" that varies the ion concentration with depth.

[0032] Highly doped (n +A heavily doped (n) n-type silicon carbide source region 140 is formed in the upper portion of the p-well 130. The n-type source region 140 may be formed by ion implantation. + ) The n-type silicon carbide region 140 serves as a source region for the unit cell transistor 100. The drift region 120 and the substrate 110 together serve as a common drain region for the unit cell transistor 100. The n-type silicon carbide substrate 110, the n-type silicon carbide drift region 120, the p-well 130, and the n-type source region 140 formed therein together comprise the semiconductor layer structure 150 of the unit cell transistor 100.

[0033] After the p-well 130 and the n-type source region 140 are formed, an n-type epitaxial pattern 160 may be grown on the semiconductor layer structure 150. The n-type epitaxial pattern 160 may have a low doping concentration (e.g., 1×10 16 / cm 3 ~1×10 17 / cm 3 The n-type epitaxial pattern 160 may have a thickness of, for example, 0.5 to 1.5 micrometers.

[0034] A gate insulating pattern 170 may be formed on the top surface of the n-type epitaxial pattern 160. The gate insulating pattern 170 may include, for example, a silicon oxide layer, although other insulating materials may be used. A gate electrode 172 may be formed on the gate insulating pattern 170 opposite the n-type epitaxial pattern 160. A source contact 180 may be formed within an opening in the n-type epitaxial layer 160, exposing the heavily doped n-type source region 140. A drain contact 190 may be formed on the bottom surface of the substrate 110.

[0035] A channel region 136 is formed in a side portion of the p-well 130. The channel region 136 may extend into the n-type epitaxial pattern 160. The channel region 136 electrically connects the n-type source region 140 to the drift region 120 when a sufficient bias voltage is applied to the gate electrode 172. When such a bias voltage is applied to the gate electrode 172, current may flow from the n-type source region 140 through the channel region 136 to the portion of the drift region 120 underlying the gate electrode 172.

[0036] It will be understood that unit cell transistor 100 is an n-type device having a source contact 180 on its top surface and a drain contact 190 on its bottom surface, whereas in a p-type device these positions would be reversed. Thus, in parts of the description that follow (including the claims), the source contacts and drain contacts may be referred to collectively as "source / drain contacts," which term collectively refers to either a source contact or a drain contact.

[0037] 1B is a graph illustrating the doping profile of the lateral p-well 134 of the unit cell transistor 100 as a function of depth from the top surface of the semiconductor layer structure 150. In this example, the p-well 130 is formed by implanting aluminum ions into the silicon carbide drift layer 120. As shown in FIG. 1B, the lateral p-well 134 has an aluminum ion doping concentration of approximately 1×10 at the top surface of the lateral p-well 134. 18 / cm 3 , and n-type epitaxial pattern 160 to a depth of about 0.5 μm, 5 × 10 19 / cm 3 The lateral p-well 134 may have a graded doping profile that increases to and then gradually decreases. The lateral p-well 134 may be implanted using a relatively low implant energy (e.g., 300-350 keV) because a relatively high doping concentration is provided at the surface of the lateral p-well 134.

[0038] As mentioned above, two important performance parameters of a power MOSFET may be the mobility of carriers in the channel region of the unit cell transistor and the threshold voltage of the device. The doping profile of the channel region 136 may have a large impact on both of these performance parameters. To have high channel mobility, it may be desirable to have a low doping concentration directly under the gate insulating layer 170. Making the top of the channel region 136 directly under the gate insulating layer 170 an n-type region (for a p-channel MOSFET) may also improve channel mobility. Such a design may further result in a lower threshold voltage. Furthermore, since the damage of the ion implantation will not be present directly under the gate insulating layer 170, damage due to such ion implantation may be further removed from the gate insulating layer 170 and therefore have less impact on device performance.

[0039] MOSFETs in the form of unit cell transistor 100 may exhibit good performance, but may be expensive to manufacture because they require growing a first set of semiconductor layers, removing the structure from a growth reactor to form p-well 130 and n-type source region 140 by ion implantation, and then placing the structure back in the growth reactor to form n-type epitaxial pattern 160.

[0040] FIG. 2A is a schematic cross-sectional view of another conventional silicon carbide power MOSFET unit cell 200 (and portions of two additional unit cells 200). As shown in FIG. 2A, the unit cell transistor 200 includes an n-type silicon carbide semiconductor substrate 210 and a lightly doped n-type (n - ) silicon carbide drift region 220. The top of the n-type silicon carbide drift region 220 is doped p-type by ion implantation to form p-wells 230, each of which comprises a pair of main p-wells 232 and side p-wells 234. +2.) An n-type silicon carbide source region 240 is formed in the upper portion of the p-well 230 by ion implantation. The substrate 210, drift region 220, p-well 230, and n-source region 140 together comprise a semiconductor layer structure 250 of the unit cell transistor 200. A gate insulation pattern 270 is formed on the semiconductor layer structure 250. A gate electrode 272 is formed on the gate insulation pattern 270. A source contact 280 is formed on the source region 240, and a drain contact 290 is formed on the underside of the substrate 210. A channel region 236 is provided in a side portion of the p-well 230 that electrically connects the source region 240 to the drift region 220 when a sufficient bias voltage is applied to the gate electrode 272.

[0041] 1A and 2A, the unit cell transistor 200 has a structure similar to that of the unit cell transistor 100 of FIG. 1A, except that the n-type epitaxial pattern 160 of the unit cell transistor 100 is omitted in the unit cell transistor 200. Therefore, further description of the cross-sectional view of FIG. 2A will be omitted. It will be further understood that the dimensions and doping concentrations of various regions of the unit cell transistor 200 may differ from the dimensions and doping concentrations of corresponding regions in the unit cell transistor 100.

[0042] 2B is a graph illustrating the doping profile of the lateral p-well 234 of the unit cell transistor 200 as a function of depth from the top surface of the semiconductor layer structure 250. As shown in FIG. 2B, the dopant concentration at the surface of the channel region 246 is approximately 1×10 17 / cm 3 The dopant concentration is about 1×10 at a depth of about 0.5 micrometers from the gate insulating layer 270. 19 / cm 3 The doping concentration then decreases to a peak doping concentration of 1×10 at a depth of about 0.7 μm. 17 / cm 3 Descend below.

[0043] Although the power MOSFET in the form of the unit cell transistor 200 exhibits good performance, the performance may not be as good as that of the power MOSFET in the form of the unit cell transistor 100 of FIG. 1A. Because the p-well 230 may be formed by a higher energy ion implantation process (e.g., the implantation energy may be about 450 keV), which increases the damage of the semiconductor layer structure, a performance degradation may occur for the power MOSFET in the form of the unit cell transistor 200. Furthermore, the damage may be directly below the gate insulating layer 270, where the damage may have the greatest impact on the device performance. In addition, the doping profile of FIG. 2B may be inferior to the doping profile of FIG. 1B, and a corresponding performance degradation may occur. However, the power MOSFET in the form of the unit cell transistor 200 may be significantly less expensive to manufacture as compared to the power MOSFET in the form of the unit cell transistor 100.

[0044] Another potential challenge with a power MOSFET in the form of unit cell transistor 200 is that it may exhibit a reduced “short circuit capability” compared to a power MOSFET in the form of unit cell transistor 100. The “short circuit capability” of a power MOSFET indicates the amount of time the power MOSFET can operate at a specified temperature without damaging the device. Under so-called short circuit conditions, the temperature of the power MOSFET can increase dramatically due to the large amount of power dissipated in the device when a large current passes through the device. The short circuit capability of a power MOSFET can be important because the characteristics of the device and its packaging will determine the amount the MOSFET will heat up in response to operating power. For example, if power MOSFET 200 handles 500 amps, which may be at a voltage of 1200 volts, the power is 1200V x 500A = 60 kilowatts. A power MOSFET with conventional packaging may have a thermal impedance of, for example, 0.01°C / W. Thus, for such a MOSFET, operation at 60 kilowatts will heat the device up to about 600°C (60 kilowatts x 0.01°C / W = 600°C). Typically, a MOSFET can only sustain such temperatures for a very short time, such as one microsecond, without failure. In contrast, the same MOSFET may be able to operate at 200°C for tens of hours without failure.

[0045] To protect the MOSFET from such failure, a control circuit may be provided that detects when a short circuit condition occurs and drops the gate voltage (e.g., 0 volts) accordingly. A short circuit condition is not a normal operating condition and typically occurs because a larger system that includes the MOSFET is not operating as intended. However, the short circuit capability of the MOSFET is important because when a short circuit condition occurs, the control system must be able to quickly shut off the gate voltage to prevent failure of the device. The shorter the duration of the short circuit capability, the faster the control circuit must be able to act.

[0046] According to embodiments of the present invention, a power MOSFET is provided that may exhibit significantly improved short circuit capability while also providing very high levels of performance in terms of blocking voltage, switching time, and threshold voltage. This improved performance may be achieved by using channeling ion implantation techniques to form deep well regions in the semiconductor structure using relatively low implantation energies.

[0047] In some embodiments, a power MOSFET is provided that includes a silicon carbide drift region having a first conductivity type, first and second well regions doped with a dopant of a second conductivity type disposed within an upper portion of the silicon carbide drift region, and a channel region within a side portion of the first well region, the channel region including an upper portion having the first conductivity type and a lower portion below the upper portion having a second conductivity type, the depth of the first well region being at least 1.5 micrometers, and the depth of the first well region being greater than the distance between the first and second well regions. The first and second well regions may be implanted regions implanted with the second conductivity type dopant and may be formed using channeling ion implantation.

[0048] In another embodiment, a power MOSFET is provided that includes a silicon carbide drift region having a first conductivity type; first and second spaced apart well regions disposed within respective upper portions of the silicon carbide drift regions and extending to an upper surface of the silicon carbide drift regions, the well regions being doped with a dopant of a second conductivity type, at least a lower portion of each of the first and second well regions having the second conductivity type, the second conductivity type being different from the first conductivity type, the first and second well regions defining a JFET region therebetween; a gate insulating layer on the top surface of the first well region; and a channel region below the gate insulating layer in a side portion of the first well region, the upper portion of the channel region having the first conductivity type. The doping concentration of the silicon carbide drift region, the width of the JFET region, the doping concentration of the channel region, and / or the depth of the first well region are selected to provide a negative temperature coefficient of drain current over a temperature range of at least 25 to 150 degrees Celsius at a drain-source current of less than 40 amperes.

[0049] According to yet a further embodiment of the present invention, there is provided a method of forming a power MOSFET in which a silicon carbide drift region having a first conductivity type is formed on a substrate. First and second well regions are formed in an upper portion of the silicon carbide drift region by implanting second conductivity type dopants into the upper portion of the silicon carbide drift region using channeled ion implantation. An upper portion of each of the first and second well regions has the first conductivity type, while a lower portion of each of the first and second well regions has a second conductivity type, the second conductivity type being different from the first conductivity type.

[0050] Exemplary embodiments of power MOSFETs according to embodiments of the present invention will now be described with reference to FIGS.

[0051] 3 is a schematic plan view of a wafer 300 including a plurality of power MOSFETs 310, according to an embodiment of the invention. The power MOSFETs 310 may be formed in rows and columns and spaced apart from one another so that the wafer 300 may later be singulated (e.g., diced) to separate the individual power MOSFETs 310 for packaging and testing. The wafer 300 may, for example, in some embodiments, include a 4H silicon carbide substrate having one or more silicon carbide layers formed thereon (e.g., by epitaxial growth). Other semiconductor layers (e.g., polysilicon layers), insulating layers, and / or metal layers may be formed on the silicon carbide semiconductor layer structure to form the power MOSFETs 310.

[0052] Figure 4A is a schematic plan view of one of the power MOSFETs 310 contained on wafer 300 of Figure 3. Figure 4B is a schematic plan view of power MOSFET 310 of Figure 4A with the source metallization and gate bond pads removed.

[0053] As shown in Figure 4A, a gate bond pad 320 and one or more source bond pads 330-1, 330-2 may be formed on a top surface of the semiconductor layer structure of the MOSFET 310. A drain bond pad 340 (represented by a dotted line square in Figure 4A) may be provided on a bottom surface of the MOSFET 310. Each bond pad 320, 330, 340 may be formed from a metal such as aluminum, and bond wires may be readily attached by conventional techniques such as thermocompression or soldering.

[0054] As will be described in more detail below, a source contact is provided that contacts a source region in the semiconductor layer structure of the MOSFET 310. The source contact may be the bottom of a source metal pattern 332 that extends across most of the top surface of the MOSFET 310. The source metal pattern 332 is shown in FIG. 4A by a dashed box because most of the source metal pattern 332 is covered by the protective layer 350. The source bond pads 330-1, 330-2 are the portions of the source metal pattern 332 that are exposed through openings 352 in the protective layer 350. Bond wires 360 are shown in FIG. 4A that may be used to connect the gate bond pad 320 and the source bond pads 330-1, 330-2 to external circuitry, or the like.

[0055] As shown in FIG. 4B, a gate electrode pattern 322 may be provided that includes a gate pad 324, a number of gate fingers 326, and one or more gate buses 328 electrically connecting the gate fingers 326 to the gate pad 324. The gate pad 324 may be directly below and electrically connected to a gate bond pad 320, and the gate fingers 326 may extend horizontally across the device. An insulating layer (not shown) may cover the gate fingers 326 and the gate bus 328. A source metal pattern 332 may be formed on the insulating layer over the gate fingers 326. Source contacts of the source metal pattern 332 extend downward between the gate fingers 326 through openings in the insulating layer (not shown) and connect to corresponding source regions in the semiconductor layer structure. The MOSFET 310 includes a number of unit cell transistors 400 arranged in parallel. The location of one unit cell 400 is shown in FIG. 4B to provide context.

[0056] Figure 5A is a schematic plan view of a unit cell transistor 400 of the power MOSFET 310 of Figures 4A-4B. Figure 5B is a schematic cross-sectional view taken along line 5B-5B of Figure 5A. It will be understood that Figure 5B shows one complete unit cell 400 and portions of two additional unit cells 400 on either side of it to provide context.

[0057] 5A-5B, the unit cell transistor 400 may be formed on an n-type silicon carbide semiconductor substrate 410, such as a single crystal 4H silicon carbide semiconductor substrate that is heavily doped with n-type impurities. The doping concentration of the substrate 410 may be, for example, 1×10, although other doping concentrations may be used. 18 atoms / cm 3 ~1×10 21 atoms / cm 3 As used herein, the "doping concentration" of a semiconductor material refers to the number of dopant atoms that cause the semiconductor material to have a certain conductivity type (i.e., either n-type or p-type) present within one cubic centimeter of the semiconductor material, as measured using standard measurement techniques such as secondary ion mass spectrometry ("SIMS"). Unless otherwise indicated, for n-type semiconductor materials, references to the doping concentration will generally refer to the concentration of n-type dopants, and for p-type semiconductor materials, references to the doping concentration will generally refer to the concentration of p-type dopants. The substrate 410 can be of any suitable thickness (e.g., 100-500 micrometers). In some embodiments, the substrate 410 can be partially or entirely removed.

[0058] Lightly doped n-type (n - 1. An n-type silicon carbide drift region 420 is provided on the substrate 410. The n-type silicon carbide drift region 420 may be formed, for example, by epitaxial growth on the silicon carbide substrate 410. The n-type silicon carbide drift region 420 may have a size of, for example, 1×10 14 ~1×10 16 Dopant / cm 3n-type silicon carbide drift region 420 may have a doping concentration of 1×10 or more. N-type silicon carbide drift region 420 may be a thick region having a vertical height above substrate 410 of, for example, 3 to 100 micrometers. Although not shown in FIG. 5B, in some embodiments, an upper portion of n-type silicon carbide drift region 420 may be more highly doped than a lower portion thereof (e.g., 1×10 or more). 16 ~5×10 16 Dopant / cm 3 doping concentration).

[0059] A well region 430 is formed within the top of the n-type drift layer 420. The well region 430 includes a main well 432 and side wells 434 on either side of the main well 432. In some embodiments, the main well 432 and side wells 434 may be formed in the same process and may have the same p-type doping concentration as a function of depth. FIG. 5C is a graph showing an example doping profile of the well region 430 in such an embodiment. In other embodiments, the side wells 434 may be doped with a p-type dopant to a lower concentration than the main well 432 (e.g., the top of the main well 432 may be doped with a p-type dopant to a lower concentration ...) of 5×10 18 ~5×10 19 / cm 3 and the lower portion of the primary well 432 may have a p-type dopant concentration of 1×10 18 ~1×10 19 / cm 3 (The well region 430 may have a p-type dopant concentration of 1000 nM, while the lateral well 434 may have a doping concentration as shown in FIG. 5C.) After the well region 430 is formed, it is doped with a high concentration (n + ) N-type silicon carbide source regions 440 may be formed in the top of well regions 430. The n-type source regions 440 may be formed by ion implantation. JFET regions 422 are defined between the well regions 430 on top of the drift layer 420. The substrate 410, drift layer 420 (including JFET regions 422), well regions 430, and source regions 440 together comprise a semiconductor layer structure 450.

[0060] The well region 430 is formed by channeling ion implantation. For example, any of the channeling ion implantation techniques disclosed in U.S. Patent Application No. 15 / 168,310, filed May 31, 2016, may be used to form the well region 430. The entire contents of U.S. Patent Application No. 15 / 168,310 are incorporated by reference herein and expressly incorporated herein in their entirety. The use of channeling ion implantation allows the deep well region 430 to be formed, but at the same time using relatively low implantation energies. As a result, the surface of the semiconductor layer structure 450 may remain relatively undamaged. Additionally, the deep well region 430 may protect the gate insulating layer 470 from damage during reverse blocking operation and may further improve the short circuit capability of the device, as described in more detail below. Additionally, the use of channeling ion implantation allows the upper portion of the semiconductor layer structure 450 to be very lightly doped. Indeed, in some embodiments, the concentration of p-type dopants may be lower than the n-type doping level of the top of the n-type drift layer 420 (which may be doped n-type during its growth), such that at least the top of the lateral well 434 (where the channel region 436 is located) exhibits n-type conductivity with a very low effective n-type dopant concentration (where the effective n-type dopant concentration is the number of n-type dopants minus the number of p-type dopants). The provision of a very lightly doped n-type channel region 436 (at least to the top of the channel) may result in improved carrier mobility. For example, in some embodiments, the top 0.2 micrometers of the implanted portion of the semiconductor layer structure 450 may exhibit n-type conductivity (i.e., the top 0.2 micrometers of each well region 430 may exhibit n-type conductivity). In other embodiments, the top 0.5 micrometers of the implanted portion of the semiconductor layer structure 450 may exhibit n-type conductivity. In yet another embodiment, the top 0.7 micrometers of the implanted portion of semiconductor layer structure 450 may exhibit n-type conductivity. In yet another embodiment, the top 1.0 micrometers of the implanted portion of semiconductor layer structure 450 may exhibit n-type conductivity.In other embodiments, the lateral well 434 may have one of the doping profiles described above, with at least the upper 0.2, 0.5, 0.7, or 1.0 micrometers of the lateral well 434 exhibiting n-type conductivity, while the main well 432 may have a different doping profile than the lateral well 434 (e.g., the main well may not include any portions having n-type conductivity).

[0061] In some embodiments, the main well 432 and the lateral well 434 may be formed in a single channeling and ion implantation step. In other embodiments, the main well 432 and the lateral well 434 may be formed in separate channeling and ion implantation steps. The main well 432 and the lateral well 434 may be formed using any of the channeling and ion implantation techniques disclosed in the above-mentioned U.S. patent application Ser. No. 15 / 168,310. Because the well region 430 may include a first portion having n-type conductivity and a second portion having p-type conductivity, the region 430 is referred to herein as a "well region" rather than a "p-well."

[0062] When channeling ion implantation is used, dopant ions can be implanted very deep into the semiconductor layer structure 450 using a relatively low implantation energy. Because a low implantation energy is used, damage to the top surface of the semiconductor layer structure 450 due to ion implantation can be reduced. Such damage can reduce carrier mobility in the channel region 436, especially when the damage is near the top surface of the semiconductor layer structure 450 under the gate insulating layer 470. Because low energy channeling ion implantation causes less damage than conventional implantation, carrier mobility can be improved, resulting in faster switching times at a given threshold voltage.

[0063] Furthermore, channeling ion implantation enables the formation of deep well regions 430. For example, channeling ion implantation can be used to easily form extremely deep well regions 430, for example, having a depth of about 3 micrometers (or more), in the semiconductor layer structure 450 using relatively modest implantation energies, such as implantation energies of about 700 keV. The deep well regions 430 improve the short circuit capability of the MOSFET 310.

[0064] Providing deeper well regions 430 allows the width of JFET region 422 to be increased. This may reduce resistance in JFET region 422, thereby improving the on-state performance of MOSFET 310. In some embodiments, the depth (D) of each well region 430 exceeds the width (W) of JFET region 422. In other embodiments, the depth of each well region 430 may be at least 1.25 times the width of JFET region 422. In still other embodiments, the depth of each well region 430 may be at least 1.5 times the width of JFET region 422. In yet additional embodiments, the depth of each well region 430 may be at least two times the width of JFET region 422. In each of the above cases, the depth of each well region 430 may be less than four times the width of JFET region 422.

[0065] In some embodiments, the well regions 430 may have a depth of at least 1.5 micrometers, where the depth of each well region 436 is the vertical height of the well region along an axis perpendicular to the top surface of the semiconductor substrate 410. In other embodiments, the well regions 430 may have a depth of at least 2.0 micrometers. In yet other embodiments, the well regions 430 may have a depth of at least 2.5 micrometers. In still other embodiments, the well regions 430 may have a depth of at least 3.0 micrometers. In each of the above cases, the depth of the well regions 430 may be less than 6.0 micrometers. In one example embodiment, the depth of the well regions 430 may be about 3 micrometers and the width of the JFET region may be about 2.4 micrometers.

[0066] After the n-type source region 440 is formed, a gate insulating pattern 470 may be formed on the top surface of the semiconductor layer structure 450. The gate insulating pattern 470 may be formed directly on the semiconductor layer structure 450 without an intervening n-type epitaxial layer. The gate insulating pattern 470 may include, for example, a silicon oxide pattern, although other insulating materials may also be used. A gate electrode 472 is formed on the gate insulating pattern 470. The gate electrode 472 may include, for example, conductive gate fingers that function as gate electrodes for the multiple unit cell transistors 400.

[0067] A source contact 480 may be formed on the heavily doped n-type source region 440 and well region 430. Although not shown to simplify the drawing, the source contact 480 may be part of a continuous source pattern 332 that extends across the top surface of the silicon carbide semiconductor layer structure of the MOSFET 310 (see FIG. 4A). The source contact 480 may include, for example, a metal, such as nickel, titanium, tungsten, and / or aluminum, and / or a thin layer stack, and / or similar materials. A drain contact 490 may be formed on the bottom surface of the substrate 410. The drain contact 490 may include, for example, a material similar to the source contact, as it forms an ohmic contact to the silicon carbide substrate.

[0068] A channel region 436 is formed in the lateral well 434. The channel region 436 electrically connects the n-type source region 440 to the JFET region 422 when a sufficient bias voltage is applied to the gate electrode 472. Because the well region 430 is formed using channeling ion implantation, the channel region 436, which is a portion of the well region 430, is also formed by channeling ion implantation. When such a bias voltage is applied to the gate electrode 472, current can flow from the n-type source region 440 through the channel region 436 to the JFET region 422 and downward to the drain contact 490, as shown by the bold arrow in FIG. 5B.

[0069] 5C is a graph showing the doping profile (of p-type dopants) of the lateral well 434 of the unit cell transistor 400 as a function of depth from the top surface of the semiconductor layer structure 450. As shown in FIG. 5C, the p-type dopant concentration at the surface of the channel region 436 is very low, around 1×10 15 / cm 3 The p-type dopant concentration increases steeply over the first 0.9 micrometers, reaching approximately 8×10 16 / cm 3 The doping concentration then reaches a peak doping concentration of about 3x10 at a depth of about 2.8 micrometers. 16 / cm 3 The doping concentration then decreases rapidly, dropping below the detection level by a depth of 3.5 µm. The doping profile in Figure 5C shows a doping concentration of 1 x 10 13 / cm 3 The dose of Al + This can be achieved using channeling ion implantation, where the impurities are implanted into the silicon carbide drift layer 420 at room temperature. <0001> , <11-23>, <-1-123>, <1-213>, <-12-13>, <2-1-13>, or <-2113> crystal axes within ±1.5°. Any suitable dopant ions may be used. In some embodiments, the implantation may be performed at different temperatures, such as, for example, at temperatures of 75° C. or higher. The particular profile shown in FIG. 5C illustrates the 4H silicon carbide drift layer 420. <0001> This is achieved by performing channeling ion implantation along the crystal axis.

[0070] As grown, the top of drift region 420 may be, for example, 1×10 16 / cm 3 ~5×10 17 / cm 3 In some embodiments, the doping concentration may be greater than or equal to 2×10 16 / cm3 ~5×10 16 / cm 3 5C, the top 0.7-0.8 micrometers of each lateral well 434 (and in some embodiments the entire well region 430 except for the n-type source region 440) may have n-type conductivity despite the implantation of p-type dopants because the background doping level of the semiconductor layer is higher than the doping level of the ion implant in the upper portion of the lateral well 434. Thus, in effect, the equivalent of the n-type epitaxial layer 160 of the unit cell transistor 100 is formed in the unit cell transistor 400, but in a much simpler manner. The n-type regions provided at the top of each lateral well 434 may have a low doping concentration and therefore may exhibit very high carrier mobility.

[0071] 5C illustrates an exemplary doping profile of well region 430 that may be achieved when well region 430 is formed by channeled ion implantation, although it will be understood that a wide variety of different doping profiles may be achieved. For example, FIG. 6 is a graph illustrating doping profiles that may be achieved using channeled ion implantation performed under similar conditions as those described above with respect to FIG. 5C, but at different implant energies. In particular, curves 491-494 in FIG. 6 illustrate ... when ion implantation is performed on the 4H silicon carbide drift layer. <0001> 6A and 6B represent doping profiles obtained along the crystallographic axes when implantation energies of 100 keV, 300 keV, 500 keV, and 900 keV are performed, respectively. For comparison purposes, FIG. 6 further includes the doping profile of FIG. 5C, marked as curve 495, corresponding to an implantation energy of 700 keV.

[0072] Some MOSFETs according to embodiments of the present invention may exhibit a zero temperature coefficient ("ZTC") point in their transfer characteristics with respect to temperature. Figure 7 is a graph comparing transfer characteristic curves of a conventional power MOSFET including unit cell transistor 200 of Figure 2A at three different operating temperatures with equivalent transfer characteristic curves of a power MOSFET including unit cell transistor 200 of Figure 5B at the same three operating temperatures.

[0073] The solid curves 500, 510, and 520 in FIG. 7 are the gate-source voltages V V of a conventional power MOSFET including the unit cell transistor 200 of FIG. 2A. GS Each solid curve 500, 510, and 520 represents the drain current as a function of a drain-source voltage V of 20 volts. DS 7 is a plot of the drain current I DS increases more rapidly at higher temperatures. This indicates that, at least in the range of drain currents shown in FIG. 7, the conventional MOSFET has a positive temperature coefficient of threshold voltage. Since a higher drain current results in increased power dissipation (since P=V×I), under short-circuit conditions, the MOSFET will dissipate more power at an increased drain current I DS The feedback loop involves an increase in the drain current I DS This allows the MOSFET to have a very short duration short circuit capability.

[0074] The negative temperature coefficient of the drain current is a function of the gate-source voltage V GS Depending on the drain-source voltage V DS MOSFET drain current I DSThis can be understood by reference to Figure 7. The dashed curves 530, 540, and 550 in Figure 7 show the gate-source voltage V GS Drain current I according to DS Again, each of the dashed curves 530, 540, and 550 represents a drain-source voltage V of 20 volts. DS 7 is a plot of drain current as a function of gate voltage at temperatures of 25° C., 100° C., and 150° C. Curves 530, 540, and 550 show drain current as a function of gate voltage at temperatures of 25° C., 100° C., and 150° C., respectively. As can be seen in FIG. 7, when a MOSFET has a negative temperature coefficient for the drain current, the curves cross each other (in this figure, the curves cross at a gate voltage of about 15 volts), such that above this gate voltage level the drain current I DS is saturated more rapidly at higher temperatures. Thus, as temperature increases, the drain current I DS is reduced and the above-mentioned feedback loop does not occur. Therefore, a MOSFET according to an embodiment of the present invention having a negative temperature coefficient for the drain current may exhibit improved short circuit capability.

[0075] In particular, MOSFETs according to embodiments of the present invention may be configured to operate at a range of device-specific operating conditions (i.e., when the MOSFET is within the device-specific operating range, V GS , V DS , and I DS , MOSFETs may exhibit a negative temperature coefficient of drain current for operating temperatures of 25° C. and 150° C. at drain currents less than 50 amps. In other embodiments, MOSFETs may exhibit a negative temperature coefficient of drain current for operating temperatures of 25° C. and 150° C. at drain currents less than 40 amps. In still other embodiments, MOSFETs may exhibit a negative temperature coefficient of drain current for operating temperatures of 25° C. and 150° C. at drain currents less than 35 amps, or less than 30 amps.

[0076] MOSFETs according to embodiments of the present invention may achieve improved short circuit capability without sacrificing other performance parameters. For example, Figure 8 is a graph illustrating the voltage blocking characteristics of a MOSFET formed using unit cell 400 described above. As shown, the MOSFET exhibits a high voltage blocking level.

[0077] 9A and 9B are graphs showing the output characteristics of a conventional MOSFET and a MOSFET according to an embodiment of the present invention. As can be seen by comparing Figs. 9A and 9B, the forward conduction voltage drops of both devices are similar. Fig. 9A further shows how the conventional MOSFET has a positive temperature coefficient of threshold voltage, while Fig. 9B shows that the MOSFET according to an embodiment of the present invention has a negative temperature coefficient of drain current.

[0078] FIG. 10 is a flow chart of a method of forming a power MOSFET according to an embodiment of the invention. As shown in FIG. 10, the process may begin with the formation of a silicon carbide drift region on a substrate (block 600). The silicon carbide drift region may have a first conductivity type. Next, first and second well regions may be formed in an upper portion of the silicon carbide drift region by implanting a second conductivity type dopant into the upper portion of the silicon carbide drift region using channeling ion implantation (block 610). An upper portion of each of the first and second well regions may have a first conductivity type, while a lower portion of each of the first and second well regions may have a second conductivity type, where the second conductivity type is different from the first conductivity type. The first and second well regions may be adjacent to one another and may define a JFET region therebetween. A depth of the first well region may exceed a distance between the first and second well regions (i.e., may exceed a width of the JFET region).

[0079] MOSFETs according to embodiments of the present invention may have significantly improved short circuit capability while otherwise providing comparable or improved operating characteristics, such as blocking voltage capability and forward threshold voltage. By using channeling ion implantation techniques to form the well region, a relatively thick, lightly doped n-type region may be formed under the gate electrode, resulting in a channel with high mobility. Channeling ion implantation may further provide a favorable doping profile with a low p-type doping level near the surface and an even higher p-type doping level deeper in the well region. Furthermore, channeling ion implantation tends to cause low levels of damage, especially at the implantation surface, because ions tend to flow down the channel in the crystal structure of the semiconductor layer and therefore have a relatively low level of collisions near the surface. This may reduce surface damage and further improve carrier mobility in the channel region. Furthermore, channeling ion implantation allows for the formation of deep well regions, such as well regions having a depth of more than 1.5 micrometers. In some embodiments, the well region can have a depth of 2 microns, 3 microns, or more. The deeper well region allows the JFET region to have an extended width, which reduces the resistance of the JFET region and therefore improves the short circuit capability of the device.

[0080] While the above description focuses on n-channel MOSFETs, it will be appreciated that in accordance with further embodiments of the present invention, the polarity of each of the semiconductor layers within each device may be reversed to provide a corresponding p-channel MOSFET. Similarly, while the embodiments of the present invention described above are MOSFETs, it will be appreciated that the techniques disclosed herein may also be used to form insulated gate bipolar junction transistors (IGBTs), including MOSFETs in accordance with embodiments of the present invention.

[0081] In the present specification, embodiments of the present invention are described with reference to cross-sectional views showing one or two unit cells of a power switching device. It will be understood that actual implementations will typically include a much larger number of unit cells. However, it will be further understood that the present invention is not limited to such devices, and the claims appended hereto also encompass MOSFETs and other power switching devices, for example, comprising a single unit cell. It will be understood that, although the present disclosure focuses on silicon carbide devices, embodiments of the present invention may also have applicability to devices formed using other wide bandgap semiconductors, such as, for example, gallium nitride, zinc selenide, or any other II-VI or III-V wide bandgap compound semiconductor.

[0082] The present invention has been described above with reference to the accompanying drawings, which show examples of the invention. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the examples set forth herein. Rather, these examples are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the figures, the sizes and relative sizes of layers and regions may be exaggerated for clarity. When an element or layer is described as "on," "connected to," or "coupled to" another element or layer, it will be understood that it may be directly on, connected to, or coupled to another element or layer, or that intervening elements or layers may be present. In contrast, when an element is described as "directly on," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. Like numbers refer to like elements throughout.

[0083] Although the terms first and second are used herein to describe various regions, layers, and / or elements, it will be understood that these regions, layers, and / or elements should not be limited by these terms. These terms are used only to distinguish one region, layer, or element from another region, layer, or element. Thus, without departing from the scope of the present invention, a first region, layer, or element described below may be referred to as a second region, layer, or element, and similarly, a second region, layer, or element may be referred to as a first region, layer, or element.

[0084] Relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe the relationship of one element to another element, as shown in the figures. It will be understood that the relative terms are intended to encompass different orientations of the device in addition to the orientation shown in the figures. For example, if the device in the figures was turned over, an element described as being on the "lower" side of the other element would now be on the "upper" side of the other element. The illustrative term "lower" may thus encompass both a "lower" and an "upper" arrangement, depending on the particular orientation of the figure. Similarly, for example, if the device in one of the figures was turned over, an element described as being "lower" or "below" the other element would now be oriented as being on the "upper" side of the other element. The illustrative term "lower" or "below" may thus encompass both an upper and lower arrangement.

[0085] The terminology used herein is for the purpose of describing specific embodiments only and is not intended to be limiting of the present invention. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes," and / or "including," as used herein, specify the presence of stated features, elements, and / or components, but do not exclude the presence or addition of one or more other features, elements, components, and / or combinations thereof.

[0086] Embodiments of the invention have been described herein using cross-sectional illustrations that are schematic. Thus, variations from the shapes of the illustrations are to be expected, for example, as a result of manufacturing techniques and / or tolerances. Thus, embodiments of the invention should not be construed as limited to the particular shapes of regions illustrated herein, but are to include deviations in shapes that result, for example, from manufacturing. For example, implanted regions illustrated as rectangular will generally have rounded or curved features at their edges and / or a gradient of implant concentration rather than a binary transition from implanted to unimplanted regions. Thus, the regions illustrated in the figures are schematic in nature, and their shapes are not intended to represent the actual shapes of regions of a device, and are not intended to limit the scope of the invention.

[0087] It will be understood that the embodiments disclosed herein may be combined, such that features illustrated and / or described in relation to a first embodiment may be included in a second embodiment as well, and vice versa.

[0088] Although the above embodiments have been described with reference to certain figures, it will be understood that some embodiments of the invention may include additional and / or intervening layers, structures, or elements, and / or certain layers, structures, or elements may be omitted. Although a few exemplary embodiments of the invention have been described, those skilled in the art will readily appreciate that many variations are possible in the exemplary embodiments without substantially departing from the novel teachings and advantages of the invention. Accordingly, all such variations are intended to be included within the scope of the invention, as defined in the claims. Accordingly, it will be understood that the foregoing is illustrative of the invention and should not be construed as limited to the specific embodiments disclosed, and that modifications to the disclosed and other embodiments are intended to be included within the scope of the appended claims. The invention is defined by the following claims, with equivalents of the claims to be included therein.

Claims

1. 1. A method of forming a power MOSFET using semiconductor manufacturing equipment, comprising: providing a silicon carbide drift region having a first conductivity type; forming first and second well regions on top of the silicon carbide drift region, each of the first and second well regions including a respective side with a channel region, the sides being formed using a channeling ion implantation process that converts a lower portion of each channel region to a second conductivity type different from the first conductivity type while leaving an upper portion of each channel region having the first conductivity type under a gate electrode of a MOSFET; a depth of the first well region exceeds a distance between the first and second well regions; A method for forming a power MOSFET.

2. The method of claim 1 , wherein the first and second well regions each have a depth of at least 1.5 micrometers.

3. 3. The method of claim 1 or 2, wherein the first and second well regions each have a depth of at least 2.0 micrometers.

4. The doping concentration of the JFET region between the first well region and the second well region is 1×10 １６ / cm ３ ~5×10 １７ / cm ３ The method according to any one of claims 1 to 3, wherein

5. 5. The method of claim 1, wherein at least the top 0.4 micrometers of the first well region has the first conductivity type.

6. 6. The method of claim 1, wherein the distance between the first well region and the second well region is at least 2.0 micrometers and the depth of the first well region is at least 2.5 micrometers.

7. 7. The method of claim 1, wherein a second conductivity type dopant concentration in the first well region can vary by less than a factor of 3 from a depth of 1.0 to 2.0 micrometers from a top surface of the silicon carbide drift region.

8. 4. The method of claim 1, wherein the channel region and a central portion of the first well region have the same doping profile of a second conductivity type dopant as a function of depth from a top surface of the silicon carbide drift region.

9. 9. The method of any one of claims 1 to 3 and 8, wherein the channeling ion implantation is a channeling ion implantation that implants dopant impurities at an angle within ±1.5° of one of the <0001>, <11-23>, <-1-123>, <1-213>, <-12-13>, <2-1-13>, or <-2113> crystallographic axes of the silicon carbide drift region.

10. 10. The method of claim 1, wherein at least the top 0.2 micrometers of the first well region has the first conductivity type.

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