Semiconductor memory device and control method thereof

Abstract

A semiconductor memory device and a control method thereof capable of improving the sense margin of a sense amplifier even when an offset cancel operation sequence is executed for a plurality of sense amplifiers of each of a plurality of pages. The semiconductor memory device includes a control unit that executes an offset cancel operation sequence for each sense amplifier of each page, the offset cancel operation sequence including at least one predetermined operation of supplying a power supply voltage common to each page to the sense amplifier. When executing the offset cancel operation sequence for each of the multiple pages, the control unit is configured to control the timing of executing the offset cancel operation sequence for each page such that, while a predetermined operation is being performed in any of the multiple pages, a predetermined operation is not performed in any other page than the page.

Description

Technical Field

[0001] The present invention relates to a semiconductor memory device and a control method thereof.

Background Art

[0002] For example, a semiconductor memory device such as a DRAM (Dynamic Random Access Memory) is configured to read data by generating a weak potential difference between a pair of bit lines based on the data held in a memory cell and amplifying this potential difference by a sense amplifier. Here, the sense amplifier is provided with a pair of N-channel field effect transistors (nMOSFETs (Metal-Oxide-Semiconductor Field Effect Transistors)) and a pair of P-channel field effect transistors (pMOSFETs). However, due to the difference in capabilities (characteristic differences) of these transistors, an offset voltage that reduces the sense margin may occur.

[0003] Therefore, a semiconductor memory device configured to cancel the offset voltage is known (for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] In the technology described in Patent Document 1, an offset cancel operation for canceling the offset voltage of a sense amplifier, a charge sharing operation for activating a word line to generate the voltage of a sensing signal on a bit line, a pre-sensing operation for amplifying the voltage of the sensing signal, and a bit line charge operation (referred to as a restore operation in Patent Document 1) for transferring sensing data to a pair of bit lines are executed to perform an offset cancel operation sequence.

[0006] Also, the offset cancel operation sequence can be performed in page units including a plurality of memory cells. FIG. 1(a) shows an example of changes in the power supply voltage VBLH and the ground voltage VSS when the offset cancel operation sequence is executed in a single page (page 1 in the example of the figure). In the example shown in FIG. 1(a), an offset cancel operation (OC) is executed for a plurality of sense amplifiers each connected to a plurality of memory cells in page 1 between times t1 and t2, and a charge sharing operation (CS) is executed for the plurality of sense amplifiers between times t2 and t3. Also, a pre-sensing operation (PS) is executed for the plurality of sense amplifiers between times t3 and t4, and a bit line charge operation (BC) is executed for the plurality of sense amplifiers at time t4. Here, when three operations, namely the offset cancel operation (OC), the pre-sensing operation (PS), and the bit line charge operation (BC), among the offset cancel operation sequence are performed, each sense amplifier is connected to the power supply voltage VBLH and the ground voltage VSS. At this time, power supply noise is generated in the power supply voltage VBLH and the ground voltage VSS due to the current consumption of each sense amplifier.

[0007] Incidentally, a DRAM requires a memory retention operation called refresh to periodically charge the electric charge, and this refresh can generally be performed in units of a plurality of pages. In this case, as shown in FIG. 1(b), when an offset cancel operation sequence is simultaneously executed in a plurality of pages (in the example of the figure, four pages from page 1 to page 4), when three operations of an offset cancel operation (OC), a pre-sensing operation (PS), and a bit line charge operation (BC) are performed, the power supply noise generated in the common power supply voltage VBLH and the ground voltage VSS for each page increases. Therefore, when an offset cancel operation sequence is executed in a plurality of pages as in the case where a refresh is performed, there is a risk that the sense margin of the sense amplifier will decrease due to the influence of the power supply noise.

[0008] The present invention has been made in view of the above problems, and an object thereof is to provide a semiconductor memory device and a control method thereof capable of improving the sense margin of a sense amplifier even when an offset cancel operation sequence is executed for a plurality of sense amplifiers in each of a plurality of pages.

Means for Solving the Problems

[0009] In order to solve the above problems, the present invention includes a plurality of pages each including a plurality of memory cells connected to the same word line and a plurality of sense amplifiers connected to each memory cell, and for the plurality of sense amplifiers in each page, a control unit that executes an offset cancel operation sequence including at least one predetermined operation for supplying a common power supply voltage for each page to the sense amplifier, and when the control unit executes the offset cancel operation sequence in each of the plurality of pages, the control unit performs the predetermined operation in any one of the plurality of pages. A semiconductor memory device is provided that is configured to control the timing of executing the offset cancel operation sequence in each page so that the predetermined operation is not performed in other pages other than the any one page while the operation is being performed.

[0010] According to such an invention, among a plurality of pages, while a predetermined operation of supplying a common power supply voltage for each page to a sense amplifier is being performed on any one of the pages, control is performed so that the predetermined operation is not performed on other pages. Therefore, it is possible to suppress the power supply voltage from being simultaneously supplied to the sense amplifiers of each of the plurality of pages. As a result, for example, compared with the case where the sense amplifiers of each of the plurality of pages are connected to the power supply voltage, since it becomes possible to reduce the power supply noise generated in the power supply voltage, even when an offset cancellation operation sequence is executed for the plurality of sense amplifiers of each of the plurality of pages, the sense margin of the sense amplifier can be improved.

[0011] Further, the present invention is a control method for a semiconductor memory device, the semiconductor memory device including: a plurality of pages each including a plurality of memory cells connected to the same word line and a plurality of sense amplifiers connected to each memory cell; and a control unit that executes an offset cancellation operation sequence including at least one predetermined operation of supplying a common power supply voltage for each page to the sense amplifiers for the plurality of sense amplifiers of each page. When the control unit executes the offset cancellation operation sequence for each of the plurality of pages, the control unit executes a step of controlling the timing of executing the offset cancellation operation sequence for each page so that the predetermined operation is not performed on other pages other than the one page while the predetermined operation is being performed on any one of the plurality of pages. A control method for a semiconductor memory device is provided.

Advantages of the Invention

[0012] According to the semiconductor memory device and its control method of the present invention, even when an offset cancellation operation sequence is executed for the plurality of sense amplifiers of each of the plurality of pages, the sense margin of the sense amplifier can be improved.

Brief Description of the Drawings

[0013]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Embodiments for Carrying Out the Invention

[0014] FIG. 2 is a diagram showing a configuration example of a semiconductor memory device according to an embodiment of the present invention. As shown in FIG. 2, the semiconductor memory device includes a plurality of pages 10 and a control unit 100. Each of the plurality of pages 10 includes a plurality of memory cells (not shown) connected to the same word line and a plurality of sense amplifiers (SA) 11 connected to each memory cell.

[0015] In the present embodiment, the control unit 100 is configured to execute an offset cancellation operation sequence including at least one predetermined operation of supplying a common power supply voltage VBLH for each page to the plurality of sense amplifiers 11 on each page 10. Further, when executing the offset cancellation operation sequence in each of the plurality of pages 10, the control unit 100 controls the timing of executing the offset cancellation operation sequence in each page 10 so that a predetermined operation is not performed in any page other than any page while a predetermined operation is being performed in any one of the plurality of pages 10.

[0016] Here, the predetermined operation may include at least one of an offset cancellation operation (OC) of the sense amplifier 11, a pre-sensing operation (PS) of the sense amplifier, and a bit line charge operation (BC). Thereby, it becomes possible to control so that any one of the offset cancellation operation (OC), the pre-sensing operation (PS) of the sense amplifier, and the bit line charge operation (BC) is not performed in any other page 10 while any one of the offset cancellation operation (OC), the pre-sensing operation (PS) of the sense amplifier, and the bit line charge operation (BC) is being performed in any one of the plurality of pages 10.

[0017] Further, the offset cancellation operation sequence may include an offset cancellation operation (OC), a charge sharing operation (CS) of the sense amplifier 11 after the offset cancellation operation, a pre-sensing operation (PS) after the charge sharing operation (CS), and a bit line charge operation (BC) after the pre-sensing operation (PS). Thereby, since it becomes possible to reduce the offset voltage of the sense amplifier 11, the sense margin of the sense amplifier 11 can be improved.

[0018] Furthermore, when the control unit 100 refreshes a plurality of memory cells in each of the plurality of pages 10, it may be configured to execute an offset cancellation operation sequence for each of the plurality of sense amplifiers 11 in each of the plurality of pages 10. Thereby, even when the offset cancellation operation sequence is executed in the plurality of pages 10 when refreshing is performed, the sense margin of the sense amplifier 11 can be improved.

[0019] Furthermore, when a predetermined operation is being performed in any one of the pages 10 and a predetermined operation is started in another page 10, the control unit 100 may be configured to stop supplying the power supply voltage VBLH to the sense amplifier 11 in any one of the pages 10. Thereby, it becomes possible to suppress the supply of the power supply voltage VBLH to the sense amplifier 11 in any one of the pages 10 while the power supply voltage VBLH is being supplied to the sense amplifier 11 in another page 10.

[0020] Furthermore, when a predetermined operation is being performed in any one of the pages 10 and a predetermined operation is started in another page 10, the control unit 100 may be configured to start the predetermined operation in the other page 10 after the predetermined operation in any one of the pages 10 has ended. Thereby, it becomes possible to suppress the supply of the power supply voltage VBLH to the sense amplifier 11 in another page 10 while the power supply voltage VBLH is being supplied to the sense amplifier 11 in any one of the pages 10.

[0021] Referring to FIG. 3, a configuration example of the sense amplifier 11 will be described. As shown in FIG. 3, the sense amplifier 11 includes a pair of pMOSFETs 11a connected to the node CSP on the high-voltage power supply side, and a pair of nMOSFETs 11b connected to the node CSN on the low-voltage power supply side. Also, a pair of complementary bit lines BLT and BLB (hereinafter referred to as "a pair of bit lines BLT and BLB") are connected to the node between the pair of pMOSFETs 11a and the pair of nMOSFETs 11b. Here, the pair of pMOSFETs 11a is an example of "a pair of first transistors" of the present invention, and the pair of nMOSFETs 11b is an example of "a pair of second transistors" of the present invention. Further, in the present embodiment, the sense amplifier 11 includes a circuit for executing an offset cancellation operation sequence described in, for example, Patent Document 1. Note that in FIG. 3, for simplicity of explanation, MOSFETs and the like used as switches for enabling the offset cancellation operation sequence are omitted.

[0022] Next, referring to FIG. 4, a detailed configuration example of the control unit 100 will be described. In the example shown in FIG. 4, only one page 10 is shown for simplicity of explanation. As shown in FIG. 4, the control unit 100 includes a first control unit 110 and a second control unit 120. The first control unit 110 includes a CSP control unit 111 and a CSP driver 112. Further, the second control unit 120 includes a CSN control unit 121 and a CSN driver 122.

[0023] The CSP control unit 111 of the first control unit 110 includes a NOT circuit to which the voltage VGP is applied and the signal OC_EN_B is input. When a low-level signal OC_EN_B is input, the CSP control unit 111 outputs a high-level signal CSP_OC_EN. The voltage of the high-level signal CSP_OC_EN is equal to the voltage VGP. Also, the CSP driver 112 of the first control unit 110 includes an nMOSFET having a drain terminal connected to the power supply voltage VBLH, a source terminal connected to the node CSP of page 10, and a gate terminal to which the signal CSP_OC_EN is input.

[0024] The CSN control unit 121 of the second control unit 120 includes a NOT circuit to which a voltage VGN is applied and a signal OC_EN_B is input. When a low-level signal OC_EN_B is input, the CSN control unit 121 outputs a high-level signal CSN_OC_EN. The voltage of the high-level signal CSN_OC_EN is equal to the voltage VGN. Also, the CSN driver 122 of the second control unit 120 includes an nMOSFET having a drain terminal connected to the node CSN on page 10, a source terminal connected to the ground voltage VSS, and a gate terminal to which the signal CSN_OC_EN is input.

[0025] Also, the control unit 100 includes a voltage supply unit 130 that supplies an equalizer voltage VBLEQ. In the example shown in FIG. 4, the voltage supply unit 130 has three nMOSFETs connected to each other, and a signal CSEQ is input to the gate terminal of each nMOSFET. The drain terminal of the first nMOSFET among the three nMOSFETs is connected to the voltage VBLEQ, and the source terminal of the first nMOSFET is connected to the drain terminal of the second nMOSFET among the three nMOSFETs. The source terminal of the second nMOSFET is connected to the drain terminal of the third nMOSFET among the three nMOSFETs, and the source terminal of the third nMOSFET is connected to the voltage VBLEQ. Also, the node between the source terminal of the first nMOSFET and the drain terminal of the second nMOSFET is connected to the node CSP, and the node between the source terminal of the second nMOSFET and the drain terminal of the third nMOSFET is connected to the node CSN.

[0026] Furthermore, the control unit 100 includes an nMOSFET 140 having a drain terminal connected to the power supply voltage VBLH, a source terminal connected to the node CSP, and a gate terminal to which the signal BLC_EN is input. Furthermore, the control unit 100 includes an nMOSFET 150 having a drain terminal connected to the node CSN, a source terminal connected to the ground voltage VSS, and a gate terminal to which the signal BLC_EN is input.

[0027] In this embodiment, when the control unit 100 performs a charge sharing operation (CS) on any one of the plurality of pages 10, it may be configured to supply another voltage (here, the equalizer voltage VBLEQ) to the plurality of sense amplifiers 11 of any one of the pages 10 instead of the power supply voltage VBLH. Further, the other voltage (equalizer voltage VBLEQ) may be a voltage lower than the power supply voltage VBLH (for example, a voltage half of the power supply voltage VBLH, etc.). Thereby, when a charge sharing operation (CS) is performed on any one of the pages 10, since another voltage (equalizer voltage VBLEQ) is supplied to the plurality of sense amplifiers 11 of any one of the pages 10, it becomes possible to stop (suppress) the supply of the power supply voltage VBLH to the plurality of sense amplifiers 11 of any one of the pages 10.

[0028] With reference to FIG. 5, an example of the operation of the control unit 100 when an offset cancellation operation sequence is executed on any one of the plurality of pages 10 will be described. Here, it is assumed that an offset cancellation operation (OC) is performed between time t11 and time t12, a charge sharing operation (CS) is performed between time t12 and time t13, a pre-sensing operation (PS) is performed between time t13 and time t14, a bit line charge operation (BC) is performed between time t14 and time t15, a bit line charge hold operation (BCP) is performed between time t15 and time t16, and the bit line charge operation (BC) is resumed after time t16. Note that each of the operations of the offset cancellation operation (OC), the charge sharing operation (CS), the pre-sensing operation (PS), and the bit line charge operation (BC) may be the same as the operations described in Patent Document 1 mentioned above.

[0029] When the offset cancellation operation (OC) starts at time t11, the signal OC_EN_B and the signal CSEQ become low levels. Also, the signal BLC_EN is at a low level. As a result, a high-level signal CSP_OC_EN having the voltage VGP is input to the CSP driver 112, and the power supply voltage VBLH is connected to the node CSP. Here, the voltage VCSP supplied to the node CSP is a voltage dropped from the power supply voltage VBLH by the on-resistance of the nMOSFET of the CSP driver 112. Also, a high-level signal CSN_OC_EN having the voltage VGN is input to the CSN driver 122, and the ground voltage VSS is connected to the node CSN. Then, the voltage VCSN is supplied to the node CSN.

[0030] When the charge sharing operation (CS) starts at time t12, the signal OC_EN_B and the signal CSEQ become high levels. Also, the signal BLC_EN is at a low level. As a result, the CSP driver 112 turns off and the connection between the power supply voltage VBLH and the node CSP is disconnected, and the CSN driver 122 turns off and the connection between the ground voltage VSS and the node CSN is disconnected. Also, the equalizer voltage VBLEQ is supplied from the voltage supply unit 130 to the nodes CSP and CSN. In this way, when the charge sharing operation is performed in any of the pages 10, another voltage (the equalizer voltage VBLEQ) is supplied to each sense amplifier 11 of any of the pages 10. Note that at time t12, a voltage is applied to the word line WL to be accessed.

[0031] When the pre-sensing operation (PS) starts at time t13, the signal OC_EN_B and the signal CSEQ become low levels. Also, the signal BLC_EN is at a low level. As a result, similar to time t11, the power supply voltage VBLH is connected to the node CSP, and the ground voltage VSS is connected to the node CSN. Then, the voltage VCSP is supplied to the node CSP, and the voltage VCSN is supplied to the node CSN.

[0032] At time t14, when a pair of bit lines BLT and BLB are cut off (isolated) from the nodes of the sense amplifier 11 (nodes N1 and N2 in the example of FIG. 3), the bit line charge operation (BC) starts. Here, the operation of cutting off the pair of bit lines BLT and BLB from the nodes of the sense amplifier 11 (nodes N1 and N2) may be the same as the operation described in Patent Document 1 mentioned above.

[0033] Next, for example, when a predetermined operation (e.g., pre-sensing operation (PS)) starts in another page 10 other than any one of the plurality of pages 10, at time t15, the bit line charge hold operation (BCP) starts. At this time, the signal OC_EN_B becomes high level. Also, the signals CSEQ and BLC_EN are low level. In this case, since each of the nodes CSP and CSN is not connected to any voltage, the nodes CSP and CSN are in a floating state.

[0034] Then, for example, when the pre-sensing operation (PS) ends in all of the plurality of pages 10, at time t16, the bit line charge operation (BC) resumes. At this time, the signal OC_EN_B becomes high level, and the signal CSEQ becomes low level. Also, the signal BLC_EN becomes high level. Thereby, the power supply voltage VBLH is supplied to the node CSP via the nMOSFET 140, and the ground voltage VSS is supplied to the node CSN via the nMOSFET 150.

[0035] In this way, an offset cancellation operation sequence is executed in any one of the pages 10.

[0036] Referring to FIG. 6, an example of the change in the power supply voltage and the ground voltage when the offset cancellation operation sequence is executed in the plurality of pages 10 in the present embodiment will be described.

[0037] Here, as shown in FIG. 6, when N (N is an integer of 2 or more) pages are provided, the control unit 100 may be configured to start an offset cancellation operation (OC) on the (i + 1)-th page when the offset cancellation operation (OC) ends on the i-th page (where i is an integer from 1 to N). Thereby, it becomes possible to shift the timing at which the offset cancellation operation sequence starts for every plurality of pages 10.

[0038] Further, as shown in FIG. 6, the control unit 100 may be configured to simultaneously perform bit line charge operations (BC) on all of the plurality of pages 10 when the presensing operations (PS) are completed on all of the plurality of pages 10. In this case, since the content of the sensing data of each sense amplifier 11 of each of the plurality of pages 10 has already been determined by the presensing operation (PS), even if the bit line charge operations (BC) are simultaneously performed on all of the plurality of pages 10, it becomes possible to transfer correct data to a pair of bit lines BLT, BLB.

[0039] In the example shown in FIG. 6, the control unit 100 controls the timing of executing the offset cancellation operation sequence on each page 10 (that is, controls the logic levels of the signals OC_EN_B, CSEQ, BLC_EN transmitted to each page 10) so that a predetermined operation (for example, offset cancellation operation (OC), presensing operation (PS), or bit line charge operation (BC)) is not performed on other pages 10 (pages 2 to 4) other than any page 10 (for example, page 1) while a predetermined operation (for example, offset cancellation operation (OC), presensing operation (PS), or bit line charge operation (BC)) is being performed on any page 10 (for example, page 1).

[0040] Also, in the example shown in FIG. 6, when a predetermined operation (e.g., bit line charge operation (BC)) is being performed on any page 10 (e.g., page 1) and a predetermined operation (e.g., pre-sensing operation (PS)) is started on another page 10 (e.g., page 2), the control unit 100 stops supplying the power supply voltage VBLH to the sense amplifier 11 on any page 10 (page 1) (i.e., performs an operation in which the power supply voltage VBLH is not supplied to the sense amplifier 11 (here, bit line charge hold operation (BCP))).

[0041] Furthermore, in the example shown in FIG. 6, when a predetermined operation (e.g., offset cancellation operation (OC)) is being performed on any page 10 (e.g., page 1) and a predetermined operation (e.g., offset cancellation operation (OC)) is started on another page 10 (e.g., page 2), after the predetermined operation (offset cancellation operation (OC)) is completed on any page 10 (page 1), the control unit 100 starts the predetermined operation (offset cancellation operation (OC)) on another page 10 (page 2).

[0042] By suppressing the simultaneous supply of the power supply voltage VBLH and the ground voltage VSS to each sense amplifier 11 of a plurality of pages 10 in this way, as shown in FIG. 6, it is possible to reduce the power supply noise generated in the power supply voltage VBLH and the ground voltage VSS.

[0043] As described above, according to the semiconductor memory device and its control method of the present embodiment, while a predetermined operation of supplying the common power supply voltage VBLH for each page to the sense amplifier 11 is being performed in any one of the plurality of pages 10, control is performed so that the predetermined operation is not performed in the other pages 10. Therefore, it is possible to suppress the power supply voltage VBLH from being simultaneously supplied to each of the sense amplifiers 11 of the plurality of pages 10. As a result, for example, compared with the case where each of the sense amplifiers 11 of the plurality of pages 10 is connected to the power supply voltage VBLH, it becomes possible to reduce the power supply noise generated in the power supply voltage VBLH. Therefore, even when an offset cancellation operation sequence is executed for each of the plurality of sense amplifiers 11 of the plurality of pages 10, it is possible to improve the sense margin of the sense amplifier.

[0044] In the above-described embodiment, the case where the control unit 100 includes the first control unit 110, the second control unit 120, the voltage supply unit 130, and the nMOSFETs 140 and 150 has been described as an example. However, the present invention is not limited to this case. For example, the control unit 100 may be configured by other circuits having the same effects as those of the above-described embodiment.

Explanation of Reference Numerals

[0045] 10... Page 11... Sense Amplifier (SA) 11a... Pair of P-channel Field Effect Transistors (pMOSFETs) 11b... Pair of N-channel Field Effect Transistors (nMOSFETs) 100... Control Unit 110... First Control Unit 111... CSP Control Unit 112... CSP Driver 120... Second Control Unit 121... CSN Control Unit 122... CSN Driver BLC_EN, CSEQ, CSP_OC_EN, CSN_OC_EN, OC_EN_B... Signals VBLEQ... Equalizer Voltage VBLH…Power supply voltage VSS…Ground voltage

Claims

1. A plurality of pages each including a plurality of memory cells connected to the same word line and a plurality of sense amplifiers connected to each of the memory cells; a control unit that executes an offset cancel operation sequence including at least one predetermined operation of supplying a power supply voltage common to each page to the sense amplifiers of each page, the control unit is configured to control a timing of executing the offset cancel operation sequence for each page when the offset cancel operation sequence is executed for each of the plurality of pages, so that while the predetermined operation is being executed for any one of the plurality of pages, the predetermined operation is not executed for any other page than the one of the plurality of pages. Semiconductor memory device.

2. the control unit is configured to execute the offset cancel operation sequence for the plurality of sense amplifiers of each of the plurality of pages when refreshing the plurality of memory cells of each of the plurality of pages.

2. The semiconductor memory device according to claim 1.

3. the control unit is configured to stop supplying the power supply voltage to a sense amplifier in one of the pages when the predetermined operation is started in the other page while the predetermined operation is being performed in the one of the pages.

2. The semiconductor memory device according to claim 1.

4. the control unit is configured to, when starting the predetermined operation on the other page while the predetermined operation is being performed on one of the pages, start the predetermined operation on the other page after the predetermined operation on the one of the pages is completed.

2. The semiconductor memory device according to claim 1.

5. The predetermined operation includes at least one of an offset cancel operation of a sense amplifier, a pre-sensing operation of the sense amplifier, and a bit line charge operation.

2. The semiconductor memory device according to claim 1.

6. The offset cancel operation sequence includes the offset cancel operation, a charge sharing operation of a sense amplifier after the offset cancel operation, the pre-sensing operation after the charge sharing operation, and the bit line charging operation after the pre-sensing operation.

6. The semiconductor memory device according to claim 5.

7. the control unit is configured to supply another voltage, instead of the power supply voltage, to the plurality of sense amplifiers of the any one of the plurality of pages when the charge sharing operation is performed in the any one of the plurality of pages.

7. The semiconductor memory device according to claim 6.

8. The other voltage is a voltage lower than the power supply voltage.

8. The semiconductor memory device according to claim 7.

9. the control unit is configured to start the offset cancel operation on an (i+1)th page when the offset cancel operation on an (i)th page (wherein N is an integer equal to or greater than 1) is completed in a case where N pages (wherein N is an integer equal to or greater than 2) are provided.

7. The semiconductor memory device according to claim 6.

10. the control unit is configured to simultaneously perform the bit line charging operation in all of the plurality of pages when the pre-sensing operation is completed in all of the plurality of pages.

7. The semiconductor memory device according to claim 6.

11. Each of the plurality of sense amplifiers includes a pair of first transistors and a pair of second transistors.

2. The semiconductor memory device according to claim 1.

12. one of the pair of first transistors and the pair of second transistors is an N-channel type field effect transistor, and the other of the pair of first transistors and the pair of second transistors is a P-channel type field effect transistor; The semiconductor memory device according to claim 11.

13. A method for controlling a semiconductor memory device, comprising: The semiconductor memory device includes: A plurality of pages each including a plurality of memory cells connected to the same word line and a plurality of sense amplifiers connected to each of the memory cells; a control unit that executes an offset cancel operation sequence including at least one predetermined operation of supplying a power supply voltage common to each page to the sense amplifiers of each page, The control unit: executing a step of controlling a timing of executing the offset cancel operation sequence for each page such that, when the offset cancel operation sequence is executed for each of the plurality of pages, the predetermined operation is not executed for any page other than the given page while the given operation is being executed for any page among the plurality of pages; A method for controlling a semiconductor memory device.

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