Light-emitting device, optical device, measuring device, and information processing device

Abstract

To provide a configuration for irradiating, via a circular optical element, an irradiation region shaped to be elongated in a first direction with light emitted from a plurality of two-dimensionally arranged surface-emitting laser element groups that are drivable independently of each other, in which the size of the circular optical element is efficiently used as compared with a configuration in which the plurality of surface-emitting laser element groups are arranged in a shape similar to that of the irradiation region.SOLUTION: A surface emitting laser element array includes a multiple surface-emitting laser element groups. In an arrangement region where the multiple surface-emitting laser element groups are arranged, the number of surface-emitting laser element groups arranged in a first direction is larger than the number of surface-emitting laser element groups arranged in a second direction perpendicular to the first direction. An irradiation region irradiated with light emitted from the multiple surface-emitting laser element groups has a shape elongated in the first direction. The arrangement region in which the multiple surface-emitting laser element groups are arranged has an aspect ratio closer to 1:1 than the irradiation region.SELECTED DRAWING: Figure 4

Description

Technical Field

[0001] The present invention relates to a surface-emitting laser element array, a light-emitting device, an optical device, a measuring device, and an information processing device.

Background Art

[0002] Patent Document 1 describes a light-emitting element array in which a large number of light-emitting elements whose threshold voltage or threshold current can be controlled by light from the outside are arranged one-dimensionally, two-dimensionally, or three-dimensionally, and at least a part of the light generated from each light-emitting element is incident on other light-emitting elements in the vicinity of each light-emitting element, and a clock line for applying a voltage or current from the outside is connected to each light-emitting element.

[0003] Patent Document 2 describes a self-scanning type light-emitting device in which a light-emitting element having a pnpnpn six-layer semiconductor structure is configured, electrodes are provided on the p-type first layer and n-type sixth layer at both ends, and the p-type third layer and n-type fourth layer in the center, the pn layer has a light-emitting diode function, and the pnpn four-layer has a thyristor function.

[0004] Patent Document 3 describes a self-scanning type light source head including a substrate, a surface-emitting semiconductor laser arranged in an array on the substrate, and a thyristor as a switch element that is arranged on the substrate and selectively turns on and off the light emission of the surface-emitting semiconductor laser.

[0005] Patent Document 4 describes a light-emitting device including a light-emitting unit in which a plurality of light-emitting element groups each having a plurality of light-emitting elements are arranged, and along the arrangement, for each of the plurality of light-emitting element groups, a plurality of light-emitting elements included in the light-emitting element group are sequentially set to a state of emitting light or not emitting light in parallel.

Prior Art Documents

Patent Documents

[0006]

Patent Document 1

Patent Document 2

[0007] When measuring the three-dimensional shape of an object to be measured based on the so-called ToF (Time of Flight) method using the flight time of light, the object to be measured may be irradiated with light from a plurality of surface-emitting laser element groups. In a configuration in which light emitted from a plurality of surface-emitting laser element groups arranged two-dimensionally and independently drivable of each other is irradiated onto an irradiation region having a shape elongated in a first direction via a circular optical element, the size of the circular optical element is effectively utilized as compared with the case where the plurality of surface-emitting laser element groups are arranged in a shape similar to the irradiation region. [Means for Solving the Problems]

[0008] The invention according to claim 1 is a surface-emitting laser element array in which a plurality of surface-emitting laser element groups each including a plurality of surface-emitting laser elements and independently drivable from each other are two-dimensionally arranged, and in an arrangement region where the plurality of surface-emitting laser element groups are arranged, the number of surface-emitting laser element groups arranged along a first direction is larger than the number of surface-emitting laser element groups arranged along a second direction orthogonal to the first direction, the shape of an irradiation region irradiated by the plurality of surface-emitting laser element groups is a shape having the first direction as its longitudinal direction, and the aspect ratio of the arrangement region where the plurality of surface-emitting laser element groups are arranged is closer to 1:1 than the aspect ratio of the irradiation region, a surface-emitting laser element array, a lens which has a size including the plurality of surface-emitting laser element groups included in the surface-emitting laser element array and is provided in an emission path of the plurality of surface-emitting laser element groups and narrows a divergence angle of light emitted from the plurality of surface-emitting laser element groups, and a diffusion member which diffuses light emitted from the plurality of surface-emitting laser element groups included in the surface-emitting laser element array and transmitted through the optical element and emits the light by spreading it over the irradiation region, or a diffraction member which diffracts the light transmitted through the optical element and emits the light by spreading it over the irradiation region, and is provided with , the plurality of surface-emitting laser element groups are formed on a common semiconductor substrate, and the plurality of surface-emitting laser elements of each surface-emitting laser element group are stacked with a thyristor that emits light from the plurality of surface-emitting laser elements by transitioning to an on state, and have a gate signal line connected to the gate of the thyristor. The gate signal line of the first surface-emitting laser element group in the plurality of surface-emitting laser element groups passes between the laser elements of the second surface-emitting laser element group. A light-emitting device. The invention according to claim 2 is the light-emitting device according to claim 1, characterized in that the length of the arrangement region in the first direction is 0.8 times or more and 1.2 times or less the length of the arrangement region in the second direction. The invention according to claim 3 is the light-emitting device according to claim 1, characterized in that the length of the arrangement region in the first direction is 0.9 times or more and 1.1 times or less the length of the arrangement region in the second direction. The invention according to claim 4 is the light-emitting device according to claim 1, characterized in that the length of the arrangement region in the first direction is 0.95 times or more and 1.05 times or less the length of the arrangement region in the second direction. The invention according to claim 5 is the light-emitting device according to any one of claims 1 to 4, characterized in that in each of the surface-emitting laser element groups, the number of surface-emitting laser elements arranged along the second direction is larger than the number of surface-emitting laser elements arranged along the first direction. Claim 6 The invention according to claim , wherein the plurality of surface emitting laser elements in each surface emitting laser element group of the plurality of surface emitting laser element groups are connected in parallel to each other, is the light emitting device according to any one of claims 1 to 5 . Claim 7 The invention according to claim , which is characterized by having a driving unit that independently drives each surface emitting laser element group of the plurality of surface emitting laser element groups, is the light emitting device according to any one of claims 1 to 6 . Claim 8 The invention according to claim , wherein the driving unit sequentially emits light from each surface emitting laser element group of the plurality of surface emitting laser element groups, is the light emitting device according to claim 7 . Claim 9 The invention according to claim is an optical device including the light emitting device according to any one of claims 1 to , and a light receiving unit that receives reflected light emitted from a plurality of surface emitting laser element groups included in the light emitting device and reflected by an object to be measured. 8 Claim 10 The invention according to claim is a measuring device including the optical device according to claim , and a three-dimensional shape specifying unit that measures a three-dimensional shape based on the time from when light is emitted from a plurality of surface emitting laser element groups included in the optical device until the light is received by the light receiving unit included in the optical device, and specifies the three-dimensional shape of the object to be measured. 9 Claim 11 The invention according to claim is an information processing device including the measuring device according to claim , and an authentication processing unit that performs authentication processing related to the use of the device based on the specification result by the three-dimensional shape specifying unit included in the measuring device. 10 [Effect of the Invention]

[0009] According to the invention described in claim 1, the size of the circular optical element can be effectively utilized as compared with the case where a plurality of surface emitting laser element groups are arranged in a shape similar to the irradiation region. ​​​According to the invention described in claim 2, the size of the circular optical element can be effectively utilized as compared with the case where the length of the array region in the first direction is less than 0.8 times or more than 1.2 times the length in the second direction. According to the invention described in claim 3, the size of the circular optical element can be more effectively utilized as compared with the case where the length of the array region in the first direction is less than 0.9 times or more than 1.1 times the length in the second direction. According to the invention described in claim 4, the size of the circular optical element can be further effectively utilized as compared with the case where the length of the array region in the first direction is less than 0.95 times or more than 1.05 times the length in the second direction. According to the invention described in claim 5, the surface emitting laser elements can be arranged so that the size of the circular optical element can be effectively used as compared with the case where the number of the plurality of surface emitting laser elements arranged along the second direction is smaller than the number arranged along the first direction in each of the surface emitting laser element groups. Claim 6 According to the invention described in, the deterioration of the light emission characteristics is suppressed as compared with the case where the plurality of surface emitting laser elements in the surface emitting laser element group are not connected in parallel to each other. Claim 7 According to the invention described in, the driving of the surface emitting laser element group becomes easier as compared with the case where there is no driving unit for independently driving the surface emitting laser element group. Claim 8 According to the invention described in, the lighting control of the surface emitting laser element group becomes easier as compared with the case where the surface emitting laser element group is not caused to emit light sequentially. Claim 9 According to the invention described in, an optical device capable of performing three-dimensional measurement is provided. Claim 10 According to the invention described in, a measuring device capable of measuring a three-dimensional shape is provided. Claim 11 According to the invention described in, an information processing apparatus equipped with an authentication process based on a three-dimensional shape is provided.

Brief Description of the Drawings

[0010]

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Embodiments for Carrying Out the Invention

[0011] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Among measuring devices for measuring the three-dimensional shape of an object to be measured, there is a device that measures the three-dimensional shape based on the so-called ToF (Time of Flight) method using the flight time of light. In the ToF method, the time from the timing when light is emitted from a light-emitting device provided in the measuring device until the timing when the irradiated light is reflected by the object to be measured and received by a three-dimensional sensor (hereinafter referred to as a 3D sensor) provided in the measuring device is measured, and the three-dimensional shape of the object to be measured is specified from the measured three-dimensional shape. Note that the object for measuring the three-dimensional shape is referred to as the object to be measured. The three-dimensional shape may be referred to as a three-dimensional image. Also, measuring the three-dimensional shape may be referred to as three-dimensional measurement, 3D measurement, or 3D sensing.

[0012] Such a measuring device is installed in a portable information processing device or the like and is used for face authentication of a user attempting to access. Conventionally, in a portable information processing device or the like, methods for authenticating a user have been used, such as passwords, fingerprints, irises, etc. In recent years, there has been a growing demand for authentication methods with higher security. Therefore, a measuring device for measuring the three-dimensional shape has been installed in the portable information processing device. That is, the three-dimensional shape of the face of the accessed user is acquired, whether access is permitted or not is identified, and the use of the own device (portable information processing device) is permitted only when the accessed user is authenticated as a permitted user.

[0013] Here, the information processing device will be described as a portable information processing terminal as an example, and it will be described that the user is authenticated by recognizing the shape of the face captured as a three-dimensional shape. Note that the information processing device can be applied to information processing devices such as personal computers (PCs) other than portable information processing terminals.

[0014] The configurations, functions, methods, etc. described in this embodiment can also be applied to measuring objects other than the face and recognizing the measured object from the measured three-dimensional shape. Further, such a measuring device is also applicable to cases where the three-dimensional shape of the measured object is continuously measured, such as augmented reality (AR). Also, the distance to the measured object is not limited.

[0015] [First Embodiment] (Information Processing Device 1) FIG. 1 is a diagram showing an example of the information processing device 1. As described above, the information processing device 1 is a portable information processing terminal as an example. The information processing apparatus 1 includes a user interface unit (hereinafter referred to as the UI unit) 2 and an optical device 3 for measuring a three-dimensional shape. The UI unit 2 is configured by integrating, for example, a display device that displays information to the user and an input device through which an instruction for information processing is input by the user's operation. The display device is, for example, a liquid crystal display or an organic EL display, and the input device is, for example, a touch panel.

[0016] The optical device 3 includes a light emitting device 4 and a three-dimensional sensor (hereinafter referred to as a 3D sensor) 5. The light emitting device 4 irradiates light toward the object to be measured, here the face in this example. The 3D sensor 5 acquires the light irradiated by the light emitting device 4 and reflected back by the face. Here, the three-dimensional shape is measured based on the so-called ToF method using the time of flight of light. Then, the three-dimensional shape of the face is specified from the three-dimensional shape. As described above, the three-dimensional shape may be measured using an object other than the face as the object to be measured. The 3D sensor 5 is an example of a light receiving unit.

[0017] The information processing apparatus 1 is configured as a computer including a CPU, a ROM, a RAM, etc. Note that the ROM includes a non-volatile rewritable memory, for example, a flash memory. Then, the programs and constants stored in the ROM are expanded in the RAM, and the information processing apparatus 1 operates and various information processes are executed when the CPU executes the programs.

[0018] FIG. 2 is a block diagram for explaining the configuration of the information processing apparatus 1. The information processing apparatus 1 includes the above-described optical device 3, a measurement control unit 8, and a system control unit 9. The measurement control unit 8 controls the optical device 3. And the measurement control unit 8 includes a three-dimensional shape specifying unit 8A. The system control unit 9 controls the entire information processing apparatus 1 as a system. And the system control unit 9 includes an authentication processing unit 9A. And the UI unit 2, a speaker 9B, a two-dimensional camera (denoted as a 2D camera in FIG. 2), etc. are connected to the system control unit 9.

[0019] The three-dimensional shape specifying unit 8A included in the measurement control unit 8 measures the three-dimensional shape from the reflected light from the object to be measured and specifies the three-dimensional shape of the object to be measured. The authentication processing unit 9A included in the system control unit 9 identifies whether access is permitted or not from the three-dimensional shape specified by the three-dimensional shape specifying unit 8A, and authenticates the user whose access is permitted. In FIG. 2, the measuring device 6 includes an optical device 3 and a measurement control unit 8.

[0020] (Light emitting device 4) FIG. 3 is a diagram for explaining a state in which light is irradiated toward the object to be measured by the light emitting device 4. Here, the light emitting device 4 shows a state as viewed from the side opposite to the side that emits light (this is referred to as the back side). The light emitting device 4 and the irradiation region 40 are arranged to face each other, but in FIG. 3, the light emitting device 4 and the irradiation region 40 are shown shifted in the vertical direction of the paper surface. Note that the irradiation region 40 is a plane orthogonal to the direction of the light emitted by the light emitting device 4 at a certain distance in the direction of the light emitted by the light emitting device 4, and is a region where the light emitted by the light emitting device 4 is irradiated toward the object to be measured. Here, the left direction of the paper surface is defined as the x direction, the upper direction of the paper surface is defined as the y direction, and the back side direction of the paper surface is defined as the z direction.

[0021] The irradiation region 40 has a length Sx in the x direction and a length Sy in the y direction. And the length Sx in the x direction is larger than the length Sy in the y direction (Sx > Sy). That is, the irradiation region 40 has a shape with the x direction as the longitudinal direction.

[0022] The light-emitting device 4 is configured such that a group of surface-emitting laser elements including a plurality of surface-emitting laser elements, as described later, are two-dimensionally arranged in the array region 100. The array region 100 has a length Lx in the x direction and a length Ly in the y direction. And, the ratio of the length Lx in the x direction to the length Ly in the y direction, that is, the aspect ratio of the array region 100 is set to be close to 1:1. Note that the length Lx in the x direction may be 0.8 times or more and 1.2 times or less the length Ly in the y direction. Further, the length Lx in the x direction is more preferably 0.9 times or more and 1.1 times or less the length Ly in the y direction. And, the length Lx in the x direction is even more preferably 0.95 times or more and 1.05 times or less the length Ly in the y direction. The surface-emitting laser element is an example of a light-emitting element, and the group of surface-emitting laser elements is an example of a group of light-emitting elements.

[0023] As described above, the shape of the array region 100 in which the group of surface-emitting laser elements in the light-emitting device 4 is arranged is set to be different from and not similar to the shape of the irradiation region 40. Note that the x direction is an example of a first direction, and the y direction is an example of a second direction orthogonal to the first direction.

[0024] FIG. 4 is a diagram for explaining the light-emitting device 4. FIG. 4(a) is a plan view of the light-emitting device 4, and FIG. 4(b) is a cross-sectional view of the light-emitting device 4 taken along line IVB-IVB in FIG. 4(a). In FIG. 4(a), unlike FIG. 3, the light-emitting device 4 shows a state as viewed from the light-emitting side (this is referred to as the front side). Therefore, the right direction of the paper surface is the x direction, the upward direction of the paper surface is the y direction, and the front direction of the paper surface is the z direction. The plan view is a view of the light-emitting device 4 as viewed from the +z direction side. Further, in FIG. 4(b), the right direction of the paper surface is the x direction, the upward direction of the paper surface is the y direction, and the back direction of the paper surface is the z direction.

[0025] As shown in FIG. 4(b), the light-emitting device 4 includes a surface-emitting laser element array 10, a condenser lens 60, and a diffusion member 30 from the lower side (-y direction side). The surface-emitting laser element array 10 includes a plurality of surface-emitting laser elements. Here, as an example, the surface-emitting laser element is a vertical cavity surface emitting laser (VCSEL). In the following, the light-emitting element will be described as a VCSEL. And the vertical cavity surface emitting laser element VCSEL is denoted as VCSEL. Therefore, the surface-emitting laser element array 10 is denoted as VCSEL array 10. In FIG. 4(b), light is schematically shown with hatching.

[0026] As shown in FIG. 4(a), a surface-emitting laser element group is formed by a plurality of surface-emitting laser elements (VCSELs). Note that the surface-emitting laser element group is denoted as a VCSEL group. The region where the VCSEL groups are arranged is the arrangement region 100. Here, as shown in FIG. 4(a), eight VCSEL groups including seven VCSELs are formed. When distinguishing each VCSEL group, it is denoted as VCSEL group #1 to #8. The VCSEL groups are arranged such that four are arranged in the x direction and two are arranged in the y direction. That is, in the arrangement region 100, the number of VCSEL groups arranged in the x direction is larger than the number in the y direction. Note that the number of VCSELs included in the VCSEL groups may be the same or different.

[0027] And the seven VCSELs in each VCSEL group are arranged such that two are arranged in the x direction and four are arranged in the y direction. In each VCSEL group, no VCSEL is provided in the upper right side of the paper surface. This is for providing a p-type ohmic electrode (see FIG. 8 described later). Note that the position of the p-type ohmic electrode may be shifted and a VCSEL may be provided. Therefore, it is assumed that two are arranged in the x direction and four are arranged in the y direction. That is, in each VCSEL group, the number of VCSELs in the y direction is larger than the number in the x direction. Here, when the VCSELs in each VCSEL group are denoted as VCSELij (i, j ≥ 1), "i" is the number of the VCSEL group, and "j" is the number of the VCSEL within the VCSEL group. Here, VCSEL group #1 includes VCSEL11 to VCSEL17. As shown in VCSEL group #1 in Fig. 4(a), in each VCSEL group, the VCSELij where j is from 1 to 3 and the VCSELij where j is from 4 to 8 are arranged in the -y direction. And the VCSELij where j is from 1 to 3 and the VCSELij where j is from 4 to 8 are arranged in parallel in the -x direction. At this time, VCSELi1 and VCSELi5, VCSELi2 and VCSELi6, and VCSELi3 and VCSELi7 are arranged to be aligned in the x direction.

[0028] In this specification, "~" indicates a plurality of components that are each distinguished by numbers, and it means including those described before and after "~" and those with the numbers in between. For example, VCSEL11~17 includes VCSEL11 to VCSEL17 in numerical order.

[0029] As shown in Fig. 4(b), the condenser lens 60 is provided on the path of the light emitted by each VCSEL (which may be referred to as the emission path), narrows the divergence angle of the light emitted by each VCSEL, and makes it incident on the diffusion member 30. The diffusion member 30 is designed to have a predetermined function when parallel light is incident. The VCSEL emits light with a divergence angle determined by its structure. Therefore, even if the light emitted by the VCSEL is directly incident on the diffusion member 30, the diffusion member 30 cannot perform the designed function. Therefore, the condenser lens 60 narrows the divergence angle of the light emitted by the VCSEL and makes it incident on the diffusion member 30. Note that the divergence angle refers to the full width at half maximum (FWHM) of the light emitted by the VCSEL. The condenser lens 60 is an example of an optical element.

[0030] The light-collecting lens 60 is, for example, a plano-convex lens with a flat side on the -y direction side, having a length Cx in the x direction and a length Cy in the y direction. Here, it is assumed to be circular with the length Cx in the x direction being the same as the length Cy in the y direction (Cx = Cy). Note that the circular shape includes, for example, an elliptical shape where the length Cx in the x direction is 0.95 times and 1.05 times the length Cy in the y direction. The major axis of the ellipse is not limited to being in the x direction or the y direction. The light-collecting lens 60 is an example of a lens and is not limited to a plano-convex lens.

[0031] The diffusion member 30 includes, for example, a resin layer with irregularities formed on the back surface (-z direction) side of a glass substrate with parallel and flat surfaces on both sides to diffuse light. The diffusion member 30 is provided on the emission path of each VCSEL emitted through the light-collecting lens 60, expands the divergence angle of the incident light, and emits light to the irradiation region 40. That is, the diffusion member 30 refracts and scatters light due to the irregularities formed in the resin layer, and spreads and emits the incident light to the irradiation region 40. The diffusion member 30 has a length Dx in the x direction and a length Dy in the y direction. Note that instead of the diffusion member 30, a diffractive member such as a diffractive optical element (DOE) that changes and emits light in a direction different from the direction of the incident light may be used.

[0032] In Fig. 4(b), although not shown, the VCSEL array 10 is provided on a circuit board not shown, and the light-collecting lens 60 and the diffusion member 30 are held at a predetermined distance from the VCSEL array 10 by a holding member not shown provided on the circuit board.

[0033] As shown in FIG. 4(a), the array region 100 of the VCSELs is set so that the aspect ratio is close to 1:1. And a condenser lens 60 is provided so as to include the array region 100. By doing so, the area of the circular condenser lens 60 (which may be referred to as size) is effectively used. As described above, in each VCSEL group, the VCSELs are arranged such that the number in the y direction is larger than the number in the x direction, and the VCSEL groups are arranged such that the number in the x direction is larger than the number in the y direction. As a result, the aspect ratio of the array region 100 is close to 1:1.

[0034] FIG. 5 is a diagram showing the array region 100 of the light-emitting device 4 to which the first embodiment is applied and the array region 100' of the light-emitting device 4' to which the first embodiment is not applied for comparison. FIG. 5(a) is the array region 100 of the light-emitting device 4 to which the first embodiment is applied, and FIG. 5(b) is the array region 100' of the light-emitting device 4' to which the first embodiment is not applied. FIGS. 5(a) and 5(b) show the light-emitting devices 4 and 4' and the irradiation region 40 shifted in the vertical direction of the paper surface in the same manner as FIG. 3. Further, in the light-emitting devices 4 and 4', the diffusion members 30 are shown separately. It is assumed that both the light-emitting devices 4 and 4' include eight VCSEL groups (VCSEL groups #1 to #8).

[0035] The irradiation region 40 is the same for the light-emitting device 4 to which the first embodiment is applied and the light-emitting device 4' to which the first embodiment is not applied. That is, the irradiation region 40 has a shape with the length Sx in the x direction being larger than the length Sy in the y direction and having the x direction as the longitudinal direction.

[0036] In the light-emitting device 4 to which the first embodiment is applied, shown in FIG. 5(a), the aspect ratio (length Lx: length Ly) of the array region 100 is provided to be close to 1:1. That is, the irradiation region 40 and the array region 100 are not similar shapes. In this case, the shape of the array region 110 of the VCSEL group #1 and the shape of the irradiation region 41 irradiated by the VCSEL group #1 are not similar shapes.

[0037] On the other hand, in the light-emitting device 4' to which the first embodiment is not applied as shown in FIG. 5(b), the array region 100' is provided in a similar shape to the irradiation region 40. That is, when the length in the x-direction of the array region 100' is Lx' and the length in the y-direction is Ly', with the proportionality coefficient being k, the length Lx' in the x-direction of the array region 100' is Sx / k, and the length Ly' in the y-direction of the array region 100' is Sy / k. In this case, the shape of the array region 110' of the VCSEL group #1 and the shape of the irradiation region 41 irradiated by the VCSEL group #1 are similar. Then, as shown in FIG. 5(b), the vertical portions of the circular condenser lens 60' are not utilized. For this reason, if the area of the array region 100' is the same as the area of the array region 100, a condenser lens 60' larger than the condenser lens 60 of the light-emitting device 4 to which the first embodiment is applied will be used.

[0038] As described above, the light-emitting device 4 to which the first embodiment is applied effectively utilizes the area of the condenser lens 60 as compared with the light-emitting device 4' to which the first embodiment is not applied.

[0039] (Equivalent Circuit of VCSEL Array 10) FIG. 6 is an example of an equivalent circuit of the VCSEL array 10 in the light-emitting device 4 to which the first embodiment is applied. Here, a control unit 50 for controlling the operation of the VCSEL array 10 is also shown. The left direction on the paper surface is the y-direction. Note that the control unit 50 is provided in the measurement control unit 8 in FIG. 2. The VCSEL array 10 includes a plurality of VCSELs. As an example, as in FIG. 4(a), one VCSEL group is composed of 7 VCSELs. In FIG. 6, 4 VCSEL groups (VCSEL groups #1 to #4) are shown.

[0040] And the VCSEL array 10 includes a setting thyristor S for each VCSEL group. The VCSEL group and the setting thyristor S are connected in series. And for the setting thyristor S as well, the number "i" of the VCSEL group will be attached. That is, the setting thyristor S included in the VCSEL group #1 is the setting thyristor S1.

[0041] The VCSEL array 10 further includes a plurality of transfer thyristors T, a plurality of coupling diodes D, a plurality of power line resistors Rg, a start diode SD, and current limiting resistors R1 and R2. Here, when distinguishing each of the plurality of transfer thyristors T, they are distinguished by attaching "i", which is the number of the VCSEL group, such as transfer thyristors T1, T2, T3, .... The same applies to the coupling diodes D and the power line resistors Rg. As will be described later, for example, the transfer thyristor T1 is provided to correspond to the VCSEL group #1.

[0042] FIG. 6 shows the portions corresponding to i = 1 to 4. "i" in the VCSEL array 10 may be a predetermined number. For example, it may be 128, 512, 1024, etc. The number of transfer thyristors T may be the same as the number of VCSEL groups. Note that the number of transfer thyristors T may exceed the number of VCSEL groups or may be less.

[0043] The transfer thyristors T are arranged in the -y direction in the order of transfer thyristors T1, T2, T3, .... The coupling diodes D are arranged in the -y direction in the order of coupling diodes D1, D2, D3, .... Note that the coupling diode D1 is provided between the transfer thyristor T1 and the transfer thyristor T2. The same applies to the other coupling diodes D. Also, the power line resistors Rg are arranged in the -y direction in the order of power line resistors Rg1, Rg2, Rg3, ....

[0044] The VCSEL and the coupling diode D are two-terminal elements having an anode and a cathode. The setting thyristor S and the transfer thyristor T are three-terminal elements having an anode, a cathode, and a gate. Note that the gate of the transfer thyristor T is denoted as gate Gt, and the gate of the setting thyristor S is denoted as gate Gs. When distinguishing each of them, "i" is attached in the same manner as described above. Here, the portion composed of the VCSEL is defined as the light emitting part 12, and the portion composed of the setting thyristor S, the transfer thyristor T, the coupling diode D, the start diode SD, the power line resistor Rg, and the current limiting resistors R1 and R2 is defined as the driving part 11.

[0045] Next, the connection relationships of each element (such as VCSEL, setting thyristor S, transfer thyristor T, etc.) will be described. As described above, VCSELij and setting thyristor Si are connected in series. That is, for setting thyristor Si, the anode is connected to the reference potential Vsub (such as ground potential (GND)), and the cathode is connected in parallel to the anode of VCSELij. The cathode of VCSELij is commonly connected to a lighting signal line 76 to which a lighting signal φI for controlling VCSELij to be in a light-emitting / non-light-emitting state is supplied.

[0046] The reference potential Vsub is supplied through a back surface electrode 90 (refer to FIGS. 7 and 8 described later) provided on the back surface of the substrate 80 constituting the VCSEL array 10, as will be described later.

[0047] For transfer thyristor T, the anode is connected to the reference potential Vsub. For odd-numbered transfer thyristors T1, T3,... the cathodes are connected to a transfer signal line 72. The transfer signal line 72 is connected to the φ1 terminal through a current limiting resistor R1. For even-numbered transfer thyristors T2, T4,... the cathodes are connected to a transfer signal line 73. The transfer signal line 73 is connected to the φ2 terminal through a current limiting resistor R2.

[0048] The coupling diodes D are connected in series with each other. That is, the cathode of one coupling diode D is connected to the anode of the adjacent coupling diode D in the -y direction. For start diode SD, the anode is connected to the transfer signal line 73, and the cathode is connected to the anode of coupling diode D1.

[0049] Then, the cathode of start diode SD and the anode of coupling diode D1 are connected to the gate Gt1 of transfer thyristor T1. The cathode of coupling diode D1 and the anode of coupling diode D2 are connected to the gate Gt2 of transfer thyristor T2. The same applies to other coupling diodes D.

[0050] The gate Gt of the transfer thyristor T is connected to the power supply line 71 via the power supply line resistance Rg. The power supply line 71 is connected to the Vgk terminal. And the gate Gt of the transfer thyristor T and the gate Gs of the setting thyristor S are connected by the wiring 75. That is, the gate Gti of the transfer thyristor Ti and the gate Gsi of the setting thyristor Si are connected by the wiring 75-i. When distinguishing the wiring 75, as described above, "i" may be added and it may be denoted as the wiring 75-i. In FIG. 6, the portions where i is 1 to 4 are shown. The wiring 75 is an example of a gate signal line.

[0051] The configuration of the control unit 50 will be described. The control unit 50 generates signals such as the lighting signal φI and supplies them to the VCSEL array 10. The VCSEL array 10 operates according to the supplied signals. The control unit 50 is composed of an electronic circuit. For example, the control unit 50 may be an integrated circuit (IC) configured to control the operation of the VCSEL array 10. The control unit 50 includes a transfer signal generation unit 51, a lighting signal generation unit 52, a power supply potential generation unit 53, and a reference potential generation unit 54.

[0052] The transfer signal generation unit 51 generates transfer signals φ1 and φ2, and supplies the transfer signal φ1 to the φ1 terminal of the VCSEL array 10 and the transfer signal φ2 to the φ2 terminal of the VCSEL array 10. The lighting signal generation unit 52 generates the lighting signal φI and supplies it to the φI terminal of the VCSEL array 10 via the current limiting resistor RI. Note that the current limiting resistor RI may be provided inside the VCSEL array 10. Also, when the current limiting resistor RI is not necessary for the operation of the VCSEL array 10, the current limiting resistor RI may not be provided.

[0053] The power supply potential generation unit 53 generates a power supply potential Vgk and supplies it to the Vgk terminal of the VCSEL array 10. The reference potential generation unit 54 generates a reference potential Vsub and supplies it to the Vsub terminal of the VCSEL array 10. The power supply potential Vgk is, for example, -3.3V. The reference potential Vsub is, as described above, the ground potential (GND) as an example.

[0054] Regarding the transfer signals φ1 and φ2 generated by the transfer signal generation unit 51 and the lighting signal φI generated by the lighting signal generation unit 52, they will be described later.

[0055] In the VCSEL array 10 shown in FIG. 6, seven VCSELs ij (j = 1 to 7) are connected to one transfer thyristor Ti as a VCSEL group via the setting thyristor Si. As will be described later, when the transfer thyristor Ti is turned on, the setting thyristor Si connected to the transfer thyristor Ti can be set to the on state. Therefore, since it is set to a state where the VCSEL can emit light, it is denoted as the setting thyristor S. Also, when the setting thyristor Si becomes on, the VCSEL ij emits light. Note that the transfer thyristor Ti is driven so as to transfer the on state in the order of "i". That is, in the transfer thyristor Ti, the on state propagates in order. Thereby, the transfer thyristor Ti sequentially lights (emits light) the VCSEL group. Here, one VCSEL group is composed of a plurality of VCSELs. And for each transfer thyristor T, a VCSEL group is connected, and the plurality of VCSELs included in the VCSEL group emit light in parallel.

[0056] In the example shown in FIG. 6, each VCSEL group includes the same number (here, seven) of VCSELs, but the number of VCSELs may be different between VCSEL groups.

[0057] The VCSEL preferably oscillates in a low-order single transverse mode (single mode). In the single mode, the intensity profile of the light (emitted light) emitted from the light-emitting point of the VCSEL (the light-emitting port 310 in FIG. 8 described later) is unimodal (a characteristic with one intensity peak). On the other hand, in a VCSEL that oscillates in a multi-transverse mode (multi-mode) including higher orders, the intensity profile tends to be distorted, such as having multiple peaks. Also, in the single mode, the divergence angle of the light (emitted light) emitted from the light-emitting point is smaller than that in the multi-mode.

[0058] And, the smaller the area of the light-emitting point of the VCSEL, the easier it is to oscillate in a single transverse mode (single mode). For this reason, the single-mode VCSEL has a small optical output. If the area of the light-emitting point is increased in an attempt to increase the optical output, it easily shifts to the multi-mode. Therefore, a plurality of VCSELs are grouped as a VCSEL group, and the plurality of VCSELs included in the VCSEL group are made to emit light in parallel to increase the optical output.

[0059] (Planar layout of the VCSEL array 10) FIG. 7 is a diagram showing an example of the planar layout of the VCSEL array 10 to which the first embodiment is applied. In FIG. 7, the upward direction on the paper surface is the x direction, and the left direction is the y direction. The VCSEL array 10 is composed of a semiconductor material capable of emitting laser light. For example, the VCSEL array 10 is composed of a GaAs-based compound semiconductor. As shown in the cross-sectional view (Figure 8 described later), the VCSEL array 10 is configured by separating a semiconductor layer stack in which a plurality of GaAs-based compound semiconductor layers are stacked into a plurality of island shapes on a p-type GaAs substrate 80. The regions left in island shapes are called islands. Etching the semiconductor layer stack into island shapes to separate the elements is called mesa etching. Here, the planar layout of the VCSEL array 10 will be described with reference to the islands 301 to 306 shown in Figure 7. Islands 301, 302, and 303 are provided for each VCSEL group. Therefore, when distinguishing islands 301, 302, and 303 for each VCSEL group, an "i" may be added as described above, and they may be denoted as island 301-i, 302-i, and 303-i. In Figure 7, the parts where i is from 1 to 8 are shown. Also, the number of VCSELs in the VCSEL group is denoted as "j" as described above. Here, j is from 1 to 7. In this way, the VCSEL array 10 is configured on a common semiconductor substrate. Therefore, the light-emitting device 4 is miniaturized.

[0060] In island 301-i, a VCSELij and a setting thyristor Si are provided. As shown in Figure 8 described later, the VCSELij and the setting thyristor Si are stacked. In Figure 7, the VCSELij and the setting thyristor Si are denoted as VCSELij / Si. For example, when "i" is 1, it is denoted as VCSEL1j / S1. The islands 301-i where i is from 1 to 4 and the islands 301-i where i is from 5 to 8 are arranged in parallel in the -x direction. And the islands 301-i where i is from 1 to 4 and the islands 301-i where i is from 5 to 8 are arranged in parallel in the -y direction.

[0061] In island 301-i, as shown in VCSEL group #1 in Figure 4(a), seven VCSELs are arranged. No reference numerals are attached.

[0062] Island 302-i is provided with a transfer thyristor Ti and a coupling diode Di. Islands 302-i are provided in parallel in the -y direction.

[0063] Island 303-i is provided with a power line resistance Rgi. Islands 303-i are provided in parallel in the -y direction.

[0064] Island 304 is provided with a start diode SD. Island 305 is provided with a current limiting resistor R1, and Island 306 is provided with a current limiting resistor R2.

[0065] (Cross-sectional structure of VCSEL array 10) Next, before explaining the connection relationships of these islands 301 to 306, the cross-sectional structures of islands 301 and 302 will be explained.

[0066] FIG. 8 is a diagram showing the cross-sectional structure of VCSEL array 10. Note that FIG. 8 is a cross-sectional view of VCSEL array 10 taken along line VIII-VIII in FIG. 7. That is, the cross-sectional view shown in FIG. 8 is a cross-section that crosses the coupling diode D1, transfer thyristor T1, VCSEL11 / S1, and VCSEL12 / S1 from the left side on the paper surface. That is, it shows the portions of islands 301-1 and 302-1.

[0067] First, island 301-1 provided with the setting thyristor S and the VCSEL will be explained. Here, the setting thyristor S and the VCSEL are stacked and configured (VCSEL11 / S1, VCSEL12 / S1). As shown in FIG. 8, on a p-type GaAs substrate 80, a p-type anode layer (hereinafter referred to as the p-anode layer. The same applies hereinafter.) 81, an n-type gate layer (n-gate layer) 82, a p-type gate layer (p-gate layer) 83, and an n-type cathode layer (n-cathode layer) 84 that constitute the setting thyristor S1 are stacked. That is, the setting thyristor S is configured with the p-anode layer 81 as the anode, the n-gate layer 82 as the n-gate, the p-gate layer 83 as the p-gate, and the n-cathode layer 84 as the cathode.

[0068] Next, a tunnel junction layer 85 is laminated on the n cathode layer 84. Then, on the tunnel junction layer 85, a p-type anode layer (p anode layer) 86, a light-emitting layer 87, and an n-type cathode layer (n cathode layer) 88 that constitute the VCSELs 11 and 12 are laminated. That is, the VCSEL is configured with the p anode layer 86 as the anode, the light-emitting layer 87 as the light-emitting layer, and the n cathode layer 88 as the cathode. The setting thyristor S1, the VCSELs 11, and 12 are connected in series via the tunnel junction layer 85. The tunnel junction layer 85 will be described later.

[0069] In the portions of the VCSELs 11 and 12, the n cathode layer 88, the light-emitting layer 87, and the p anode layer 86 are removed by etching so that the tunnel junction layer 85 around the VCSEL is exposed. Here, the cross-sectional shape of the VCSEL is circular. That is, the portion of the VCSEL is formed in a columnar shape. Therefore, the portion of the VCSEL is denoted as the post 311 (see FIG. 7).

[0070] The p anode layer 81, the n gate layer 82, the p gate layer 83, the n cathode layer 84, and the tunnel junction layer 85 that constitute the setting thyristor S are continuous among the VCSELs (VCSELs 11 to 17) belonging to the VCSEL group #1.

[0071] Also, in the island 301-1, on the portion where the tunnel junction layer 85 and the n cathode layer 84 are further removed to expose the p gate layer 83, a p ohmic electrode 331 made of a metal material that easily forms an ohmic contact with a p-type semiconductor layer such as the p gate layer 83 is provided as the gate Gs1 of the setting thyristor S1.

[0072] An n ohmic electrode 321 made of a metal material that easily forms an ohmic contact with an n-type semiconductor layer such as the n cathode layer 88 is provided on the n cathode layer 88 of the VCSEL. Note that the n ohmic electrode 321 is provided in a circular shape so as to surround the light emission port 310 (see FIG. 7).

[0073] The p-anode layer 86 of the post 311 includes a current constriction layer 86b. Here, as an example, the p-anode layer 86 is composed of three layers: a lower p-anode layer 86a, a current constriction layer 86b, and an upper p-anode layer 86c. The current constriction layer 86b is made of a material with a high Al composition ratio, such as AlAs. When Al becomes Al 2 O 3 by oxidation, a layer is formed in which the electrical resistance increases and the current flow becomes difficult (the blackened part in Fig. 8).

[0074] Since the post 311 is provided in a columnar shape, when the current constriction layer 86b is oxidized from the side surface of the exposed p-anode layer 86, the oxidation proceeds from the peripheral part to the central part in the circular cross-section. By not oxidizing the central part, the central part in the cross-section of the VCSEL becomes a current passing region 86d where the current easily flows, and the peripheral part becomes a current blocking region 86e where the current hardly flows. Note that the VCSEL emits light in a part where the current path is restricted by the current passing region 86d of the light emitting layer 87. The region on the surface of the VCSEL corresponding to this current passing region 86d is the light emitting point and the light output port 310.

[0075] The current constriction layer 86b is provided to oscillate the VCSEL in a low-order single transverse mode (single mode). That is, by making the cross-sectional shape of the post 311 in which the VCSEL is formed circular and oxidizing from the peripheral part, the cross-sectional shape of the light output port 310 is made circular and the area is reduced. In addition, there are many defects caused by mesa etching in the peripheral part of the VCSEL, and non-radiative recombination easily occurs. Therefore, by providing the current blocking region 86e, the power consumed by non-radiative recombination is suppressed. Thus, low power consumption and improvement of the light extraction efficiency can be achieved. Note that the light extraction efficiency is the amount of light that can be extracted per unit power.

[0076] Next, the island 302-1 provided with the transfer thyristor T1 and the coupling diode D1 will be described. The transfer thyristor T1, like the setting thyristor S, is composed of a p anode layer 81, an n gate layer 82, a p gate layer 83, and an n cathode layer 84. That is, the transfer thyristor T1 is configured with the p anode layer 81 as the anode, the n gate layer 82 as the n gate, the p gate layer 83 as the p gate, and the n cathode layer 84 as the cathode. Here, a gate electrode (p ohmic electrode 332 described later) is provided on the p gate layer 83.

[0077] The coupling diode D1 is composed of a p gate layer 83 and an n cathode layer 84. That is, the coupling diode D1 is configured with the p gate layer 83 as the anode and the n cathode layer 84 as the cathode.

[0078] In the island 302-1, the n cathode layer 88, the light-emitting layer 87, the p anode layer 86, and the tunnel junction layer 85 in the portion where the setting thyristor S and the VCSEL are stacked are removed. And in the portion of the transfer thyristor T1 and the portion of the coupling diode D1, the n cathode layer 84 is removed so that the n cathode layer 84 remains as the post 312 and the post 313.

[0079] An n ohmic electrode 322 is provided as the cathode electrode of the transfer thyristor T1 on the n cathode layer 84 of the post 312. Similarly, an n ohmic electrode 323 is provided as the cathode electrode of the coupling diode D1 on the n cathode layer 84 of the post 313.

[0080] The p ohmic electrode 332 provided on the p gate layer 83 functions as the gate Gt1 of the transfer thyristor T1 and the anode electrode of the coupling diode D1.

[0081] And an interlayer insulating layer 91 is provided so as to cover the surface. On the interlayer insulating layer 91, via through-holes (openings), a wiring 75-1 that connects a p-ohmic electrode 331 (gate Gs1) provided in the island 301-1 and a p-ohmic electrode 332 (gate Gt1) provided in the island 302-1, and a wiring 75-2 that connects a p-ohmic electrode (gate Gs2) provided in the island 301-2 and a p-ohmic electrode (gate Gt1) provided in the island 302-2 are provided. Also, on the interlayer insulating layer 91, a transfer signal line 72 connected to the n-ohmic electrode 322 is provided. And on the interlayer insulating layer 91, a transfer signal line 73 is provided. Further, on the interlayer insulating layer 91, a wiring 74-2 connected to the n-ohmic electrode 323 via a through-hole is provided.

[0082] Furthermore, an interlayer insulating layer 92 is provided so as to cover the surface. And on the interlayer insulating layer 92, a lighting signal line 76 connected to the n-ohmic electrode 321 provided in the island 301-1 is provided via through-holes provided in the interlayer insulating layer 92 and the interlayer insulating layer 91. That is, the wiring 75 (wiring 75-1, 75-2) and the lighting signal line 76 have a multilayer wiring structure via the interlayer insulating layer 92.

[0083] In addition, when the interlayer insulating layers 91 and 92 have poor transparency to the emitted light of the VCSEL, an optical emission layer having excellent transparency to the emitted light of the VCSEL may be provided instead of the interlayer insulating layers 91 and 92 on the optical emission port 310.

[0084] The islands 301, 302, 303, 304, 305, and 306 are separated from each other by being removed by etching until the surrounding semiconductor layer stack reaches the substrate 80. Note that etching may be performed until reaching the p-anode layer 81, or etching may be performed until reaching a part in the thickness direction of the p-anode layer 81.

[0085] Returning to FIG. 7, other islands 303, 304, 305, and 306 will be described. In island 303, a power line resistance Rg1 is configured. In island 303-1, the n cathode layer 88, light emitting layer 87, p anode layer 86, tunnel junction layer 85, and n cathode layer 84 in the semiconductor layer stack are removed, exposing the p gate layer 83. A pair of p ohmic electrodes are provided on the exposed p gate layer 83. And the p gate layer 83 between the p ohmic electrodes is used as a resistor.

[0086] In island 304, a start diode SD is provided. In island 304, the n cathode layer 88, light emitting layer 87, p anode layer 86, and tunnel junction layer 85 in the semiconductor layer stack are removed. And except for the post 314 where the n cathode layer 84 remains, the p gate layer 83 is exposed. For the start diode SD, the n cathode layer 84 constituting the post 314 is the cathode, and the p gate layer 83 is the anode. And the n ohmic electrode provided on the n cathode layer 84 of the post 314 is the cathode electrode, and the p ohmic electrode provided on the exposed p gate layer 83 is the anode electrode.

[0087] In island 305, a current limiting resistor R1 is provided, and in island 306, a current limiting resistor R2 is provided. Islands 305 and 306 have the same configuration as island 303, and the p gate layer 83 between the pair of p ohmic electrodes provided on the exposed p gate layer 83 is used as the current limiting resistors R1 and R2, respectively.

[0088] The connection relationship between islands 301 to 306 and the islands will be described. As described above, the n cathode layer 88, which is the cathode of the VCSEL provided at the post 311 of island 301-1, is connected in parallel to the lighting signal line 76 via the n ohmic electrode 321. The same applies to the other islands 301. The n-cathode layer 88, which is the cathode of the transfer thyristor T1 provided at the post 312 of the island 302-1, is connected to the transfer signal line 72 via the n-ohmic electrode 322. Note that the same applies to the transfer thyristor T3 provided in the island 302-3 (the third island 302 located on the -y direction side). That is, the cathode (n-cathode layer 88) of the transfer thyristor Ti with an odd-numbered i is connected to the transfer signal line 72.

[0089] On the other hand, the cathode (n-cathode layer 88) of the transfer thyristor T2 provided in the island 302-2 (the second island 302 located on the -y direction side) is connected to the transfer signal line 73. That is, the cathode (n-cathode layer 88) of the transfer thyristor Ti with an even-numbered i is connected to the transfer signal line 73.

[0090] The p-ohmic electrode 331, which is the gate Gs1 of the island 301-1, and the p-ohmic electrode 332, which is the gate Gt1 of the island 301-2, are connected by the wiring 75-1. The cathode (n-cathode layer 88) of the coupling diode D1 provided at the post 313 of the island 302-1 is connected to the wiring 74-2 via the n-ohmic electrode 323 (see FIG. 8). The wiring 74-2 is connected to the p-ohmic electrode (not labeled) of the adjacent island 302-2 and the p-ohmic electrode (not labeled) of the power line resistance Rg2 of the island 303-2.

[0091] The p-ohmic electrode 333 provided in the island 302-1 (provided on the p-gate layer 83 in the same manner as the p-ohmic electrode 332 of the gate Gt1), one p-ohmic electrode of the power line resistance Rg1 provided in the island 303-1, and the n-ohmic electrode, which is the cathode electrode of the start diode SD provided in the island 304, are connected by the wiring 74-1.

[0092] Also, the other p-ohmic electrode of the power line resistance Rg1 of the island 303-1 is connected to the power line 71. The power line 71 is connected to the Vgk terminal. The same applies to the other islands 303.

[0093] The transfer signal line 72 is connected to one p-ohmic electrode (not labeled) of the current limiting resistor R1 of the island 305. The other p-ohmic electrode (not labeled) of the current limiting resistor R1 is connected to the φ1 terminal. The transfer signal line 73 is connected to the p-ohmic electrode of the start diode SD of the island 303 and is also connected to one p-ohmic electrode (not labeled) of the current limiting resistor R2 of the island 306. The other p-ohmic electrode (not labeled) of the current limiting resistor R2 of the island 306 is connected to the φ2 terminal.

[0094] In the above, the islands 301-1, 302-1, 303-1 have been described as examples, but the same applies to the other islands 301, 302, 303. Therefore, in FIG. 7, for example, it is denoted as such as the wiring 74-1 (74), indicating that the same applies to the other wirings 74.

[0095] <Thyristor> Next, the operations of the setting thyristor S and the transfer thyristor T will be described. The setting thyristor S and the transfer thyristor T are collectively referred to as the thyristor. The thyristor is composed of a p-anode layer 81, an n-gate layer 82, a p-gate layer 83, and an n-cathode layer 84 laminated. As described above, the thyristor is a semiconductor element having three terminals of anode, cathode, and gate, and is composed of, for example, p-type semiconductor layers (p-anode layer 81, p-gate layer 83) and n-type semiconductor layers (n-gate layer 82, n-cathode layer 84) made of GaAs, GaAlAs, AlAs, etc. That is, the thyristor has a pnpn structure. Here, as an example, the forward potential (diffusion potential) Vd of the pn junction composed of the p-type semiconductor layer and the n-type semiconductor layer is set to 1.5V.

[0096] As an example, the reference potential Vsub of the p-anode layer 81 is set to 0 V as a high-level potential (hereinafter referred to as "H"), and the power supply potential Vgk supplied to the Vgk terminal (see FIG. 6) is set to -3.3 V as a low-level potential (hereinafter referred to as "L"). Therefore, it may be expressed as "H(0 V)" and "L(-3.3 V)". As shown in FIG. 6, the Vgk terminal is connected to the gate via the power supply line resistance Rg. That is, in the case where the thyristor is the transfer thyristor T1, the Vgk terminal is connected to the gate Gt1 via the power supply line resistance Rg1.

[0097] In the off state of the thyristor where no current flows between the anode and the cathode, when a potential lower than the threshold voltage (a negative potential with a large absolute value) is applied to the cathode, it shifts to the on state (turns on). Here, the threshold voltage of the thyristor is the value obtained by subtracting the forward potential Vd (1.5 V) of the pn junction from the potential of the gate. When it is in the on state, the gate of the thyristor becomes a potential close to the potential of the anode. Here, since the anode is 0 V, it is assumed that the gate becomes 0 V. Also, the cathode of the thyristor in the on state becomes a potential close to the potential obtained by subtracting the forward potential Vd (1.5 V) of the pn junction from the potential of the anode (the absolute value is referred to as the holding voltage). Here, since the anode is 0 V, the cathode of the thyristor in the on state becomes a potential close to -1.5 V (a negative potential with an absolute value larger than 1.5 V). Here, it is assumed that the holding voltage is 1.5 V.

[0098] The thyristor in the on state maintains the on state when a potential lower than the potential required to maintain the on state at the cathode (a negative potential with a large absolute value) is continuously applied and a current (holding current) capable of maintaining the on state is supplied. On the other hand, the thyristor in the on state shifts to the off state (turns off) when the cathode becomes a potential higher than the potential required to maintain the on state (a potential close to the above -1.5 V) (a negative potential with a small absolute value, 0 V, or a positive potential).

[0099] <Tunnel junction layer 85> Next, as shown in FIG. 8, the setting thyristor S and the VCSEL in the island 301 are stacked via the tunnel junction layer 85. Thereby, the setting thyristor S and the VCSEL are connected in series. FIG. 9 is a diagram for further explaining the stacked structure of the setting thyristor S and the VCSEL. FIG. 9(a) is a schematic energy band diagram in the stacked structure of the setting thyristor S and the VCSEL, FIG. 9(b) is an energy band diagram in the reverse bias state of the tunnel junction layer 85, and FIG. 9(c) shows the current-voltage characteristics of the tunnel junction layer 85.

[0100] A voltage is applied between the lighting signal φI applied to the n-ohmic electrode 321 shown in FIGS. 7 and 8 and the reference potential Vsub of the back electrode 90 so that the setting thyristor S and the VCSEL are each forward-biased. Then, as shown in the energy band diagram of FIG. 9(a), the n ++ layer 85a and the p ++ layer 85b that make up the tunnel junction layer 85 are reverse-biased.

[0101] The tunnel junction layer 85 is a junction of an n ++ layer 85a doped with a high concentration of n-type impurities and a p ++ layer 85b doped with a high concentration of p-type impurities. Therefore, the width of the depletion region is narrow, and when forward-biased, electrons tunnel from the conduction band on the n ++ layer 85a side to the valence band on the p ++ layer 85b side. At this time, negative resistance characteristics appear (see the forward bias side (+V) in FIG. 9(c)).

[0102] On the other hand, as shown in FIG. 9(b), when the tunnel junction layer 85 is reverse-biased (-V), the potential Ev of the valence band (valence band) on the p ++ layer 85b side becomes higher than the potential Ec of the conduction band (conduction band) on the n ++ layer 85a side. Then, from the valence band (valence band) of the p ++ layer 85b, to the n ++Electrons tunnel into the conduction band on the layer 85a side. And, the larger the reverse bias voltage (-V) becomes, the easier it is for electrons to tunnel. That is, as shown on the reverse bias side (-V) of Fig. 9(c), the tunnel junction layer 85 (tunnel junction) allows current to flow more easily as the reverse bias increases.

[0103] Therefore, as shown in Fig. 9(a), when a voltage is applied so that each of the setting thyristor S and the VCSEL is forward-biased and the setting thyristor S turns on and transitions to the on state, current flows from the setting thyristor S to the VCSEL even if the tunnel junction layer 85 is reverse-biased.

[0104] Note that instead of the tunnel junction layer 85, a group-III-V compound layer having metallic conductivity and epitaxially grown on a group-III-V compound semiconductor layer may be used. InNAs, which will be described as an example of the material of the metallic conductive group-III-V compound layer, has a negative bandgap energy, for example, when the composition ratio x of InN is in the range of about 0.1 to about 0.8. Also, InNSb has a negative bandgap energy, for example, when the composition ratio x of InN is in the range of about 0.2 to about 0.75. The fact that the bandgap energy becomes negative means that there is no bandgap. Therefore, it exhibits conductive characteristics (conduction characteristics) similar to those of a metal. That is, the metallic conductive characteristics (conductivity) mean that current flows if there is a potential gradient, similar to a metal.

[0105] And, the lattice constants of group-III-V compounds (semiconductors) such as GaAs and InP are in the range of 5.6 Å to 5.9 Å. And this lattice constant is close to the lattice constant of Si, about 5.43 Å, and the lattice constant of Ge, about 5.66 Å. On the other hand, the lattice constant of InN, which is also a group-III-V compound, is about 5.0 Å in the zinc blende structure, and the lattice constant of InAs is about 6.06 Å. Therefore, the lattice constant of InNAs, which is a compound of InN and InAs, can be a value close to 5.6 Å to 5.9 Å such as GaAs. In addition, the lattice constant of InSb, which is a III-V compound, is approximately 6.48 Å. Therefore, since the lattice constant of InN is approximately 5.0 Å, the lattice constant of InNSb, which is a compound of InSb and InN, can be a value close to 5.6 Å to 5.9 Å such as GaAs.

[0106] That is, InNAs and InNSb can be monolithically epitaxially grown on a layer of a III-V compound (semiconductor) such as GaAs. Also, a layer of a III-V compound (semiconductor) such as GaAs can be monolithically laminated by epitaxial growth on a layer of InNAs or InNSb.

[0107] Therefore, if the setting thyristor S and the VCSEL are stacked in series via a metal-conductive III-V compound layer instead of the tunnel junction layer 85, it is possible to suppress the reverse bias of the n-cathode layer 84 of the setting thyristor S and the p-anode layer 86 of the VCSEL.

[0108] <Operation of the Stacked Setting Thyristor S and VCSEL> Next, the operation of the stacked setting thyristor S and VCSEL will be described. Here, the turn-on voltage of the VCSEL is set to 1.5 V. That is, if a voltage of 1.5 V or more is applied between the anode and cathode of the VCSEL, the VCSEL emits light. Assume that the lighting signal φI is 0 V ("H(0 V)") or -3.3 V ("L(-3.3 V)"). 0 V is the potential to turn off the VCSEL, and -3.3 V is the potential to turn on the VCSEL from the off state.

[0109] When shifting the VCSEL from the off state to the on state, the lighting signal φI is set to "L(-3.3V)". At this time, when -1.5V is applied to the gate Gs of the setting thyristor S, the threshold value of the setting thyristor S becomes -3V, which is obtained by subtracting the forward potential Vd(1.5V) of the pn junction from the potential (-1.5V) of the gate Gs. At this time, since the lighting signal φI is -3.3V, the setting thyristor S turns on and shifts from the off state to the on state, and at the same time, the VCSEL also shifts from the off state to the on state. That is, the VCSEL emits laser light and emits light. Then, since the voltage (holding voltage Vr) applied to the on-state setting thyristor S is 1.5V, 1.8V is applied to the laser diode LD. Since the VCSEL has a rising voltage of 1.5V, the VCSEL continues to emit light.

[0110] On the other hand, when the lighting signal φI is set to 0V, both ends of the series connection of the setting thyristor S and the VCSEL become 0V, the setting thyristor S shifts from the on state to the off state (turns off), and the VCSEL stops emitting light. The operation of the VCSEL array 10 will be described in detail later.

[0111] (Configuration of the semiconductor layer stack) As described above, the semiconductor layer stack is composed of a substrate 80, a p anode layer 81, an n gate layer 82, a p gate layer 83, an n cathode layer 84, a tunnel junction layer 85, a p anode layer 86, a light emitting layer 87, and an n cathode layer 88 stacked together. As described above, the substrate 80 is described by taking p-type GaAs as an example, but it may also be n-type GaAs, intrinsic (i) GaAs without added impurities. Further, it may be InP, GaN, InAs, other III-V group, II-VI material semiconductor substrates, sapphire, Si, Ge, etc. When the substrate is changed, the material monolithically laminated on the substrate uses a material that is substantially matched to the lattice constant of the substrate (including a strained structure, a strain relaxation layer, and metamorphic growth). As an example, on an InAs substrate, InAs, InAsSb, GaInAsSb, etc. are used, on an InP substrate, InP, InGaAsP, etc. are used, on a GaN substrate or a sapphire substrate, GaN, AlGaN, InGaN are used, and on a Si substrate, Si, SiGe, GaP, etc. are used. However, when the substrate 80 is electrically insulating, it is necessary to separately provide a wiring for supplying the reference potential Vsub. Further, when the semiconductor layer laminate excluding the substrate 80 is attached to another support substrate and the semiconductor layer laminate is provided on the other support substrate, it is not necessary for the support substrate to match the lattice constant.

[0112] The p-anode layer 81 is, for example, p-type Al 18 / cm 3 GaAs with an impurity concentration of 1×10 0.9 . The Al composition may be changed within the range of 0 to 1. The n-gate layer 82 is, for example, n-type Al 17 / cm 3 GaAs with an impurity concentration of 1×10 0.9 . The Al composition may be changed within the range of 0 to 1. The p-gate layer 83 is, for example, p-type Al 17 / cm 3 GaAs with an impurity concentration of 1×10 0.9 . The Al composition may be changed within the range of 0 to 1. The n-cathode layer 84 is, for example, n-type Al 18 / cm 3 GaAs with an impurity concentration of 1×10 0.9 . The Al composition may be changed within the range of 0 to 1.

[0113] The tunnel junction layer 85 is composed of a junction between an n layer 85a doped with a high concentration of n-type impurities and a p layer 85b doped with a high concentration of n-type impurities (see Fig. 7(a)). The n layer 85a and the p layer 85b have, for example, a high impurity concentration of 1×10 / cm. Note that the impurity concentration of a normal junction is on the order of 10 / cm to 10 / cm. The combination of the n layer 85a and the p layer 85b (hereinafter denoted as n layer 85a / p layer 85b) is, for example, n GaInP / p GaAs, n GaInP / p AlGaAs, n GaAs / p GaAs, n AlGaAs / p AlGaAs, n InGaAs / p InGaAs, n GaInAsP / p GaInAsP, n GaAsSb / p GaAsSb. Note that combinations can be mutually changed. ++ The p anode layer 86 is formed by laminating a lower p anode layer 86a, a current confinement layer 86b, and an upper p anode layer 86c in that order. The lower p anode layer 86a and the upper p anode layer 86c are, for example, p-type AlGaAs with an impurity concentration of 5×10 / cm. The Al composition may be changed within the range of 0 to 1. ++ The current confinement layer 86b is, for example, AlAs or p-type AlGaAs with a high impurity concentration of Al. When Al is oxidized, Al O ++ ++ 20 3 17 3 18 3 ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

[0114] 17 3 0.9 2 3 ​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​As long as the formation results in increased electrical resistance and the formation of the current blocking region 86e, it is acceptable. Note that hydrogen ions (H + ) can be implanted into semiconductor layers such as GaAs and AlGaAs to form the current blocking region 86e (H + ion implantation).

[0115] The light emitting layer 87 has a quantum well structure in which well layers and barrier layers are alternately stacked. The well layers are, for example, GaAs, AlGaAs, InGaAs, GaAsP, AlGaInP, GaInAsP, GaInP, etc., and the barrier layers are AlGaAs, GaAs, GaInP, GaInAsP, etc. Note that the light emitting layer 87 may be a quantum wire or a quantum dot.

[0116] The n cathode layer 88 is, for example, n-type Al 17 / cm 3 GaAs with an impurity concentration of 5×10 0.9 . The Al composition may be changed within the range of 0 to 1.

[0117] These semiconductor layers are stacked, for example, by metal organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE) to form a semiconductor layer stack.

[0118] Note that instead of the above AlGaAs-based materials, it may be composed of GaInP, etc. Also, it may be configured using a GaN substrate or an InP-based substrate. Further, each of the VCSEL composed of the p anode layer 86, the light emitting layer 87, and the n cathode layer 88, and the setting thyristor S and the transfer thyristor T composed of the p anode layer 81, the n gate layer 82, the p gate layer 83, and the n cathode layer 84 may be made of materials with different lattice constants. This can be achieved by metamorphic growth or by growing the setting thyristor S and the transfer thyristor T separately and attaching them to each other. In that case, the tunnel junction layer 85 only needs to be substantially matched to either lattice constant.

[0119] Since the VCSEL array 10 can be manufactured by techniques such as known photolithography and etching, the description of the manufacturing method will be omitted.

[0120] (Operation of VCSEL Array 10) FIG. 10 is a diagram showing an example of a time chart for controlling light emission / non-light emission of the VCSEL groups in the VCSEL array 10. Here, the case where each VCSEL group described in FIGS. 6 and 7 includes seven VCSELs will be described as an example. In FIG. 10, it is assumed that time elapses in alphabetical order (a, b, c,...). The timing chart shown in FIG. 10 shows the portions for controlling VCSEL groups #1 to #4. And the periods for sequentially causing VCSEL groups #1 to #4 to emit light are defined as periods U-1 to U-4. Here, as will be described later, the lengths of the respective periods of periods U-1 to U-4 are assumed to be different, but they may be the same.

[0121] With reference to FIG. 6, the time chart of FIG. 10 will be described. At time a, power is supplied to the control unit 50 shown in FIG. 6. Then, the reference potential Vsub is set to "H (0 V)" and the power supply potential Vgk is set to "L (-3.3 V)". Next, the waveforms of each signal (transfer signal φ1, φ2, lighting signal φI) will be described. Since periods U-1 to U-4 are basically the same, the description will be centered on period U-1. When periods U-1 to U-4 are not distinguished, they will be denoted as period U.

[0122] The transfer signal φ1 is a signal that becomes "H (0 V)" or "L (-3.3 V)". The transfer signal φ1 is "H (0 V)" at time a and transitions to "L (-3.3 V)" at time b. And at time i, it returns to "H (0 V)". And at time m, it transitions to "L (-3.3 V)" again. The transfer signal φ2 is also a signal that becomes "H (0 V)" or "L (-3.3 V)". The transfer signal φ2 is "H (0 V)" at time a and transitions to "L (-3.3 V)" at time h. And at time n, it returns to "H (0 V)".

[0123] After time b, the transfer signals φ1 and φ2 alternate between "H(0V)" and "L(-3.3V)" with a period (for example, the period from time h to time i) when they are both "L(-3.3V)" in between. Therefore, from time b when the transfer signal φ1 transitions from "H(0V)" to "L(-3.3V)" to time h when the transfer signal φ2 transitions from "H(0V)" to "L(-3.3V)" is defined as period U-1. Conversely, from time h when the transfer signal φ2 transitions from "H(0V)" to "L(-3.3V)" to time m when the transfer signal φ1 transitions from "H(0V)" to "L(-3.3V)" is defined as period U-2. Periods U-3 and U-4 are the same.

[0124] The lighting signal φI is a signal that becomes either "H(0V)" or "L(-3.3V)". And the lighting signal φI repeats between "H(0V)" and "L(-3.3V)" during the period when one of the transfer signals φ1 and φ2 is "H(0V)" and the other is "L(-3.3V)" in each period U, for example, from time c to time g in period U-1, or from time j to time l in period U-2. And it is "H(0V)" in other periods.

[0125] Next, while referring to FIG. 6, the time chart of FIG. 10 will be described. In FIG. 10, the period during which the VCSEL emits light is shown by a solid line. At time a, power is supplied to the control unit 50 shown in FIG. 1, and the reference potential Vsub is set to "H(0V)" and the power supply potential Vgk is set to "L(-3.3V)". Then, the transfer signals φ1 and φ2 are set to "H(0V)". The start diode SD has its cathode at the power supply potential Vgk ("L(-3.3V)") via the power supply line resistance Rg1 and its anode at the transfer signal φ2 "H(0V)" via the current limiting resistance R2. Therefore, the start diode SD is forward-biased, and the gate Gt1 of the transfer thyristor T1 becomes -1.5V. As a result, the threshold voltage of the transfer thyristor T1 is -3V.

[0126] At time b, the transfer signal φ1 transitions from "H (0V)" to "L (-3.3V)". At this time, since the threshold voltage of the transfer thyristor T1 is -3V, it turns on and transitions from the off state to the on state. Then, the gate Gt1 becomes 0V. As a result, the gate Gs1 of the setting thyristor S1 connected to the gate Gt1 becomes 0V. Then, the threshold voltage of the setting thyristor S1 becomes -1.5V. At time b, the lighting signal φI is "H (0V)". That is, 0V is applied to the series connection of the setting thyristor S1 and VCSEL11~VCSEL17. For this reason, the setting thyristor S1 is in the off state, and VCSEL11~VCSEL17 do not emit light.

[0127] At time c, when the lighting signal φI transitions from "H (0V)" to "L (-3.3V)", the setting thyristor S1 with a threshold voltage of -1.5V turns on and transitions from the off state to the on state. Then, as described above, current flows through VCSEL11~VCSEL17 and they emit light. At this time, the voltage between the cathode and anode of the setting thyristor S1 becomes 1.5V, and the voltage between the cathode and anode of VCSEL11~VCSEL17 becomes 1.8V. Therefore, the light emission of VCSEL11~VCSEL17 is maintained. That is, at time c, VCSEL11~VCSEL17 belonging to VCSEL group #1 emit light in parallel.

[0128] At time d, when the lighting signal φI transitions from "L (-3.3V)" to "H (0V)", both ends of the series connection of the setting thyristor S1 and VCSEL11~VCSEL17 become 0V, the setting thyristor S1 turns off and transitions from the on state to the off state, and VCSEL11~VCSEL17 stop emitting light. That is, at time d, VCSEL11~VCSEL17 belonging to VCSEL group #1 stop emitting light in parallel. However, the threshold voltage of the setting thyristor S1 is maintained at -3V.

[0129] Therefore, at time e, when the lighting signal φI transitions from "H (0V)" to "L (-3.3V)", the set thyristors S11 to S14 with a threshold voltage of -3V turn on again and transition from the off state to the on state, and VCSEL11 to VCSEL17 emit light. At time f, when the lighting signal φI transitions from "L (-3.3V)" to "H (0V)", the set thyristor S1 turns off again and transitions from the on state to the off state, and VCSEL11 to VCSEL17 stop emitting light.

[0130] That is, from the time b when the transfer signal φ1 transitions from "H (0V)" to "L (-3.3V)" to the time h when the transfer signal φ2 transitions from "H (0V)" to "L (-3.3V)", in the period U-1, the lighting signal φI is repeatedly transitioned from "H (0V)" to "L (-3.3V)" and then from "L (-3.3V)" to "H (0V)". By doing so, VCSEL11 to VCSEL14 belonging to the VCSEL group #1 emit light in parallel in a pulsed (intermittent) manner. In the period U-1, four pulses are emitted.

[0131] Similarly, in the period U-2 from time h to time m, VCSEL21 to VCSEL27 belonging to the VCSEL group #2 are made to emit light in parallel as three pulses. Also, in the period U-3 from time m to time o, VCSEL31 to VCSEL34 belonging to the VCSEL group #3 are made to emit light in parallel as three pulses. Note that the emission time per pulse in the period U-3 is set longer than in the periods U-1 and U-2. Furthermore, in the period U-4 from time o to time r, VCSEL41 to VCSEL44 belonging to the VCSEL group #4 are made to emit light in parallel as five pulses. Note that the emission time per pulse in the period U-4 is set shorter than in the periods U-1 and U-2.

[0132] In the above description, it was assumed that a plurality of pulses are emitted during period U, but a single emission may also be possible. Further, if the lighting signal φI is maintained at "H (0 V)" during period U, both ends of the series connection of the setting thyristor S and the VCSEL group remain at 0 V. Therefore, the VCSEL group does not emit light. That is, the VCSEL group may be maintained non-luminous during a predetermined period U.

[0133] As described above, by using the drive unit 11, sequential lighting control is performed by self-scanning. Then, by causing a plurality of VCSELs belonging to the VCSEL group to emit light in parallel, compared to the case of increasing the light output by increasing the size of the light-emitting point, the uniformity of light emission is impaired, the light emission profile becomes distorted, or the divergence angle becomes large. It is possible to suppress the deterioration of the light emission characteristics of the VCSEL such as an increase.

[0134] (Array of VCSEL groups) FIG. 11 is a diagram for explaining the arrangement of the VCSEL groups in the VCSEL array 10 to which the first embodiment is applied. In FIG. 11, the VCSEL array 10 will be described as including eight VCSEL groups as an example, as shown in FIGS. 4 and 7. Note that FIG. 11 extracts and shows the connection relationship between the gate Gt of the transfer thyristor T in the island 302 and the gate Gs of the setting thyristor S in the island 301 in FIG. 7.

[0135] As shown in FIG. 11, the islands 301-1 to 301-4 and the islands 301-5 to 301-8 are each arranged in the -x direction. The arrangement of the islands 301-1 to 301-4 and the arrangement of the islands 301-5 to 301-8 are arranged in parallel in the -y direction. By doing so, the wirings 75 (wirings 75-1 to 75-8) connecting the gates Gt1 to Gt8 and the gates Gs1 to Gs8 are provided without crossing or approaching each other.

[0136] In the arrangement shown in FIG. 11, when the on-state of the transfer thyristor T is sequentially transferred in the -y direction, the lighting of the VCSEL group is sequentially controlled in the -x direction. That is, after the lighting of the VCSEL group from VCSEL group #1 to VCSEL group #4 is sequentially controlled in the -x direction, the lighting of the VCSEL group from VCSEL group #5 to VCSEL group #8 is sequentially controlled in the -x direction. That is, the lighting control is performed in a direction (-x direction) orthogonal to the direction (-y direction) in which the on-state of the transfer thyristor T is transferred.

[0137] FIG. 12 is a diagram for explaining the arrangement of the VCSEL group in the VCSEL array 10' to which the first embodiment for comparison is not applied. Also in the VCSEL array 10' shown in FIG. 12, the connection relationship between the gate Gt of the transfer thyristor T in the island 302 and the gate Gs of the setting thyristor S in the island 301 is extracted and illustrated.

[0138] As shown in FIG. 12, islands 301-1 to 301-2, islands 301-3 to 301-4, islands 301-5 to 301-6, and islands 301-7 to 301-8 are each arranged in the -y direction. And the arrangements of islands 301-1 to 301-2, the arrangements of islands 301-3 to 301-4, the arrangements of islands 301-5 to 301-6, and the arrangements of islands 301-7 to 301-8 are arranged in parallel in the -x direction. In this way, when the on-state of the transfer thyristor T is sequentially transferred in the -y direction, in the arrangement region 100, the lighting of the VCSEL group is also sequentially controlled in the -y direction. That is, after the lighting of VCSEL group #1 and VCSEL group #2 is sequentially controlled in the -y direction, the lighting of VCSEL group #3 and VCSEL group #4 is sequentially controlled in the -y direction. The same applies to VCSEL groups #5 to #8. That is, the lighting control is performed in a direction (-y direction) parallel to the direction (-y direction) in which the on-state of the transfer thyristor T is transferred.

[0139] However, in the VCSEL array 10', the wiring 75-2 connecting the gate Gt2 and the gate Gs2, and the wiring 75-3 connecting the gate Gt3 and the gate Gs3 cross each other (the location indicated by α). Also, the wiring 75-2 connecting the gate Gt2 and the gate Gs2, the wiring 75-4 connecting the gate Gt4 and the gate Gs4, and the wiring 75-5 connecting the gate Gt5 and the gate Gs5 come close to each other (the location indicated by β). Then, the wiring 75-5 connecting the gate Gt5 and the gate Gs5 and the wiring 75-6 connecting the gate Gt6 and the gate Gs6 come close to each other (the location indicated by γ). Furthermore, the wiring 75-7 connecting the gate Gt7 and the gate Gs7 and the wiring 75-8 connecting the gate Gt8 and the gate Gs8 come close to each other (the location indicated by δ).

[0140] In the arrangement shown in FIG. 12, the lighting control is performed in the direction (-y direction) parallel to the direction (-y direction) in which the on state of the transfer thyristor T is transferred. However, since the wiring 75 connecting the gate Gt of the transfer thyristor T in the island 302 and the gate Gs of the setting thyristor S in the island 301 cross or come close to each other, it is difficult to provide the wiring 75.

[0141] As described above, if the lighting control of the VCSEL group is performed in a direction orthogonal to the direction in which the on state of the transfer thyristor T is transferred, like the VCSEL array 10 to which the first embodiment shown in FIG. 11 is applied, the wiring 75 connecting the gate Gt of the transfer thyristor T in the island 302 and the gate Gs of the setting thyristor S in the island 301 can be provided without crossing or coming close to each other.

[0142] In FIG. 11, the VCSEL group is controlled to light in the -x direction. However, the VCSEL group and the wiring 75 may be arranged so that the lighting control is performed in the +x direction.

[0143] [Second Embodiment] In the VCSEL array 10 to which the first embodiment is applied, the lighting control of the VCSEL group is performed in a direction orthogonal to the direction in which the on-state of the transfer thyristor T is transferred. In the VCSEL array 10, the lighting control of the VCSEL group is performed in one direction orthogonal to the direction in which the on-state of the transfer thyristor T is transferred. In the VCSEL array 20 to which the second embodiment is applied, the lighting control of the VCSEL group is performed so as to reciprocate alternately in a direction orthogonal to the direction in which the on-state of the transfer thyristor T is transferred. Since other configurations are the same as those in the first embodiment, the description thereof is omitted, and the arrangement of the VCSEL group in the VCSEL array 20, which is a different part, will be described. Note that members having the same function are denoted by the same reference numerals.

[0144] (Arrangement of VCSEL group) FIG. 13 is a diagram for explaining the arrangement of the VCSEL group in the VCSEL array 20 to which the second embodiment is applied. In FIG. 13, the VCSEL array 20 will be described as including eight VCSEL groups as shown in FIGS. 4 and 7 in the first embodiment. Also in FIG. 13, the connection relationship between the gate Gt of the transfer thyristor T in the island 302 and the gate Gs of the setting thyristor S in the island 301 is extracted and illustrated.

[0145] As shown in FIG. 13, the islands 301-1 to 301-4 are arranged in the -x direction, and the islands 301-5 to 301-8 are arranged in the +x direction. And the islands 301-5 to 301-8 have a planar structure in which the islands 301-5 to 301-8 in the first embodiment shown in FIG. 11 are inverted in the y direction. Even in this way, the wirings 75 (wirings 75-1 to 75-8) connecting the gates Gt1 to Gt8 and the gates Gs1 to Gs8 are provided without intersecting or approaching each other.

[0146] When the on-state of the transfer thyristor T is sequentially transferred in the -y direction, in the array region 100, the VCSEL groups #1 to #4 are sequentially controlled to light up in the -x direction. Next, the VCSEL groups #5 to #8 are sequentially controlled to light up in the +x direction. That is, in the VCSEL array 20 in the second embodiment, the lighting control of the VCSEL groups is performed alternately (in the -x direction and the +x direction) in the direction orthogonal to the direction in which the on-state of the transfer thyristor T is transferred. And the wiring connecting the gate Gt of the transfer thyristor T in the island 302 and the gate Gs of the setting thyristor S in the island 301 is provided without crossing or approaching each other.

[0147] [Third Embodiment] In the VCSEL array, a light-emitting current is supplied to the VCSEL group by the lighting signal line 76. Since a large current flows through the lighting signal line 76, it is required that the current loss is small. At this time, if the lighting signal line 76 is provided for each VCSEL group, the resistance of the lighting signal line 76 will become high. Also, the lighting control of the VCSEL group is performed by the wiring 75 connecting the gate Gt of the transfer thyristor T and the gate Gs of the setting thyristor S. If the wiring 75 is provided between the VCSEL groups, the number of VCSEL groups is restricted by the interval between the VCSEL groups. Also, if the number of VCSEL groups is increased, the interval between the VCSEL groups becomes wide, and the interval between the VCSELs between the adjacent VCSEL groups becomes wider than the interval between the VCSELs within the VCSEL group. In the VCSEL array 21 to which the third embodiment is applied, the VCSELs arranged within the VCSEL group and the VCSELs between the adjacent VCSEL groups are arranged at equal intervals.

[0148] (Planar layout of the VCSEL array 21) FIG. 14 is a diagram showing an example of a planar layout of a VCSEL array 21 to which the third embodiment is applied. In FIG. 14, the configuration of the island 301 in FIG. 7 is different. Since other configurations are the same as those of the VCSEL array 10 in the first embodiment, the description thereof is omitted, and the arrangement of the VCSEL groups in the VCSEL array 21, which is the different part, will be described. Note that members having the same function are denoted by the same reference numerals. Each VCSEL group of the VCSEL array 21 includes 12 VCSELs.

[0149] As shown by the dashed line in FIG. 14, the lighting signal line 76 that supplies the light-emitting current to the VCSEL groups is commonly provided in the same manner as in the first embodiment across all the VCSEL groups. That is, the lighting signal line 76 is configured as so-called solid wiring except for the light-emitting port 310.

[0150] A larger current flows through the lighting signal line 76 than through the wiring 75 that connects the gate Gt of the transfer thyristor T and the gate Gs of the setting thyristor S. For example, a current 10 to 100 times that of the wiring 75 flows through the lighting signal line 76. Therefore, it is preferable that the current loss is small. Thus, the lighting signal line 76 is commonly provided across all the VCSEL groups and is a wide wiring. On the other hand, since less current flows through the wiring 75, the current loss may be large. That is, the wiring 75 may have a large resistance. That is, the wiring 75 may have a smaller thickness and width and may be longer than the lighting signal line 76. Here, the thickness, width, and length are collectively referred to as volume. That is, the wiring 75 may have a smaller volume than the lighting signal line 76.

[0151] As shown in Fig. 14, in the VCSEL array 21, the wiring 75 is configured to have a narrower width compared to Fig. 7. For this reason, within the VCESL group, the VCSELs are provided with an interval D in the x-direction interval D1 and the y-direction interval D2 (D1 = D2 = D). Further, between adjacent VCSEL groups, the VCSELs are provided with an interval D in the x-direction interval D3 and the y-direction interval D4. That is, within the VCESL group and between the VCSEL groups, the VCSELs are arranged at the same interval, that is, at equal intervals.

[0152] Within the VCSEL group, by arranging the VCSELs at equal intervals, the difference in light intensity within the irradiation region 40 is suppressed compared to the case where they are not arranged at equal intervals. That is, the uniformity of the light intensity within the irradiation region 40 is improved. Also, between the VCSEL groups, by arranging the VCSELs at equal intervals, the difference in light intensity at the boundary portion between the irradiation regions 40 is suppressed compared to the case where they are not arranged at equal intervals.

[0153] Since the wiring 75 may have a small volume as described above, it is provided so as to cross the VCSEL group. In Fig. 14, for example, the wiring 75 is provided between the VCSELs of the VCSEL group #1. This is the same as in the first embodiment. Here, the wiring 75 is an example of a gate signal line, and the lighting signal line 76 is an example of a supply line.

[0154] [Fourth Embodiment] As described in the VCSEL array 21 to which the third embodiment is applied, since the current flowing through the wiring 75 is small, the current loss may be large. That is, the wiring 75 may have a large resistance. That is, the wiring 75 may have a smaller thickness and width and may be longer compared to the lighting signal line 76. Therefore, the wiring 75 may be provided to go around the outside of the array region 100 in which a plurality of VCSEL groups are arranged.

[0155] (Arrangement of VCSEL Groups) FIG. 15 is a diagram for explaining the arrangement of VCSEL groups in the VCSEL array 22 to which the fourth embodiment is applied. In FIG. 15, the VCSEL array 22 will be described as including 12 VCSEL groups (VCSEL groups #1 to #12). Also in FIG. 15, the connection relationship between the gate Gt of the transfer thyristor T in the island 302 (see FIG. 7) and the gate Gs of the setting thyristor S in the island 301 (only the island 301-1 is shown in FIG. 15) is extracted and illustrated. Although the VCSELs are not shown in FIG. 15, it is assumed that the VCSELs are arranged at equal intervals within and between the VCSEL groups.

[0156] As shown in FIG. 15, the VCSEL groups #1, #2, #3, and #4 are arranged in the +x direction. The VCSELs #12, #7, #5, and #6 are arranged in the +x direction. The VCSEL groups #11, #10, #9, and #8 are arranged in the +x direction. Then, the VCSEL groups #11, #10, #9, #8, the VCSEL groups #12, #7, #5, #6, and the VCSEL groups #1, #2, #3, #4 are arranged in the +y direction. And the gates Gs (gates Gs1 to Gs12) of the setting thyristors S of the VCSEL groups are connected to the gates Gt (Gt1 to Gt12) of the transfer thyristor T by wirings 75 (wirings 75-1 to 75-12).

[0157] The VCSEL groups #1, #2, #3, #9, #10, and #11 are located at the edge portion on the side far from the gate Gt of the transfer thyristor T in the array region 100. And the wirings 75-1, 75-2, 75-3, 75-9, 75-10, 75-11, and 75-12 connected to the VCSEL groups #1, #2, #3, #9, #10, #11, and #12 are provided to go around the outside of the array region 100. That is, these wirings 75 would be shorter if provided across the VCSEL groups, but are provided to go around the outside of the array region 100 and are long.

[0158] Note that the VCSEL groups #4, #6, and #8 are located closer to the gate Gt of the transfer thyristor T in the array region 100. Therefore, the wirings 75-4, 75-6, and 75-8 connected to the VCSEL groups #4, #6, and #8 are provided between the array region 100 and the gate Gt. And the wirings 75-5 and 75-7 connected to the VCSEL groups #5 and #7 located in the center are provided across the VCSEL groups.

[0159] As described above, since the current flowing through the wiring 75 is small, the resistance may be large. Therefore, the wiring 75 may have a long length. For this reason, the wirings 75 (wirings 75-1, 75-2, 75-3, 75-9, 75-10, 75-11) connected to the VCSEL groups (VCSEL groups #1, #2, #3, #9, #10, #11) at the edge of the array region 100 may be provided to detour outside the array region 100. By doing so, the options for the position where the wiring 75 is provided are expanded, and it becomes easier to provide the wiring 75. Note that in the fourth embodiment, the order of the array and the order of lighting do not match, but they may be made to match. In that case, specifically, the VCSEL groups #1, #2, #3, #4, #12, #7, #5, #6, #11, #10, #9, #8 are connected to the gates Gt1 to Gt12 in the order of lighting from the lower left to the upper left, then from the middle bottom to the middle top, and finally from the lower right to the upper right. In that case, the detour path of the wiring 75 may not be changed, and they may be crossed before the gates Gt1 to Gt12, or only the wiring from the lower left to the upper left may be made to detour, and the other wirings may be provided across other VCSEL groups such as the VCSEL groups #5, #6, #7.

[0160] [Fifth Embodiment] FIG. 16 is a diagram showing an example of a planar layout of a VCSEL array to which the fifth embodiment is applied. FIG. 16 shows an example in which the position of the wiring 75 in FIG. 14 is closer to the light emission port 310 portion of the VCSEL. Here, around the light emission port 310 of the VCSEL included in the second light emitting element group (here, as an example, VCSEL group #2), specifically, on the mesa structure (post 311) formed by mesa etching, the wiring 75 (here, as an example, wiring 75-1) connected to the first light emitting element group (here, as an example, VCSEL group #1) is arranged. Here, the wiring 75-1 is an example of the first gate signal line in the fifth embodiment. Further, in this example, the gate electrode (p-ohmic electrode 331) of the VCSEL included in the VCSEL group #2 is also arranged on the mesa structure around the light emission port 310 of the VCSEL. Therefore, the wiring (here, as an example, wiring 75-2) serving as the second gate signal line of the VCSEL included in the VCSEL group #2 is close to the wiring 75-1. For this reason, it is configured by so-called multilayer wiring in which the wiring 75-1 and the wiring 75-2 are arranged in different layers. Although the case where the VCSEL is configured by a mesa structure has been described, the VCSEL may be configured by a trench structure. In that case, if the wiring 75-1 is arranged around the light emission port 310 bypassing the trench structure, the height difference at the portion where the wiring 75-1 passes is suppressed, and disconnection is less likely to occur.

[0161] The n-ohmic electrode 321 provided in the n-cathode layer 88 of the post 311 is connected to the lighting signal line 75 (see FIG. 8) via the through hole 321a.

[0162] In the first embodiment, the second embodiment, the third embodiment, the fourth embodiment, and the fifth embodiment, the VCSEL arrays 10, 20, 21, 22 have a structure in which the VCSELs are stacked on the set thyristor S on the substrate 80 side. The VCSEL arrays 10, 20, 21, 22 may have a structure in which the set thyristor S is stacked on the VCSEL on the substrate 80 side.

[0163] Also, although the VCSEL is controlled between a light-emitting state and a non-light-emitting state, it may be set to a light-emitting state with a minute amount of light in advance, and controlled to increase the light amount when the setting thyristor S transitions from the off state to the on state. Also, between VCSEL groups that are lit in sequence, control may be performed such that the light-emitting states overlap.

[0164] In the first embodiment, the second embodiment, the third embodiment, the fourth embodiment, and the fifth embodiment, the lighting control of the VCSEL group is performed by self-scanning by the drive unit 11 including the transfer thyristor T through which the on state is sequentially transferred. By doing so, the lighting control of the VCSEL group becomes easy. However, the drive unit 11 only needs to be able to independently control the lighting of the VCSEL group. Also, the VCSEL groups do not need to be driven in order. And, if the transfer thyristor further has a memory unit, after the on state is sequentially propagated in the transfer thyristor Ti, the signal is once stored in the memory unit, and the signal is sent to a plurality of VCSEL groups simultaneously, so that a plurality of VCSEL groups may be configured to light up simultaneously. And, the drive unit 11 may be composed of transistors provided for each VCSEL group instead of the transfer thyristor T or the like. Also, the VCSEL group (light-emitting element group) is configured such that the VCSELs (light-emitting elements) of the same group are adjacent to each other. By doing so, the configuration of the VCSEL group becomes easy. However, it is not necessary for the VCSELs to be arranged in a solid manner, and VCSELs connected to the same gate signal line may be regarded as one VCSEL group.

[0165] In the first embodiment, the second embodiment, the third embodiment, the fourth embodiment, and the fifth embodiment, the p-type substrate 80 is used, but as an n-type substrate, a configuration with the reverse pn relationship may be used. In this case, the polarity of the potential may be reversed.

Description of Reference Numerals

[0166] 1... Information processing device, 2... User interface (UI) unit, 3... Optical device, 4, 4'... Light-emitting device, 5... Three-dimensional sensor (3D sensor), 6... Measuring device, 8... Measurement control unit, 8A... Three-dimensional shape specifying unit, 9... System control unit, 9A... Authentication processing unit, 10, 10', 20, 21, 22... Surface-emitting laser diode array (VCSEL array), 11... Driving unit, 12... Light-emitting unit, 30... Diffusion member, 40, 41... Irradiation region, 50... Control unit, 51... Transfer signal generation unit, 52... Lighting signal generation unit, 53... Power supply potential generation unit, 54... Reference potential generation unit, 60, 60'... Condensing lens, 71... Power supply line, 72, 73... Transfer signal lines, 74, 75... Wiring, 76... Lighting signal line, 100, 100', 110, 110'... Array region, φ1, φ2... Transfer signal, D... Coupling diode, S... Setting thyristor, T... Transfer thyristor, VCSEL... Vertical cavity surface-emitting laser diode

Claims

1. A surface-emitting laser element array in which a plurality of surface-emitting laser element groups each including a plurality of surface-emitting laser elements are two-dimensionally arranged and can be independently driven from each other, in an array region where the plurality of surface-emitting laser element groups are arranged, the number of surface-emitting laser element groups arranged along a first direction is larger than the number of surface-emitting laser element groups arranged along a second direction orthogonal to the first direction, the shape of an irradiation region irradiated by the plurality of surface-emitting laser element groups is a shape having the first direction as its longitudinal direction, a surface-emitting laser element array in which the aspect ratio of the array region where the plurality of surface-emitting laser element groups are arranged is closer to 1:1 than the aspect ratio of the irradiation region, a lens which has a size including the plurality of surface-emitting laser element groups included in the surface-emitting laser element array, is provided in an emission path of the plurality of surface-emitting laser element groups, and narrows a divergence angle of light emitted from the plurality of surface-emitting laser element groups, a diffusion member that diffuses light emitted from the plurality of surface-emitting laser element groups included in the surface-emitting laser element array and transmitted through the optical element and emits the diffused light over the irradiation region, or a diffraction member that diffracts the light transmitted through the optical element and emits the diffracted light over the irradiation region, the plurality of surface-emitting laser element groups are formed on a common semiconductor substrate, the plurality of surface-emitting laser elements of each surface-emitting laser element group are stacked with a thyristor that causes the plurality of surface-emitting laser elements to emit light by shifting to an on state, and have a gate signal line connected to a gate of the thyristor, and the gate signal line of the first surface-emitting laser element group among the plurality of surface-emitting laser element groups passes between the laser elements of the second surface-emitting laser element group A light-emitting device.

2. The light-emitting device according to claim 1, wherein a length of the array region in the first direction is 0.8 times or more and 1.2 times or less a length of the array region in the second direction.

3. The light-emitting device according to claim 1, wherein a length of the array region in the first direction is 0.9 times or more and 1.1 times or less a length of the array region in the second direction.

4. The light-emitting device according to claim 1, wherein a length of the array region in the first direction is 0.95 times or more and 1.05 times or less a length of the array region in the second direction.

5. The light-emitting device according to any one of claims 1 to 4, characterized in that, in each of the surface-emitting laser element groups, the number of the plurality of surface-emitting laser elements arranged along the second direction is larger than the number of those arranged along the first direction.

6. The light-emitting device according to any one of claims 1 to 5, characterized in that the plurality of surface-emitting laser elements in each of the surface-emitting laser element groups of the plurality of surface-emitting laser element groups are connected in parallel to each other.

7. The light-emitting device according to any one of claims 1 to 6, characterized by having a driving unit that independently drives each of the surface-emitting laser element groups of the plurality of surface-emitting laser element groups.

8. The light-emitting device according to claim 7, characterized in that the driving unit causes each of the surface-emitting laser element groups of the plurality of surface-emitting laser element groups to emit light sequentially.

9. A light-emitting device according to any one of claims 1 to 8, a light-receiving unit that receives reflected light that is emitted from a plurality of surface-emitting laser element groups included in the light-emitting device and reflected by an object to be measured, and an optical device including the same.

10. An optical device according to claim 9, a three-dimensional shape specifying unit that measures a three-dimensional shape based on the time from when light is emitted from a plurality of surface-emitting laser element groups included in the optical device until it is received by the light-receiving unit included in the optical device, and specifies the three-dimensional shape of the object to be measured, and a measuring device including the same.

11. A measuring device according to claim 10, an authentication processing unit that performs authentication processing related to the use of the device itself based on the specification result by the three-dimensional shape specifying unit included in the measuring device, and an information processing device including the same.

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