Gate driver

Abstract

To improve the dielectric strength of a gate driver.SOLUTION: A gate driver includes a low voltage circuit that operates by a first voltage applied thereto, a high voltage circuit that operates by a second voltage higher than the first voltage applied thereto, and a transformer chip 80 as an insulating chip. The transformer ship 80 includes: a substrate 84; an insulating layer 86 formed on the substrate 84; a first transformer 41A having a first coil 43A and a second coil 44A embedded in the insulating layer 86 and arranged opposite to each other; and a second transformer 42A having a first coil 45A and a second coil 46A embedded in the insulating layer 86 and arranged opposite to each other. The low voltage circuit and the high voltage circuit are connected via a first transformer 41A and a second transformer 42A connected in series with each other, and transmit a signal via the first transformer 41A and the second transformer 42A.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] This disclosure relates to a gate driver.

Background Art

[0002] As a gate driver that applies a gate voltage to the gate of a switching element such as a transistor, for example, an isolated gate driver is known. For example, Patent Document 1 describes a semiconductor integrated circuit as an isolated gate driver including a transformer having a primary side first coil and a secondary side second coil.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] Here, the gate driver may include a low-voltage circuit that operates when a first voltage is applied, and a high-voltage circuit that operates when a second voltage higher than the first voltage is applied. In this case, an insulating element such as a transformer is used to insulate the low-voltage circuit and the high-voltage circuit. In such a gate driver, improvement of the withstand voltage may be required.

Means for Solving the Problems

[0005] A gate driver that solves the above problems is a gate driver that applies a gate voltage to the gate of a switching element, comprising: a low-voltage circuit that operates when a first voltage is applied; a high-voltage circuit that operates when a second voltage higher than the first voltage is applied; and an insulating chip, wherein the insulating chip comprises: a substrate; an insulating layer formed on the substrate; a first insulating element having a first conductor and a second conductor embedded in the insulating layer and arranged opposite to each other; and a second insulating element having a third conductor and a fourth conductor embedded in the insulating layer and arranged opposite to each other, wherein the low-voltage circuit and the high-voltage circuit are connected via the first insulating element and the second insulating element which are connected in series with each other, and signals are transmitted via the first insulating element and the second insulating element.

[0006] In this configuration, the low-voltage circuit and the high-voltage circuit are connected via a first and second insulating element connected in series with each other, and signals are transmitted through both insulating elements. This improves the dielectric strength of the gate driver compared to the case with only one insulating element.

[0007] Furthermore, with this configuration, since the first insulating element and the second insulating element are provided within a single insulating chip, that is, dedicated chips are provided for the first insulating element and the second insulating element, a common insulating chip can be used for different low-voltage and high-voltage circuits. This reduces manufacturing costs when manufacturing multiple types of gate drivers, at least one of which is different for low-voltage and high-voltage circuits. [Effects of the Invention]

[0008] The above gate driver makes it possible to improve the dielectric strength. [Brief explanation of the drawing]

[0009] [Figure 1] A schematic circuit diagram of the gate driver of the first embodiment. [Figure 2] A plan view showing the internal configuration of the gate driver of the first embodiment. [Figure 3] Schematic cross-sectional view of the transformer chip shown in Figure 2. [Figure 4] A plan view showing the internal configuration of the gate driver in the comparative example. [Figure 5] A schematic circuit diagram of the gate driver according to the second embodiment. [Figure 6] A plan view showing the internal configuration of the gate driver of the second embodiment. [Figure 7] Schematic cross-sectional view of the capacitor chip shown in Figure 6. [Figure 8] A schematic cross-sectional view of the modified transformer chip. [Figure 9] A schematic cross-sectional view of the modified transformer chip. [Figure 10] A schematic cross-sectional view of the modified transformer chip. [Figure 11] A schematic plan view showing the transformer and its surroundings within the transformer chip, illustrating the example of the modified transformer chip. [Figure 12] Schematic cross-sectional view of the 12-12 line of the transformer chip in Figure 11. [Figure 13] A schematic circuit diagram of the gate driver in the modified example. [Modes for carrying out the invention]

[0010] The following describes embodiments of the gate driver with reference to the drawings. The embodiments shown below are examples of configurations and methods for realizing the technical concept, and the materials, shapes, structures, arrangements, dimensions, etc. of each component are not limited to those described below.

[0011] [First Embodiment] The gate driver 10 of the first embodiment will be described with reference to Figures 1 to 4. Figure 1 shows a simplified example of the circuit configuration of the gate driver 10.

[0012] As shown in FIG. 1, the gate driver 10 applies a gate voltage to the gate of a switching element, and is applied, for example, to an inverter device 500 mounted on an electric vehicle or a hybrid vehicle. The inverter device 500 includes a pair of switching elements 501 and 502 connected in series to each other, a gate driver 10, and an ECU 503 that controls the gate driver 10. The switching element 501 is, for example, a high-side switching element connected to a driving power source, and the switching element 502 is a low-side switching element. Examples of the switching elements 501 and 502 include transistors such as SiMOSFET, SiCMOSFET, and IGBT. The gate driver 10 of the present embodiment applies a gate voltage to the gate of the switching element 501. In the following description, the case where MOSFETs are used for the switching elements 501 and 502 will be described.

[0013] The gate driver 10 is provided for each of the switching elements 501 and 502, and drives the switching elements 501 and 502 individually. In the present embodiment, for convenience of explanation, the gate driver 10 that drives the switching element 501 will be described.

[0014] The gate driver 10 includes a low-voltage circuit 20 to which a first voltage V1 is applied, a high-voltage circuit 30 to which a second voltage V2 higher than the first voltage V1 is applied, and a transformer 40 provided between the low-voltage circuit 20 and the high-voltage circuit 30. That is, the low-voltage circuit 20 and the high-voltage circuit 30 are connected via the transformer 40. The first voltage V1 and the second voltage V2 are DC voltages.

[0015] The gate driver 10 of the present embodiment is configured such that a signal is transmitted from the low-voltage circuit 20 to the high-voltage circuit 30 via the transformer 40 based on a control signal from the ECU 503 as an external control device, and a gate voltage is output from the high-voltage circuit 30. Here, the control signal from the ECU 503 corresponds to an external command.

[0016] Signals transmitted from the low-voltage circuit 20 to the high-voltage circuit 30, that is, signals output from the low-voltage circuit 20, are, for example, signals for driving the switching element 501. As an example, a set signal and a reset signal can be cited. The set signal is a signal that transmits the rising edge of the control signal from the ECU 503, and the reset signal is a signal that transmits the falling edge of the control signal from the ECU 503. It can also be said that the set signal and the reset signal are signals for generating the gate voltage of the switching element 501. Therefore, the set signal and the reset signal correspond to the first signal.

[0017] Specifically, the low-voltage circuit 20 is a circuit that operates when the first voltage V1 is applied. The low-voltage circuit 20 is a circuit electrically connected to the ECU 503, and generates a set signal and a reset signal based on the control signal input from the ECU 503. For example, the low-voltage circuit 20 generates a set signal in response to the rising edge of the control signal, while generating a reset signal in response to the falling edge of the control signal. Then, the low-voltage circuit 20 transmits the generated set signal and reset signal toward the high-voltage circuit 30.

[0018] The high-voltage circuit 30 is a circuit that operates when the second voltage V2 is applied. The high-voltage circuit 30 is a circuit electrically connected to the gate of the switching element 501, and generates a gate voltage for driving the switching element 501 based on the set signal and the reset signal received from the low-voltage circuit 20, and applies that gate voltage to the gate of the switching element 501. That is, it can also be said that the high-voltage circuit 30 generates a gate voltage to be applied to the gate of the switching element 501 based on the first signal output from the low-voltage circuit 20. Specifically, the high-voltage circuit 30 generates a gate voltage that turns on the switching element 501 based on the set signal, and applies it to the gate of the switching element 501. On the other hand, the high-voltage circuit 30 generates a gate voltage that turns off the switching element 501 based on the reset signal, and applies that gate voltage to the gate of the switching element 501. In this way, the on / off of the switching element 501 is controlled by the gate driver 10.

[0019] The high-voltage circuit 30 includes, for example, an RS-type flip-flop circuit to which a set signal and a reset signal are input, and a driver unit that generates a gate voltage based on the output signal of the RS-type flip-flop circuit. However, the specific circuit configuration of the high-voltage circuit 30 is arbitrary.

[0020] In the gate driver 10 of this embodiment, the low-voltage circuit 20 and the high-voltage circuit 30 are isolated by a transformer 40. Specifically, the transformer 40 restricts the transmission of DC voltage between the low-voltage circuit 20 and the high-voltage circuit 30, while allowing the transmission of various signals such as set signals and reset signals.

[0021] In other words, the state in which the low-voltage circuit 20 and the high-voltage circuit 30 are isolated means that the transmission of DC voltage between the low-voltage circuit 20 and the high-voltage circuit 30 is blocked, while the transmission of signals between the low-voltage circuit 20 and the high-voltage circuit 30 is permitted.

[0022] The dielectric strength of the gate driver 10 is, for example, 2500 Vrms or more and 7500 Vrms or less. In this embodiment, the dielectric strength of the gate driver 10 is approximately 5000 Vrms. However, the specific value of the dielectric strength of the gate driver 10 is not limited to this and is arbitrary.

[0023] In this embodiment, the ground of the low-voltage circuit 20 and the ground of the high-voltage circuit 30 are provided independently. Hereinafter, the ground potential of the low-voltage circuit 20 will be referred to as the first reference potential, and the ground potential of the high-voltage circuit 30 will be referred to as the second reference potential. In this case, the first voltage V1 is the voltage from the first reference potential, and the second voltage V2 is the voltage from the second reference potential. The first voltage V1 is, for example, 4.5V or more and 5.5V or less, and the second voltage V2 is, for example, 9V or more and 24V or less.

[0024] The following provides a detailed explanation of Transformer 40. The gate driver 10 of this embodiment is equipped with two transformers 40 to accommodate the transmission of two types of signals from the low-voltage circuit 20 to the high-voltage circuit 30. Specifically, the gate driver 10 is equipped with a transformer 40 used for transmitting a set signal and a transformer 40 used for transmitting a reset signal. For the sake of explanation, the transformer 40 used for transmitting the set signal will be referred to as transformer 40A, and the transformer 40 used for transmitting the reset signal will be referred to as transformer 40B.

[0025] The gate driver 10 includes a low-voltage signal line 21A connecting the low-voltage circuit 20 and the transformer 40A, and a low-voltage signal line 21B connecting the low-voltage circuit 20 and the transformer 40B. Therefore, the low-voltage signal line 21A transmits a set signal from the low-voltage circuit 20 to the transformer 40A. The low-voltage signal line 21B transmits a reset signal from the low-voltage circuit 20 to the transformer 40B.

[0026] The gate driver 10 includes a high-voltage signal line 31A connecting transformer 40A and high-voltage circuit 30, and a high-voltage signal line 31B connecting transformer 40B and high-voltage circuit 30. Therefore, high-voltage signal line 31A transmits a set signal from transformer 40A to high-voltage circuit 30. High-voltage signal line 31B transmits a reset signal from transformer 40B to high-voltage circuit 30.

[0027] Transformer 40A transmits a set signal from the low-voltage circuit 20 to the high-voltage circuit 30, while electrically isolating the low-voltage circuit 20 from the high-voltage circuit 30. Transformer 40A has a first transformer 41A and a second transformer 42A connected in series with each other. In this embodiment, the first transformer 41A corresponds to the first insulating element, and the second transformer 42A corresponds to the second insulating element.

[0028] The gate driver 10 is equipped with a pair of connection signal lines 11A and 12A that connect the first transformer 41A and the second transformer 42A. Therefore, the pair of connection signal lines 11A and 12A are signal lines through which set signals are transmitted.

[0029] In this embodiment, the dielectric strength of each transformer 41A and 42A is, for example, 2500 Vrms or more and 7500 Vrms or less. However, the dielectric strength of each transformer 41A and 42A may be 2500 Vrms or more and 5700 Vrms or less. In this embodiment, the dielectric strength of the second transformer 42A is set lower than that of the first transformer 41A. However, this is not limited to this, and the dielectric strength of each transformer 41A and 42A can be arbitrary.

[0030] The first transformer 41A includes a first coil 43A and a second coil 44A that is electrically insulated from the first coil 43A and magnetically coupled to it. The second transformer 42A includes a first coil 45A and a second coil 46A that is electrically insulated from the first coil 45A and magnetically coupled to it.

[0031] The first coil 43A is connected to the low-voltage circuit 20 by the low-voltage signal line 21A, while also being connected to the ground of the low-voltage circuit 20. In other words, the first end of the first coil 43A is electrically connected to the low-voltage circuit 20, and the second end of the first coil 43A is electrically connected to the ground of the low-voltage circuit 20. Therefore, the potential at the second end of the first coil 43A becomes the first reference potential. The first reference potential is, for example, 0V.

[0032] The second coil 44A is connected to the first coil 45A. In one example, the second coil 44A and the first coil 45A are connected to each other in an electrically floating state. That is, the first end of the second coil 44A and the first end of the first coil 45A are connected by a connecting signal line 11A. The second end of the second coil 44A and the second end of the first coil 45A are connected by a connecting signal line 12A. In this way, the second coil 44A and the first coil 45A act as relay coils that relay the signal transmission between the first coil 43A and the second coil 46A.

[0033] The second coil 46A is connected to the high-voltage circuit 30 by the high-voltage signal line 31A, while also being connected to the ground of the high-voltage circuit 30. In other words, the first end of the second coil 46A is electrically connected to the high-voltage circuit 30, and the second end of the second coil 46A is electrically connected to the ground of the high-voltage circuit 30. Therefore, the potential at the second end of the second coil 46A becomes the second reference potential. Since the ground of the high-voltage circuit 30 is connected to the source of the switching element 501, the second reference potential fluctuates with the driving of the inverter device 500 and may exceed, for example, 600V.

[0034] Transformer 40B transmits a reset signal from the low-voltage circuit 20 to the high-voltage circuit 30, while electrically isolating the low-voltage circuit 20 from the high-voltage circuit 30. Transformer 40B includes a first transformer 41B and a second transformer 42B connected in series with each other. In this embodiment, the first transformer 41B corresponds to a first insulating element, and the second transformer 42B corresponds to a second insulating element.

[0035] The gate driver 10 is equipped with a pair of connection signal lines 11B and 12B that connect the first transformer 41B and the second transformer 42B. Therefore, the pair of connection signal lines 11B and 12B are signal lines that transmit the reset signal.

[0036] The first transformer 41B includes a first coil 43B and a second coil 44B that is electrically insulated from the first coil 43B and magnetically coupled to it. The second transformer 42B includes a first coil 45B and a second coil 46B that is electrically insulated from the first coil 45B and magnetically coupled to it. The dielectric strength of the first transformer 41B is the same as that of the first transformer 41A, and the dielectric strength of the second transformer 42B is the same as that of the second transformer 42A. The connection configuration of the first transformer 41B and the second transformer 42B is the same as that of the first transformer 41A and the second transformer 42A, so a detailed explanation is omitted.

[0037] The set signal output from the low-voltage circuit 20 is transmitted to the high-voltage circuit 30 via the first transformer 41A and the second transformer 42A. The reset signal output from the low-voltage circuit 20 is transmitted to the high-voltage circuit 30 via the first transformer 41B and the second transformer 42B.

[0038] Figure 2 shows an example of a plan view illustrating the internal configuration of the gate driver 10. Note that Figure 1 shows a simplified circuit configuration of the gate driver 10, so the number of external terminals of the gate driver 10 in Figure 2 is greater than the number of external terminals of the gate driver 10 in Figure 1. Here, the number of external terminals of the gate driver 10 refers to the number of external electrodes that can connect the gate driver 10 to external electronic components such as the ECU 503 and the switching element 501 (see Figure 1). Also, the number of signal lines (the number of wires W described later) that transmit signals from the low-voltage circuit 20 to the high-voltage circuit 30 in the gate driver 10 in Figure 2 is greater than the number of signal lines of the gate driver 10 in Figure 1.

[0039] As shown in Figure 2, the gate driver 10 is a semiconductor device in which multiple semiconductor chips are packaged together, and is mounted on a circuit board provided in, for example, an inverter device 500. Note that each switching element 501, 502 is mounted on a separate mounting board from the circuit board. A cooler is attached to this mounting board.

[0040] The gate driver 10 is packaged in an SO-type package, and in this embodiment, it is packaged in an SOP. The gate driver 10 comprises a low-voltage circuit chip 60, a high-voltage circuit chip 70, and a transformer chip 80 as semiconductor chips, a low-voltage lead frame 90 on which the low-voltage circuit chip 60 is mounted, a high-voltage lead frame 100 on which the high-voltage circuit chip 70 is mounted, and a sealing resin 110 that seals parts of each lead frame 90, 100 and each chip 60, 70, 80. In this embodiment, the transformer chip 80 corresponds to an insulating chip that insulates the low-voltage circuit 20 and the high-voltage circuit 30. Also, in Figure 2, the sealing resin 110 is shown by a dashed line for the purpose of explaining the internal structure of the gate driver 10. Furthermore, the package type of the gate driver 10 can be arbitrarily changed.

[0041] The sealing resin 110 is made of an electrically insulating material, for example, a black epoxy resin. The sealing resin 110 is formed in the shape of a rectangular plate with the z direction as the thickness direction. The sealing resin 110 has four resin sides 111 to 114. In detail, the sealing resin 110 has resin sides 111 and 112 as end faces in the x direction, and resin sides 113 and 114 as end faces in the y direction. The x and y directions are perpendicular to the z direction. The x and y directions are orthogonal to each other. In the following description, "plan view" means viewing from the z direction.

[0042] The low-voltage lead frame 90 and the high-voltage lead frame 100 are each made of a conductor, which in this embodiment is made of Cu (copper). Each lead frame 90, 100 is provided spanning both the inside and outside of the sealing resin 110.

[0043] The low-voltage lead frame 90 includes a low-voltage die pad 91 located within the sealing resin 110, and a plurality of low-voltage leads 92 arranged to span both the inside and outside of the sealing resin 110. Each low-voltage lead 92 constitutes an external terminal that electrically connects to an external electronic device such as an ECU 503 (see Figure 1).

[0044] The low-voltage die pad 91 is mounted on a low-voltage circuit chip 60 and a transformer chip 80. In a plan view, the low-voltage die pad 91 is positioned such that its center in the y-direction is closer to the resin side surface 113 than the center of the sealing resin 110 in the y-direction. In this embodiment, the low-voltage die pad 91 is not exposed from the sealing resin 110. In a plan view, the shape of the low-voltage die pad 91 is rectangular, with the x-direction being the longer side and the y-direction being the shorter side.

[0045] Multiple low-pressure leads 92 are arranged spaced apart from each other in the x-direction. Each of the low-pressure leads 92 located at both ends in the x-direction is integrated with the low-pressure die pad 91. A portion of each low-pressure lead 92 protrudes outward from the resin side surface 113 toward the sealing resin 110.

[0046] The high-voltage lead frame 100 includes a high-voltage die pad 101 located within the sealing resin 110, and a plurality of high-voltage leads 102 arranged to span both the inside and outside of the sealing resin 110. Each high-voltage lead 102 constitutes an external terminal that electrically connects to external electronic equipment such as the gate of a switching element 501 (see Figure 1).

[0047] A high-voltage circuit chip 70 is mounted on the high-voltage die pad 101. In a plan view, the high-voltage die pad 101 is positioned closer to the resin side surface 114 than the low-voltage die pad 91 in the y-direction. In this embodiment, the high-voltage die pad 101 is not exposed from the sealing resin 110. In a plan view, the shape of the high-voltage die pad 101 is rectangular, with the x-direction being the longer side and the y-direction being the shorter side.

[0048] The low-pressure die pad 91 and the high-pressure die pad 101 are spaced apart in the y-direction. Therefore, the y-direction can also be considered the direction of alignment of both die pads 91 and 101. The y-direction dimensions of the low-voltage die pad 91 and the high-voltage die pad 101 are determined by the size and number of semiconductor chips to be mounted. In this embodiment, the low-voltage circuit chip 60 and the transformer chip 80 are mounted on the low-voltage die pad 91, and the high-voltage circuit chip 70 is mounted on the high-voltage die pad 101. Therefore, the y-direction dimension of the low-voltage die pad 91 is larger than that of the high-voltage die pad 101.

[0049] Multiple high-voltage leads 102 are arranged spaced apart from each other in the x-direction. One pair of the multiple high-voltage leads 102 is integrated with the high-voltage die pad 101. A portion of each high-voltage lead 102 protrudes outward from the resin side surface 114 toward the sealing resin 110.

[0050] In this embodiment, the number of high-voltage leads 102 is the same as the number of low-voltage leads 92. As can be seen from Figure 2, the multiple low-voltage leads 92 and the multiple high-voltage leads 102 are arranged in a direction (x direction) perpendicular to the arrangement direction (y direction) of the low-voltage die pads 91 and high-voltage die pads 101. Note that the number of high-voltage leads 102 and the number of low-voltage leads 92 can be changed as needed.

[0051] In this embodiment, the low-pressure die pad 91 is supported by a pair of low-pressure leads 92 integrated with the low-pressure die pad 91, and the high-pressure die pad 101 is supported by a pair of high-pressure leads 102 integrated with the high-pressure die pad 101. Therefore, each die pad 91, 101 is not provided with suspension leads exposed on the resin side surfaces 111, 112. As a result, the creepage distance between the low-pressure lead frame 90 and the high-pressure lead frame 100 can be made large.

[0052] The low-voltage circuit chip 60, the high-voltage circuit chip 70, and the transformer chip 80 are arranged spaced apart from each other in the y-direction. In the y-direction, they are arranged in the order of low-voltage circuit chip 60, transformer chip 80, and high-voltage circuit chip 70 from the low-voltage lead 92 toward the high-voltage lead 102.

[0053] The low-voltage circuit chip 60 includes the low-voltage circuit 20 shown in Figure 1. In plan view, the low-voltage circuit chip 60 has a rectangular shape with a short side and a long side. In plan view, the low-voltage circuit chip 60 is mounted on the low-voltage die pad 91 such that the long side is along the x-direction and the short side is along the y-direction. The low-voltage circuit chip 60 has a main chip surface 60s and a chip back surface (not shown) that face opposite each other in the z-direction. The chip back surface of the low-voltage circuit chip 60 is bonded to the low-voltage die pad 91 by a conductive bonding material such as solder or Ag (silver) paste.

[0054] Multiple first electrode pads 61, multiple second electrode pads 62, and multiple third electrode pads 63 are formed on the main surface 60s of the low-voltage circuit chip 60. Each electrode pad 61 to 63 is electrically connected to the low-voltage circuit 20. Each electrode pad 61 to 63 is electrically connected to the low-voltage circuit 20.

[0055] Multiple first electrode pads 61 are positioned closer to the low-voltage leads 92 than to the center of the chip main surface 60s in the y-direction. Multiple first electrode pads 61 are arranged in the x-direction. Multiple second electrode pads 62 are positioned at the ends of the chip main surface 60s in the y-direction that are closer to the transformer tip 80. Multiple second electrode pads 62 are arranged in the x-direction. Multiple third electrode pads 63 are positioned at both ends of the chip main surface 60s in the x-direction.

[0056] The high-voltage circuit chip 70 includes the high-voltage circuit 30 shown in Figure 1. In plan view, the high-voltage circuit chip 70 has a rectangular shape with a short side and a long side. In plan view, the high-voltage circuit chip 70 is mounted on the high-voltage die pad 101 such that the long side is along the x-direction and the short side is along the y-direction. The high-voltage circuit chip 70 has a main chip surface 70s and a chip back surface (not shown) that face opposite each other in the z-direction. The chip back surface of the high-voltage circuit chip 70 is bonded to the high-voltage die pad 101 by a conductive bonding material.

[0057] Multiple first electrode pads 71, multiple second electrode pads 72, and multiple third electrode pads 73 are formed on the main surface 70s of the high-voltage circuit chip 70. Each electrode pad 71 to 73 is electrically connected to the high-voltage circuit 30.

[0058] Multiple first electrode pads 71 ​​are located at the end of the chip main surface 70s in the y-direction that is closer to the trans tip 80. The multiple first electrode pads 71 ​​are arranged in the x-direction. Multiple second electrode pads 72 are located at the end of the chip main surface 70s in the y-direction that is further away from the trans tip 80. The multiple second electrode pads 72 are arranged in the x-direction. Multiple third electrode pads 73 are located at both ends of the chip main surface 70s in the x-direction.

[0059] The transchip 80 includes the transchip 40. In plan view, the shape of the transchip 80 is rectangular with a short side and a long side. In this embodiment, in plan view, the transchip 80 is mounted on the low-pressure die pad 91 such that the long side is aligned with the x-direction and the short side is aligned with the y-direction.

[0060] The transformer chip 80 is positioned adjacent to the low-voltage circuit chip 60 in the y-direction. The transformer chip 80 is positioned closer to the high-voltage circuit chip 70 than to the low-voltage circuit chip 60.

[0061] As shown in Figure 3, the trans tip 80 has a main tip surface 80s and a back tip surface 80r that face opposite each other in the z direction. The back tip surface 80r of the trans tip 80 is bonded to the low-pressure die pad 91 by a conductive bonding material SD.

[0062] As shown in Figure 2, the main surface 80s of the transformer chip 80 has a plurality of first electrode pads 81 and a plurality of second electrode pads 82 formed thereon. The transformer chip 80 also has a plurality of connecting wires 83. The plurality of first electrode pads 81 are arranged, for example, at the end of the main surface 80s in the y-direction that is closer to the low-voltage circuit chip 60. The plurality of first electrode pads 81 are arranged in the x-direction. The plurality of second electrode pads 82 are arranged, for example, at the end of the main surface 80s in the y-direction that is closer to the high-voltage circuit chip 70. The plurality of second electrode pads 82 are arranged in the x-direction. Transformers 40A and 40B are positioned between the plurality of first electrode pads 81 and the plurality of second electrode pads 82 in the y-direction. The plurality of connecting wires 83 are positioned inward from the ends of the main surface 80s in the y-direction. Each electrode pad 81, 82 and connecting wire 83 is electrically connected to the transformers 40A and 40B.

[0063] In order to set the dielectric strength of the gate driver 10 to a predetermined dielectric strength, it is necessary to space out the low-voltage die pad 91 and the high-voltage die pad 101, where the lead frames 90 and 100 are closest to each other. For this reason, in a plan view, the distance between the high-voltage circuit chip 70 and the transformer chip 80 is greater than the distance between the low-voltage circuit chip 60 and the transformer chip 80.

[0064] Multiple wires W are connected to each of the low-voltage circuit chip 60, the transformer chip 80, and the high-voltage circuit chip 70. Each wire W is a bonding wire formed by a wire bonding apparatus and consists of a conductor such as Au (gold), Al (aluminum), or Cu.

[0065] The low-voltage circuit chip 60 is electrically connected to the low-voltage lead frame 90 by wire W. More specifically, the multiple first electrode pads 61 and multiple low-voltage leads 92 of the low-voltage circuit chip 60 are connected by wire W. The multiple third electrode pads 63 of the low-voltage circuit chip 60 and a pair of low-voltage leads 92 integrated with the low-voltage die pad 91 are connected by wire W. As a result, the low-voltage circuit 20 (see Figure 1) and the multiple low-voltage leads 92 (external electrodes of the gate driver 10 that are electrically connected to the ECU 503) are electrically connected. In this embodiment, the pair of low-voltage leads 92 integrated with the low-voltage die pad 91 constitute the ground terminal, and the low-voltage circuit 20 and the low-voltage die pad 91 are electrically connected by wire W, so the low-voltage die pad 91 is at the same potential as the ground of the low-voltage circuit 20.

[0066] Each of the high-voltage circuit chip 70 and the multiple high-voltage leads 102 of the high-voltage lead frame 100 are electrically connected by a wire W. More specifically, the multiple second electrode pads 72 and multiple third electrode pads 73 of the high-voltage circuit chip 70 are connected to the high-voltage leads 102 by a wire W. As a result, the high-voltage circuit 30 (see Figure 1) and the multiple high-voltage leads 102 (external electrodes of the gate driver 10 that are electrically connected to the inverter device 500, such as the switching element 501) are electrically connected. In this embodiment, a pair of high-voltage leads 102 integrated with the high-voltage die pad 101 constitute the ground terminal, and the high-voltage circuit 30 and the high-voltage die pad 101 are electrically connected by a wire W, so that the high-voltage die pad 101 is at the same potential as the ground of the high-voltage circuit 30.

[0067] The transformer chip 80 is connected to both the low-voltage circuit chip 60 and the high-voltage circuit chip 70 by wire W. More specifically, the first electrode pad 81 of the transformer chip 80 is connected to the second electrode pad 62 of the low-voltage circuit chip 60 by wire W. The second electrode pad 82 of the transformer chip 80 is connected to the first electrode pad 71 of the high-voltage circuit chip 70 by wire W.

[0068] Furthermore, both the first coil 43A of transformer 40A and the first coil 43B of transformer 40B (see Figure 1) are electrically connected to the ground of the low-voltage circuit 20 via wire W and the low-voltage circuit chip 60, etc. Both the second coil 46A of transformer 40A and the second coil 46B of transformer 40B (see Figure 1) are electrically connected to the ground of the high-voltage circuit 30 via wire W and the high-voltage circuit chip 70, etc.

[0069] Referring to Figure 3, an example of the internal structure of the transformer chip 80 will be described. Figure 3 shows a schematic cross-sectional structure of transformer 40A of the transformer chip 80. Note that transformer 40B has the same configuration as transformer 40A, so its description will be omitted. In the following description, the direction from the back surface 80r of the transformer chip 80 towards the main surface 80s of the chip will be considered upward, and the direction from the main surface 80s towards the back surface 80r of the chip will be considered downward.

[0070] As shown in Figure 3, the transformer chip 80 includes both transformers 40A and 40B (see Figure 1), and more specifically, both transformers 40A and 40B are integrated into a single chip. In other words, the transformer chip 80 is a separate chip dedicated to both transformers 40A and 40B, distinct from the low-voltage circuit chip 60 and the high-voltage circuit chip 70. As shown in Figure 2, the transformer chip 80 is mounted with the first transformer 41A of transformer 40A and the first transformer 41B of transformer 40B located on the low-voltage circuit chip 60 side, and the second transformer 42A of transformer 40A and the second transformer 42B of transformer 40B located on the high-voltage circuit chip 70 side.

[0071] As shown in Figure 3, the trans chip 80 has a substrate 84 and an insulating layer laminate 85 formed on the substrate 84. The substrate 84 is made of, for example, a semiconductor substrate, and in this embodiment, is a substrate formed from a material containing Si (silicon). The substrate 84 has a main substrate surface 84s and a substrate back surface 84r that face opposite each other in the z direction. The substrate back surface 84r constitutes the chip back surface 80r of the transformer chip 80.

[0072] The insulating layer laminate 85 is formed by stacking multiple insulating layers 86 in the z direction, each consisting of a first insulating layer 86a and a second insulating layer 86b stacked on the first insulating layer 86a. In other words, the z direction is the thickness direction of the insulating layer laminate 85. It can also be said that the z direction is the thickness direction of the insulating layer 86. The insulating layer 86 is formed on the main substrate surface 84s of the substrate 84.

[0073] The first insulating layer 86a is, for example, an etching stopper film and consists of a SiN film, a SiC film, a SiCN film, etc. In this embodiment, the first insulating layer 86a is made of a SiN film. The second insulating layer 86b is, for example, an interlayer insulating film and consists of an SiO2 film. The bottom insulating layer 86 that is in contact with the main substrate surface 84s of the substrate 84 is made of the second insulating layer 86b. The thickness T1 of the insulating layer laminate 85 is greater than the thickness T2 of the substrate 84.

[0074] The first transformer 41A and the second transformer 42A are embedded within the insulating layer 86. As shown in Figures 2 and 3, the first transformer 41A and the second transformer 42A are aligned in the x-direction and spaced apart in the y-direction. It can also be said that the first transformer 41A and the second transformer 42A are spaced apart in the direction in which the chips 60, 70, and 80 are arranged.

[0075] The first coil 43A and the second coil 44A of the first transformer 41A are arranged facing each other in the z direction via an insulating layer 86. In this embodiment, the first coil 43A and the second coil 44A are arranged facing each other in the z direction via a plurality of insulating layers 86. Each coil 43A, 44A is configured as a conductive layer embedded in a single insulating layer 86. More specifically, the insulating layer 86 in which each coil 43A, 44A is embedded has grooves formed that penetrate both the first insulating layer 86a and the second insulating layer 86b in the z direction. The conductive layers constituting each coil 43A, 44A are embedded in the grooves of the insulating layer 86.

[0076] In other words, the first coil 43A and the second coil 44A can be said to be embedded within an insulating layer laminate 85 in which multiple insulating layers 86 are stacked. That is, the first coil 43A and the second coil 44A of this embodiment can be said to be embedded within an insulating layer laminate 85 consisting of multiple insulating layers 86, in a state in which they are spaced apart from each other and facing each other via one or more insulating layers 86.

[0077] In the z-direction, the second coil 44A is located further from the substrate 84 than the first coil 43A. In other words, the second coil 44A is located above the first coil 43A. Also, the first coil 43A is located closer to the substrate 84 than the second coil 44A in the z-direction. In this embodiment, the second coil 44A corresponds to the second conductor of the first insulating element, and the first coil 43A corresponds to the first conductor of the first insulating element.

[0078] The first coil 45A and the second coil 46A of the second transformer 42A are arranged facing each other in the z direction via an insulating layer 86. Each coil 45A and 46A, like each coil 43A and 44A, is configured as a conductive layer embedded in a single insulating layer 86. In the z direction, the first coil 45A is located further from the substrate 84 than the second coil 46A. In other words, the first coil 45A is located above the second coil 46A. Also, the second coil 46A is located closer to the substrate 84 than the first coil 45A in the z direction. In this embodiment, the first coil 45A corresponds to the fourth conductor of the second insulating element, and the second coil 46A corresponds to the third conductor of the second insulating element. Furthermore, the first coil 45A corresponds to the fourth coil, and the second coil 46A corresponds to the third coil.

[0079] The transchip 80 further comprises a protective film 87 formed on an insulating layer laminate 85 and a passivation film 88 formed on the protective film 87. The protective film 87 is a film that protects the insulating layer laminate 85 and is made of, for example, an SiO2 film. The passivation film 88 is a surface protective film of the transchip 80 and is made of, for example, a SiN film. The passivation film 88 constitutes the main chip surface 80s of the transchip 80.

[0080] Multiple first electrode pads 81, multiple second electrode pads 82, and multiple connecting wires 83 are formed on the insulating layer laminate 85. Each connecting wire 83 is made of, for example, Al. Both the protective film 87 and the passivation film 88 are formed to cover the outer periphery of the upper surface of each pad 81, 82 and the connecting wires 83. As a result, each pad 81, 82 has an exposed surface for connecting the wire W.

[0081] The first end of the first coil 43A is electrically connected to the first electrode pad 81 for electrically connecting to the low-voltage circuit 20. This electrically connects the low-voltage circuit 20 and the first coil 43A. On the other hand, the second end of the first coil 43A is electrically connected to the first electrode pad 81 for electrically connecting to the ground of the low-voltage circuit 20. This electrically connects the ground of the low-voltage circuit 20 and the first coil 43A.

[0082] The second coil 44A and the first coil 45A are connected by a connecting wire 83. In other words, both ends of the second coil 44A and the first coil 45A are connected by the connecting wire 83. Therefore, the connecting wire 83 connecting the second coil 44A and the first coil 45A constitutes the connecting signal lines 11A and 12A. Thus, the transformer chip 80 is equipped with a connecting wire 83 that connects the first transformer 41A and the second transformer 42A in series. In this embodiment, the connecting wire 83 corresponds to a wiring.

[0083] The first end of the second coil 46A is electrically connected to the second electrode pad 82 for electrically connecting to the high-voltage circuit 30. This electrically connects the high-voltage circuit 30 and the second coil 46A. On the other hand, the second end of the second coil 46A is electrically connected to the second electrode pad 82 for electrically connecting to the ground of the high-voltage circuit 30. This electrically connects the ground of the high-voltage circuit 30 and the second coil 46A.

[0084] As shown in Figure 2, each coil 44A and 45A is formed in an elliptical spiral shape in a plan view. Although not shown, the shapes of each coil 43A and 46A in a plan view are similar. The first coil 43A and the second coil 44A are formed with the same winding direction in a plan view. As shown in Figure 3, the first coil 45A and the second coil 46A are formed with the same winding direction when viewed from the z direction. The second coil 44A and the first coil 45A are formed with opposite winding directions when viewed from the z direction. The first coil 43A and the second coil 46A are formed with opposite winding directions when viewed from the z direction.

[0085] Next, the positional relationships of the first coils 43A, 45A and the second coils 44A, 46A within the transformer chip 80 will be explained. Note that the positional relationships of the first coils 43B, 45B and the second coils 44B, 46B within the transformer chip 80 are the same as those of the first coils 43A, 45A and the second coils 44A, 46A within the transformer chip 80, so their explanation will be omitted.

[0086] The positions of the first coils 43A and 45A and the second coils 44A and 46A within the transformer chip 80 are set so that the dielectric strength of the transformer chip 80 is a preset dielectric strength.

[0087] The distance D11 between the first coil 43A and the second coil 44A is greater than the distance D12 between the first coil 45A and the second coil 46A. In one example, distance D11 is more than twice the distance D12. However, it is not limited to this, and distance D11 may be less than twice the distance D12.

[0088] In this embodiment, the second coil 44A and the first coil 45A are positioned in the same location in the z-direction. On the other hand, in the z-direction, the second coil 46A is located further away from the substrate 84 (i.e., higher) than the first coil 43A. As a result, the distance D11 is greater than the distance D12.

[0089] In this case, viewed from the y-direction, the second coil 46A is positioned between the first coil 43A and the second coil 44A in the z-direction. That is, the distance D14 between the second coil 46A and the substrate 84 is greater than the distance D13 between the first coil 43A and the substrate 84. In one example, the distance D14 is more than twice the distance D13. However, it is not limited to this, and the distance D14 may be less than twice the distance D13.

[0090] Since the second coil 46A is electrically connected to the high-voltage die pad 101, the ground of the second coil 46A and the substrate 84 may be at different potentials. For this reason, the second coil 46A and the substrate 84 need to be isolated from each other. In other words, by increasing the distance D14 between the second coil 46A and the substrate 84, the dielectric strength of the transformer chip 80 can be improved.

[0091] In one example, the distance D14 between the second coil 46A and the substrate 84 is greater than or equal to the distance D12 between the first coil 45A and the second coil 46A. In this embodiment, distance D14 is greater than distance D12. In one example, distance D14 is more than twice the distance D12. However, it is not limited to this, and distance D14 may be less than twice the distance D12.

[0092] In another example, the distance D14 between the second coil 46A and the substrate 84 is greater than or equal to the distance D11 between the first coil 43A and the second coil 44A. In this embodiment, the distance D14 is equal to the distance D11.

[0093] It can also be said that the first coil 43A is located closer to the substrate 84 than the second coil 46A. Since both the first coil 43A and the substrate 84 are electrically connected to the low-voltage die pad 91, the ground of the first coil 43A and the substrate 84 are at the same potential. Therefore, even if the first coil 43A is placed close to the substrate 84, a decrease in the dielectric strength of the transformer chip 80 can be suppressed. In this embodiment, the distance D13 between the first coil 43A and the substrate 84 is smaller than the distance D11 between the first coil 43A and the second coil 44A. Distance D13 is less than or equal to half of distance D11. However, it is not limited to this, and distance D13 may be greater than half of distance D11.

[0094] In another example, the distance D15 between the second coil 46A and the first coil 43A is greater than or equal to the distance D14 between the second coil 46A and the substrate 84. Distance D15 is the shortest distance between the second coil 46A and the first coil 43A. In this embodiment, distance D15 is equal to distance D14. Distance D15 is greater than or equal to the distance D11 between the first coil 43A and the second coil 44A. In this embodiment, since distance D14 is equal to distance D11, distance D15 is equal to distance D11.

[0095] The distance D16 between the second coil 44A and the first coil 45A is set according to the distance D15 between the second coil 46A and the first coil 43A. Specifically, the central axis J1 of the first coil 43A and the central axis J2 of the second coil 44A coincide, and the central axis J3 of the first coil 45A and the central axis J4 of the second coil 46A coincide. Therefore, the x and y positions of the first coil 43A and the second coil 46A are set as a result of setting the distance D15. In a plan view, the x and y positions of the second coil 44A and the first coil 45A are the same as the x and y positions of the first coil 43A and the second coil 46A, so the distance D16 is set.

[0096] The operation of the gate driver 10 of this embodiment will be described with reference to Figures 2 and 4. Figure 4 shows the cross-sectional structure of the transchip of the comparative example gate driver 10X. In the description of the comparative example gate driver 10X, components common to the gate driver 10 will be described using the same reference numerals.

[0097] As shown in Figure 4, the comparative example gate driver 10X has a configuration in which the low-voltage circuit chip 60 includes first transformers 41A and 41B, and the high-voltage circuit chip 70 includes second transformers 42A and 42B. The low-voltage circuit 20 and the first transformers 41A and 41B are electrically connected. The high-voltage circuit 30 and the second transformers 42A and 42B are electrically connected.

[0098] The low-voltage circuit chip 60 and the high-voltage circuit chip 70 are connected by a wire W. This electrically connects the second coil 44A of the first transformer 41A and the second coil 46A of the second transformer 42A, and also electrically connects the second coil 44B of the first transformer 41B and the second coil 46B of the second transformer 42B.

[0099] Thus, in the comparative example gate driver 10X, the first transformers 41A and 41B are included in the low-voltage circuit chip 60X, and the second transformers 42A and 42B are included in the high-voltage circuit chip 70X. Therefore, when changing the configuration of the low-voltage circuit 20 or the high-voltage circuit 30, it is necessary to change the low-voltage circuit chip 60X or the high-voltage circuit chip 70X, even if the configurations of the first transformers 41A and 41B and the second transformers 42A and 42B are the same.

[0100] In this embodiment, a single transformer chip 80 includes the first transformers 41A, 41B and the second transformers 42A, 42B. In other words, the gate driver 10 has dedicated chips for the first transformers 41A, 41B and the second transformers 42A, 42B. Therefore, unlike the low-voltage circuit chip 60X and high-voltage circuit chip 70X in the comparative example gate driver 10X, there is no need to change the first transformers 41A, 41B and the second transformers 42A, 42B when the configuration of the low-voltage circuit 20 or high-voltage circuit 30 is changed.

[0101] The gate driver 10 of this embodiment provides the following effects. While the following description focuses on the first transformer 41A and the second transformer 42A, similar effects can be obtained with the first transformer 41B and the second transformer 42B.

[0102] (1-1) The gate driver 10 includes a low-voltage circuit 20 that operates when a first voltage V1 is applied, a high-voltage circuit 30 that operates when a second voltage V2 higher than the first voltage V1 is applied, and a transformer chip 80. The transformer chip 80 includes a substrate 84, an insulating layer 86 formed on the substrate 84, a first transformer 41A having a first coil 43A and a second coil 44A embedded in the insulating layer 86 and facing each other, and a second transformer 42A having a first coil 45A and a second coil 46A embedded in the insulating layer 86 and facing each other. The low-voltage circuit 20 and the high-voltage circuit 30 are connected via the first transformer 41A and the second transformer 42A which are connected in series with each other, and signals are transmitted via the first transformer 41A and the second transformer 42A.

[0103] In this configuration, the low-voltage circuit 20 and the high-voltage circuit 30 are connected via a first transformer 41A and a second transformer 42A that are connected in series with each other, and signals are transmitted through both transformers 41A and 42A. This improves the dielectric strength of the gate driver 10 compared to a configuration in which signals are transmitted through a single transformer.

[0104] Here, a possible configuration in which the gate driver 10 has two transformers connected in series is to include, for example, a first chip including a low-voltage circuit and a first transformer, and a second chip including a high-voltage circuit and a second transformer, and connect the first and second transformers in series by connecting these chips with wires. However, in this configuration, if the low-voltage circuit or the high-voltage circuit is changed, the entire chip must be changed, which increases the cost when manufacturing multiple types of gate drivers.

[0105] In this regard, according to this embodiment, since the first transformer 41A and the second transformer 42A are provided within a single transformer chip 80, that is, a chip dedicated to the transformer 40 is provided, a common transformer chip 80 can be used for different low-voltage circuits 20 and high-voltage circuits 30. This makes it possible to reduce costs when manufacturing multiple types of gate drivers 10 in which at least one of the low-voltage circuits 20 and high-voltage circuits 30 is different.

[0106] (1-2) The gate driver 10 includes a low-voltage die pad 91 on which a low-voltage circuit 20 is mounted. The transformer chip 80 is mounted on the low-voltage die pad 91. The low-voltage circuit 20 is electrically connected to the first coil 43A, the high-voltage circuit 30 is electrically connected to the second coil 46A, and the second coil 44A is electrically connected to the first coil 45A. The first coil 43A is located closer to the substrate 84 than the second coil 44A in the z direction. The second coil 46A is located closer to the substrate 84 than the first coil 45A in the z direction. In the z direction, the second coil 46A is located further from the substrate 84 than the first coil 43A.

[0107] In this configuration, when the first coil 43A and the substrate 84 are connected to the ground of the low-voltage circuit 20, it is difficult for a high voltage to be applied to the first coil 43A. On the other hand, when the second coil 44A is connected to the ground of the high-voltage circuit 30, the potential of the second coil 46A tends to be higher than that of the substrate 84. Therefore, a high voltage is easily applied between the second coil 46A and the substrate 84.

[0108] In this embodiment, the distance D14 between the second coil 46A, to which high voltage is easily applied, and the substrate 84 is made larger than the distance D13 between the first coil 43A, to which high voltage is less easily applied, and the substrate 84. This improves the dielectric strength of the transformer chip 80.

[0109] (1-3) The distance D14 between the second coil 46A of the second transformer 42A and the substrate 84 is greater than or equal to the distance D11 between the first coil 43A and the second coil 44A of the first transformer 41A. With this configuration, the distance D14 between the second coil 46A, to which high voltage is easily applied, and the substrate 84 can be made larger, thereby improving the dielectric strength of the transformer chip 80.

[0110] (1-4) The distance D14 between the second coil 46A of the second transformer 42A and the substrate 84 is greater than or equal to the distance D12 between the first coil 45A and the second coil 46A of the second transformer 42A. With this configuration, the distance D14 between the second coil 46A and the substrate 84 can be made larger while suppressing an increase in the z-direction dimension of the transformer chip 80, thereby improving the dielectric strength of the transformer chip 80. In addition, the voltage applied between the first coil 45A and the second coil 46A tends to be lower than the voltage applied between the second coil 46A and the substrate 84. For this reason, the dielectric strength of the transformer chip 80 can be ensured even if the distance D12 is small.

[0111] (1-5) The distance D15 between the second coil 46A of the second transformer 42A and the first coil 43A of the first transformer 41A is greater than or equal to the distance D14 between the second coil 46A and the substrate 84.

[0112] When the first transformer 41A and the second transformer 42A are integrated into a single chip, high voltage is easily applied between the first coil 43A of the first transformer 41A and the second coil 46A of the second transformer 42A, making dielectric breakdown likely. In this embodiment, however, since the distance D15 between the second coil 46A and the first coil 43A is set to be greater than or equal to the distance D14 between the second coil 46A and the substrate 84, dielectric breakdown is less likely to occur between the first coil 43A and the second coil 46A. Therefore, the dielectric strength of the transformer chip 80 can be improved.

[0113] (1-6) The distance D11 between the first coil 43A and the second coil 44A of the first transformer 41A is greater than the distance D12 between the first coil 45A and the second coil 46A of the second transformer 42A. This configuration makes it possible to suppress dielectric breakdown between the first coil 43A and the second coil 44A. As a result, even if dielectric breakdown occurs between the first coil 45A and the second coil 46A due to some factor, it is possible to suppress the application of a high voltage to the first coil 43A.

[0114] (1-7) The second coil 44A of the first transformer 41A and the first coil 45A of the second transformer 42A are aligned with each other in the z direction. With this configuration, since both the second coil 44A and the first coil 45A are provided on the same insulating layer 86, both coils 44A and 45A can be manufactured simultaneously, thereby simplifying the manufacturing of the transformer chip 80.

[0115] (1-8) The second coil 44A of the first transformer 41A and the first coil 45A of the second transformer 42A are connected by a connecting wire 83. With this configuration, the distance between the second coil 44A and the first coil 45A in the y-direction can be reduced compared to the connection structure between the second coil 44A and the first coil 45A using wire W. Therefore, the transformer chip 80 can be miniaturized.

[0116] (1-9) In a plan view, the first transformer 41A and the second transformer 42A are aligned in the x-direction and spaced apart in the y-direction. With this configuration, in a plan view, the transformer chip 80 can be made smaller compared to a configuration in which the first transformer 41A and the second transformer 42A are offset in the x-direction.

[0117] (1-10) The first transformer 41A is positioned closer to the low-voltage circuit chip 60 than the second transformer 42A of the transformer chip 80. With this configuration, since the first transformer 41A, which is electrically connected to the low-voltage circuit 20, is positioned closer to the low-voltage circuit chip 60, the conductive path between the low-voltage circuit 20 and the first transformer 41A can be shortened. Therefore, the inductance caused by the length of the conductive path between the low-voltage circuit 20 and the first transformer 41A can be reduced.

[0118] Furthermore, the second transformer 42A is positioned closer to the high-voltage circuit chip 70 than the first transformer 41A within the transformer chip 80. With this configuration, since the second transformer 42A, which is electrically connected to the high-voltage circuit 30, is positioned closer to the high-voltage circuit chip 70, the conductive path between the high-voltage circuit 30 and the second transformer 42A can be shortened. Therefore, the inductance caused by the length of the conductive path between the high-voltage circuit 30 and the second transformer 42A can be reduced.

[0119] (1-11) The winding directions of the coils 43A and 44A of the first transformer 41A and the winding directions of the coils 45A and 46A of the second transformer 42A are opposite. With this configuration, the magnetic fields of the coils 43A and 44A and the magnetic fields of the coils 45A and 46A can be strengthened against each other. This allows the first transformer 41A and the second transformer 42A to be brought closer together in the y-direction. Therefore, the transformer chip 80 can be miniaturized.

[0120] [Second Embodiment] The gate driver 10 of the second embodiment will be described with reference to Figures 5 to 7. The gate driver 10 of this embodiment differs from the gate driver 10 of the first embodiment in that the insulating structure has been changed from one using a transformer 40 to one using a capacitor 50. In the following description, the differences from the first embodiment will be mainly described, and components common to both the first embodiment and this embodiment will be denoted by the same reference numerals, and their descriptions will be omitted.

[0121] As shown in Figure 5, the capacitor 50, which serves as an insulating structure to electrically isolate the low-voltage circuit 20 from the high-voltage circuit 30, has a capacitor 50A connected to a signal line that transmits a set signal and a capacitor 50B connected to a signal line that transmits a reset signal. Both capacitors 50A and 50B are provided between the low-voltage circuit 20 and the high-voltage circuit 30.

[0122] The gate driver 10 includes a connection signal line 13A provided between the low-voltage signal line 21A and the high-voltage signal line 31A as a signal line for transmitting a set signal, and a connection signal line 13B provided between the low-voltage signal line 21B and the high-voltage signal line 31B as a signal line for transmitting a reset signal. In other words, the signal lines for transmitting the set signal include the low-voltage signal line 21A, the high-voltage signal line 31A, and the connection signal line 13A. The signal lines for transmitting the reset signal include the low-voltage signal line 21B, the high-voltage signal line 31B, and the connection signal line 13B.

[0123] Capacitor 50A has a first capacitor 51A and a second capacitor 52A connected in series with each other via a connecting signal line 13A. The first capacitor 51A is electrically connected to the low-voltage circuit 20, and the second capacitor 52A is electrically connected to the high-voltage circuit 30. In detail, the first capacitor 51A has a first electrode 53A and a second electrode 54A, and the second capacitor 52A has a first electrode 55A and a second electrode 56A. The first electrode 53A of the first capacitor 51A is connected to the low-voltage circuit 20 by a low-voltage signal line 21A, and the second electrode 54A is connected to the first electrode 55A of the second capacitor 52A via a connecting signal line 13A. The second electrode 56A of the second capacitor 52A is connected to the high-voltage circuit 30 by a high-voltage signal line 31A. Therefore, the low-voltage circuit 20 and the high-voltage circuit 30 transmit set signals via the first capacitor 51A and the second capacitor 52A connected in series with each other.

[0124] Capacitor 50B has a first capacitor 51B and a second capacitor 52B connected in series with each other via a connection signal line 13B. The first capacitor 51B has a first electrode 53B and a second electrode 54B, and the second capacitor 52B has a first electrode 55B and a second electrode 56B. The configuration of capacitor 50B and the connection configuration with the low-voltage circuit 20 and the high-voltage circuit 30 are the same as those of capacitor 50A, so a detailed explanation is omitted. The low-voltage circuit 20 and the high-voltage circuit 30 transmit a reset signal via the first capacitor 51B and the second capacitor 52B connected in series with each other.

[0125] As shown in Figure 6, the gate driver 10 includes a capacitor chip 120 containing capacitors 50A and 50B, instead of the transformer chip 80 of the first embodiment. The arrangement configuration of the capacitor chip 120 in the gate driver 10 is the same as that of the transformer chip 80 of the first embodiment. For this reason, the capacitor chip 120 is mounted on the low-voltage die pad 91. In this embodiment, the capacitor chip 120 corresponds to an isolation chip.

[0126] As shown in Figure 7, the capacitor chip 120 has a main chip surface 120s and a back surface 120r that face opposite each other in the z direction. The back surface 120r of the capacitor chip 120 is bonded to the low-pressure die pad 91 by a conductive bonding material SD.

[0127] As shown in Figure 6, the main surface 120s of the capacitor chip 120 has a plurality of first electrode pads 121 and a plurality of second electrode pads 122 formed thereon. The capacitor chip 120 also has a plurality of connection wires 123. The plurality of first electrode pads 121 are located at the end of the main surface 120s in the y-direction that is closer to the low-voltage circuit chip 60. The plurality of first electrode pads 121 are arranged in the x-direction. The plurality of second electrode pads 122 are located at the end of the main surface 120s in the y-direction that is closer to the high-voltage circuit chip 70. The plurality of second electrode pads 122 are arranged in the x-direction. In a plan view, capacitors 50A and 50B are arranged between the plurality of first electrode pads 121 and the plurality of second electrode pads 122 in the y-direction. Capacitors 50A and 50B are aligned with each other in the y-direction and spaced apart from each other in the x-direction. Multiple connection wires 123 are positioned inward from both ends of the chip main surface 120s in the y-direction. Each electrode pad 121, 122 and connection wire 123 is electrically connected to capacitors 50A and 50B.

[0128] Referring to Figure 7, an example of the internal structure of the capacitor chip 120 will be described. Figure 7 shows a schematic cross-sectional structure of capacitor 50A. Note that capacitor 50B has the same configuration as capacitor 50A, so its description will be omitted. In the following description, the direction from the back surface 120r of the capacitor chip 120 toward the main surface 120s of the chip will be considered upward, and the direction from the main surface 120s toward the back surface 120r of the chip will be considered downward.

[0129] As shown in Figure 7, the capacitor chip 120 includes both capacitors 50A and 50B (see Figure 6), and more specifically, both capacitors 50A and 50B are integrated into a single chip. Similar to the transformer chip 80 of the first embodiment (see Figure 3), the capacitor chip 120 has a substrate 124 and an insulating layer laminate 125 formed on the substrate 124.

[0130] The substrate 124 is made of, for example, a semiconductor substrate, and in this embodiment, is a substrate formed from a material containing Si. The substrate 124 has a main substrate surface 124s and a substrate back surface 124r that face opposite each other in the z direction. The substrate back surface 124r constitutes the chip back surface 120r of the capacitor chip 120.

[0131] The insulating layer laminate 125 is formed by stacking multiple insulating layers 126 in the z direction, each consisting of a first insulating layer 126a and a second insulating layer 126b laminated on the first insulating layer 126a. The insulating layer 126 is formed on the main substrate surface 124s of the substrate 124. In this embodiment, the insulating layer 126 is made of a dielectric layer. The materials of the first insulating layer 126a and the second insulating layer 126b may be the same as, for example, the first insulating layer 86a and the second insulating layer 86b in the first embodiment (both see Figure 3). The thickness T3 of the insulating layer laminate 125 is greater than the thickness T4 of the substrate 124.

[0132] A first capacitor 51A and a second capacitor 52A are embedded within the insulating layer 126. As shown in Figures 6 and 7, the first capacitor 51A and the second capacitor 52A are aligned in the x-direction and spaced apart in the y-direction. It can also be said that the first capacitor 51A and the second capacitor 52A are spaced apart in the direction in which the chips 60, 70, and 120 are arranged. As shown in Figure 6, the capacitor chip 120 is mounted such that the first capacitor 51A of capacitor 50A and the first capacitor 51B of capacitor 50B are located on the low-voltage circuit chip 60 side, and the second capacitor 52A of capacitor 50A and the second capacitor 52B of capacitor 50B are located on the high-voltage circuit chip 70 side.

[0133] As shown in Figure 6, the shapes of the electrodes 54A and 55A of each capacitor 51A and 52A in a plan view are rectangular. Although not shown, the shapes of the electrodes 53A and 56A of each capacitor 51A and 52A in a plan view are also rectangular. In this embodiment, the size of the first electrode 53A of the first capacitor 51A is equal to the size of the second electrode 54A. The size of the first electrode 55A of the second capacitor 52A is equal to the size of the second electrode 56A. As shown in Figure 6, in this embodiment, the size of the second electrode 54A is equal to the size of the first electrode 55A. Note that the sizes of these electrodes 53A, 54A, 55A, and 56A are arbitrary and can be changed individually.

[0134] As shown in Figure 7, the first electrode 53A and the second electrode 54A of the first capacitor 51A are arranged facing each other in the z direction via an insulating layer 126. Each electrode 53A and 54A is configured as a conductive layer embedded within a single insulating layer 126. In other words, the insulating layer 126 into which each electrode 53A and 54A is embedded has openings that penetrate both the first insulating layer 126a and the second insulating layer 126b in the z direction. The conductive layers constituting each electrode 53A and 54A are embedded in the openings of the insulating layer 126.

[0135] In other words, the first electrode 53A and the second electrode 54A can be said to be embedded within an insulating layer laminate 125 in which multiple insulating layers 126 are stacked. That is, the first electrode 53A and the second electrode 54A of this embodiment can be said to be embedded within an insulating layer laminate 125 consisting of multiple insulating layers 126, in a state in which they are spaced apart from each other and facing each other via one or more insulating layers 126.

[0136] In the z-direction, the second electrode 54A is located further from the substrate 124 than the first electrode 53A. In other words, the second electrode 54A is located above the first electrode 53A. In this embodiment, the second electrode 54A corresponds to the second conductor of the first insulating element, and the first electrode 53A corresponds to the first conductor of the first insulating element. Furthermore, the second electrode 54A corresponds to the second electrode plate, and the first electrode 53A corresponds to the first electrode plate.

[0137] The first electrode 55A and the second electrode 56A of the second capacitor 52A are arranged facing each other in the z direction via an insulating layer 126. Each electrode 55A, 56A, like each electrode 53A, 54A, is configured as a conductive layer embedded in a single insulating layer 126. In the z direction, the first electrode 55A is located further from the substrate 124 than the second electrode 56A. In other words, the first electrode 55A is located above the second electrode 56A. In this embodiment, the first electrode 55A corresponds to the fourth conductor of the second insulating element, and the second electrode 56A corresponds to the third conductor of the second insulating element. Furthermore, the first electrode 55A corresponds to the fourth electrode plate, and the second electrode 56A corresponds to the third electrode plate.

[0138] The capacitor chip 120, like the transformer chip 80, further includes a protective film 127 formed on the insulating layer laminate 125 and a passivation film 128 formed on the protective film 127. The protective film 127 and the passivation film 128 are made of the same material as the protective film 87 and passivation film 88 of the transformer chip 80 (see Figure 3). The passivation film 128 constitutes the main chip surface 120s of the capacitor chip 120.

[0139] Multiple first electrode pads 121, multiple second electrode pads 122, and multiple connecting wires 123 are formed on the insulating layer laminate 125. Both the protective film 127 and the passivation film 128 are formed to cover the outer periphery of the upper surface of each pad 121, 122 and the connecting wires 123. As a result, each pad 121, 122 has an exposed surface for connecting the wire W.

[0140] The first electrode 53A is electrically connected to the first electrode pad 121 for electrical connection to the low-voltage circuit 20. This electrically connects the low-voltage circuit 20 and the first electrode 53A. The second electrode 54A and the first electrode 55A are connected by a connecting wire 123. This electrically connects the second electrode 54A and the first electrode 55A. The second electrode 56A is electrically connected to the second electrode pad 122 for electrical connection to the high-voltage circuit 30. This electrically connects the high-voltage circuit 30 and the second electrode 56A. Therefore, the connecting wire 123 connecting the second electrode 54A and the first electrode 55A constitutes the connecting signal line 13A. Thus, the capacitor chip 120 includes a connecting wire 123 that connects the first capacitor 51A and the second capacitor 52A in series. In this embodiment, the connecting wire 123 corresponds to a wiring.

[0141] Next, the positional relationships of the first electrodes 53A, 55A and the second electrodes 54A, 56A within the capacitor chip 120 will be explained. Note that the positional relationships of the first electrodes 53B, 55B and the second electrodes 54B, 56B within the capacitor chip 120 are the same as those of the first electrodes 53A, 55A and the second electrodes 54A, 56A within the capacitor chip 120, so their explanation will be omitted.

[0142] The positions of the first electrodes 53A, 55A and the second electrodes 54A, 56A within the capacitor chip 120 are set so that the dielectric strength of the capacitor chip 120 is a preset dielectric strength.

[0143] The distance D21 between the first electrode 53A and the second electrode 54A is greater than the distance D22 between the first electrode 55A and the second electrode 56B. In this embodiment, the distance D21 is at least twice the distance D22. However, it is not limited to this, and the distance D21 may be less than twice the distance D22.

[0144] In this embodiment, the second electrode 54A and the first electrode 55A are aligned with each other in the z-direction. On the other hand, in the z-direction, the second electrode 56A is located further away from the substrate 124 (i.e., above) than the first electrode 53A. As a result, the distance D21 is greater than the distance D22.

[0145] In this case, viewed from the y-direction, the second electrode 56A is positioned between the first electrode 53A and the second electrode 54A in the z-direction. That is, the distance D24 between the second electrode 56A and the substrate 124 is greater than the distance D23 between the first electrode 53A and the substrate 124. In this embodiment, the distance D24 is at least twice the distance D23. However, it is not limited to this, and the distance D24 may be less than twice the distance D23.

[0146] Since the second electrode 56A is electrically connected to the high-voltage die pad 101 and the substrate 124 is electrically connected to the low-voltage die pad 91, the ground of the second electrode 56A and the substrate 124 may be at different potentials. For this reason, the second electrode 56A and the substrate 124 need to be isolated from each other. In other words, by increasing the distance D24 between the second electrode 56A and the substrate 124, the dielectric strength of the capacitor chip 120 can be improved.

[0147] It can also be said that the first electrode 53A is located closer to the substrate 124 than the second electrode 54A. Since both the first electrode 53A and the substrate 124 are electrically connected to the low-voltage die pad 91, the ground of the first electrode 53A and the substrate 124 are at the same potential. Therefore, even if the first electrode 53A is placed close to the substrate 124, a decrease in the dielectric breakdown voltage of the capacitor chip 120 can be suppressed. In this embodiment, the distance D23 between the first electrode 53A and the substrate 124 is smaller than the distance D21 between the first electrode 53A and the second electrode 54A. The distance D23 may be less than or equal to half the distance D21. However, it is not limited to this, and the distance D23 may be greater than half the distance D21.

[0148] In one example, the distance D24 between the second electrode 56A and the substrate 124 is greater than or equal to the distance D22 between the first electrode 55A and the second electrode 56A. In this embodiment, distance D24 is greater than distance D22. Distance D24 may be more than twice the distance D22. However, it is not limited to this, and distance D24 may be less than twice the distance D22.

[0149] In another example, the distance D24 between the second electrode 56A and the substrate 124 is greater than or equal to the distance D21 between the first electrode 53A and the second electrode 54A. In this embodiment, distance D24 is equal to distance D21.

[0150] In another example, the distance D25 between the second electrode 56A and the first electrode 53A is greater than or equal to the distance D24 between the second electrode 56A and the substrate 124. In this embodiment, distance D25 is equal to distance D24. Distance D25 is greater than or equal to the distance D21 between the first electrode 53A and the second electrode 54A. In this embodiment, since distance D24 is equal to distance D21, distance D25 is equal to distance D21.

[0151] The distance D26 between the second electrode 54A and the first electrode 55A is set according to the distance D25 between the second electrode 56A and the first electrode 53A. Specifically, the center of the first electrode 53A coincides with the center of the second electrode 54A, and the center of the first electrode 55A coincides with the center of the second electrode 56A. Therefore, the x and y positions of the first electrode 53A and the second electrode 56A are set as a result of setting the distance D25. In a plan view, the x and y positions of the second electrode 54A and the first electrode 55A are the same as the x and y positions of the first electrode 53A and the second electrode 56A, so the distance D26 is set. Furthermore, the gate driver 10 of this embodiment provides the same effects as the gate driver 10 of the first embodiment.

[0152] [Example of changes] The embodiments described above are illustrative of possible forms of the gate driver relating to this disclosure and are not intended to limit its form. The gate driver relating to this disclosure may take forms different from those illustrated in the embodiments described above. For example, a form in which some of the configurations of the embodiments described above are replaced, modified, or omitted, or a form in which new configurations are added to the embodiments described above. Furthermore, the following modifications can be combined with each other as long as they do not technically contradict each other. In the following modifications, parts common to the embodiments described above are denoted by the same reference numerals as in the embodiments described above, and their descriptions are omitted.

[0153] In the first embodiment, the configuration and material of the substrate 84 can be arbitrarily changed. In the first example, as shown in Figure 8, the substrate 84 may be a substrate formed from a material including glass. In this case, since the substrate 84 has electrical insulating properties, it is difficult for a high voltage to be applied between the second coil 46A of the second transformer 42A and the substrate 84. For this reason, the second coil 46A can be brought closer to the substrate 84. In one example, the position of the second coil 46A in the z direction is aligned with the position of the first coil 43A of the first transformer 41A in the z direction. In other words, the first coil 43A and the second coil 46A are positioned at positions aligned with each other in the z direction. That is, the second coil 46A and the first coil 43A are provided in the same insulating layer 86 among the multiple insulating layers 86. In the illustrated example, the second coil 46A and the first coil 43A are provided in the bottom insulating layer 86 among the multiple insulating layers 86.

[0154] Since the second coil 44A and the first coil 45A are positioned aligned with each other in the z-direction, the distance D11 between the first coil 43A and the second coil 44A is equal to the distance D12 between the first coil 45A and the second coil 46A. In the illustrated example, the distance D15 between the first coil 43A and the second coil 46A is greater than or equal to the distances D11 and D12. In the illustrated example, the distance D15 is greater than the distances D11 and D12. Also in the illustrated example, the distance D15 is equal to the distance D15 between the second coil 44A and the first coil 45A.

[0155] In this configuration, since the substrate 84 is made of a material including glass, it is difficult to apply a high voltage between the second coil 46A and the substrate 84. Therefore, the dielectric strength of the transformer chip 80 is set based on the dielectric strength between the first coil 43A and the second coil 46A. Thus, the dielectric strength of the transformer chip 80 can be easily set.

[0156] In the second example, as shown in Figure 9, the substrate 84 may be an SOI (Silicon on Insulator) substrate. The substrate 84 has a lower Si layer 84a, an SiO2 layer 84b as an insulating layer laminated on the lower Si layer 84a, and an upper Si layer 84c laminated on the SiO2 layer 84b. The SiO2 layer 84b can also be said to be positioned between the lower Si layer 84a and the upper Si layer 84c. Here, the lower Si layer 84a corresponds to the first semiconductor layer, the upper Si layer 84c corresponds to the second semiconductor layer, and the SiO2 layer 84b corresponds to the semiconductor oxide layer.

[0157] The lower surface of the lower Si layer 84a constitutes the chip back surface 80r of the trans chip 80. In the illustrated example, the SiO2 layer 84b is laminated over the entire upper surface of the lower Si layer 84a. The upper Si layer 84c is laminated over the entire upper surface of the SiO2 layer 84b.

[0158] An insulating strip 84d is formed in the upper Si layer 84c, which penetrates the upper Si layer 84c and reaches the SiO2 layer 84b. In other words, the insulating strip 84d is in contact with the SiO2 layer 84b. The insulating strip 84d is, for example, a DTI (Deep Trench Isolation). One or more insulating strips 84d are provided. In the illustrated example, two insulating strips 84d are provided spaced apart from each other in the y direction. In a plan view, the two insulating strips 84d are positioned between the first coil 43A, which is the first lower conductor, and the second coil 46A, which is the second lower conductor. The two insulating strips 84d separate the upper Si layer 84c into a first Si layer 84ca facing the first coil 43A and a second Si layer 84cb facing the second coil 46A. Here, the first Si layer 84ca corresponds to the first isolation semiconductor layer, and the second Si layer 84cb corresponds to the second isolation semiconductor layer.

[0159] Since the upper Si layer 84c is insulated from the lower Si layer 84a by the SiO2 layer 84b, and the first Si layer 84ca and the second Si layer 84cb are insulated by the separation zone 84d, the second coil 46A may be positioned close to the substrate 84 (upper Si layer 84c) in the z direction. In the illustrated example, the second coil 46A and the first coil 43A are positioned aligned with each other in the z direction.

[0160] Since the second coil 44A and the first coil 45A are positioned aligned with each other in the z-direction, the distance D11 between the first coil 43A and the second coil 44A is equal to the distance D12 between the first coil 45A and the second coil 46A. Also, the distance D13 between the first coil 43A and the substrate 84 (upper Si layer 84c) is equal to the distance D14 between the second coil 46A and the substrate 84 (upper Si layer 84c). In the illustrated example, the distance D15 between the first coil 43A and the second coil 46A is greater than the distances D13 and D14. Also, distance D15 is greater than or equal to the distances D11 and D12. In the illustrated example, distance D15 is greater than the distances D11 and D12. Also, in the illustrated example, distance D15 is equal to the distance D16 between the second coil 44A and the first coil 45A.

[0161] With this configuration, the distance D12 between the first coil 45A and the second coil 46A of the second transformer 42A can be increased, thereby improving the dielectric strength of the transformer tip 80.

[0162] Furthermore, the configuration of the substrate 84 shown in Figures 8 and 9 can also be applied to the substrate 124 of the capacitor chip 120 of the second embodiment. In this case, the positional relationship between the first electrode 53A and the second electrode 54A of the first capacitor 51A and the first electrode 55A and the second electrode 56A of the second capacitor 52A is the same as the positional relationship between the first coil 43A and the second coil 44A of the first transformer 41A and the first coil 45A and the second coil 46A of the second transformer 42A shown in Figures 8 and 9.

[0163] In the first embodiment, the transchip 80 may be mounted on the high-voltage die pad 101. Figure 10 shows a schematic cross-sectional structure of the transchip 80 mounted on the high-voltage die pad 101.

[0164] As shown in Figure 10, in the modified transformer chip 80, similar to the first embodiment, the first coil 43A is electrically connected to the low-voltage circuit 20 via the first electrode pad 81, and the second coil 46A is electrically connected to the high-voltage circuit 30 via the second electrode pad 82. The second coil 44A and the first coil 45A are electrically connected via a connecting wire 83.

[0165] On the other hand, as shown in Figure 10, in the modified transformer chip 80, the positional relationship between the first coil 43A and the second coil 44A of the first transformer 41A and the first coil 45A and the second coil 46A of the second transformer 42A is different. More specifically, in the z direction, the first coil 43A is located further from the substrate 84 than the second coil 46A. Viewed from the y direction, the first coil 43A can also be said to be positioned between the z-direction positions of the first coil 45A and the second coil 46A. Furthermore, the second coil 44A and the first coil 45A are aligned with each other in the z direction. For this reason, the distance D12 between the first coil 45A and the second coil 46A is greater than the distance D11 between the first coil 43A and the second coil 44A. The distance D13 between the first coil 43A and the substrate 84 is greater than the distance D14 between the second coil 46A and the substrate 84.

[0166] The distance D13 between the first coil 43A and the substrate 84 is greater than or equal to the distance D11 between the first coil 43A and the second coil 44A. In the illustrated example, distance D13 is greater than distance D11.

[0167] The distance D13 between the first coil 43A and the substrate 84 is greater than or equal to the distance D12 between the first coil 45A and the second coil 46A. In the illustrated example, distance D13 is equal to distance D12.

[0168] The distance D15 between the first coil 43A and the second coil 46A is greater than or equal to the distance D13 between the first coil 43A and the substrate 84. In the illustrated example, distance D15 is equal to distance D13.

[0169] The distance D15 between the first coil 43A and the second coil 46A is greater than or equal to the distance D12 between the first coil 45A and the second coil 46A. In the illustrated example, distance D15 is equal to distance D12.

[0170] This configuration provides the same effects as the gate driver 10 of the first embodiment. In the second embodiment, the capacitor chip 120 may be mounted on the high-voltage die pad 101. In this case, the positional relationship between the first electrode 53A and the second electrode 54A of the first capacitor 51A and the first electrode 55A and the second electrode 56A of the second capacitor 52A is the same as the positional relationship between the first coil 43A and the second coil 44A of the first transformer 41A and the first coil 45A and the second coil 46A of the second transformer 42A shown in Figure 10.

[0171] In the first embodiment, the positions in the z-direction of the second coil 44A of the first transformer 41A and the first coil 45A of the second transformer 42A can be arbitrarily changed. The positions in the z-direction of the second coil 44A and the first coil 45A may be different from each other. For example, the second coil 44A may be located lower than the first coil 45A. The second embodiment may also be modified in a similar manner.

[0172] In the first embodiment, the distance D11 between the first coil 43A and the second coil 44A may be less than or equal to the distance D12 between the first coil 45A and the second coil 46A. In this case, the distance D13 between the first coil 43A and the substrate 84 may be greater than or equal to the distance D14 between the second coil 46A and the substrate 84. The second embodiment may also be modified in a similar manner.

[0173] In the first embodiment, the distance D14 between the second coil 46A and the substrate 84 may be less than or equal to the distance D13 between the first coil 43A and the substrate 84. That is, the second coil 46A may be aligned with the first coil 43A in the z direction, or it may be positioned closer to the substrate 84 than the first coil 43A. In this case, it is preferable that the distance D13 between the first coil 43A and the substrate 84 is greater than or equal to the distance D14 between the second coil 46A and the substrate 84 in the first embodiment. The second embodiment may also be modified in a similar manner.

[0174] In the first embodiment, the distance D15 between the second coil 46A and the first coil 43A may be less than the distance D14 between the second coil 46A and the substrate 84. Also, the distance D15 between the second coil 46A and the first coil 43A may be less than the distance D11 between the first coil 43A and the second coil 44A. The second embodiment may be similarly modified.

[0175] In the first embodiment, the number of turns of the first coil 43A and the number of turns of the second coil 44A can each be arbitrarily changed. The number of turns of the first coil 45A and the number of turns of the second coil 46A can each be arbitrarily changed. For example, the number of turns of the second coil 44A may be greater than the number of turns of the first coil 43A. The number of turns of the first coil 45A may be greater than the number of turns of the second coil 46A. Thus, the number of turns of the second coil of the first transformer may be greater than the number of turns of the first coil, and the number of turns of the fourth coil of the second transformer may be greater than the number of turns of the third coil.

[0176] In the first embodiment, dummy patterns may be provided around the second coils 44A and 44B of the first transformers 41A and 41B. This can suppress electric field concentration on the second coils 44A and 44B. Also, dummy patterns may be provided around the second coils 46A and 46B of the second transformers 42A and 42B. This can suppress electric field concentration on the second coils 46A and 46B.

[0177] Examples of such dummy patterns are shown in Figures 11 and 12. Figure 11 is a schematic plan view of the transformer chip 80, with the first transformers 41A, 41B and the second transformers 42A, 42B and the dummy patterns 130, 140 shown by dashed lines. Figure 12 is a schematic cross-sectional view of the transformer chip 80 showing the cross-sectional structure of the first transformer 41A and the second transformer 42A. Incidentally, in Figure 11, for convenience, we treat it as an example where two first transformers 41A, 41B and two second transformers 42A, 42B are provided. For this reason, in the following explanation, we will describe one set of first transformers 41A, 41B and second transformers 42A, 42B, and omit the explanation of the other set of first transformers 41A, 41B and second transformers 42A, 42B.

[0178] As shown in Figure 11, the dummy pattern 130 is a dummy pattern provided on the first transformers 41A and 41B. The dummy pattern 130 has a first dummy pattern 131, a second dummy pattern 132, and a third dummy pattern 133. Each dummy pattern 131 to 133 may contain at least one of Ti (titanium), TiN (titanium nitride), Au, Ag, Cu, Al, and W (tungsten). Here, the dummy pattern 130 corresponds to the dummy pattern for the first transformer.

[0179] The first dummy pattern 131 is formed around the second coils 44A and 44B of the first transformers 41A and 41B, respectively, when viewed from the z direction. In the illustrated example, the first dummy pattern 131 is formed in the region between adjacent second coils 44A and 44B in the x direction.

[0180] The first dummy pattern 131 is independent of the second coils 44A and 44B. In other words, the first dummy pattern 131 is not electrically connected to the second coils 44A and 44B. Although not shown in the diagram, the first dummy pattern 131 is formed with a different pattern from the second coils 44A and 44B.

[0181] Although not shown in the diagram, the first dummy pattern 131 is positioned in the z-direction aligned with the second coil 44A. Also, although not shown in the diagram, since the second coil 44B is positioned in the z-direction aligned with the second coil 44A, the first dummy pattern 131 is positioned in the z-direction aligned with the second coil 44B. In other words, the first dummy pattern 131 is positioned further from the substrate 84 than the first coils 43A and 43B.

[0182] By applying a voltage higher than that of the first coils 43A and 43B, for example, the same voltage as the second coils 44A and 44B, to the first dummy pattern 131, the voltage drop between the second coils 44A and 44B and the first dummy pattern 131 can be suppressed. Therefore, electric field concentration on the second coils 44A and 44B can be suppressed.

[0183] The second dummy pattern 132 is formed to surround the two second coils 44A and the two second coils 44B when viewed from the z direction. The second dummy pattern 132 is formed to be electrically floating.

[0184] As shown in Figure 12, the second dummy pattern 132 is positioned in the z-direction aligned with the second coil 44A. Although not shown, the second dummy pattern 132 is also positioned in the z-direction aligned with the second coil 44B. In other words, the second dummy pattern 132 is positioned further from the substrate 84 than the first coils 43A and 43B.

[0185] By applying a voltage higher than that of the first coils 43A and 43B, for example, the same voltage as the second coils 44A and 44B, to the second dummy pattern 132, electric field concentration on the second coils 44A and 44B can be suppressed. In addition, the second dummy pattern 132 can suppress the increase in electric field strength around the second coils 44A and 44B, as well as suppress electric field concentration on the connecting wiring 83.

[0186] As shown in Figure 11, the third dummy pattern 133 is formed in the region between the second coils 44A, 44B and the second dummy pattern 132 when viewed from the z direction. The third dummy pattern 133 is formed to surround the two second coils 44A and the two second coils 44B when viewed from the z direction. The third dummy pattern 133 is independent of the second coils 44A, 44B. In other words, the third dummy pattern 133 is not electrically connected to the second coils 44A, 44B.

[0187] As shown in Figure 12, the third dummy pattern 133 is positioned in the z-direction aligned with the second coil 44A. Although not shown, the third dummy pattern 133 is also positioned in the z-direction aligned with the second coil 44B. Thus, each dummy pattern 131 to 133 is positioned in a position aligned with each other in the z-direction. In other words, the third dummy pattern 133 is positioned further from the substrate 84 than the first coils 43A and 43B.

[0188] By applying a higher voltage to the third dummy pattern 133 than to the first coils 43A and 43B, for example, the same voltage as the second coils 44A and 44B, the voltage drop between the second coils 44A and 44B and the third dummy pattern 133 can be suppressed. Therefore, electric field concentration on the second coils 44A and 44B can be suppressed.

[0189] As shown in Figure 11, the dummy pattern 140 is a dummy pattern provided on the second transformers 42A and 42B. The dummy pattern 140 is spaced apart from the dummy pattern 130 in the y direction. In other words, an insulating layer 86 (see Figure 12) is interposed between the dummy pattern 140 and the dummy pattern 130.

[0190] The dummy pattern 140 includes a first dummy pattern 141, a second dummy pattern 142, and a third dummy pattern 143. Each dummy pattern 141 to 143 is formed from the same material as each dummy pattern 131 to 133. Here, dummy pattern 140 corresponds to the dummy pattern for the second transformer.

[0191] The first dummy pattern 141 is formed around the second coils 46A and 46B of the second transformers 42A and 42B, respectively, when viewed from the z direction. In the illustrated example, the first dummy pattern 141 is formed in the region between the adjacent first coils 45A and 45B in the x direction.

[0192] The first dummy pattern 141 is independent of the second coils 46A and 46B. In other words, the first dummy pattern 141 is not electrically connected to the second coils 46A and 46B. Although not shown in the diagram, the first dummy pattern 141 is formed with a different pattern from the second coils 46A and 46B.

[0193] Although not shown in the diagram, the first dummy pattern 141 is positioned in the z-direction aligned with the second coil 46A. Also, although not shown in the diagram, since the second coil 46B is positioned in the z-direction aligned with the second coil 46A, the first dummy pattern 141 is positioned in the z-direction aligned with the second coil 46B. In other words, the first dummy pattern 141 is positioned closer to the substrate 84 than the first coils 45A and 45B.

[0194] By applying a voltage higher than that of the first coils 45A and 45B, for example, the same voltage as the second coils 46A and 46B, to the first dummy pattern 141, the voltage drop between the second coils 46A and 46B and the first dummy pattern 141 can be suppressed. Therefore, electric field concentration on the second coils 46A and 46B can be suppressed.

[0195] As shown in Figure 12, the second dummy pattern 142 is formed to surround the two second coils 46A and the two second coils 46B when viewed from the z direction. The second dummy pattern 142 is formed to be electrically floating. As shown in Figure 11, the second dummy pattern 142 has the same shape as the second dummy pattern 132 of the first transformers 41A and 41B.

[0196] As shown in Figure 12, the second dummy pattern 142 is positioned in the z-direction aligned with the second coil 46A. Although not shown, the second dummy pattern 142 is also positioned in the z-direction aligned with the second coil 46B. In other words, the second dummy pattern 142 is positioned closer to the substrate 84 than the first coils 45A and 45B.

[0197] By applying a voltage higher than that of the first coils 45A and 45B, for example, the same voltage as the second coils 46A and 46B, to the second dummy pattern 142, electric field concentration on the second coils 46A and 46B can be suppressed. In addition, the second dummy pattern 142 can suppress the increase in electric field strength around the second coils 46A and 46B, as well as suppress electric field concentration on the connecting wiring 83.

[0198] The third dummy pattern 143 is formed in the region between the second coils 46A, 46B and the second dummy pattern 142 in the z direction. When viewed from the z direction, the third dummy pattern 143 is formed to surround the two second coils 46A and the two second coils 46B. As shown in Figure 11, the third dummy pattern 143 has the same shape as the third dummy pattern 133 of the first transformers 41A, 41B. The third dummy pattern 143 is independent of the first coils 45A, 45B. In other words, the third dummy pattern 143 is not electrically connected to the first coils 45A, 45B.

[0199] As shown in Figure 12, the third dummy pattern 143 is positioned in the z-direction aligned with the second coil 46A. Although not shown, the third dummy pattern 143 is also positioned in the z-direction aligned with the second coil 46B. Thus, each dummy pattern 141 to 143 is positioned in the z-direction aligned with each other. In other words, the third dummy pattern 143 is positioned closer to the substrate 84 than the first coils 45A and 45B. Also, as shown in Figure 12, in the z-direction, the second coils 46A and 46B are positioned closer to the substrate 84 than the second coils 44A and 44B, so each dummy pattern 141 to 143 is positioned closer to the substrate 84 than each dummy pattern 131 to 133 in the z-direction.

[0200] By applying a higher voltage to the third dummy pattern 143 than to the first coils 45A and 45B, for example, the same voltage as the second coils 46A and 46B, the voltage drop between the second coils 46A and 46B and the third dummy pattern 143 can be suppressed. Therefore, electric field concentration on the second coils 46A and 46B can be suppressed.

[0201] Next, we will explain the positional relationship between dummy patterns 130 and 140 and the first coil 43A and the second coil 46A. Note that the positional relationship between dummy patterns 130 and 140 and the first coil 43B and the second coil 46B is the same as that between dummy patterns 130 and 140 and the first coil 43A and the second coil 46A, so we will omit that explanation.

[0202] Although not shown in the diagram, the distance in the z-direction between the first dummy pattern 131 and the first coil 43A is greater than the distance D12 between the first coil 45A and the second coil 46A (see Figure 12). As shown in Figure 12, the distance D31 in the z-direction between the second dummy pattern 132 and the first coil 43A is greater than the distance D12 between the first coil 45A and the second coil 46A. The distance D32 in the z-direction between the third dummy pattern 133 and the first coil 43A is greater than the distance D12 between the first coil 45A and the second coil 46A. It can also be said that each dummy pattern 131 to 133 is positioned in the z-direction aligned with the first coil 45A.

[0203] Each dummy pattern 141-143 is positioned further from the substrate 84 than the first coil 43A in the z-direction. It can also be said that each dummy pattern 141-143 is positioned between the first coil 43A and the second coil 44A in the z-direction.

[0204] Although not shown in the diagram, the distance in the z-direction between the first dummy pattern 141 and the substrate 84 is greater than or equal to the distance D11 (see Figure 12) between the first coil 43A and the second coil 44A in the z-direction. The distance D15 (see Figure 12) between the first coil 43A and the second coil 46A is greater than or equal to the distance in the z-direction between the first dummy pattern 141 and the substrate 84. In one example, the distance D15 is equal to the distance in the z-direction between the first dummy pattern 141 and the substrate 84.

[0205] As shown in Figure 12, the distance D33 between the second dummy pattern 142 and the substrate 84 in the z-direction is greater than or equal to the distance D12 between the first coil 45A and the second coil 46A in the z-direction. In the illustrated example, distance D33 is greater than distance D12. The distance D15 between the first coil 43A and the second coil 46A is greater than or equal to the distance D33 between the second dummy pattern 142 and the substrate 84 in the z-direction. In the illustrated example, distance D15 is equal to distance D33.

[0206] The distance D34 between the third dummy pattern 143 and the substrate 84 in the z-direction is greater than or equal to the distance D12. In the illustrated example, distance D34 is greater than distance D12. The distance D15 between the first coil 43A and the second coil 46A is greater than or equal to the distance D34 between the third dummy pattern 143 and the substrate 84 in the z-direction. In the illustrated example, distance D15 is equal to distance D34.

[0207] In the modified examples shown in Figures 11 and 12, one or two of the first dummy pattern 131, the second dummy pattern 132, and the third dummy pattern 133 may be omitted from dummy pattern 130. Similarly, one or two of the first dummy pattern 141, the second dummy pattern 142, and the third dummy pattern 143 may be omitted from dummy pattern 140.

[0208] In the modified examples shown in Figures 11 and 12, the first coils 45A and 45B of the second transformers 42A and 42B may be provided with dummy patterns similar to dummy patterns 130 and 140. In other words, the second transformers 42A and 42B may be provided with dummy patterns on both the first coils 45A and 45B and the second coils 46A and 46B.

[0209] In each embodiment, multiple insulating layers 86(126) were formed on the substrate 84(124), but this is not limited to this. For example, one insulating layer 86(126) may be formed on the substrate 84(124). In this case, the thickness of the insulating layer 86(126) is greater than the thickness of the insulating layer 86(126) in each embodiment.

[0210] In the first embodiment, the gate driver 10 may include an isolation module housing a transformer 40 in a single package. The isolation module includes a transformer chip 80 and a die pad on which the transformer chip 80 is mounted. The isolation module may further include a plurality of leads, wires connecting the plurality of leads to the transformer chip 80, and a sealing resin that seals at least the transformer chip 80, the die pad, and the wires. The plurality of leads are electrically connectable to both the low-voltage circuit 20 and the high-voltage circuit 30. Similarly in the second embodiment, the gate driver 10 may also include an isolation module housing a capacitor 50 in a single package. That is, the isolation module includes an insulating chip and a die pad on which the insulating chip is mounted. This isolation module is used to isolate the low-voltage circuit 20 and the high-voltage circuit 30 included in the gate driver 10.

[0211] In the first embodiment, the gate driver 10 may include a low-voltage circuit unit that houses a low-voltage circuit 20 and a transformer 40 in a single package. The low-voltage circuit unit may include a low-voltage circuit chip 60, a transformer chip 80, and a die pad on which the low-voltage circuit chip 60 and the transformer chip 80 are mounted. The low-voltage circuit unit may further include a plurality of first leads, first wires connecting the plurality of first leads to the low-voltage circuit chip 60, a plurality of second leads, second wires connecting the plurality of second leads to the transformer chip 80, and a sealing resin that seals the low-voltage circuit chip 60, the transformer chip 80, the die pad, and each wire. The plurality of first leads can be electrically connected to, for example, an ECU 503, and the plurality of second leads can be electrically connected to a high-voltage circuit 30. Similarly in the second embodiment, the gate driver 10 may also include a low-voltage circuit unit that houses a low-voltage circuit 20 and a capacitor 50 in a single package. In other words, the low-voltage circuit unit comprises a low-voltage circuit 20, an isolation chip, and a die pad on which the low-voltage circuit chip 60 and the isolation chip are mounted. To put it another way, the low-voltage circuit unit comprises a low-voltage circuit 20 and an isolation module.

[0212] In the first embodiment, the gate driver 10 may include a high-voltage circuit unit that houses a high-voltage circuit 30 and a transformer 40 in a single package. The high-voltage circuit unit may include a high-voltage circuit chip 70, a transformer chip 80, and a die pad on which the high-voltage circuit chip 70 and the transformer chip 80 are mounted. The high-voltage circuit unit may further include a plurality of first leads, first wires connecting the plurality of first leads to the high-voltage circuit chip 70, a plurality of second leads, second wires connecting the plurality of second leads to the transformer chip 80, and a sealing resin that seals the high-voltage circuit chip 70, the transformer chip 80, the die pad, and each wire. The plurality of first leads can be electrically connected to, for example, the source of a switching element 501, and the plurality of second leads can be electrically connected to a low-voltage circuit 20. Similarly in the second embodiment, the gate driver 10 may also include a high-voltage circuit unit that houses a high-voltage circuit 30 and a capacitor 50 in a single package. In other words, the high-voltage circuit unit comprises a high-voltage circuit chip 70, an insulating chip, and a die pad on which the high-voltage circuit chip 70 and the insulating chip are mounted. To put it another way, the high-voltage circuit unit comprises a high-voltage circuit 30 and an insulating module.

[0213] In each embodiment, the gate driver 10 may transmit signals from the high-voltage circuit 30 to the low-voltage circuit 20 via the first and second insulating elements. As an example, as shown in Figure 13, a configuration in which a signal path for transmitting signals from the high-voltage circuit 30 to the low-voltage circuit 20 is added to the gate driver 10 of the first embodiment will be described.

[0214] As shown in Figure 13, the gate driver 10 is equipped with a transformer 40C for transmitting signals from the high-voltage circuit 30 to the low-voltage circuit 20. The transformer 40C transmits signals from the high-voltage circuit 30 to the low-voltage circuit 20 while isolating the high-voltage circuit 30 from the low-voltage circuit 20. This signal is, for example, an abnormality detection signal that is output when an abnormality of the switching element 501 is detected. Examples of abnormalities of the switching element 501 include an abnormality where the temperature of the switching element 501 rises excessively (temperature abnormality), an abnormality where an excessively large current flows through the switching element 501 (overcurrent), and an abnormality where an excessively high voltage is applied to the switching element 501 (overvoltage). In other words, when the gate driver 10 detects a temperature abnormality, overcurrent, overvoltage, etc. of the switching element 501, it transmits an abnormality detection signal from the high-voltage circuit 30 to the low-voltage circuit 20 via the transformer 40C.

[0215] Transformer 40C has a first transformer 41C and a second transformer 42C. The first transformer 41C has the same configuration as the first transformers 41A and 41B and has a first coil 43C and a second coil 44C. The second transformer 42C has the same configuration as the second transformers 42A and 42B and has a first coil 45C and a second coil 46C.

[0216] The first coil 43C is connected to the low-voltage signal line 21C, which is connected to the low-voltage circuit 20, while also being connected to the ground of the low-voltage circuit 20. The second coil 44C and the first coil 45C are connected by a pair of connecting signal lines 11C and 12C. The second coil 46C is connected to the high-voltage signal line 31C, which is connected to the high-voltage circuit 30, while also being connected to the ground of the high-voltage circuit 30.

[0217] The signal output from the high-voltage circuit 30 is transmitted to the low-voltage circuit 20 via the second transformer 42C and the first transformer 41C. In the illustrated example, the second transformer 42C and the first transformer 41C are arranged in that order in the direction of signal transmission.

[0218] As shown in the modified example in Figure 13, signals are transmitted bidirectionally between the low-voltage circuit 20 and the high-voltage circuit 30. These signals include a first signal transmitted from the low-voltage circuit 20 to the high-voltage circuit 30 and a second signal transmitted from the high-voltage circuit 30 to the low-voltage circuit 20. The first signal is transmitted from the low-voltage circuit 20 to the high-voltage circuit 30 via the first transformer 41A (41B) and the second transformer 42A (42B) in that order. The second signal is transmitted from the high-voltage circuit 30 to the low-voltage circuit 20 via the second transformer 42C and the first transformer 41C in that order.

[0219] [Note] The technical concepts that can be understood from each of the above embodiments and their respective modifications are described below. (Note A1) A gate driver for applying a gate voltage to the gate of a switching element, comprising: a low-voltage circuit that operates when a first voltage is applied; a high-voltage circuit that operates when a second voltage higher than the first voltage is applied; and an insulating chip, wherein the insulating chip comprises: a substrate; an insulating layer formed on the substrate; a first insulating element having a first conductor and a second conductor embedded in the insulating layer and arranged opposite to each other; and a second insulating element having a third conductor and a fourth conductor embedded in the insulating layer and arranged opposite to each other, wherein the low-voltage circuit and the high-voltage circuit are connected via the first insulating element and the second insulating element connected in series with each other, and a signal is transmitted via the first insulating element and the second insulating element, the gate driver.

[0220] (Note A2) The gate driver according to Note A1, wherein the first conductor is located closer to the substrate than the second conductor in the thickness direction of the insulating layer, the third conductor is located closer to the substrate than the fourth conductor in the thickness direction of the insulating layer, and the gate driver comprises a high-voltage die pad on which a high-voltage circuit chip including the high-voltage circuit is mounted, the insulating chip is mounted on the high-voltage die pad, the low-voltage circuit and the first conductor are electrically connected, the high-voltage circuit and the third conductor are electrically connected, the second conductor and the fourth conductor are electrically connected, and in the thickness direction of the insulating layer, the first conductor is located further from the substrate than the third conductor.

[0221] (Note A3) The gate driver according to Note A2, wherein the distance between the first conductor and the substrate is greater than or equal to the distance between the third conductor and the fourth conductor. (Appendix A4) The gate driver according to Appendix A2 or A3, wherein the distance between the first conductor and the substrate is greater than or equal to the distance between the first conductor and the second conductor.

[0222] (Note A5) The gate driver according to any one of Notes A2 to A4, wherein the distance between the first conductor and the fourth conductor is greater than or equal to the distance between the first conductor and the substrate. (Note A6) The gate driver according to any one of Notes A2 to A5, wherein the distance between the third conductor and the fourth conductor is greater than the distance between the first conductor and the second conductor.

[0223] (Note A7) The gate driver according to Note A1, wherein the insulating chip is a transformer chip in which the first insulating element includes a first transformer having a first coil as a first conductor and a second coil as a second conductor, and the second insulating element includes a second transformer having a third coil as a third conductor and a fourth coil as a fourth conductor, the first coil is positioned closer to the substrate than the second coil in the thickness direction of the insulating layer, the third coil is positioned closer to the substrate than the fourth coil in the thickness direction of the insulating layer, and the gate driver according to Note A1 comprises a low-voltage die pad on which a low-voltage circuit chip including the low-voltage circuit is mounted, the insulating chip is mounted on the low-voltage die pad, the low-voltage circuit and the first coil are electrically connected, the high-voltage circuit and the third coil are electrically connected, and the second coil and the fourth coil are electrically connected.

[0224] (Note A8) The gate driver according to Note A7, wherein the insulating chip has a dummy pattern for a first transformer formed around the second coil and a dummy pattern for a second transformer formed around the third coil.

[0225] (Note A9) The gate driver according to Note A8, wherein in the thickness direction of the insulating layer, the dummy pattern for the first transformer is located further away from the substrate than the first coil.

[0226] (Note A10) The gate driver as described in Note A9, wherein the dummy pattern for the first transformer is aligned with the second coil in the thickness direction of the insulating layer. (Note A11) The gate driver according to any one of Notes A8 to A10, wherein the dummy pattern for the second transformer is located further away from the substrate than the first coil in the thickness direction of the insulating layer.

[0227] (Note A12) The gate driver as described in Note A11, wherein the distance between the dummy pattern for the second transformer and the substrate is greater than or equal to the distance between the first coil and the second coil.

[0228] (Note A13) The gate driver according to Note A11 or A12, wherein the distance between the dummy pattern for the second transformer and the substrate is greater than or equal to the distance between the third coil and the fourth coil.

[0229] (Note A14) The gate driver according to any one of Notes A11 to A13, wherein the distance between the third coil and the first coil is greater than or equal to the distance between the dummy pattern for the second transformer and the substrate.

[0230] (Note A15) The gate driver according to any one of Notes A1 to A14, wherein the low-voltage circuit generates a first signal for generating the gate voltage based on an external command, and the high-voltage circuit generates the gate voltage based on the first signal.

[0231] (Note B1) An insulating chip comprising a substrate, an insulating layer formed on the substrate, a first insulating element embedded in the insulating layer and having a first conductor and a second conductor arranged opposite to each other, a second insulating element embedded in the insulating layer and having a third conductor and a fourth conductor arranged opposite to each other, and wiring connecting the first insulating element and the second insulating element in series.

[0232] (Note B2) The insulating chip according to Note B1, wherein the insulating chip is a transformer chip in which the first insulating element includes a first transformer having a first coil as the first conductor and a second coil as the second conductor, and the second insulating element includes a second transformer having a third coil as the third conductor and a fourth coil as the fourth conductor.

[0233] (Note B3) The insulating chip according to Note B1, wherein the insulating chip is a capacitor chip in which the first insulating element includes a first capacitor having a first electrode plate as the first conductor and a second electrode plate as the second conductor, and the second insulating element includes a second capacitor having a third electrode plate as the third conductor and a fourth electrode plate as the fourth conductor.

[0234] (Appendix B4) An isolation module comprising an isolation chip described in any one of Appendices B1 to B3, and a die pad on which the isolation chip is mounted. (Note B5) The isolation module is the isolation module described in Note B4, used to isolate the low-voltage circuit and the high-voltage circuit included in the gate driver.

[0235] (Appendix B6) A low-voltage circuit unit comprising the insulating module described in Appendix B5 and the low-voltage circuit. (Appendix B7) A high-voltage circuit unit comprising the insulating module described in Appendix B5 and the high-voltage circuit. [Explanation of symbols]

[0236] 10... Gate Driver 20... Low-voltage circuits 30…High-voltage circuits 40…transformer 41A, 41B... First transformer (first insulating element) 42A, 42B... Second transformer (second insulating element) 43A, 43B... First coil (first conductor) 44A, 44B... Second coil (second conductor) 45A, 45B... First coil (fourth conductor, fourth coil) 46A, 46B... Second coil (third conductor, third coil) 50… Capacitor 51A, 51B... First capacitor (first insulating element) 52A, 52B... Second capacitor (second insulating element) 53A, 53B... First electrode (first conductor, first electrode plate) 54A, 54B... Second electrode (second conductor, second electrode plate) 55A, 55B... First electrode (fourth conductor, fourth electrode plate) 56A, 56B... Second electrode (third conductor, third electrode plate) 60... Low-voltage circuit chip 70…High-voltage circuit chip 80…Transformer chip (isolation chip) 83...Connection wiring (wiring) 84... Circuit board 84a...Lower Si layer (first semiconductor layer) 84b…SiO2 layer (semiconductor oxide layer) 84c... Upper Si layer (second semiconductor layer) 84ca…First Si layer (first isolation semiconductor layer) 84cb...Second Si layer (second isolation semiconductor layer) 84d...Divider 86...Insulating layer 91... Low-voltage die pad 101... High-pressure die pad 120... Capacitor chip (insulating chip) 123...Connection wiring (wiring) 124... Circuit board 126...Insulating layer 501, 502… Switching elements

Claims

1. A gate driver that applies a gate voltage to a gate of a switching element, a low-voltage circuit that operates when a first voltage is applied; a high-voltage circuit that operates when a second voltage higher than the first voltage is applied; an insulating tip; Equipped with The insulating tip is A substrate; an insulating layer formed on the substrate; a first insulating element embedded in the insulating layer and having a first conductor and a second conductor disposed opposite each other; a second insulating element embedded in the insulating layer and having a third conductor and a fourth conductor disposed opposite each other; and The low-voltage circuit and the high-voltage circuit are connected via the first insulating element and the second insulating element which are connected in series with each other, and signals are transmitted via the first insulating element and the second insulating element. Gate driver.

2. the first conductor is disposed closer to the substrate than the second conductor in a thickness direction of the insulating layer; the third conductor is disposed closer to the substrate than the fourth conductor in a thickness direction of the insulating layer; a low-voltage die pad on which a low-voltage circuit chip including the low-voltage circuit is mounted; the insulating chip is mounted on the low-voltage die pad; the low-voltage circuit and the first conductor are electrically connected; the high-voltage circuit and the third conductor are electrically connected, The second conductor and the fourth conductor are electrically connected to each other. The gate driver of claim 1 .

3. In the thickness direction of the insulating layer, the third conductor is located farther from the substrate than the first conductor. The gate driver according to claim 2 .

4. The distance between the third conductor and the substrate is equal to or greater than the distance between the first conductor and the second conductor. The gate driver according to claim 3 .

5. The distance between the third conductor and the substrate is equal to or greater than the distance between the third conductor and the fourth conductor.

5. The gate driver according to claim 3 or 4.

6. The distance between the third conductor and the first conductor is equal to or greater than the distance between the third conductor and the substrate. The gate driver according to any one of claims 3 to 5.

7. The distance between the first conductor and the second conductor is greater than the distance between the third conductor and the fourth conductor. The gate driver according to any one of claims 3 to 6.

8. The second conductor and the fourth conductor are arranged at positions aligned with each other in the thickness direction of the insulating layer. The gate driver according to any one of claims 1 to 7.

9. The substrate is a substrate formed from a material containing Si. The gate driver according to any one of claims 1 to 8.

10. The substrate is made of a material including glass. The gate driver according to any one of claims 1 to 8.

11. The substrate has a first semiconductor layer, a second semiconductor layer, and a semiconductor oxide layer disposed between the first semiconductor layer and the second semiconductor layer. The gate driver according to any one of claims 1 to 8.

12. a separation band made of an insulating material that penetrates the second semiconductor layer and reaches the semiconductor oxide layer is formed in the second semiconductor layer; The separation band is disposed between the first conductor and the third conductor when viewed in the thickness direction of the insulating layer, and separates the second semiconductor layer into a first separation semiconductor layer facing the first conductor and a second separation semiconductor layer facing the third conductor. The gate driver of claim 11 .

13. The first conductor and the third conductor are arranged at positions aligned with each other in the thickness direction of the insulating layer. The gate driver according to any one of claims 9 to 12.

14. the first insulating element includes a first transformer having a first coil as the first conductor and a second coil as the second conductor; The second insulating element includes a second transformer having a third coil as the third conductor and a fourth coil as the fourth conductor. The gate driver according to any one of claims 1 to 13.

15. the first insulating element includes a first capacitor having a first electrode plate as the first conductor and a second electrode plate as the second conductor; The second insulating element includes a second capacitor having a third electrode plate as the third conductor and a fourth electrode plate as the fourth conductor. The gate driver according to any one of claims 1 to 13.

16. the signal includes a first signal transmitted from the low voltage circuit to the high voltage circuit; The first signal output from the low-voltage circuit is transmitted to the high-voltage circuit via the first insulating element and the second insulating element in this order. The gate driver according to any one of claims 1 to 15.

17. the signals include a second signal transmitted from the high voltage circuit to the low voltage circuit; The second signal output from the high-voltage circuit is transmitted to the low-voltage circuit via the second insulating element and the first insulating element in this order.

17. The gate driver of claim 16.

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