Semiconductor Device

Abstract

To provide a semiconductor device including an IGBT region and a diode region.SOLUTION: A semiconductor device 1 includes a semiconductor layer 2 having a first main surface 3 on one side and a second main surface 4 on the other side, an IGBT region 8 formed on the first main surface 3, a diode region 9 formed outside the IGBT region 8 on the first main surface 3, an insulating layer 79 selectively covering the IGBT region 8 and the diode region 9 on the first main surface 3, and an emitter terminal 13 that covers the insulating layer 79 and has a portion connected to the semiconductor layer 2 in the diode region 9.SELECTED DRAWING: Figure 10

Description

[Technical field]

[0001] The present invention relates to a semiconductor device including an IGBT region and a diode region. [Background technology]

[0002] Patent Document 1 discloses an RC-IGBT (Reverse Conducting-Insulated Gate Bipolar Transistor) as an example of a semiconductor device. The RC-IGBT includes an IGBT region and a diode region fabricated in a common semiconductor layer. The IGBT region includes an IGBT. The diode region includes a diode. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2010-118642 A Summary of the Invention [Problem to be solved by the invention]

[0004] One embodiment provides a semiconductor device including an IGBT region and a diode region. [Means for solving the problem]

[0005] One embodiment provides a semiconductor device including a semiconductor layer having a first main surface on one side and a second main surface on the other side, a plurality of IGBT regions formed in the first main surface, a plurality of diode regions formed outside the IGBT regions in the first main surface, an insulating layer selectively covering the IGBT regions and the diode regions on the first main surface, and an emitter terminal covering the insulating layer and having a portion connected to the semiconductor layer in the diode region.

[0006] One embodiment includes a semiconductor layer having a first main surface on one side and a second main surface on the other side, the semiconductor layer including an active region, a plurality of IGBT regions formed in the active region, and a plurality of diode regions formed in the active region adjacent to the plurality of IGBT regions, wherein a total extension of a boundary line between the plurality of IGBT regions and the plurality of diode regions is represented by L, a total area of ​​the plurality of diode regions is represented by SD, and a dispersion degree of the plurality of diode regions with respect to the active region is represented by Log e (L 2 / SD), the dispersity is 2 or more and 15 or less.

[0007] The above and other objects, features and advantages will become apparent from the following detailed description of the embodiments taken in conjunction with the accompanying drawings. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a plan view showing a semiconductor device according to a first embodiment of the present invention. [Diagram 2] FIG. 2 is a plan view showing the structure of the first main surface of the semiconductor layer. [Diagram 3] FIG. 3 is a graph showing the relationship between the surge current resistance and the degree of dispersion investigated by simulation. [Figure 4] FIG. 4 is a graph showing the relationship between forward current and forward voltage investigated by simulation. [Diagram 5] FIG. 5 is an enlarged view of region V shown in FIG. [Figure 6] FIG. 6 is an enlarged view of region VI shown in FIG. [Figure 7] FIG. 7 is an enlarged view of region VII shown in FIG. [Figure 8] FIG. 8 is an enlarged view of region VIII shown in FIG. [Figure 9] FIG. 9 is a cross-sectional view taken along line IX-IX shown in FIG. [Figure 10] FIG. 10 is a cross-sectional view taken along the line XX shown in FIG. [Figure 11] FIG. 11 is a cross-sectional view taken along line XI-XI shown in FIG. [Figure 12] FIG. 12 is a cross-sectional view taken along line XII-XII shown in FIG. [Figure 13] FIG. 13 is a graph showing the relationship between recovery loss and forward voltage investigated by simulation. [Figure 14] FIG. 14 is an enlarged view of region XIV shown in FIG. [Figure 15] FIG. 15 is a circuit diagram showing the electrical structure of the area shown in FIG. [Figure 16] FIG. 16 is a cross-sectional view taken along the line XVI-XVI shown in FIG. [Figure 17] FIG. 17 is a cross-sectional view taken along line XVII-XVII shown in FIG. [Figure 18] FIG. 18 is an enlarged view of region XVIII shown in FIG. [Figure 19] FIG. 19 is a cross-sectional view taken along line XIX-XIX shown in FIG. [Figure 20A] 20A is a cross-sectional view of a region corresponding to FIG. 10, and is a cross-sectional view for explaining an example of a manufacturing method of the semiconductor device shown in FIG. [Figure 20B] FIG. 20B is a cross-sectional view showing a step subsequent to that of FIG. 20A. [Figure 20C] FIG. 20C is a cross-sectional view showing a step subsequent to that of FIG. 20B. [Figure 20D] FIG. 20D is a cross-sectional view showing a step subsequent to that shown in FIG. 20C. [Figure 20E] FIG. 20E is a cross-sectional view showing a step subsequent to that shown in FIG. 20D. [Figure 20F] FIG. 20F is a cross-sectional view showing a step subsequent to that of FIG. 20E. [Figure 20G] FIG. 20G is a cross-sectional view showing a step subsequent to that of FIG. 20F. [Figure 20H] FIG. 20H is a cross-sectional view showing a step subsequent to that shown in FIG. 20G. [Figure 20I] FIG. 20I is a cross-sectional view showing a step subsequent to that shown in FIG. 20H. [Figure 20J] FIG. 20J is a cross-sectional view showing a step subsequent to that shown in FIG. 20I. [Figure 20K] FIG. 20K is a cross-sectional view showing a step subsequent to that shown in FIG. 20J. [Figure 20L] FIG. 20L is a cross-sectional view showing a step subsequent to that shown in FIG. 20K. [Figure 20M] FIG. 20M is a cross-sectional view showing a step subsequent to that shown in FIG. 20L. [Figure 20N] FIG. 20N is a cross-sectional view showing a step subsequent to that shown in FIG. 20M. [Figure 20O] FIG. 20O is a cross-sectional view showing a step subsequent to that shown in FIG. 20N. [Figure 20P] FIG. 20P is a cross-sectional view showing a step subsequent to that shown in FIG. 20O. [Figure 20Q] FIG. 20Q is a cross-sectional view showing a step subsequent to that of FIG. 20P. [Figure 20R] FIG. 20R is a cross-sectional view showing a step subsequent to that of FIG. 20Q. [Figure 20S] FIG. 20S is a cross-sectional view showing a step subsequent to that shown in FIG. 20R. [Figure 20T] FIG. 20T is a cross-sectional view showing a step subsequent to that shown in FIG. 20S. [Figure 21] FIG. 21 is an enlarged view of a region corresponding to FIG. 5, showing a semiconductor device according to a second embodiment of the present invention. [Figure 22] 22 is a cross-sectional view of a region corresponding to FIG. 10, and is a cross-sectional view for explaining the structure of the semiconductor device shown in FIG. [Diagram 23] FIG. 23 is a graph showing the reverse recovery characteristics of a pn junction diode investigated by simulation. [Figure 24] FIG. 24 is a perspective view showing an example of a semiconductor module. [Diagram 25] FIG. 25 is a circuit diagram showing an electrical structure of the semiconductor module shown in FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Fig. 1 is a plan view showing a semiconductor device 1 according to a first embodiment of the present invention. Fig. 2 is a plan view showing the structure of a first main surface 3 of a semiconductor layer 2.

[0010] The semiconductor device 1 is an electronic component having a reverse conducting-insulated gate bipolar transistor (RC-IGBT) that integrally includes an IGBT and a diode.

[0011] 1 and 2, semiconductor device 1 includes a rectangular parallelepiped semiconductor layer 2. Semiconductor layer 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and side surfaces 5A, 5B, 5C, and 5D connecting first main surface 3 and second main surface 4.

[0012] The first main surface 3 and the second main surface 4 are formed in a quadrangular shape in a plan view seen from their normal direction Z (hereinafter simply referred to as "plan view"). The side surface 5A and the side surface 5C extend along a first direction X and face each other in a second direction Y intersecting the first direction X. The side surface 5B and the side surface 5D extend along the second direction Y and face each other in the first direction X. The second direction Y is specifically perpendicular to the first direction X.

[0013] The thickness of the semiconductor layer 2 may be 50 μm or more and 200 μm or less. The thickness of the semiconductor layer 2 may be 50 μm or more and 100 μm or less, 100 μm or more and 150 μm or less, or 150 μm or more and 200 μm or less. By reducing the thickness of the semiconductor layer 2, the resistance value of the semiconductor layer 2 can be reduced.

[0014] The semiconductor layer 2 includes an active region 6 and an outer region 7. The active region 6 is a region in which an RC-IGBT is formed. The active region 6 is set in the center of the semiconductor layer 2 and spaced from the side surfaces 5A to 5D toward the inner region in a plan view. The active region 6 may be set in a quadrangle shape having four sides parallel to the side surfaces 5A to 5D in a plan view.

[0015] The outer region 7 is a region outside the active region 6. The outer region 7 extends in a band shape along the periphery of the active region 6 in a plan view. Specifically, the outer region 7 is set to have an endless shape (square ring shape) surrounding the active region 6 in a plan view.

[0016] The active region 6 includes an IGBT region 8 and a diode region 9. In FIG. 2, the diode region 9 is shown by hatching for clarity. The IGBT region 8 is a region in which an IGBT is formed. The diode region 9 is a region in which a diode is formed. The diode region 9 is adjacent to the IGBT region 8.

[0017] The active region 6 specifically includes an RC-IGBT array 12. A plurality of RC-IGBT arrays 12 (six in this embodiment) are formed at intervals in the second direction Y. The RC-IGBT array 12 has a first end portion on one side (side surface 5B side) and a second end portion on the other side (side surface 5D side).

[0018] The RC-IGBT array 12 has a loop arrangement including a repeating series of IGBT regions 8, diode regions 9, IGBT regions 8, diode regions 9, ... arranged in a line along a first direction X from a first end to a second end. In this embodiment, the first end of the RC-IGBT array 12 is formed by the IGBT regions 8. In this embodiment, the second end of the RC-IGBT array 12 is formed by the IGBT regions 8. The first end of the RC-IGBT array 12 may be formed by the diode regions 9. The second end of the RC-IGBT array 12 may be formed by the diode regions 9.

[0019] In this manner, a plurality of IGBT regions 8 are dispersed and arranged in the active region 6. The plurality of IGBT regions 8 are formed at intervals along the first direction X and the second direction Y. In this embodiment, the plurality of IGBT regions 8 are arranged in a matrix in plan view. The plurality of IGBT regions 8 face each other along the first direction X and face each other along the second direction Y.

[0020] In this embodiment, each of the IGBT regions 8 is formed in a quadrangular shape in a plan view. Specifically, each of the IGBT regions 8 is formed in a rectangular shape extending along the second direction Y.

[0021] The width WI of each IGBT region 8 may be 10 μm or more and 1000 μm or less. The width WI is the width of the IGBT region 8 in the first direction X. The width WI may be 10 μm or more and 100 μm or less, 100 μm or more and 200 μm or less, 200 μm or more and 300 μm or less, 300 μm or more and 400 μm or less, 400 μm or more and 500 μm or less, 500 μm or more and 600 μm or less, 600 μm or more and 700 μm or less, 700 μm or more and 800 μm or less, 800 μm or more and 900 μm or less, or 900 μm or more and 1000 μm or less. The width WI is preferably 100 μm or more. The width WI is more preferably 200 μm or more.

[0022] Furthermore, a plurality of diode regions 9 are dispersed and arranged in the active region 6. The plurality of diode regions 9 are formed at intervals along the first direction X and the second direction Y. In this embodiment, the plurality of diode regions 9 are arranged in a matrix in plan view. The plurality of diode regions 9 face each other along the first direction X and face each other along the second direction Y.

[0023] Specifically, each of the diode regions 9 is formed adjacent to the IGBT region 8 in the first direction X. In this embodiment, each of the diode regions 9 is formed in a quadrangular shape in a plan view. Specifically, each of the diode regions 9 is formed in a rectangular shape extending along the second direction Y.

[0024] It is preferable that the planar area of each diode region 9 is less than or equal to the planar area of each IGBT region 8. It is more preferable that the planar area of each diode region 9 is less than the planar area of each IGBT region 8. The width WD of each diode region 9 is preferably less than or equal to the width WI of each IGBT region 8. The width WD is the width of the diode region 9 in the first direction X. It is more preferable that the width WD of each diode region 9 is less than the width WI of each IGBT region 8.

[0025] The width WD may be 5 μm or more and less than 1000 μm. The width WD may be 5 μm or more and 100 μm or less, 100 μm or more and 200 μm or less, 200 μm or more and 300 μm or less, 300 μm or more and 400 μm or less, 400 μm or more and 500 μm or less, 500 μm or more and 600 μm or less, 600 μm or more and 700 μm or less, 700 μm or more and 800 μm or less, 800 μm or more and 900 μm or less, or 900 μm or more and less than 1000 μm. The width WD is preferably 100 μm or more. The width WD is more preferably 200 μm or more.

[0026] The plurality of IGBT regions 8 are formed in the active region 6 at a first ratio RI. The first ratio RI is the ratio SI / SA of the total area SI of the plurality of IGBT regions 8 to the area SA of the active region 6 in a plan view.

[0027] The plurality of diode regions 9 are formed in the active region 6 at a second ratio RD. The second ratio RD is the ratio SD / SA of the total area SD of the plurality of diode regions 9 to the area SA of the active region 6 in a plan view. The second ratio RD is preferably less than or equal to the first ratio RI (RD≦RI). It is more preferable that the second ratio RD is less than the first ratio RI (RD<RI).

[0028] In this embodiment, the second ratio RD is less than the first ratio RI (RD < RI). That is, the first ratio RI is 0.5 or more, and the second ratio RD is less than 0.5. The first ratio RI may be 0.5 or more and 0.6 or less, 0.6 or more and 0.7 or less, 0.7 or more and 0.8 or less, 0.8 or more and 0.9 or less, or 0.9 or more and less than 1. The second ratio R2 may exceed 0 and be 0.1 or less, 0.1 or more and 0.2 or less, 0.2 or more and 0.3 or less, 0.3 or more and 0.4 or less, or 0.4 or more and less than 0.5.

[0029] The first ratio RI is preferably 0.6 or more and 0.9 or less, and the second ratio RD is preferably 0.1 or more and 0.4 or less. In this embodiment, the first ratio RI is 0.7, and the second ratio RD is 0.3.

[0030] When the degree of dispersion D of the plurality of diode regions 9 with respect to the active region 6 is defined by the formula Log e (L 2 / SD), the degree of dispersion D is preferably 2 or more and 15 or less. In the above formula, "L" is the total extension of the boundary lines between the plurality of IGBT regions 8 and the plurality of diode regions 9 in a plan view. In the above formula, "SD" is the total area of the plurality of diode regions 9 in a plan view.

[0031] The total extension L of the boundary lines is also the total extension of the portions of the diode regions 9 that face the IGBT regions 8. In this embodiment, both the IGBT regions 8 and the diode regions 9 are partitioned into rectangular shapes in a plan view. Therefore, the total extension L of the boundary lines is the total extension of the sides of the plurality of diode regions 9 that face the IGBT regions 8.

[0032] The dispersion D is adjusted by increasing or decreasing the total length L or the total area SD, or both the total length L and the total area SD, under the condition that the second ratio RD is less than the first ratio RI (RD < RI). In other words, the dispersion D is adjusted by increasing or decreasing the number or the planar area of the IGBT regions 8 and the diode regions 9, or both the number and the planar area, respectively, under the condition that the second ratio RD is less than the first ratio RI (RD < RI). The total length L and / or the total area SD may be adjusted for each of the plurality of RC-IGBT arrays 12.

[0033] FIG. 3 is a graph showing the relationship between the withstand voltage against the surge current Is and the dispersion D investigated by simulation. In FIG. 3, the vertical axis represents the withstand voltage against the surge current Is [A], and the horizontal axis represents the dispersion D. The withstand voltage against the surge current Is is the maximum value of the surge current Is that the semiconductor device 1 can withstand.

[0034] Referring to FIG. 3, when the dispersion D is increased, the withstand voltage against the surge current Is increases. Specifically, the withstand voltage against the surge current Is monotonically increases in the range where the dispersion D exceeds 0 and is less than 5, and saturates in the range where the dispersion D is 5 or more.

[0035] In the range where the dispersion D exceeds 0 and is less than 2, the withstand voltage against the surge current Is was less than 400 A. In the range where the dispersion D is 2 or more and less than 5, the withstand voltage against the surge current Is was 400 A or more and less than 1400 A. In the range where the dispersion D is 5 or more, the withstand voltage against the surge current Is was 1400 A or more and 1600 A or less. From these results, it was found that increasing the dispersion D can increase the breakdown withstand voltage of the semiconductor device 1.

[0036] FIG. 4 is a graph showing the relationship between the forward current IF and the forward voltage VF investigated by simulation. In FIG. 4, the vertical axis represents the forward current IF [A], and the horizontal axis represents the forward voltage VF [V].

[0037] FIG. 4 shows the first characteristic L1 (see solid line) and the second characteristic L2 when the dispersity D is "3". 2 The first characteristic L1 shows the characteristic when the diode is operated in the forward direction without applying a bias voltage Vge to the IGBT. The second characteristic L 2 shows the characteristics when the diode is operated in the forward direction with a bias voltage Vge applied to the IGBT.

[0038] 4 shows a third characteristic L3 (see solid line) and a fourth characteristic L4 (see dashed line) when the dispersion degree D is "15". The third characteristic L3 shows the characteristic when the diode is operated in the forward direction with no bias voltage Vge applied to the IGBT. The fourth characteristic L4 shows the characteristic when the diode is operated in the forward direction with a bias voltage Vge applied to the IGBT.

[0039] First characteristic L1 and second characteristic L 2 Referring to the third characteristic L3 and the fourth characteristic L4, when the dispersity D is "3", the forward voltage VF increases after the application of the bias voltage Vge. Similarly, referring to the third characteristic L3 and the fourth characteristic L4, when the dispersity D is "15", the forward voltage VF increases after the application of the bias voltage Vge.

[0040] With reference to the first characteristic L1 to the fourth characteristic L4, the amount of change in the forward voltage VF when the dispersity D is "15" was larger than the amount of change in the forward voltage VF when the dispersity D is "3." When the dispersity D exceeds "15," the amount of change in the forward voltage VF exceeds a practical range.

[0041] From the results in Fig. 4, it was found that the larger the value of the dispersity D, the larger the change in the forward voltage VF before and after the application of the bias voltage Vge. Also, from the results in Fig. 3 and Fig. 4, it was found that there is a trade-off between the larger the value of the dispersity D, the greater the withstand capability against the surge current Is, but also the larger the change in the forward voltage VF.

[0042] When the degree of dispersion D is small, multiple diode regions 9 are concentrated in a specific location, and the current flowing into each diode region 9 increases. As a result, the withstand capability against surge current Is decreases. On the other hand, when the degree of dispersion D is large, multiple diode regions 9 are dispersed, and the current flowing into each diode region 9 decreases. As a result, the withstand capability against surge current Is increases.

[0043] On the other hand, when the diode is operated in the forward direction with the bias voltage Vge applied to the IGBT, the amount of carriers (holes) flowing from the IGBT region 8 to the diode region 9 decreases. As a result, the forward voltage VF of the diode fluctuates.

[0044] When the dispersion degree D is set to a relatively large value, the total length L of the boundary line between the IGBT region 8 and the diode region 9 becomes relatively large, and the number of paths through which carriers (holes) flow from the IGBT region 8 to the diode region 9 increases. As a result, the amount of change in the forward voltage VF before and after the application of the bias voltage Vge increases. The dispersion degree D must be set in consideration of the trade-off between the withstand capability for the surge current Is and the amount of change in the forward voltage VF.

[0045] 3 and 4, it is found that the dispersity D is preferably set in the range of 2 to 15. When the dispersity D is set in the range of 2 to 15, the withstand capability against the surge current Is can be increased while suppressing the fluctuation in the forward voltage VF before and after the application of the bias voltage Vge.

[0046] The dispersity D may be 2 to 3, 3 to 4, 4 to 5, 5 to 6, 6 to 7, 7 to 8, 8 to 9, 9 to 10, 10 to 11, 11 to 12, 12 to 13, or 14 to 15. The dispersity D is preferably less than 15.

[0047] It is particularly preferable that the dispersity D is set in the range of 2 or more and 7 or less, or in the range of 7 or more and 12 or less. When the dispersity D is set in the range of 2 or more and 7 or less, it is possible to reliably suppress fluctuations in the forward voltage VF while increasing the withstand capability against the surge current Is. When the dispersity D is set in the range of 7 or more and 12 or less, it is possible to reliably suppress fluctuations in the forward voltage VF while increasing the withstand capability against the surge current Is.

[0048] The area SA of the active region 6 is adjusted according to the size of the semiconductor layer 2, and is not limited to a specific value. As an example, the area SA is 1 mm 2 More than 250mm 2 The area SA may be less than 1 mm 2 More than 50mm 2 Below, 50mm 2 More than 100mm 2 Below, 100mm 2 More than 150mm 2 Below, 150mm 2 More than 200mm 2 Less than or equal to 200mm 2 More than 250mm 2 It may be the following.

[0049] The total area SI of the multiple IGBT regions 8, the total area SD of the multiple diode regions 9, and the total length L of the boundary lines are adjusted according to the size of the area SA of the active region 6, and are not limited to specific numerical values.

[0050] The total area SI is, for example, 0.5 mm 2 More than 225mm 2 The total area SI may be less than 0.5 mm 2 More than 50mm 2 Below, 50mm 2 More than 100mm 2 Below, 100mm 2 More than 150mm 2 Below, 150mm 2 More than 200mm 2 Less than or equal to 200mm 2 More than 225mm 2It may be the following.

[0051] The total area SD is, for example, 0.1 mm 2 More than 100mm 2 The total area SD may be less than 0.1 mm 2 More than 25mm 2 Below, 25mm 2 More than 50mm 2 Below, 50mm 2 More than 75mm 2 Less than or equal to 75mm 2 More than 100mm 2 It may be the following.

[0052] The total length L may be, for example, 100 μm or more and 3500 μm or less, 100 μm or more and 500 μm or less, 500 μm or more and 1000 μm or less, 1000 μm or more and 1500 μm or less, 1500 μm or more and 2000 μm or less, 2000 μm or more and 2500 μm or less, 2500 μm or more and 3000 μm or less, or 3000 μm or more and 3500 μm or less.

[0053] 1 and 2 again, the active area 6 further includes a sensor area 11. The sensor area 11 is an area in which a temperature sensor is formed. The sensor area 11 is formed in an area between two RC-IGBT arrays 12 adjacent to each other in the second direction Y. In this embodiment, the sensor area 11 is formed in the center of the active area 6. Heat is likely to increase in the center of the active area 6. Therefore, by arranging a temperature sensor in the center of the active area 6, the temperature of the semiconductor layer 2 can be appropriately detected.

[0054] The semiconductor device 1 includes an emitter terminal electrode 13 (see the dashed line in FIG. 1) as a first main surface electrode formed on the first main surface 3 of the semiconductor layer 2 in the active region 6. The emitter terminal electrode 13 transmits an emitter signal to the active region 6 (IGBT region 8). The emitter signal may be a reference potential or a ground potential.

[0055] The semiconductor device 1 includes a plurality of terminal electrodes 14, 15, 16, 17, and 18 (five in this embodiment) formed on the first main surface 3 of the semiconductor layer 2 in the outer region 7. The terminal electrodes 14 to 18 are arranged at intervals from one another along the side surface 5D. The terminal electrodes 14 to 18 are formed in a quadrangular shape in a plan view.

[0056] In this embodiment, the multiple terminal electrodes 14 to 18 include a gate terminal electrode 14, a first sense terminal electrode 15, a second sense terminal electrode 16, a current detection terminal electrode 17, and an open terminal electrode 18. The gate terminal electrode 14 transmits a gate signal to the active region 6 (IGBT region 8). The first sense terminal electrode 15 and the second sense terminal electrode 16 transmit a control signal for controlling the sensor region 11 (temperature sensor). Although a detailed description is omitted, the current detection terminal electrode 17 is an electrode for detecting a current flowing through the active region 6 and extracting it to the outside. The open terminal electrode 18 is in an electrically floating state.

[0057] The gate terminal electrode 14, the first sense terminal electrode 15, the second sense terminal electrode 16, the current detection terminal electrode 17, and the open terminal electrode 18 may be arranged arbitrarily. In this embodiment, the open terminal electrode 18, the current detection terminal electrode 17, the gate terminal electrode 14, the first sense terminal electrode 15, and the second sense terminal electrode 16 are arranged in this order from the side surface 5A toward the side surface 5C.

[0058] The semiconductor device 1 includes a gate wiring 19 electrically connected to the gate terminal electrode 14. The gate wiring 19 is also called a gate finger. The gate wiring 19 extends from the outer region 7 toward the active region 6. The gate wiring 19 transmits a gate signal applied to the gate terminal electrode 14 to the active region 6 (IGBT region 8).

[0059] Specifically, the gate wiring 19 includes a first region 19a located in the outer region 7 and a second region 19b located in the active region 6. The first region 19a is electrically connected to the gate terminal electrode 14. In this embodiment, the first region 19a is selectively routed in a region on the side surface 5D side in the outer region 7.

[0060] A plurality of second regions 19b (five in this embodiment) are formed in the active region 6. The second regions 19b are formed at intervals along the second direction Y. The second regions 19b are each formed in a region between two adjacent RC-IGBT arrays 12. The second regions 19b extend in a strip shape along the first direction X.

[0061] The second regions 19b each extend from a region on the side face 5D side to a region on the side face 5B side in the outer region 7. The second regions 19b may cross the active region 6. The second regions 19b are continuous with the first region 19a in the outer region 7. The second regions 19b transmit gate signals to one or both of two RC-IGBT arrays 12 adjacent to each other.

[0062] A gate signal applied to the gate terminal electrode 14 is transmitted to the second region 19b via the first region 19a. As a result, the gate signal is transmitted to the active region 6 (IGBT region 8) via the second region 19b.

[0063] The semiconductor device 1 includes a first sense wiring 20 electrically connected to the first sense terminal electrode 15. The first sense wiring 20 extends from the outer region 7 toward the sensor region 11. The first sense wiring 20 transmits a control signal for the temperature sensor.

[0064] Specifically, the first sense wiring 20 includes a first region 20a located in the outer region 7 and a second region 20b located in the active region 6. The first region 20a is electrically connected to the first sense terminal electrode 15. In this embodiment, the first region 20a is selectively routed in a region on the side surface 5D side in the outer region 7.

[0065] The second region 20b is formed in a region in which the sensor region 11 is formed between adjacent RC-IGBT arrays 12. The second region 20b extends in a strip shape along the first direction X from the outer region 7 toward the sensor region 11.

[0066] The second region 20b is electrically connected to the temperature sensor in the sensor region 11. The second region 20b is connected to the first region 20a in the outer region 7. An electrical signal applied to the first sense terminal electrode 15 is transmitted to the second region 21b via the first region 20a. As a result, the electrical signal is transmitted to the temperature sensor via the second region 21b.

[0067] A second sense wire 21 is electrically connected to the second sense terminal electrode 16. The second sense wire 21 extends from the outer region 7 toward the sensor region 11. The second sense wire 21 transmits a control signal for the temperature sensor.

[0068] Specifically, the second sense wiring 21 includes a first region 21a located in the outer region 7 and a second region 21b located in the active region 6. The first region 21a is electrically connected to the second sense terminal electrode 16. In this embodiment, the first region 21a is selectively routed in a region on the side surface 5D side in the outer region 7.

[0069] The second region 21b is formed in a region between adjacent RC-IGBT arrays 12 in which the sensor region 11 is formed. The second region 21b extends in a strip shape along the first direction X from the outer region 7 toward the sensor region 11. The second region 21b is electrically connected to a temperature sensor in the sensor region 11.

[0070] The second region 21b is continuous with the first region 21a in the outer region 7. An electric signal applied to the second sense terminal electrode 16 is transmitted to the second region 21b via the first region 21a. As a result, the electric signal is transmitted to the temperature sensor via the second region 21b.

[0071] In the region between adjacent RC-IGBT arrays 12 where the sensor region 11 is formed, a gate wiring 19, a first sense wiring 20, and a second sense wiring 21 are formed. The gate wiring 19, the first sense wiring 20, and the second sense wiring 21 run in parallel in the region between two adjacent RC-IGBT arrays 12.

[0072] With this structure, it is possible to reduce the area in which the wiring is formed while improving the accuracy of temperature detection by the temperature sensor. In other words, it is possible to suppress a reduction in the active area 6 caused by the temperature sensor formed in the active area 6. As a result, it is possible to suppress a reduction in the area in which the RC-IGBT array 12 can be formed while improving the accuracy of temperature detection by the temperature sensor.

[0073] FIG. 5 is an enlarged view of region V shown in FIG. 1. FIG. 6 is an enlarged view of region VI shown in FIG. 5. FIG. 7 is an enlarged view of region VII shown in FIG. 6. FIG. 8 is an enlarged view of region VIII shown in FIG. 6. FIG. 9 is a cross-sectional view taken along line IX-IX shown in FIG. 7. FIG. 10 is a cross-sectional view taken along line XX shown in FIG. 8. FIG. 11 is a cross-sectional view taken along line XI-XI shown in FIG. 7. FIG. 12 is a cross-sectional view taken along line XII-XII shown in FIG. 8.

[0074] 5 to 12, the semiconductor device 1 includes n - The drift region 30 includes an n-type drift region 30. Specifically, the drift region 30 is formed in the entire region of the semiconductor layer 2. The n-type impurity concentration of the drift region 30 is 1.0×10 13 cm -3 Above 1.0×10 15 cm -3 It may be the following.

[0075] In this embodiment, the semiconductor layer 2 is - The drift region 30 has a single-layer structure including a semiconductor substrate 31. The semiconductor substrate 31 may be a silicon FZ (Floating Zone) substrate formed through a FZ method. The drift region 30 is formed by the semiconductor substrate 31.

[0076] The semiconductor device 1 includes a collector terminal electrode 32 as a second main surface electrode formed on the second main surface 4 of the semiconductor layer 2. The collector terminal electrode 32 is electrically connected to the second main surface 4. Specifically, the collector terminal electrode 32 is electrically connected to the IGBT region 8 (a collector region 34 described later) and the diode region 9 (a cathode region 61 described later). The collector terminal electrode 32 forms an ohmic contact with the second main surface 4. The collector terminal electrode 32 transmits a collector signal to the IGBT region 8 and the diode region 9.

[0077] The collector terminal electrode 32 may include at least one of a Ti layer, a Ni layer, an Au layer, an Ag layer, and an Al layer. The collector terminal electrode 32 may have a single layer structure including a Ti layer, a Ni layer, an Au layer, an Ag layer, or an Al layer. The collector terminal electrode 32 may have a laminated structure in which at least two of a Ti layer, a Ni layer, an Au layer, an Ag layer, and an Al layer are laminated in any manner.

[0078] The semiconductor device 1 includes an n-type buffer layer 33 formed in a surface layer portion of the second main surface 4 of the semiconductor layer 2. The buffer layer 33 may be formed over the entire surface layer portion of the second main surface 4. The n-type impurity concentration of the buffer layer 33 is higher than the n-type impurity concentration of the drift region 30. The n-type impurity concentration of the buffer layer 33 is 1.0×10 15 cm -3 Above 1.0×10 17 cm -3 It may be the following.

[0079] The thickness of the buffer layer 33 may be 0.5 μm or more and 30 μm or less. The thickness of the buffer layer 33 may be 0.5 μm or more and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, 15 μm or more and 20 μm or less, 20 μm or more and 25 μm or less, or 25 μm or more and 30 μm or less.

[0080] 9 to 12, each IGBT region 8 includes a p-type collector region 34 formed in a surface layer portion of second main surface 4 of semiconductor layer 2. Collector region 34 is exposed from second main surface 4. Collector region 34 may be formed in the entire surface layer portion of second main surface 4 except for diode region 9. The p-type impurity concentration of collector region 34 is 1.0×10 15 cm -3 Above 1.0×10 18 cm -3 The collector region 34 forms an ohmic contact with the collector terminal electrode 32.

[0081] Each IGBT region 8 includes a FET structure 35 formed on the first main surface 3 of the semiconductor layer 2. In this embodiment, each IGBT region 8 includes a trench-gate type FET structure 35. Specifically, the FET structure 35 includes a trench gate structure 36 formed on the first main surface 3. In Figs. 6 to 8, the trench gate structure 36 is indicated by hatching.

[0082] A plurality of trench gate structures 36 are formed at intervals along the first direction X in the IGBT region 8. The distance between two trench gate structures 36 adjacent to each other in the first direction X may be 1 μm or more and 8 μm or less. The distance between two trench gate structures 36 may be 1 μm or more and 2 μm or less, 2 μm or more and 3 μm or less, 3 μm or more and 4 μm or less, 4 μm or more and 5 μm or less, 5 μm or more and 6 μm or less, 6 μm or more and 7 μm or less, or 7 μm or more and 8 μm or less.

[0083] The multiple trench gate structures 36 are formed in a band shape extending along the second direction Y in a plan view. The multiple trench gate structures 36 are formed in a stripe shape as a whole. Each of the multiple trench gate structures 36 has one end on one side in the second direction Y and the other end on the other side in the second direction Y.

[0084] The FET structure 35 includes a first outer trench gate structure 37 and a second outer trench gate structure 38. The first outer trench gate structure 37 extends along a first direction X and connects one ends of the multiple trench gate structures 36. The second outer trench gate structure 38 extends along the first direction X and connects the other ends of the multiple trench gate structures 36.

[0085] Except for the fact that the first outer trench gate structure 37 and the second outer trench gate structure 38 extend in different directions, they have the same structure as the trench gate structure 36. In the following, the structure of the trench gate structure 36 will be described, and descriptions of the structures of the first outer trench gate structure 37 and the second outer trench gate structure 38 will be omitted.

[0086] Each trench gate structure 36 includes a gate trench 39, a gate insulating layer 40, and a gate electrode layer 41. The gate trench 39 is formed in the first major surface 3. The gate trench 39 includes a sidewall and a bottom wall. The sidewall of the gate trench 39 may be formed perpendicular to the first major surface 3.

[0087] The sidewalls of the gate trench 39 may be inclined downward from the first main surface 3 toward the bottom wall. The gate trench 39 may be formed in a tapered shape in which the opening area on the opening side is larger than the bottom area. The bottom wall of the gate trench 39 may be formed parallel to the first main surface 3. The bottom wall of the gate trench 39 may be formed in a curved shape toward the second main surface 4.

[0088] The gate trench 39 includes an opening edge portion. The opening edge portion connects the first main surface 3 and the sidewall of the gate trench 39. The opening edge portion has an inclined portion that slopes downward from the first main surface 3 toward the sidewall of the gate trench 39. The inclined portion is formed in a curved shape recessed toward the second main surface 4. As a result, a wide portion having an opening width wider than the opening width on the bottom wall side is formed on the opening side of the gate trench 39. The inclined portion may be formed in a curved shape protruding toward the second main surface 4.

[0089] The gate trench 39 includes a bottom wall edge portion. The bottom wall edge portion connects the side wall and the bottom wall of the gate trench 39. The bottom wall edge portion may be formed in a curved shape toward the second main surface 4.

[0090] The depth of the gate trench 39 may be 2 μm or more and 10 μm or less. The depth of the gate trench 39 may be 2 μm or more and 3 μm or less, 3 μm or more and 4 μm or less, 4 μm or more and 5 μm or less, 5 μm or more and 6 μm or less, 6 μm or more and 7 μm or less, 8 μm or more and 9 μm or less, or 9 μm or more and 10 μm or less.

[0091] The width of the gate trench 39 may be 0.5 μm or more and 3 μm or less. The width of the gate trench 39 is the width of the gate trench 39 in the first direction X. The width of the gate trench 39 may be 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, or 2.5 μm or more and 3 μm or less.

[0092] The gate insulating layer 40 is formed in a film shape along the inner wall of the gate trench 39. The gate insulating layer 40 defines a recess space in the gate trench 39. In this embodiment, the gate insulating layer 40 includes a silicon oxide film. The gate insulating layer 40 may include a silicon nitride film instead of or in addition to the silicon oxide film.

[0093] The gate insulating layer 40 includes a first region 40a, a second region 40b, and a third region 40c. The first region 40a covers the sidewall of the gate trench 39. The second region 40b covers the bottom wall of the gate trench 39. The third region 40c covers the opening edge portion of the gate trench 39.

[0094] The thickness of the second region 20b may be equal to or greater than the thickness of the first region 40a. The thickness of the second region 40b may be greater than the thickness of the first region 40a. The thickness of the third region 40c may be equal to or greater than the thickness of the first region 40a. The thickness of the third region 40c may be greater than the thickness of the first region 40a.

[0095] The third region 40c includes a bulging portion that bulges toward the inside of the gate trench 39 at the opening edge portion of the gate trench 39. The third region 40c bulges in a curved shape toward the inside of the gate trench 39. The third region 40c narrows the opening of the gate trench 39 at the opening edge portion of the gate trench 39. Of course, the gate insulating layer 40 may be formed to have a uniform thickness.

[0096] The gate electrode layer 41 is embedded in the gate trench 39 with the gate insulating layer 40 sandwiched therebetween. Specifically, the gate electrode layer 41 is embedded in a recess space defined by the gate insulating layer 40 in the gate trench 39. The gate electrode layer 41 is controlled by a gate signal. The gate electrode layer 41 may include conductive polysilicon.

[0097] The gate electrode layer 41 is formed in a wall shape extending along the normal direction Z in a cross-sectional view. The gate electrode layer 41 has an upper end portion located on the opening side of the gate trench 39. The upper end portion of the gate electrode layer 41 is located on the bottom wall side of the gate trench 39 with respect to the first main surface 3.

[0098] A recess that recesses toward the bottom wall of the gate trench 39 is formed at the upper end of the gate electrode layer 41. The recess at the upper end of the gate electrode layer 41 is formed in a tapered shape toward the bottom wall of the gate trench 39. The upper end of the gate electrode layer 41 has a constricted portion that is constricted along the third region 40c of the gate insulating layer 40.

[0099] The FET structure 35 includes a p-type body region 45 formed in a surface layer portion of the first main surface 3 of the semiconductor layer 2. The p-type impurity concentration of the body region 45 is 1.0×10 17 cm -3 Above 1.0×10 18 cm -3 It may be the following.

[0100] The body region 45 is formed on both sides of the trench gate structure 36. The body region 45 is formed in a strip shape extending along the trench gate structure 36 in a plan view. The body region 45 is exposed from the side wall of the gate trench 39. The bottom of the body region 45 is formed in a region between the first main surface 3 and the bottom wall of the gate trench 39 in relation to the normal direction Z.

[0101] The FET structure 35 is formed in a surface layer of the body region 45. + The n-type impurity concentration of the emitter region 46 is greater than the n-type impurity concentration of the drift region 30. The n-type impurity concentration of the emitter region 46 is greater than the n-type impurity concentration of the drift region 30. 19 cm -3 Above 1.0×10 20 cm -3 It may be the following.

[0102] In this embodiment, the FET structure 35 includes a plurality of emitter regions 46 formed on both sides of the trench gate structure 36. The emitter regions 46 are formed in strip shapes extending along the trench gate structure 36 in a plan view. The emitter regions 46 are exposed from the first main surface 3 and the sidewalls of the gate trench 39. The bottoms of the emitter regions 46 are formed in a region between the upper end of the gate electrode layer 41 and the bottom of the body region 45 in relation to the normal direction Z.

[0103] In this embodiment, the FET structure 35 is an n-type FET formed in a region of the semiconductor layer 2 on the second main surface 4 side with respect to the body region 45. + The n-type impurity concentration of the carrier storage region 47 is greater than the n-type impurity concentration of the drift region 30. The n-type impurity concentration of the carrier storage region 47 is 1.0×10 15 cm -3 Above 1.0×10 17 cm -3 It may be the following.

[0104] In this embodiment, the FET structure 35 includes a plurality of carrier storage regions 47 formed on both sides of the trench gate structure 36. The carrier storage regions 47 are formed in strip shapes extending along the trench gate structure 36 in a plan view. The carrier storage regions 47 are exposed from the side walls of the gate trench 39. The bottoms of the carrier storage regions 47 are formed in a region between the bottom of the body region 45 and the bottom wall of the gate trench 39 in relation to the normal direction Z.

[0105] The carrier storage region 47 prevents carriers (holes) supplied to the semiconductor layer 2 from being drawn back (discharged) to the body region 45. This causes holes to accumulate in the region directly below the FET structure 35 in the semiconductor layer 2. As a result, the on-resistance and the on-voltage are reduced.

[0106] The FET structure 35 includes an emitter trench 48 formed in the first major surface 3 of the semiconductor layer 2. The FET structure 35, in this embodiment, includes a plurality of emitter trenches 48 formed on either side of the trench gate structure 36. The emitter trench 48 exposes the emitter region 46. The emitter trench 48, in this embodiment, penetrates the emitter region 46.

[0107] The emitter trench 48 is formed at a distance from the trench gate structure 36 in the first direction X. The emitter trench 48 extends in a strip shape along the trench gate structure 36 in a plan view. In the second direction Y, the length of the emitter trench 48 is equal to or less than the length of the trench gate structure 36. Specifically, the length of the emitter trench 48 is less than the length of the trench gate structure 36.

[0108] The FET structure 35 includes a p-type FET formed in the body region 45 along the bottom wall of the emitter trench 48. + The contact region 49 includes a p-type contact region 49 having a p-type impurity concentration greater than the p-type impurity concentration of the body region 45. The p-type impurity concentration of the contact region 49 is 1.0×10 19 cm -3 Above 1.0×10 20 cm -3 It may be the following.

[0109] The contact region 49 is exposed from the bottom wall of the emitter trench 48. In a plan view, the contact region 49 extends in a strip shape along the emitter trench 48. The bottom of the contact region 49 is formed in a region between the bottom wall of the emitter trench 48 and the bottom of the body region 45 in relation to the normal direction Z.

[0110] Thus, in the FET structure 35, the gate electrode layer 41 faces the body region 45 and the emitter region 46 with the gate insulating layer 40 in between. In this configuration, the gate electrode layer 41 also faces the carrier storage region 47 with the gate insulating layer 40 in between. The channel of the IGBT is formed in the region between the emitter region 46 and the drift region 30 (carrier storage region 47) in the body region 45. The on / off of the channel is controlled by a gate signal.

[0111] Each IGBT region 8 includes a region isolation structure 50 that separates the FET structure 35 from other regions on the first main surface 3 of the semiconductor layer 2. Specifically, each IGBT region 8 includes a plurality of region isolation structures 50 formed on both sides of the FET structure 35. The region isolation structures 50 are formed in regions adjacent to the FET structure 35 on the surface layer portion of the first main surface 3. The region isolation structures 50 are respectively formed in regions between the plurality of FET structures 35 adjacent to each other. As a result, the plurality of FET structures 35 are separated from each other by the region isolation structures 50.

[0112] In the IGBT region 8, an IE (Injection Enhanced) structure 51 is formed by the FET structures 35 and the region isolation structures 50. In the IE structure 51, a plurality of FET structures 35 are arranged in a state spaced apart from each other by the region isolation structures 50.

[0113] The region isolation structure 50 restricts the movement of holes injected into the semiconductor layer 2. That is, the holes bypass the region isolation structure 50 and flow into the FET structure 35. This causes holes to accumulate in the region directly below the FET structure 35 in the semiconductor layer 2, increasing the hole density. As a result, the on-resistance and the on-voltage are reduced.

[0114] The region isolation structure 50 is a p-type semiconductor layer formed in a region adjacent to the FET structure 35 in the surface layer portion of the first main surface 3 of the semiconductor layer 2. + The floating region 52 includes a p-type floating region 52. The floating region 52 is formed in an electrically floating state. The p-type impurity concentration of the floating region 52 may be equal to or higher than the p-type impurity concentration of the body region 45. The p-type impurity concentration of the floating region 52 may be greater than the p-type impurity concentration of the body region 45. The p-type impurity concentration of the floating region 52 is 1.0×10 16 cm -3 Above 1.0×10 20 cm -3 The p-type impurity concentration of the floating region 52 may be 1.0×10 18 cm -3 Above 1.0×10 20cm -3 It is preferable that:

[0115] The bottom of the floating region 52 is formed in a region between the bottom of the carrier storage region 47 and the second main surface 4 in the normal direction Z. In this embodiment, the bottom of the floating region 52 is formed in a region between the bottom wall of the gate trench 39 and the second main surface 4 in the normal direction Z. The floating region 52 is formed in a strip shape extending along the FET structure 35 in a plan view. In the second direction Y, the length of the floating region 52 is smaller than the length of the gate trench 39.

[0116] The region isolation structure 50 includes a region isolation trench structure 53 that separates the floating region 52 from the FET structure 35. The region isolation trench structure 53 is formed in a ring shape (a square ring in this embodiment) surrounding the floating region 52 in a plan view.

[0117] The region isolation trench structure 53 includes a region isolation trench 54, a region isolation insulating layer 55, and a region isolation electrode layer 56. The region isolation trench 54 is formed in the first main surface 3 of the semiconductor layer 2. The region isolation trench 54 includes a sidewall and a bottom wall. The sidewall of the region isolation trench 54 may be formed perpendicular to the first main surface 3.

[0118] The sidewalls of the region isolation trench 54 may be inclined downward from the first main surface 3 toward the bottom wall. The region isolation trench 54 may be formed in a tapered shape in which the opening area on the opening side is larger than the bottom area. The emitter region 46, the body region 45, and the carrier storage region 47 are exposed from the sidewalls (outer sidewalls) of the region isolation trench 54 that face the FET structure 35. The floating region 52 is exposed from the sidewalls (inner sidewalls) of the region isolation trench 54 that face the floating region 52.

[0119] The bottom wall of the region isolation trench 54 may be formed parallel to the first main surface 3. The bottom wall of the region isolation trench 54 may be formed curved toward the second main surface 4. The bottom wall of the region isolation trench 54 is covered by the bottom of the floating region 52. In other words, the floating region 52 has a covering portion that covers the bottom wall of the region isolation trench 54.

[0120] The region isolation trench 54 includes an opening edge portion. The opening edge portion connects the first main surface 3 and the sidewall of the region isolation trench 54. The opening edge portion has an inclined portion that slopes downward from the first main surface 3 toward the sidewall of the region isolation trench 54. The inclined portion is formed in a curved shape recessed toward the second main surface 4. As a result, a wide portion having an opening width wider than the opening width on the bottom wall side is formed on the opening side of the region isolation trench 54. The inclined portion may be formed in a curved shape protruding toward the second main surface 4.

[0121] The region isolation trench 54 includes a bottom wall edge portion. The bottom wall edge portion connects the side wall and the bottom wall of the region isolation trench 54. The bottom wall edge portion may be formed in a curved shape toward the second main surface 4 of the semiconductor layer 2.

[0122] The depth of the region isolation trench 54 may be 2 μm or more and 10 μm or less. The depth of the region isolation trench 54 may be 2 μm or more and 3 μm or less, 3 μm or more and 4 μm or less, 4 μm or more and 5 μm or less, 5 μm or more and 6 μm or less, 6 μm or more and 7 μm or less, 8 μm or more and 9 μm or less, or 9 μm or more and 10 μm or less. The depth of the region isolation trench 54 may be equal to the depth of the gate trench 39.

[0123] The width of the region isolation trench 54 may be 0.5 μm or more and 3 μm or less. The width of the region isolation trench 54 is the width of the region isolation trench 54 in the first direction X. The width of the region isolation trench 54 may be 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, or 2.5 μm or more and 3 μm or less. The width of the region isolation trench 54 may be equal to the width of the gate trench 39.

[0124] The region isolation insulating layer 55 is formed in the form of a film along the inner wall of the region isolation trench 54. The region isolation insulating layer 55 defines a recess space in the region isolation trench 54. In this embodiment, the region isolation insulating layer 55 includes a silicon oxide film. The region isolation insulating layer 55 may include a silicon nitride film instead of or in addition to the silicon oxide film.

[0125] The region isolation insulating layer 55 includes a first region 55a, a second region 55b, and a third region 55c. The first region 55a covers the sidewall of the region isolation trench 54. The second region 55b covers the bottom wall of the region isolation trench 54. The third region 55c covers the opening edge portion of the region isolation trench 54.

[0126] The thickness of the second region 20b may be equal to or greater than the thickness of the first region 55a. The thickness of the second region 55b may be greater than the thickness of the first region 55a. The thickness of the third region 55c may be equal to or greater than the thickness of the first region 55a. The thickness of the third region 55c may be greater than the thickness of the first region 55a.

[0127] The third region 55c includes a bulging portion that bulges toward the inside of the region isolation trench 54 at the opening edge portion. The third region 55c bulges in a curved shape toward the inside of the region isolation trench 54. The third region 55c narrows the opening of the region isolation trench 54 at the opening edge portion. Of course, the region isolation insulating layer 55 having a uniform thickness may be formed.

[0128] The region isolation electrode layer 56 is embedded in the region isolation trench 54 with the region isolation insulating layer 55 sandwiched therebetween. Specifically, the region isolation electrode layer 56 is embedded in a recess space defined by the region isolation insulating layer 55 in the region isolation trench 54. The region isolation electrode layer 56 may include conductive polysilicon. The region isolation electrode layer 56 is controlled by an emitter signal.

[0129] The region separation electrode layer 56 is formed in a wall shape extending along the normal direction Z in a cross-sectional view. The region separation electrode layer 56 has an upper end portion located on the opening side of the region separation trench 54. The upper end portion of the region separation electrode layer 56 is located on the bottom wall side of the region separation trench 54 with respect to the first main surface 3.

[0130] A recess recessed toward the bottom wall of the region isolation trench 54 is formed at the upper end of the region isolation electrode layer 56. The recess at the upper end of the region isolation electrode layer 56 is formed in a tapered shape toward the bottom wall of the region isolation trench 54. The upper end of the region isolation electrode layer 56 has a constricted portion that is constricted along the third region 55c of the region isolation insulating layer 55.

[0131] 9 to 12, each diode region 9 is formed in a surface layer portion of the second main surface 4 of the semiconductor layer 2. + The n-type impurity concentration of the cathode region 61 is greater than the n-type impurity concentration of the drift region 30. The n-type impurity concentration of the cathode region 61 is 1.0×10 19 cm -3 Above 1.0×10 20 cm -3 It may be the following.

[0132] The cathode region 61 is exposed from the second main surface 4. The cathode region 61 forms an ohmic contact with the collector terminal electrode 32. The cathode region 61 is electrically connected to the collector region 34 at a side along the second direction Y. In this embodiment, the cathode region 61 is surrounded by the collector region 34 of the IGBT region 8. That is, the cathode region 61 is electrically connected to the collector region 34 at a side along the first direction X and a side along the second direction Y.

[0133] Each diode region 9 is formed in a surface layer portion of the first main surface 3 of the semiconductor layer 2. - The anode region 62 includes a p-type anode region 62 (first impurity region). The p-type impurity concentration of the anode region 62 may be equal to or lower than the p-type impurity concentration of the body region 45. The p-type impurity concentration of the anode region 62 is preferably lower than the p-type impurity concentration of the body region 45. The p-type impurity concentration of the anode region 62 is 1.0×10 15 cm -3 Above 1.0×10 18 cm -3 It may be less than.

[0134] The anode region 62 forms a pn junction with the semiconductor layer 2. This forms a pn junction diode with the anode region 62 as the anode and the semiconductor layer 2 (cathode region 61) as the cathode. In this embodiment, a plurality of anode regions 62 are formed at intervals along the first direction X in a plan view. Each of the plurality of anode regions 62 is formed in a band shape extending along the second direction Y in a plan view. The plurality of anode regions 62 are formed in a stripe shape as a whole.

[0135] The anode region 62 overlaps with the cathode region 61 in the normal direction Z. In this embodiment, all of the multiple anode regions 62 overlap with the cathode region 61 in the normal direction Z. The bottom of the anode region 62 is formed in a region between the first main surface 3 and the bottom wall of the gate trench 39 in the normal direction Z.

[0136] The distance between two anode regions 62 adjacent to each other in the first direction X may be 0.5 μm or more and 3 μm or less. The distance between two anode regions 62 may be 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, or 2.5 μm or more and 3 μm or less.

[0137] In the second direction Y, the length of the anode region 62 may be equal to or less than the length of the trench gate structure 36. The length of the anode region 62 may be less than the length of the trench gate structure 36.

[0138] Each diode region 9 includes an anode separation structure 63 that separates the anode region 62 from other regions. The anode separation structure 63 is indicated by hatching in Figures 6 and 8. Specifically, each diode region 9 includes a plurality of anode separation structures 63 that separate the plurality of anode regions 62, respectively.

[0139] The multiple anode separation structures 63 are each formed in a region between multiple adjacent anode regions 62. Specifically, the multiple anode separation structures 63 are each formed in a ring shape (a rectangular ring shape in this embodiment) surrounding the anode region 62 in a plan view. The anode separation structure 63 that partitions one anode region 62 and the anode separation structure 63 that partitions the other anode region 62 are integrally formed in the region between the multiple adjacent anode regions 62.

[0140] The anode isolation structure 63 includes an anode isolation trench 64, an anode isolation insulating layer 65, and an anode isolation electrode layer 66. The anode isolation trench 64 is formed in the first main surface 3. The anode isolation trench 64 includes a sidewall and a bottom wall. The sidewall of the anode isolation trench 64 may be formed perpendicular to the first main surface 3.

[0141] The sidewall of the anode separation trench 64 may be inclined downward from the first main surface 3 toward the bottom wall. The anode separation trench 64 may be formed in a tapered shape in which the opening area of ​​the opening side is larger than the bottom area. The bottom wall of the anode separation trench 64 may be formed parallel to the first main surface 3. The bottom wall of the anode separation trench 64 may be formed in a curved shape toward the second main surface 4.

[0142] The anode separation trench 64 includes an opening edge portion. The opening edge portion connects the first main surface 3 and the sidewall of the anode separation trench 64. The opening edge portion has an inclined portion that slopes downward from the first main surface 3 toward the sidewall of the anode separation trench 64. The inclined portion is formed in a curved shape recessed toward the second main surface 4. As a result, a wide portion having an opening width wider than the opening width on the bottom wall side is formed on the opening side of the anode separation trench 64. The inclined portion may be formed in a curved shape that protrudes toward the second main surface 4 of the semiconductor layer 2.

[0143] The anode separation trench 64 includes a bottom wall edge portion. The bottom wall edge portion connects the side wall and the bottom wall of the anode separation trench 64. The bottom wall edge portion may be formed in a curved shape toward the second main surface 4.

[0144] The depth of the anode isolation trench 64 may be 2 μm or more and 10 μm or less. The depth of the anode isolation trench 64 may be 2 μm or more and 3 μm or less, 3 μm or more and 4 μm or less, 4 μm or more and 5 μm or less, 5 μm or more and 6 μm or less, 6 μm or more and 7 μm or less, 8 μm or more and 9 μm or less, or 9 μm or more and 10 μm or less. The depth of the anode isolation trench 64 may be equal to the depth of the gate trench 39. The depth of the anode isolation trench 64 may be equal to the depth of the region isolation trench 54.

[0145] The width of the anode isolation trench 64 may be 0.5 μm or more and 3 μm or less. The width of the anode isolation trench 64 is the width of the anode isolation trench 64 in the first direction X. The width of the anode isolation trench 64 may be 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, or 2.5 μm or more and 3 μm or less. The width of the anode isolation trench 64 may be equal to the width of the gate trench 39. The width of the anode isolation trench 64 may be equal to the width of the region isolation trench 54.

[0146] The anode isolation insulating layer 65 is formed in the form of a film along the inner wall of the anode isolation trench 64. The anode isolation insulating layer 65 defines a recess space in the anode isolation trench 64. In this embodiment, the anode isolation insulating layer 65 includes a silicon oxide film. The anode isolation insulating layer 65 may include a silicon nitride film instead of or in addition to the silicon oxide film.

[0147] The portion of the anode isolation insulating layer 65 covering the sidewall (sidewall extending along the second direction Y) of the anode isolation trench 64 includes an upper end portion located on the opening side of the anode isolation trench 64. The upper end portion of the anode isolation insulating layer 65 is located on the bottom wall side of the anode isolation trench 64 with respect to the first main surface 3.

[0148] The anode isolation insulating layer 65 includes a first region 65a, a second region 65b, and a third region 65c. The first region 65a covers the sidewall of the anode isolation trench 64. The second region 65b covers the bottom wall of the anode isolation trench 64. The upper end of the anode isolation insulating layer 65 is formed by the second region 65b.

[0149] The thickness of the second region 65b may be equal to or greater than the thickness of the first region 65a. The thickness of the second region 65b may be greater than the thickness of the first region 65a. A portion of the second region 65b located on the opening side of the anode separation trench 64 may bulge inwardly of the anode separation trench 64.

[0150] In this embodiment, the third region 65c covers the opening edge portions of the anode separation trench 64 at both ends of the anode separation trench 64 in the second direction Y (see FIG. 12). The thickness of the third region 65c may be greater than the thickness of the first region 65a.

[0151] The third region 65c includes a bulging portion that bulges toward the inside of the anode isolation trench 64 at the opening edge of the anode isolation trench 64. The third region 65c curvedly bulges toward the inside of the anode isolation trench 64. The third region 65c narrows the opening of the anode isolation trench 64 at the opening edge of the gate trench 39. Of course, the anode isolation insulating layer 65 having a uniform thickness may be formed.

[0152] The anode separation electrode layer 66 is embedded in the anode separation trench 64 with the anode separation insulating layer 65 sandwiched therebetween. Specifically, the anode separation electrode layer 66 is embedded in a recess space defined by the anode separation insulating layer 65 in the anode separation trench 64. The anode separation electrode layer 66 may include conductive polysilicon. The anode separation electrode layer 66 is controlled by an emitter signal.

[0153] The anode separation electrode layer 66 is formed in a wall shape extending along the normal direction Z in a cross-sectional view. The anode separation electrode layer 66 has an upper end portion located on the opening side of the anode separation trench 64. The upper end portion of the anode separation electrode layer 66 is located on the bottom wall side of the anode separation trench 64 with respect to the first main surface 3.

[0154] An upper end portion of the anode separation electrode layer 66 is formed in a tapered shape toward the first main surface 3 side. A recess that is recessed toward the bottom wall of the anode separation trench 64 is formed at the upper end portion of the anode separation electrode layer 66. The recess of the anode separation electrode layer 66 is formed in a tapered shape toward the bottom wall of the anode separation trench 64.

[0155] Within the anode separation trench 64, a recess 67 is defined by the sidewall of the anode separation trench 64, the upper end of the anode separation electrode layer 66, and the upper end of the anode separation insulating layer 65. The wide portion of the anode separation trench 64 is formed by the recess 67. The sidewall of the recess 67 (the sidewall of the anode separation trench 64) exposes the anode region 62.

[0156] The bottom of the anode region 62 is formed in a region between the first main surface 3 and the bottom wall of the anode separation trench 64 in the normal direction Z. The bottom of the anode region 62 is formed in a region on the first main surface 3 side with respect to the bottom of the carrier storage region 47 in the normal direction Z.

[0157] The plurality of floating regions 52 includes a proximate floating region 52A that is closest to the diode region 9. In this embodiment, the proximate floating region 52A is separated from the FET structure 35 and the anode region 62 by an anode isolation structure 63.

[0158] The entire area of ​​the adjacent floating region 52A overlaps with the collector region 34 in the normal direction Z. In other words, the anode isolation structure 63 that defines the adjacent floating region 52A overlaps with the collector region 34 in the normal direction Z. In this embodiment, the boundary between the IGBT region 8 and the diode region 9 is defined by a portion of the anode isolation structure 63 that extends through the region between the adjacent floating region 52A and the anode region 62.

[0159] Of course, the adjacent floating region 52A may be separated from the FET structure 35 and the anode region 62 by a region separating trench structure 53 instead of the anode isolation structure 63. In this case, the boundary between the IGBT region 8 and the diode region 9 is defined by a portion of the region separating trench structure 53 that extends through the region between the adjacent floating region 52A and the anode region 62.

[0160] Proximal floating region 52A may be omitted, in which case the boundary between IGBT region 8 and diode region 9 is defined by the portion of anode isolation structure 63 that extends through the area between FET structure 35 and anode region 62.

[0161] 9 to 12, semiconductor device 1 includes an interlayer insulating layer 79 formed on first main surface 3 of semiconductor layer 2. Interlayer insulating layer 79 is formed in a film shape along first main surface 3 and selectively covers first main surface 3. Specifically, interlayer insulating layer 79 selectively covers IGBT region 8 and diode region 9.

[0162] The interlayer insulating layer 79 may include silicon oxide or silicon nitride. The interlayer insulating layer 79 may include at least one of NSG (Non-doped Silicate Glass), PSG (Phosphor Silicate Glass), and BPSG (Boron Phosphor Silicate Glass).

[0163] The thickness of the interlayer insulating layer 79 may be 0.1 μm or more and 1 μm or less. The thickness of the interlayer insulating layer 79 may be 0.1 μm or more and 0.2 μm or less, 0.2 μm or more and 0.4 μm or less, 0.4 μm or more and 0.6 μm or less, 0.6 μm or more and 0.8 μm or less, or 0.8 μm or more and 1 μm or less.

[0164] In this embodiment, the interlayer insulating layer 79 has a laminated structure including a first insulating layer 80, a second insulating layer 81, and a third insulating layer 82, which are laminated in this order from the first main surface 3 side. The first insulating layer 80 preferably includes silicon oxide (for example, a thermal oxide film). The second insulating layer 81 preferably includes an NGS layer. The second insulating layer 81 may include a PSG layer or a BPSG layer instead of the NGS layer. The third insulating layer 82 preferably includes a BPSG layer. The third insulating layer 82 may include an NGS layer or a PSG layer instead of the BPSG layer. The third insulating layer 82 preferably includes an insulating material having properties different from those of the second insulating layer 81.

[0165] The first insulating layer 80 is formed in a film shape on the first main surface 3. The first insulating layer 80 is continuous with the gate insulating layer 40, the region isolation insulating layer 55, and the anode isolation insulating layer 65. The second insulating layer 81 is formed in a film shape on the first insulating layer 80. The third insulating layer 82 is formed in a film shape on the second insulating layer 81.

[0166] The thickness of the first insulating layer 80 may be 500 Å or more and 2000 Å or less. The thickness of the first insulating layer 80 may be 500 Å or more and 1000 Å or less, 1000 Å or more and 1500 Å or less, or 1500 Å or more and 2000 Å or less.

[0167] The thickness of the second insulating layer 81 may be 500 Å or more and 4000 Å or less. The thickness of the second insulating layer 81 may be 500 Å or more and 1000 Å or less, 1000 Å or more and 1500 Å or less, 1500 Å or more and 2000 Å or less, 2000 Å or more and 2500 Å or less, 2500 Å or more and 3000 Å or less, 3000 Å or more and 3500 Å or more and 4000 Å or less.

[0168] The thickness of the third insulating layer 82 may be 1000 Å or more and 8000 Å or less. The thickness of the third insulating layer 82 may be 1000 Å or more and 2000 Å or less, 2000 Å or more and 4000 Å or less, 4000 Å or more and 6000 Å or less, or 6000 Å or more and 8000 Å or less.

[0169] 11, the gate electrode layer 41 of the FET structure 35 has a gate extraction electrode layer 41a extended from the gate trench 39 onto the first main surface 3. The gate extraction electrode layer 41a is extended from the gate trench 39 of the first outer trench gate structure 37 onto the first main surface 3. The gate extraction electrode layer 41a is extended along the second direction Y.

[0170] Specifically, the gate extraction electrode layer 41a is formed inside the interlayer insulating layer 79. The gate extraction electrode layer 41a is extended onto the first insulating layer 80 and is interposed in a region between the first insulating layer 80 and the second insulating layer 81. The gate extraction electrode layer 41a is electrically connected to the gate wiring 19 in a region not shown. A gate signal applied to the gate terminal electrode 14 is transmitted to the gate electrode layer 41 via the gate wiring 19 and the gate extraction electrode layer 41a.

[0171] 11, the region isolation electrode layer 56 of the region isolation structure 50 has an isolation extraction electrode layer 56a extended from the region isolation trench 54 onto the first main surface 3. The region isolation electrode layer 56 is extended along the second direction Y.

[0172] The separated extraction electrode layer 56a is specifically formed inside the interlayer insulating layer 79. The separated extraction electrode layer 56a is extended onto the first insulating layer 80 and is interposed in the region between the first insulating layer 80 and the second insulating layer 81. The separated extraction electrode layer 56a is electrically connected to the emitter terminal electrode 13. An emitter signal applied to the separated extraction electrode layer 56a is transmitted to the region separation electrode layer 56 via the separated extraction electrode layer 56a.

[0173] 12, the anode separation electrode layer 66 of the anode separation structure 63 has an anode extraction electrode layer 66a extended from the anode separation trench 64 onto the first main surface 3. The anode extraction electrode layer 66a is extended along the second direction Y.

[0174] The anode extraction electrode layer 66a is specifically formed inside the interlayer insulating layer 79. The anode extraction electrode layer 66a is extracted onto the first insulating layer 80 and is interposed in the region between the first insulating layer 80 and the second insulating layer 81. The anode extraction electrode layer 66a is electrically connected to the emitter terminal electrode 13. An emitter signal applied to the anode extraction electrode layer 66a is transmitted to the anode separation electrode layer 66 via the anode extraction electrode layer 66a.

[0175] 9 and 10, the interlayer insulating layer 79 includes an emitter opening 83. The emitter opening 83 exposes the emitter trench 48. The emitter opening 83 communicates with the emitter trench 48. In this embodiment, the emitter trench 48 is formed in the first main surface 3, penetrating the first insulating layer 80 and the second insulating layer 81.

[0176] The emitter opening 83 penetrates the third insulating layer 82 to expose the emitter trench 48. The emitter opening 83 forms an opening between the emitter opening 83 and the emitter trench 48. The edge of the emitter opening 83 is curved toward the inside of the interlayer insulating layer 79. As a result, the emitter opening 83 has an opening width larger than the opening width of the emitter trench 48.

[0177] 10 and 12 , the interlayer insulating layer 79 includes a diode opening 84. The diode opening 84 exposes the diode region 9. Specifically, the diode opening 84 penetrates the interlayer insulating layer 79 and exposes the multiple anode regions 62 and the multiple anode isolation structures 63.

[0178] A portion of the inner wall of the diode opening 84 along the second direction Y may be located above the anode region 62. A portion of the inner wall of the diode opening 84 along the second direction Y may be located above the anode separation structure 63. In this embodiment, the portion of the inner wall of the diode opening 84 along the second direction Y is located above the anode region 62 closest to the proximal floating region 52A.

[0179] The interlayer insulating layer 79 may cover one or more anode regions 62. The interlayer insulating layer 79 may cover at least one but not more than five anode regions 62. The interlayer insulating layer 79 may cover one or more anode isolation structures 63. The interlayer insulating layer 79 may cover at least one but not more than five anode isolation structures 63. The diode opening 84 may expose all of the anode regions 62. The diode opening 84 may expose some or all of the proximal floating region 52A.

[0180] The interlayer insulating layer 79 includes a first opening 86. The first opening 86 exposes the separate extraction electrode layer 56a in the IGBT region 8. The first opening 86 is formed such that the opening width narrows from the opening side toward the bottom wall side.

[0181] The interlayer insulating layer 79 includes a second opening 87. The second opening 87 exposes the anode extraction electrode layer 66a in the diode region 9. The second opening 87 is formed such that the opening width narrows from the opening side toward the bottom wall side.

[0182] 9 and 10, semiconductor device 1 includes an emitter plug electrode 91 embedded in a portion of interlayer insulating layer 79 covering IGBT region 8. Emitter plug electrode 91 penetrates interlayer insulating layer 79 and is electrically connected to emitter region 46 and contact region 49. Emitter plug electrode 91 is specifically embedded in emitter trench 48. Emitter plug electrode 91 is electrically connected to emitter region 46 and contact region 49 in emitter trench 48.

[0183] In this embodiment, the emitter plug electrode 91 has a laminated structure including a barrier electrode layer 92 and a main electrode layer 93. The barrier electrode layer 92 is formed in a film shape along the inner wall of the emitter trench 48 so as to contact the interlayer insulating layer 79. The barrier electrode layer 92 defines a recess space in the emitter trench 48.

[0184] The barrier electrode layer 92 may have a single-layer structure including a titanium layer or a titanium nitride layer, or may have a laminated structure including a titanium layer and a titanium nitride layer. In this case, the titanium nitride layer may be laminated on the titanium layer.

[0185] The main electrode layer 93 is embedded in the emitter trench 48 with the barrier electrode layer 92 sandwiched therebetween. Specifically, the main electrode layer 93 is embedded in a recess space defined by the barrier electrode layer 92 in the emitter trench 48. The main electrode layer 93 may contain tungsten.

[0186] 11, semiconductor device 1 includes a first plug electrode 94 embedded in first opening 86. First plug electrode 94 is electrically connected to isolated extraction electrode layer 56a in first opening 86. First plug electrode 94 has a structure corresponding to that of emitter plug electrode 91. The description of emitter plug electrode 91 applies mutatis mutandis to the description of first plug electrode 94. Structures of first plug electrode 94 that correspond to the structures described for emitter plug electrode 91 are denoted by the same reference numerals and descriptions thereof will be omitted.

[0187] 12, the semiconductor device 1 includes a second plug electrode 95 embedded in the second opening 87. The second plug electrode 95 is electrically connected to the anode extraction electrode layer 66a in the second opening 87. The second plug electrode 95 has a structure corresponding to that of the emitter plug electrode 91. The description of the emitter plug electrode 91 applies mutatis mutandis to the description of the second plug electrode 95. The structures of the second plug electrode 95 corresponding to those described for the emitter plug electrode 91 are denoted by the same reference numerals and will not be described.

[0188] 9 to 12, the emitter terminal electrode 13 described above is formed on an interlayer insulating layer 79. The emitter terminal electrode 13 may contain at least one of aluminum, copper, an aluminum-silicon-copper alloy, an aluminum-silicon alloy, and an aluminum-copper alloy.

[0189] The emitter terminal electrode 13 may have a single layer structure containing any one of these conductive materials. The emitter terminal electrode 13 may have a layered structure in which at least two of these conductive materials are layered in any order. In this embodiment, the emitter terminal electrode 13 is made of an aluminum-silicon-copper alloy.

[0190] The emitter terminal electrode 13 is electrically connected to the emitter region 46 and the contact region 49 via the emitter plug electrode 91 on the interlayer insulating layer 79. Specifically, the emitter terminal electrode 13 extends into the emitter opening 83 from above the interlayer insulating layer 79. The emitter terminal electrode 13 is electrically connected to the emitter plug electrode 91 in the emitter opening 83. As a result, the emitter terminal electrode 13 is electrically connected to the emitter region 46 and the contact region 49 via the emitter plug electrode 91.

[0191] 10 and 12, the emitter terminal electrode 13 further extends into the diode opening 84 through the inner wall of the diode opening 84 from above the interlayer insulating layer 79. The emitter terminal electrode 13 functions as an anode terminal electrode in the diode region 9.

[0192] The emitter terminal electrode 13 is in contact with the inner wall of the diode opening 84. The emitter terminal electrode 13 is electrically connected to the anode region 62 at the diode opening 84. The emitter terminal electrode 13 is electrically connected to the anode separation electrode layer 66 at the diode opening 84. In this embodiment, the emitter terminal electrode 13 is directly connected to the anode region 62 and the anode separation electrode layer 66.

[0193] Specifically, the emitter terminal electrode 13 extends from above the first main surface 3 into the recess 67 (anode separation trench 64) within the diode opening 84. The emitter terminal electrode 13 is connected to the anode separation electrode layer 66 within the recess 67. The emitter terminal electrode 13 is also connected to the anode region 62 on the first main surface 3 and within the recess 67. The emitter terminal electrode 13 forms an ohmic contact with the anode region 62.

[0194] The angle θ that the inner wall of the diode opening 84 forms with the first main surface 3 is preferably equal to or greater than 45° and equal to or less than 90°. The angle θ is the angle that the inner wall of the diode opening 84 forms with the first main surface 3 within the covering portion of the interlayer insulating layer 79 that covers the first main surface 3.

[0195] Specifically, the angle θ is the angle that a line connecting the top of the inner wall of the diode opening 84 located on the opening side of the diode opening 84 and the base located on the bottom side of the diode opening 84 forms with the first main surface 3 within the interlayer insulating layer 79.

[0196] The angle θ may be 45° to 50°, 50° to 55°, 55° to 60°, 60° to 65°, 65° to 70°, 70° to 75°, 75° to 80°, 80° to 85°, or 85° to 90°. The angle θ is preferably 60° to 90°.

[0197] When the angle θ is less than 45°, a thin film portion is formed in the portion of the interlayer insulating layer 79 covering the diode region 9. When a thin film portion is formed in the interlayer insulating layer 79, the emitter terminal electrode 13 faces the first main surface 3 (anode region 62 and / or anode separation electrode layer 66) with the thin film portion of the interlayer insulating layer 79 sandwiched therebetween. In this case, an electric field is concentrated in the thin film portion of the interlayer insulating layer 79, and as a result, there is a possibility that the dielectric breakdown resistance will decrease starting from the thin film portion of the interlayer insulating layer 79.

[0198] Therefore, in this embodiment, the inner wall of the diode opening 84 is formed so that the angle θ is 45° or more (preferably 60° or more), thereby preventing a thin film portion from being formed in the interlayer insulating layer 79. This makes it possible to prevent a decrease in the dielectric breakdown resistance caused by undesired electric field concentration.

[0199] 11 and 12, the emitter terminal electrode 13 is electrically connected to a first plug electrode 94 and a second plug electrode 95 on the interlayer insulating layer 79. The emitter signal is transmitted to the region isolation electrode layer 56 via the first plug electrode 94. The emitter signal is transmitted to the anode isolation electrode layer 66 via the second plug electrode 95.

[0200] Although not specifically shown, when a conductive wire (e.g., a bonding wire) is connected to the emitter terminal electrode 13, a single-layer electrode made of a nickel layer or a gold layer, or a laminated electrode including a nickel layer and a gold layer may be formed on the emitter terminal electrode 13. In the laminated electrode, the gold layer may be formed on the nickel layer.

[0201] Although specific illustrations are omitted, the gate terminal electrode 14, the first sense terminal electrode 15, the second sense terminal electrode 16, the current detection terminal electrode 17 and the open terminal electrode 18 are formed on the interlayer insulating layer 79, similar to the emitter terminal electrode 13.

[0202] Each of the terminal electrodes 14-18 may contain at least one of aluminum, copper, an aluminum-silicon-copper alloy, an aluminum-silicon alloy, and an aluminum-copper alloy. Each of the terminal electrodes 14-18 may have a single-layer structure containing any one of these conductive materials. Each of the terminal electrodes 14-18 may have a layered structure in which at least two of these conductive materials are layered in any order. In this embodiment, the terminal electrodes 14-18 contain the same conductive material as the emitter terminal electrode 13.

[0203] When a conductive wire (e.g., a bonding wire) is connected to each of the terminal electrodes 14 to 18, a single-layer electrode made of a nickel layer or a gold layer, or a laminated electrode including a nickel layer and a gold layer may be formed on each of the terminal electrodes 14 to 18. In the laminated electrode, the gold layer may be formed on the nickel layer.

[0204] Figure 13 is a graph showing the relationship between the recovery loss Err and the forward voltage VF, which was investigated by simulation. In Figure 13, the vertical axis is the recovery loss Err [mJ cm -2 13, the horizontal axis represents forward voltage VF [V], and the horizontal axis represents forward voltage VF [V]. In FIG. 13, a first plot point P1, a second plot point P2, and a third plot point P3 are shown.

[0205] The first plot point P1 indicates the characteristics of a first embodiment of the semiconductor device 1. The first embodiment has a structure in which the p-type impurity concentration of the anode region 62 is equal to the p-type impurity concentration of the body region 45, and the emitter terminal electrode 13 is electrically connected to the anode region 62 via a barrier electrode layer. The barrier electrode layer, like the barrier electrode layer 92, may have a single-layer structure including a titanium layer or a titanium nitride layer, or a laminated structure including a titanium layer and a titanium nitride layer.

[0206] The second plot point P2 indicates the characteristics of a second embodiment of the semiconductor device 1. The second embodiment has a structure in which the p-type impurity concentration of the anode region 62 is lower than the p-type impurity concentration of the body region 45, and the emitter terminal electrode 13 is electrically connected to the anode region 62 via a barrier electrode layer. The barrier electrode layer, like the barrier electrode layer 92, may have a single-layer structure including a titanium layer or a titanium nitride layer, or a laminated structure including a titanium layer and a titanium nitride layer.

[0207] The third plot point P3 shows the characteristics of a third embodiment of the semiconductor device 1. The third embodiment has a structure in which the p-type impurity concentration of the anode region 62 is lower than the p-type impurity concentration of the body region 45, and the emitter terminal electrode 13 is directly connected to the anode region 62 without a barrier electrode layer. The third plot point P3 is also a characteristic of the semiconductor device 1.

[0208] Referring to the first plot point P1, the first embodiment has a relatively low forward voltage VF, but a relatively high recovery loss Err. In the first embodiment, the recovery loss Err is 69 mJ cm -2 and the forward voltage VF was 0.88V.

[0209] With reference to the second plot point P2, in the second embodiment, the recovery loss Err is reduced and the forward voltage VF is increased compared to the first embodiment. In the second embodiment, the recovery loss Err is 40 mJ cm -2 and the forward voltage VF was 1.38V.

[0210] With reference to the third plot point P3, in the third embodiment, the recovery loss Err decreased and the forward voltage VF increased compared to the first embodiment. In the third embodiment, the recovery loss Err increased and the forward voltage VF decreased compared to the second embodiment. In the third embodiment, the recovery loss Err was 42 mJ cm -2 and the forward voltage VF was 1.13V.

[0211] In the first embodiment, the p-type impurity concentration of the anode region 62 is equal to the p-type impurity concentration of the body region 45. This improves the ohmic properties of the barrier electrode layer with respect to the anode region 62, thereby achieving a good forward voltage VF. However, in the first embodiment, there is a tradeoff in that the high concentration of the anode region 62 increases the recovery loss Err.

[0212] In the second embodiment, the recovery loss Err is reduced due to the reduction in the concentration of the anode region 62. However, in the second embodiment, the reduction in the concentration of the anode region 62 reduces the ohmic property of the barrier electrode layer with respect to the anode region 62, which causes a trade-off in that the forward voltage VF increases.

[0213] In the third embodiment, the recovery loss Err is reduced due to the lowering of the concentration of the anode region 62. In the third embodiment, the emitter terminal electrode 13 is directly connected to the anode region 62, so there is no decrease in ohmic properties due to the barrier electrode layer. The emitter terminal electrode 13 forms relatively good ohmic contact with the anode region 62. This makes it possible to reduce the recovery loss Err while suppressing an increase in the forward voltage VF.

[0214] 13, when a relatively low recovery loss Err is required, the structures according to the second embodiment and the third embodiment are preferable. Also, when a relatively low forward voltage VF and a relatively low recovery loss Err are required, the structure according to the third embodiment is preferable.

[0215] In the IGBT region 8, it is also possible to directly connect the emitter terminal electrode 13 to the emitter region 46 or the contact region 49. In this case, however, since the barrier electrode layer 92 does not exist, interdiffusion of constituent materials occurs between the semiconductor layer 2 and the emitter terminal electrode 13. In particular, if the emitter terminal electrode 13 contains aluminum, the aluminum diffuses into the semiconductor layer 2, causing fluctuations in the IGBT characteristics, such as fluctuations in the gate threshold voltage.

[0216] In this case, there is also a problem that relatively advanced manufacturing conditions are required because the emitter terminal electrode 13 needs to be appropriately embedded in the emitter trench 48. That is, the emitter trench 48 is introduced due to the narrowing of the pitch of the multiple trench gate structures 36.

[0217] In a structure in which the multiple trench gate structures 36 are arranged at a narrow pitch, the contact areas with the emitter regions 46 and the contact regions 49 are reduced. The emitter trenches 48 are formed to reliably achieve contact with the emitter regions 46 and the contact regions 49 in such a narrow pitch structure.

[0218] The width of the emitter trench 48 is relatively narrow because it is formed in a region between adjacent trench gate structures 36. Relatively advanced manufacturing conditions are required to embed the emitter terminal electrode 13 in the relatively narrow emitter trench 48 while connecting the emitter terminal electrode 13 to the anode region 62.

[0219] Therefore, in this embodiment, an emitter plug electrode 91 is embedded in the emitter trench 48. The emitter plug electrode 91 has a laminated structure including a barrier electrode layer 92 containing titanium and / or titanium nitride and a main electrode layer 93 containing tungsten.

[0220] Titanium and / or titanium nitride have excellent thin film and film forming properties, while tungsten has excellent embedding properties, which allows emitter plug electrode 91 to be appropriately embedded in emitter trench 48.

[0221] Furthermore, the barrier electrode layer 92 suppresses the conductive material of the emitter terminal electrode 13 and the conductive material of the main electrode layer 93 from diffusing into the semiconductor layer 2. This allows the emitter terminal electrode 13 to be appropriately electrically connected to the emitter region 46 and the contact region 49 via the emitter plug electrode 91.

[0222] On the other hand, unlike the IGBT region 8, the diode region 9 does not have a complicated structure and does not require advanced manufacturing conditions. In the diode region 9, as shown in Fig. 13, even if the emitter terminal electrode 13 is directly connected to the anode region 62 without a barrier electrode layer, it is possible to suppress the recovery loss Err while suppressing an increase in the forward voltage VF. Therefore, it is possible to appropriately improve the diode characteristics while suppressing the fluctuation of the IGBT characteristics.

[0223] Fig. 14 is an enlarged view of region XIV shown in Fig. 1. Fig. 15 is a circuit diagram showing an electrical structure of the region shown in Fig. 14. Fig. 16 is a cross-sectional view taken along line XVI-XVI shown in Fig. 14. Fig. 17 is a cross-sectional view taken along line XVII-XVII shown in Fig. 14.

[0224] 14 to 17, the sensor region 11 includes a temperature sensitive diode sensor 100 as an example of a temperature sensor. The temperature sensitive diode sensor 100 has a parallel circuit 103 including a first diode 101 and a second diode 102. The second diode 102 is connected in reverse parallel to the first diode 101. In other words, the anode of the second diode 102 is connected to the cathode of the first diode 101, and the cathode of the second diode 102 is connected to the anode of the first diode 101.

[0225] Specifically, the parallel circuit 103 has a configuration in which a first series circuit 104 including a plurality (four in this embodiment) of first diodes 101 connected in series in the forward direction, and a second series circuit 105 including a plurality (four in this embodiment) of second diodes 102 connected in series in the forward direction are connected in reverse parallel.

[0226] 16 and 17, the temperature sensitive diode sensor 100 includes a polysilicon layer 106 formed on the first main surface 3 of the semiconductor layer 2. The temperature sensitive diode sensor 100 is formed by selectively introducing n-type impurities and p-type impurities into the undoped polysilicon layer 106.

[0227] Specifically, the polysilicon layer 106 is formed on the first insulating layer 80. The polysilicon layer 106 has a first surface 107 on one side, a second surface 108 on the other side, and a side surface 109 connecting the first surface 107 and the second surface 108. The first surface 107 and the second surface 108 are formed in a quadrangular shape (rectangular shape in this embodiment) in a plan view. The second surface 108 of the polysilicon layer 106 is in contact with the first insulating layer 80. The polysilicon layer 106 is electrically insulated from the semiconductor layer 2 by the first insulating layer 80.

[0228] The thickness of the polysilicon layer 106 may be 0.2 μm or more and 1 μm or less. The thickness of the polysilicon layer 106 may be 0.2 μm or more and 0.4 μm or less, 0.4 μm or more and 0.6 μm or less, 0.6 μm or more and 0.8 μm or less, or 0.8 μm or more and 1 μm or less.

[0229] The temperature sensitive diode sensor 100 includes a first circuit forming region 111 and a second circuit forming region 112 formed in a polysilicon layer 106. The first circuit forming region 111 and the second circuit forming region 112 are set at an interval from each other along the short side direction of the polysilicon layer 106 (second direction Y in this embodiment).

[0230] In this embodiment, the first circuit formation region 111 includes a plurality of (four in this embodiment) first diode formation regions 113. The first diode formation regions 113 are regions in which the first diodes 101 are formed. The plurality of first diode formation regions 113 are set at intervals from one another in the longitudinal direction of the polysilicon layer 106 (first direction X in this embodiment).

[0231] In this embodiment, each of the first diode-forming regions 113 is formed in a quadrangular shape in a plan view. Each of the first diode-forming regions 113 is partitioned from other regions in the form of a cell by a slit formed in the polysilicon layer 106. Each of the first diode-forming regions 113 may be partitioned from other regions by an impurity-free region of the polysilicon layer 106.

[0232] In this embodiment, the second circuit formation region 112 includes a plurality of (four in this embodiment) second diode formation regions 114. The second diode formation regions 114 are regions in which the second diodes 102 are formed. The second diode formation regions 114 are set at intervals from one another in the longitudinal direction of the polysilicon layer 106 (first direction X in this embodiment).

[0233] In this embodiment, each second diode-forming region 114 is formed in a quadrangular shape in a plan view. Each second diode-forming region 114 is partitioned from other regions in the form of a cell by a slit formed in the polysilicon layer 106. Each second diode-forming region 114 may be partitioned from other regions by an impurity-free region of the polysilicon layer 106.

[0234] Each first diode-forming region 113 includes a p-type first anode region 115 and an n-type first cathode region 116. The first anode region 115 is formed in the center of the first diode-forming region 113. In this embodiment, the first anode region 115 is exposed from the first surface 107 and the second surface 108 of the polysilicon layer 106.

[0235] The first anode region 115 is formed in a circular shape in a plan view. The planar shape of the first anode region 115 is arbitrary. The first anode region 115 may be formed in a polygonal shape such as a triangular shape, a rectangular shape, or a hexagonal shape, or an elliptical shape in a plan view.

[0236] The first cathode region 116 is formed along the periphery of the first anode region 115. In this embodiment, the first cathode region 116 is formed in an annular shape surrounding the first cathode region 115 in a plan view. In this embodiment, the first cathode region 116 is exposed from the first surface 107 and the second surface 108 of the polysilicon layer 106.

[0237] The first cathode region 116 is electrically connected to the first anode region 115. The first cathode region 116 is connected to the first anode region 115 over the entire thickness direction of the polysilicon layer 106. The first cathode region 116 forms a pn junction with the first anode region 115. As a result, each first diode formation region 113 includes one first diode 101 with the first anode region 115 as the anode and the first cathode region 116 as the cathode.

[0238] Each second diode forming region 114 includes a p-type second anode region 117 and an n-type second cathode region 118. The second anode region 117 is formed in the center of the second diode forming region 114. In this embodiment, the second anode region 117 is exposed from the first surface 107 and the second surface 108 of the polysilicon layer 106.

[0239] The second anode region 117 is formed in a circular shape in a plan view. The second anode region 117 may have any planar shape. The second anode region 117 may be formed in a polygonal shape such as a triangular shape, a rectangular shape, or a hexagonal shape, or in an elliptical shape in a plan view.

[0240] The second cathode region 118 is formed along the periphery of the second anode region 117. In this embodiment, the second cathode region 118 is formed in an annular shape surrounding the second cathode region 117 in a plan view. In this embodiment, the second cathode region 118 is exposed from the first surface 107 and the second surface 108 of the polysilicon layer 106.

[0241] The second cathode region 118 is electrically connected to the second anode region 117. The second cathode region 118 is connected to the second anode region 117 over the entire thickness direction of the polysilicon layer 106. The second cathode region 118 forms a pn junction with the second anode region 117. As a result, each second diode formation region 114 includes one second diode 102 with the second anode region 117 as the anode and the second cathode region 118 as the cathode.

[0242] The aforementioned interlayer insulating layer 79 covers the polysilicon layer 106. The interlayer insulating layer 79 includes a first anode opening 121 and a first cathode opening 122 in a portion covering each first diode forming region 113. The first anode opening 121 exposes the first anode region 115. The first anode opening 121 is formed by penetrating the interlayer insulating layer 79 and digging down the surface portion of the polysilicon layer 106. The bottom of the first anode opening 121 is located within the first anode region 115.

[0243] The first anode opening 121 extends in a band shape along the periphery of the first anode region 115 in a plan view. Specifically, the first anode opening 121 is formed in a circular ring shape in a plan view. The planar shape of the first anode opening 121 is arbitrary and is not limited to a circular ring shape. The first anode opening 121 may be formed in a polygonal ring shape such as a triangular ring, a square ring, or a hexagonal ring, or an elliptical ring shape, or a polygonal shape such as a triangular shape, a square shape, or a hexagonal shape, or an elliptical shape in a plan view.

[0244] In this embodiment, one first anode opening 121 is formed in each first diode-forming region 113. The number of first anode openings 121 is arbitrary. Therefore, a plurality of first anode openings 121 may be formed in each first diode-forming region 113 at intervals.

[0245] The first cathode opening 122 exposes the first cathode region 116 of the first diode formation region 113. The first cathode opening 122 is formed by penetrating the interlayer insulating layer 79 and digging down the surface portion of the polysilicon layer 106. The bottom of the first cathode opening 122 is located within the first cathode region 116.

[0246] The first cathode opening 122 extends in a band shape along the periphery of the first anode region 115 in a plan view. The first cathode opening 122 is formed in a C-shape in a plan view. The planar shape of the first cathode opening 122 is arbitrary and is not limited to a C-shape. The first cathode opening 122 may be formed in a polygonal shape such as a triangular shape, a rectangular shape, or a hexagonal shape, or in an elliptical shape in a plan view.

[0247] In this embodiment, one first cathode opening 122 is formed in each first diode-forming region 113. The number of first cathode openings 122 is arbitrary. Therefore, a plurality of first cathode openings 122 may be formed in each first diode-forming region 113 at intervals.

[0248] The interlayer insulating layer 79 includes a second anode opening 123 and a second cathode opening 124 in a portion covering each second diode forming region 114. The second anode opening 123 exposes the second anode region 117. The second anode opening 123 is formed by penetrating the interlayer insulating layer 79 and digging down a surface portion of the polysilicon layer 106. The bottom of the second anode opening 123 is located within the second anode region 117.

[0249] The second anode opening 123 extends in a band shape along the periphery of the second anode region 117 in a plan view. Specifically, the second anode opening 123 is formed in a circular ring shape in a plan view. The planar shape of the second anode opening 123 is arbitrary and is not limited to a circular ring shape. The second anode opening 123 may be formed in a polygonal ring shape such as a triangular ring, a square ring, or a hexagonal ring, or an elliptical ring shape, or a polygonal shape such as a triangular shape, a square shape, or a hexagonal shape, or an elliptical shape in a plan view.

[0250] In this embodiment, one second anode opening 123 is formed in each second diode-forming region 114. The number of second anode openings 123 is arbitrary. Therefore, a plurality of second anode openings 123 may be formed in each second diode-forming region 114 at intervals.

[0251] The second cathode opening 124 exposes the second cathode region 118 of the second diode formation region 114. The second cathode opening 124 is formed by penetrating the interlayer insulating layer 79 and digging down the surface portion of the polysilicon layer 106. The bottom of the second cathode opening 124 is located within the second cathode region 118.

[0252] The second cathode opening 124 extends in a band shape along the periphery of the second anode region 117 in a plan view. The second cathode opening 124 is formed in a C-shape in a plan view. The planar shape of the second cathode opening 124 is arbitrary and is not limited to a C-shape. The second cathode opening 124 may be formed in a polygonal shape such as a triangular shape, a rectangular shape, or a hexagonal shape, or in an elliptical shape in a plan view.

[0253] In this embodiment, one second cathode opening 124 is formed in each second diode-forming region 114. The number of second cathode openings 124 is arbitrary. Therefore, a plurality of second cathode openings 124 may be formed in each second diode-forming region 114 at intervals.

[0254] The semiconductor device 1 includes a first diode wiring 131 formed on a portion of the interlayer insulating layer 79 that covers the first circuit formation region 111. The first diode wiring 131 connects a plurality of first diodes 101 in series in the forward direction between the first sense wiring 20 and the second sense wiring 21. The first diode wiring 131 has one end connected to the first sense wiring 20 and the other end connected to the second sense wiring 21.

[0255] The first diode wiring 131 may include at least one of aluminum, copper, an aluminum-silicon-copper alloy, an aluminum-silicon alloy, and an aluminum-copper alloy.

[0256] Specifically, the first diode wiring 131 includes a plurality of first anode electrodes 133, a plurality of first cathode electrodes 134, and a plurality of first connection electrodes 135. Each of the first anode electrodes 133 is formed on a portion of the interlayer insulating layer 79 that covers each of the first diode forming regions 113.

[0257] The first anode electrode 133 is formed in a circular shape in a plan view. The planar shape of the first anode electrode 133 is arbitrary. The first anode electrode 133 may be formed in a polygonal shape such as a triangular shape, a rectangular shape, or a hexagonal shape, or in an elliptical shape in a plan view.

[0258] The first anode electrode 133 extends into the first anode opening 121 from above the interlayer insulating layer 79. The first anode electrode 133 is electrically connected to the first anode region 115 within the first anode opening 121.

[0259] Each of the first cathode electrodes 134 is formed on a portion of the interlayer insulating layer 79 that covers each of the first diode-forming regions 113. Each of the first cathode electrodes 134 extends in a strip shape along the first anode electrodes 133 in a plan view.

[0260] In this embodiment, the first cathode electrode 134 is formed in a C-shape in plan view. The planar shape of the first cathode electrode 134 is arbitrary and is not limited to a C-shape. The first cathode electrode 134 may be formed in a polygonal shape such as a triangular shape, a rectangular shape, or a hexagonal shape, or an elliptical shape in plan view.

[0261] The first cathode electrode 134 extends into the first cathode opening 122 from above the interlayer insulating layer 79. The first cathode electrode 134 is electrically connected to the first cathode region 116 in the first cathode opening 122.

[0262] Each first connection electrode 135 is formed on a portion of the interlayer insulating layer 79 covering a region between adjacent first diode-forming regions 113. The first connection electrode 135 is drawn from the first cathode electrode 134 of one first diode-forming region 113 and connected to the first anode electrode 133 of the other first diode-forming region 113.

[0263] In this embodiment, the first connection electrode 135 is formed in a strip shape extending along the longitudinal direction (first direction X in this embodiment) of the polysilicon layer 106 in a plan view. The first connection electrode 135 may be routed in a line shape in a region between a plurality of first diode-forming regions 113 adjacent to each other.

[0264] One first connection electrode 135 located at one end of the polysilicon layer 106 in the longitudinal direction is connected to the second sense wiring 21. One first connection electrode 135 located at the other end of the polysilicon layer 106 in the longitudinal direction is connected to the first sense wiring 20. As a result, a first series circuit 104 including a plurality of (four in this embodiment) first diodes 101 connected in series in the forward direction to the first sense wiring 20 is formed in the region between the first sense wiring 20 and the second sense wiring 21.

[0265] The semiconductor device 1 includes a second diode wiring 132 formed on a portion of the interlayer insulating layer 79 that covers the second circuit formation region 112. The second diode wiring 132 connects a plurality of second diodes 102 in series in the forward direction between the first sense wiring 20 and the second sense wiring 21. The second diode wiring 132 has one end connected to the first sense wiring 20 and the other end connected to the second sense wiring 21.

[0266] The second diode wiring 132 may include at least one of aluminum, copper, an aluminum-silicon-copper alloy, an aluminum-silicon alloy, and an aluminum-copper alloy.

[0267] Specifically, the second diode wiring 132 includes a plurality of second anode electrodes 136, a plurality of second cathode electrodes 137, and a plurality of second connection electrodes 138. Each of the second anode electrodes 136 is formed on a portion of the interlayer insulating layer 79 that covers each of the second diode forming regions 114.

[0268] The second anode electrode 136 is formed in a circular shape in a plan view. The second anode electrode 136 may have any planar shape. The second anode electrode 136 may be formed in a polygonal shape such as a triangular shape, a rectangular shape, or a hexagonal shape, or in an elliptical shape in a plan view.

[0269] The second anode electrode 136 extends into the second anode opening 123 from above the interlayer insulating layer 79. The second anode electrode 136 is electrically connected to the second anode region 117 within the second anode opening 123.

[0270] Each second cathode electrode 137 is formed on a portion of the interlayer insulating layer 79 that covers each second diode-forming region 114. Each second cathode electrode 137 extends in a strip shape along the second anode electrode 136 in a plan view.

[0271] In this embodiment, the second cathode electrode 137 is formed in a C-shape in plan view. The planar shape of the second cathode electrode 137 is arbitrary and is not limited to a C-shape. The second cathode electrode 137 may be formed in a polygonal shape such as a triangular shape, a rectangular shape, or a hexagonal shape, or an elliptical shape in plan view.

[0272] The second cathode electrode 137 extends into the second cathode opening from above the interlayer insulating layer 79. The second cathode electrode 137 is electrically connected to the second cathode region 118 in the second cathode opening .

[0273] Each second connection electrode 138 is formed on a portion of the interlayer insulating layer 79 covering a region between adjacent second diode-forming regions 114. The second connection electrode 138 is drawn from the second cathode electrode 137 of one second diode-forming region 114 and connected to the second anode electrode 136 of the other second diode-forming region 114.

[0274] In this embodiment, the second connection electrode 138 is formed in a strip shape extending along the longitudinal direction (the first direction X in this embodiment) of the polysilicon layer 106 in a plan view. The second connection electrode 138 may be routed in a line shape in a region between the plurality of second diode-forming regions 114 adjacent to each other.

[0275] The second connection electrode 138 located at one end of the polysilicon layer 106 in the longitudinal direction is connected to the second sense wiring 21. The second connection electrode 138 located at the other end of the polysilicon layer 106 in the longitudinal direction is connected to the first sense wiring 20. As a result, a second series circuit 105 including a plurality of second diodes 102 (four in this embodiment) connected in series in the forward direction to the second sense wiring 21 is formed in the region between the first sense wiring 20 and the second sense wiring 21.

[0276] Fig. 18 is an enlarged view of an area XVIII shown in Fig. 1. Fig. 19 is a cross-sectional view taken along line XIX-XIX shown in Fig. 18.

[0277] 18 and 19, the gate wiring 19 includes a low resistance wiring portion 150, a first high resistance wiring portion 151 and a second high resistance wiring portion 152 in this embodiment.

[0278] The low-resistance wiring section 150 has a relatively low resistance value, and forms a main current path of the gate wiring 19. The low-resistance wiring section 150 is formed on the first main surface 3 (interlayer insulating layer 79) of the semiconductor layer 2 with a gap therebetween from the gate terminal electrode 14. The low-resistance wiring section 150 is formed along the periphery of the gate terminal electrode 14, and is selectively routed on the first main surface 3 (interlayer insulating layer 79) of the semiconductor layer 2.

[0279] The low-resistance wiring section 150 may contain at least one of aluminum, copper, an aluminum-silicon-copper alloy, an aluminum-silicon alloy, and an aluminum-copper alloy. The low-resistance wiring section 150 may be formed of the same metal material as the gate terminal electrode 14.

[0280] The first high resistance wiring portion 151 has a resistance value higher than that of the low resistance wiring portion 150. The first high resistance wiring portion 151 may include conductive polysilicon. The first high resistance wiring portion 151 is interposed in a region between the gate terminal electrode 14 and the low resistance wiring portion 150, and is electrically connected to the gate terminal electrode 14 and the low resistance wiring portion 150. A gate signal input to the gate terminal electrode 14 is transmitted to the low resistance wiring portion 150 via the first high resistance wiring portion 151.

[0281] Specifically, the first high resistance wiring portion 151 is formed in a region below the gate terminal electrode 14 and the low resistance wiring portion 150. The first high resistance wiring portion 151 is formed in a region between the first main surface 3 and the interlayer insulating layer 79. The first high resistance wiring portion 151 is formed on the first insulating layer 80.

[0282] The first high-resistance wiring portion 151 includes a first lead portion 151a and a second lead portion 151b. The first lead portion 151a is led from above the first insulating layer 80 to a region immediately below the gate terminal electrode 14. The second lead portion 151b is led from above the first insulating layer 80 to a region immediately below the low-resistance wiring portion 150.

[0283] A first opening 153 and a second opening 154 are formed in a region of the interlayer insulating layer 79 covering the first high-resistance wiring portion 151. The first opening 153 exposes the first drawn portion 151a of the first high-resistance wiring portion 151. The second opening 154 exposes the second drawn portion 151b of the second high-resistance wiring portion 152.

[0284] A first plug electrode 155 is embedded in the first opening 153. The first lead portion 151a is electrically connected to the gate terminal electrode 14 via the first plug electrode 155. The description of the emitter plug electrode 91 applies mutatis mutandis to the description of the first plug electrode 155. Structures of the first plug electrode 155 corresponding to the structures described for the emitter plug electrode 91 are denoted by the same reference numerals and descriptions thereof will be omitted.

[0285] A second plug electrode 156 is embedded in the second opening 154. The second lead portion 151b is electrically connected to the first high-resistance wiring portion 151 via the second plug electrode 156. The description of the emitter plug electrode 91 applies mutatis mutandis to the description of the second plug electrode 156. The structures of the second plug electrode 156 that correspond to the structures described for the emitter plug electrode 91 are denoted by the same reference numerals and descriptions thereof will be omitted.

[0286] The second high resistance wiring portion 152 has a resistance value higher than that of the low resistance wiring portion 150. The second high resistance wiring portion 152 may include conductive polysilicon. The second high resistance wiring portion 152 is interposed in a region between the gate extraction electrode layer 41a and the low resistance wiring portion 150, and is electrically connected to the gate extraction electrode layer 41a and the low resistance wiring portion 150. The gate signal transmitted to the low resistance wiring portion 150 is transmitted to the gate extraction electrode layer 41a via the second high resistance wiring portion 152.

[0287] The second high resistance wiring portion 152 is specifically formed in a lower layer region of the low resistance wiring portion 150. The second high resistance wiring portion 152 is formed in the same layer as the gate extraction electrode layer 41a. The second high resistance wiring portion 152 is formed in a region between the first main surface 3 and the interlayer insulating layer 79. The second high resistance wiring portion 152 is formed on the first insulating layer 80.

[0288] The second high-resistance wiring portion 152 has an extraction portion 152a that is extracted from above the first insulating layer 80 to a region directly below the low-resistance wiring portion 150. The second high-resistance wiring portion 152 also has a connection portion that is continuous with the gate extraction electrode layer 41a in a region not shown.

[0289] A third opening 157 is formed in the interlayer insulating layer 79 in a region covering the second high-resistance wiring portion 152. The third opening 157 allows the drawn-out portion 152a of the second high-resistance wiring portion 152 to be exposed.

[0290] A third plug electrode 158 is embedded in the third opening 157. The description of the third plug electrode 158 shall apply mutatis mutandis to the description of the emitter plug electrode 91. The structures of the third plug electrode 158 that correspond to the structures described for the emitter plug electrode 91 are denoted by the same reference characters and descriptions thereof will be omitted.

[0291] Lead-out portion 152a is electrically connected to low-resistance wiring portion 150 via third plug electrode 158. The connection position between lead-out portion 152a and low-resistance wiring portion 150 is arbitrary and is not limited to the locations shown in FIGS.

[0292] The shorter the distance between the low-resistance wiring portion 150 and the gate extraction electrode layer 41a, the more the wiring resistance can be reduced. The connection position of the extraction portion 152a and the low-resistance wiring portion 150 is preferably set in consideration of the wiring resistance between the low-resistance wiring portion 150 and the gate extraction electrode layer 41a.

[0293] A gate signal input to the gate terminal electrode 14 is transmitted to the gate extraction electrode layer 41a via the first high-resistance wiring portion 151, the low-resistance wiring portion 150, and the second high-resistance wiring portion 152. The gate signal transmitted to the gate extraction electrode layer 41a is transmitted to the gate electrode layer 41.

[0294] In this manner, the gate wiring 19 includes the first high-resistance wiring portion 151 interposed between the low-resistance wiring portion 150 and the gate terminal electrode 14. A gate signal input to the gate terminal electrode 14 is transmitted to the low-resistance wiring portion 150 via the first high-resistance wiring portion 151.

[0295] The first high-resistance wiring section 151 suppresses an inrush current from flowing from the gate terminal electrode 14 to the low-resistance wiring section 150. On the other hand, the low-resistance wiring section 150 transmits the gate signal to the FET structure 35 while suppressing a voltage drop of the gate signal. This makes it possible to suppress malfunction of the FET structure 35 caused by the inrush current. In addition, since the malfunction of the FET structure 35 can be suppressed, it is also possible to reduce switching noise.

[0296] Furthermore, the gate wiring 19 includes a second high resistance wiring portion 152 interposed between the low resistance wiring portion 150 and the gate extraction electrode layer 41a. The second high resistance wiring portion 152 suppresses an inrush current from flowing from the low resistance wiring portion 150 to the gate extraction electrode layer 41a. This makes it possible to appropriately suppress malfunction of the FET structure 35 caused by the inrush current. Furthermore, since the malfunction of the FET structure 35 can be appropriately suppressed, switching noise can be appropriately reduced.

[0297] As described above, according to the semiconductor device 1, the total length of the boundary lines between the plurality of IGBT regions 8 and the plurality of diode regions 9 is represented by L, the total area of ​​the plurality of diode regions 9 is represented by SD, and the dispersion degree D of the plurality of diode regions 9 with respect to the active region 6 is represented by Log e (L 2 / SD), the dispersion D is equal to or greater than 2 and equal to or less than 15. This makes it possible to improve the withstand capability against surge current Is while suppressing the fluctuation in forward voltage VF before and after application of bias voltage Vge to the IGBT (see Figures 3 and 4).

[0298] When the dispersity D is set in the range of 2 to 7, the withstand capability against the surge current Is can be increased while reliably suppressing an increase in the forward voltage VF caused by the application of the bias voltage Vge. On the other hand, when the dispersity D is set in the range of 7 to 12, the withstand capability against the surge current Is can be reliably increased while suppressing an increase in the forward voltage VF caused by the application of the bias voltage Vge.

[0299] The semiconductor device 1 also includes an interlayer insulating layer 79 having a diode opening 84 that exposes the diode region 9. In the interlayer insulating layer 79, an angle θ formed between an inner wall of the diode opening 84 and the first main surface 3 is equal to or greater than 45° and equal to or less than 90°.

[0300] When the angle θ is less than 45°, a thin film portion is formed in the portion of the interlayer insulating layer 79 covering the diode region 9. When a thin film portion is formed in the interlayer insulating layer 79, the emitter terminal electrode 13 faces the first main surface 3 (anode region 62 and / or anode separation electrode layer 66) with the thin film portion of the interlayer insulating layer 79 sandwiched therebetween. In this case, an electric field is concentrated in the thin film portion of the interlayer insulating layer 79, and as a result, there is a possibility that the dielectric breakdown resistance will decrease starting from the thin film portion of the interlayer insulating layer 79.

[0301] Therefore, in this embodiment, the inner wall of the diode opening 84 is formed so that the angle θ is 45° or more (preferably 60° or more), thereby preventing the formation of a thin film portion in the interlayer insulating layer 79. This makes it possible to prevent dielectric breakdown of the interlayer insulating layer 79 caused by undesired electric field concentration, thereby making it possible to prevent a decrease in the dielectric breakdown resistance.

[0302] Moreover, the semiconductor device 1 has a structure in which the p-type impurity concentration of the anode region 62 is lower than the p-type impurity concentration of the body region 45, and the emitter terminal electrode 13 is directly connected to the anode region 62 without a barrier electrode layer. Specifically, the emitter terminal electrode 13 forms an ohmic contact with the anode region 62. This makes it possible to suppress the recovery loss Err while suppressing an increase in the forward voltage VF (see the third embodiment (third plot point P3) in FIG. 13).

[0303] The semiconductor device 1 may have a structure in which the p-type impurity concentration of the anode region 62 is lower than the p-type impurity concentration of the body region 45, and the emitter terminal electrode 13 is electrically connected to the anode region 62 via a barrier electrode layer. In this case, the recovery loss Err can be suppressed (see the second embodiment (second plot point P2) in FIG. 13).

[0304] Figures 20A to 20T are cross-sectional views of a region corresponding to Figure 10, and are cross-sectional views for explaining an example of a manufacturing method of the semiconductor device 1 shown in Figure 1. In the following, the manufacturing process of the IGBT region 8 and the diode region 9 will be explained.

[0305] Referring to FIG. 20A, in manufacturing the semiconductor device 1, first, - A mold semiconductor wafer 162 is prepared. The semiconductor wafer 162 has a first wafer main surface 163 and a second wafer main surface 164. The first wafer main surface 163 and the second wafer main surface 164 of the semiconductor wafer 162 correspond to the first main surface 3 and the second main surface 4 of the semiconductor layer 2, respectively.

[0306] Next, a plurality of device formation regions 165 corresponding to the semiconductor devices 1 are set on the semiconductor wafer 162. Each device formation region 165 includes an active region 6 and an outer region 7. The active region 6 includes an IGBT region 8 and a diode region 9. The same structures are simultaneously formed in the plurality of device formation regions 165. After a predetermined structure is formed in each device formation region 165, the semiconductor wafer 162 is cut along the periphery of each device formation region 165. The structure of one device formation region 165 will be described below.

[0307] Next, referring to FIG. 20B, + A plurality of floating regions 52 of a mold are formed in the IGBT region 8. In this process, first, an ion introduction mask 166 having a predetermined pattern is formed on the first wafer main surface 163. The ion introduction mask 166 has a plurality of openings 166A that expose the regions where the plurality of floating regions 52 are to be formed.

[0308] Next, p-type impurities are introduced into the semiconductor wafer 162 through the ion introduction mask 166. As a result, a plurality of floating regions 52 are formed in the IGBT region 8. Thereafter, the ion introduction mask 166 is removed.

[0309] 20C, a gate trench 39 and a region isolation trench 54 are formed in the IGBT region 8, and an anode isolation trench 64 is formed in the diode region 9. In this step, first, a hard mask 167 having a predetermined pattern is formed on the first wafer main surface 163.

[0310] The hard mask 167 has a plurality of openings 167A that expose regions in which the gate trench 39, the region isolation trench 54, and the anode isolation trench 64 are to be formed. The hard mask 167 may be formed by an oxidation treatment method for the first wafer main surface 163.

[0311] Next, unnecessary portions of the semiconductor wafer 162 are removed by an etching method through the hard mask 167. The etching method may be a wet etching method. As a result, the gate trench 39 and the region isolation trench 54 are formed in the IGBT region 8, and the anode isolation trench 64 is formed in the diode region 9. The hard mask 167 is then removed.

[0312] 20D, the floating regions 52 are diffused into the semiconductor wafer 162. The floating regions 52 are diffused to a depth position that covers the bottom walls of the region isolation trenches 54.

[0313] 20E, the gate insulating layer 40, the region isolation insulating layer 55, the anode isolation insulating layer 65, and the first insulating layer 80 are formed on the first wafer main surface 163. The gate insulating layer 40, the region isolation insulating layer 55, the anode isolation insulating layer 65, and the first insulating layer 80 may be formed by a CVD (Chemical Vapor Deposition) method or an oxidation treatment method (for example, a thermal oxidation treatment method).

[0314] Next, referring to Fig. 20F, a base electrode layer 168 is formed. The base electrode layer 168 becomes a base for the gate wiring 19, the gate electrode layer 41, the gate lead electrode layer 41a, the region isolation electrode layer 56, the isolation lead electrode layer 56a, the anode isolation electrode layer 66, and the anode lead electrode layer 66a. The base electrode layer 168 includes conductive polysilicon. The base electrode layer 168 may be formed by a CVD method.

[0315] 20G, unnecessary portions of the base electrode layer 168 are removed. In this step, first, a mask (not shown) having a predetermined pattern is formed on the base electrode layer 168. The mask covers the regions where the gate wiring 19, the gate extraction electrode layer 41a, the separation extraction electrode layer 56a, and the anode extraction electrode layer 66a are to be formed, and has openings that expose the regions other than these regions.

[0316] Next, unnecessary portions of the base electrode layer 168 are removed by etching through a mask. The etching may be wet etching. The unnecessary portions of the base electrode layer 168 are removed until the first insulating layer 80 is exposed. This forms the gate wiring 19, the gate electrode layer 41, the gate lead electrode layer 41a, the region separation electrode layer 56, the separation lead electrode layer 56a, the anode separation electrode layer 66, and the anode lead electrode layer 66a. The mask is then removed.

[0317] Next, referring to FIG. 20H, +A plurality of carrier storage regions 47 of a mold are formed in the IGBT region 8. In this process, first, an ion introduction mask (not shown) having a predetermined pattern is formed on the first wafer main surface 163. The ion introduction mask has a plurality of openings that expose the regions where the plurality of carrier storage regions 47 are to be formed.

[0318] Next, n-type impurities are introduced into the semiconductor wafer 162 through the ion introduction mask, thereby forming a plurality of carrier storage regions 47 in the IGBT region 8. The ion introduction mask is then removed.

[0319] Next, a plurality of p-type body regions 45 are formed in the IGBT region 8. In this process, first, an ion introduction mask (not shown) having a predetermined pattern is formed on the first wafer main surface 163. The ion introduction mask has a plurality of openings that expose the regions where the plurality of body regions 45 are to be formed.

[0320] Next, p-type impurities are introduced into the semiconductor wafer 162 through the ion introduction mask, thereby forming a plurality of body regions 45 in the IGBT region 8. Thereafter, the ion introduction mask is removed.

[0321] Next, referring to FIG. 20I, - A plurality of p-type anode regions 62 are formed in the diode region 9. The p-type impurity concentration of each anode region 62 is lower than the p-type impurity concentration of each body region 45. In this process, first, an ion introduction mask (not shown) having a predetermined pattern is formed on the first wafer main surface 163. The ion introduction mask has a plurality of openings that expose the regions in which the plurality of anode regions 62 are to be formed.

[0322] Next, p-type impurities are introduced into the semiconductor wafer 162 through the ion introduction mask, thereby forming a plurality of anode regions 62 in the diode region 9. The ion introduction mask is then removed.

[0323] Next, referring to FIG. 20J, + A plurality of emitter regions 46 of a mold are formed in the IGBT region 8. In this process, first, an ion introduction mask (not shown) having a predetermined pattern is formed on the first wafer main surface 163. The ion introduction mask has a plurality of openings that expose the regions where the plurality of emitter regions 46 are to be formed.

[0324] Next, n-type impurities are introduced into the semiconductor wafer 162 through the ion introduction mask, thereby forming a plurality of emitter regions 46 in the IGBT region 8. The ion introduction mask is then removed.

[0325] Next, referring to FIG. 20K, a second insulating layer 81 and a third insulating layer 82 are formed in this order from the first wafer main surface 163 side. The second insulating layer 81 includes an NSG layer. The second insulating layer 81 may be formed by a CVD method. The third insulating layer 82 includes a BPSG layer. The third insulating layer 82 may be formed by a CVD method. In this way, an interlayer insulating layer 79 including the first insulating layer 80, the second insulating layer 81, and the third insulating layer 82 is formed.

[0326] 20L, a plurality of emitter trenches 48 and a plurality of emitter openings 83 are formed in the IGBT region 8. Also in this step, a first opening 86 is formed in the IGBT region 8, and a second opening 87 is formed in the diode region 9.

[0327] In this step, first, a mask 169 having a predetermined pattern is formed on the interlayer insulating layer 79. The mask 169 has a plurality of openings 169A that expose the regions where the emitter trench 48, the emitter opening 83, the first opening 86, and the second opening 87 are to be formed.

[0328] Next, unnecessary portions of the interlayer insulating layer 79 are removed by etching through the mask 169. The etching may be a wet etching method. In this step, unnecessary portions of the third insulating layer 82, unnecessary portions of the second insulating layer 81, and unnecessary portions of the first insulating layer 80 are removed in this order by etching.

[0329] In this step, after the first insulating layer 80 is removed, a portion of the first wafer main surface 163 exposed from the mask 169 is further removed. This forms the emitter trench 48, the emitter opening 83, the first opening 86, and the second opening 87. Thereafter, the mask 169 is removed.

[0330] Next, referring to FIG. 20M, + A plurality of contact regions 49 of a mold are formed in the IGBT region 8. In this process, first, an ion introduction mask (not shown) having a predetermined pattern is formed on the interlayer insulating layer 79. The ion introduction mask has a plurality of openings that expose the plurality of emitter trenches 48 (emitter openings 83) as regions where the plurality of contact regions 49 are to be formed.

[0331] Next, p-type impurities are introduced into the semiconductor wafer 162 through the ion introduction mask, thereby forming a plurality of contact regions 49 in the IGBT region 8. The ion introduction mask is then removed.

[0332] 20N, a plug base electrode layer 170 is formed on the interlayer insulating layer 79. The plug base electrode layer 170 serves as a base for the emitter plug electrode 91, the first plug electrode 94, and the second plug electrode 95. This step includes a step of forming a barrier electrode layer 92 and a main electrode layer 93 in this order from the interlayer insulating layer 79 side.

[0333] The step of forming the barrier electrode layer 92 includes a step of forming a titanium layer and a titanium nitride layer in this order from the interlayer insulating layer 79 side. The titanium layer and the titanium nitride layer may each be formed by a sputtering method. The barrier electrode layer 92 may have a single-layer structure including a titanium layer or a titanium nitride layer. The main electrode layer 93 includes tungsten. The main electrode layer 93 may be formed by a sputtering method. As a result, the plug base electrode layer 170 is formed on the interlayer insulating layer 79.

[0334] 20O, the unnecessary portion of the plug base electrode layer 170 is removed. The unnecessary portion of the plug base electrode layer 170 may be removed by an etching method. The unnecessary portion of the plug base electrode layer 170 is removed until the interlayer insulating layer 79 is exposed.

[0335] Specifically, the unnecessary portion of the plug base electrode layer 170 is removed until the emitter opening 83 is exposed and the plug base electrode layer 170 is embedded in the emitter trench 48, the first opening 86, and the second opening 87. As a result, the emitter plug electrode 91, the first plug electrode 94, and the second plug electrode 95 are formed.

[0336] 20P, a plurality of diode openings 84 are formed in the diode region 9. In this step, first, a mask 171 having a predetermined pattern is formed on the interlayer insulating layer 79. The mask 171 has a plurality of openings 171A that expose regions in which the plurality of diode openings 84 are to be formed.

[0337] Next, unnecessary portions of the interlayer insulating layer 79 are removed by etching through the mask 171. The etching is preferably anisotropic etching. The anisotropic etching may be dry etching (specifically, RIE (Reactive Ion Etching)).

[0338] In this process, unnecessary portions of the first insulating layer 80, the second insulating layer 81, and the third insulating layer 82 are sequentially removed by anisotropic etching, thereby forming a plurality of diode openings 84. Also, recesses 67 are formed in the anode isolation trenches 64. Then, the mask 171 is removed.

[0339] In the process of forming the diode opening 84, the processing conditions of the anisotropic etching method are adjusted so that the angle θ between the inner wall of the diode opening 84 in the interlayer insulating layer 79 and the first wafer main surface 163 is greater than or equal to 45° and less than or equal to 90°.

[0340] The angle θ may be 45° to 50°, 50° to 55°, 55° to 60°, 60° to 65°, 65° to 70°, 70° to 75°, 75° to 80°, 80° to 85°, or 85° to 90°. The angle θ is preferably 60° to 90°.

[0341] It is also possible to employ an isotropic etching method (for example, a wet etching method) in the process of forming the diode opening 84. In this case, however, the interlayer insulating layer 79 is also removed in the lateral direction parallel to the first wafer main surface 163, and therefore the angle θ of the inner wall may become less than 45° due to over-etching.

[0342] In particular, in the case of isotropic etching, since advanced processing conditions are required to control the amount of removal of the interlayer insulating layer 79, it is difficult to appropriately adjust the angle θ. Even if the interlayer insulating layer 79 is removed according to predetermined processing conditions, the desired angle θ may not be achieved due to over-etching. Therefore, in this process, the interlayer insulating layer 79 is removed by anisotropic etching. This allows the angle θ to be appropriately adjusted.

[0343] Next, referring to FIG. 20Q, the emitter terminal electrode 13, the gate terminal electrode 14, the first sense terminal electrode 15, the second sense terminal electrode 16, the current detection terminal electrode 17 and the release terminal electrode 18 are formed on the first wafer main surface 163.

[0344] In this step, first, a base terminal electrode layer is formed to become the base of the multiple terminals 13 to 18. The base terminal electrode layer contains an aluminum-silicon-copper alloy. The base terminal electrode layer may be formed by a sputtering method.

[0345] Next, a mask (not shown) having a predetermined pattern is formed on the base terminal electrode layer. The mask covers the regions where the multiple terminals 13 to 18 are to be formed, and has openings that expose the other regions. Next, unnecessary portions of the base terminal electrode layer are removed by etching through the mask. The etching method may be wet etching. In this way, the multiple terminals 13 to 18 are formed. Thereafter, the mask is removed.

[0346] 20R, the semiconductor wafer 162 is thinned to a predetermined thickness. The thinning step includes a step of thinning the semiconductor wafer 162 by a grinding method on the second wafer main surface 164. The grinding method may be a chemical mechanical polishing (CMP) method.

[0347] The thinning step may include a step of thinning the semiconductor wafer 162 by etching the second wafer main surface 164 instead of grinding. The etching method may be wet etching.

[0348] The thinning step may include a step of thinning the semiconductor wafer 162 by grinding and etching the second wafer main surface 164. The semiconductor wafer 162 may be thinned by performing the grinding method and the etching method in this order. The semiconductor wafer 162 may be thinned by performing the etching method and the grinding method in this order.

[0349] When only the grinding method is performed, the second wafer main surface 164 of the semiconductor wafer 162 becomes a ground surface having grinding marks. In this case, the second main surface 4 of the semiconductor layer 2 becomes a ground surface having grinding marks. The thinning process of the semiconductor wafer 162 is performed as necessary and may be omitted.

[0350] 20S, an n-type buffer layer 33 is formed in a surface layer portion of the second wafer main surface 164. In this process, n-type impurities are introduced into the entire area of ​​the second wafer main surface 164 of the semiconductor wafer 162. As a result, the n-type buffer layer 33 is formed.

[0351] Next, p-type collector region 34 is formed in the surface layer portion of second wafer main surface 164. In this process, first, an ion introduction mask (not shown) having a predetermined pattern is formed on second wafer main surface 164. The ion introduction mask has openings that expose the regions where collector region 34 is to be formed. Next, p-type impurities are introduced into second wafer main surface 164 through the ion introduction mask. This forms collector region 34. Thereafter, the ion introduction mask is removed.

[0352] Next, n + A plurality of cathode regions 61 of a mold are formed in a surface layer portion of the second wafer main surface 164. In this process, first, an ion introduction mask (not shown) having a predetermined pattern is formed on the second wafer main surface 164. The ion introduction mask has a plurality of openings that expose the regions in which the plurality of cathode regions 61 are to be formed. Next, n-type impurities are introduced into the second wafer main surface 164 through the ion introduction mask. This forms a plurality of cathode regions 61. Thereafter, the ion introduction mask is removed.

[0353] Next, referring to FIG. 20T, the collector terminal electrode 32 is formed on the second wafer main surface 164. The collector terminal electrode 32 may include at least one of a Ti layer, a Ni layer, an Au layer, an Ag layer, and an Al layer. The collector terminal electrode 32 may be formed by a sputtering method. Thereafter, the semiconductor wafer 162 is cut along the periphery of each device formation region 165 to cut out the semiconductor device 1. Through the steps including those described above, the semiconductor device 1 is manufactured.

[0354] After the thinning process of the semiconductor wafer 162, and prior to the formation process of the collector terminal electrode 32, an annealing process may be performed on the second wafer main surface 164. The annealing process may be a laser annealing process. In this case, a Si amorphous layer may be formed in the surface layer portion of the second wafer main surface 164. Also, in this case, a lattice defect region including lattice defects may be formed in the surface layer portion of the second wafer main surface 164.

[0355] A Si amorphous layer may be formed on a surface layer portion of the second main surface 4 of the semiconductor layer 2 cut out from the semiconductor wafer 162. A lattice defect region including lattice defects may be formed on a surface layer portion of the second main surface 4 of the semiconductor layer 2. With such a structure, it is possible to improve the ohmic properties of the collector terminal electrode 32 with respect to the second main surface 4 (collector region 34 and cathode region 61).

[0356] The order of the steps of forming the carrier storage region 47, the body region 45, the anode region 62, and the emitter region 46 may be arbitrary and is not limited to the order of the steps described above.

[0357] However, from the viewpoint of suppressing undesired diffusion caused by heating, it is preferable to form the regions in the order of depth introduced into the semiconductor wafer 162. In other words, it is preferable to form the carrier storage region 47, which is formed in the deepest region, first, and the emitter region 46, which is formed in the shallowest region, last. In this case, undesired diffusion of the body region 45, the emitter region 46, the carrier storage region 47, and the anode region 62 can be suppressed.

[0358] The order of the steps of forming buffer layer 33, cathode region 61, and collector region 34 may be arbitrary and is not limited to the order of the steps described above. The steps of thinning semiconductor wafer 162, forming buffer layer 33, cathode region 61, and collector region 34 may be performed at any timing after the step of preparing semiconductor wafer 162 and before the step of forming multiple terminals 13-18.

[0359] For example, the steps of thinning the semiconductor wafer 162, forming the buffer layer 33, forming the cathode region 61, and forming the collector region 34 may be performed prior to the step of forming the floating region 52.

[0360] However, from the viewpoint of suppressing undesired diffusion caused by heating, it is preferable that the process of thinning the semiconductor wafer 162, the process of forming the buffer layer 33, the process of forming the cathode region 61, and the process of forming the collector region 34 are performed after the process of forming the body region 45, the process of forming the emitter region 46, the process of forming the carrier storage region 47, and the process of forming the anode region 62.

[0361] Fig. 21 is an enlarged view of a region corresponding to Fig. 5, showing a semiconductor device 181 according to a second embodiment of the present invention. Fig. 22 is a cross-sectional view of a region corresponding to Fig. 10, for explaining the structure of the semiconductor device 181 shown in Fig. 21.

[0362] In the following, the same reference numerals will be used to denote structures corresponding to those described with respect to the semiconductor device 1, and descriptions thereof will be omitted. In Fig. 21, the region in which the collector region 34 is formed is indicated by dotted hatching.

[0363] 21 and 22, the collector region 34 in this embodiment includes an extension region 182. The extension region 182 is extended to the periphery of the diode region 9 across the boundary between the IGBT region 8 and the diode region 9. The extension region 182 is extended from the IGBT region 8 to the diode region 9 along the first direction X.

[0364] In this embodiment, the lead-out region 182 is formed in a band shape along the periphery of the diode region 9 in a plan view. Specifically, the lead-out region 182 is formed in a ring shape (endless in this embodiment) surrounding the inner region of the diode region 9 in a plan view. As a result, the lead-out region 182 is led out from the IGBT region 8 to the diode region 9 along the first direction X and the second direction Y.

[0365] The lead-out region 182 overlaps the diode region 9 with a predetermined overlap width W in a plan view. The start point of the overlap width W is set at the boundary between the IGBT region 8 and the diode region 9. In this embodiment, the start point of the overlap width W is set at the center of the anode isolation trench 64 that is closest to the IGBT region 8 and in contact with the anode region 62. The end point of the overlap width W is set at the boundary between the lead-out region 182 and the cathode region 61.

[0366] The ratio W / WD of the overlap width W to the width WD of the diode region 9 may be 0.001 or more and 0.5 or less. The ratio W / WD may be 0.001 or more and 0.01 or less, 0.01 or more and 0.05 or less, 0.05 or more and 0.1 or less, 0.1 or more and 0.15 or less, 0.15 or more and 0.2 or less, 0.2 or more and 0.25 or less, 0.25 or more and 0.3 or less, 0.35 or more and 0.4 or less, 0.4 or more and 0.45 or less, or 0.45 or more and 0.5 or less.

[0367] The overlap width W may be 1 μm or more and 200 μm or less. The overlap width W may be 1 μm or more and 50 μm or less, 50 μm or more and 100 μm or less, 100 μm or more and 150 μm or less, or 150 μm or more and 200 μm or less.

[0368] The overlap width W may be 1 μm to 20 μm, 20 μm to 40 μm, 40 μm to 60 μm, 60 μm to 80 μm, 80 μm to 100 μm, 100 μm to 120 μm, 120 μm to 140 μm, 140 μm to 160 μm, 160 μm to 180 μm, or 180 μm to 200 μm. The overlap width W is preferably 10 μm to 150 μm.

[0369] The lead-out region 182 may face one or a plurality of anode regions 62 with respect to the normal direction Z. The lead-out region 182 may face 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, or 20 anode regions 62. The lead-out region 182 preferably faces 1 to 10 anode regions 62.

[0370] The lead-out region 182 may face one or a plurality of anode separation trenches 64 with respect to the normal direction Z. The lead-out region 182 may face 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, or 20 anode separation trenches 64. The lead-out region 182 is preferably faced with 1 to 10 anode separation trenches 64.

[0371] Figure 23 shows a graph of the reverse recovery characteristics of a pn junction diode, investigated by simulation. In this figure, the vertical axis is the current density [A cm -3 ], and the horizontal axis represents time [μs].

[0372] Fig. 23 shows a first characteristic α, a second characteristic β, and a third characteristic γ. The first characteristic α shows the reverse recovery current characteristic of a pn junction diode when the overlap width W is 0 μm. The second characteristic β shows the reverse recovery current characteristic of a pn junction diode when the overlap width W is 100 μm. The third characteristic γ shows the reverse recovery current characteristic of a pn junction diode when the overlap width W is 150 μm.

[0373] With reference to the first characteristic α, the second characteristic β, and the third characteristic γ, it was found that the reverse recovery current of the pn junction diode is reduced and the reverse recovery time of the pn junction diode is shortened by increasing the overlap width W. In other words, it was found that the recovery loss Err can be reduced by increasing the overlap width W. However, if the overlap width W is made too large, the cathode region 61 disappears and the diode characteristics are lost, so the overlap width W is preferably 1 μm or more and 200 μm or less.

[0374] 24 is a perspective view showing one embodiment of a semiconductor module 201. In the semiconductor module 201, one or more semiconductor chips 202 are incorporated.

[0375] In this embodiment, the semiconductor module 201 has a structure incorporating two semiconductor chips 202. For convenience, the two semiconductor chips 202 will be referred to below as a first semiconductor chip 202A and a second semiconductor chip 202B, respectively.

[0376] The semiconductor device 1 according to the first embodiment or the semiconductor device 181 according to the second embodiment is applied to the first semiconductor chip 202A. The semiconductor device 1 according to the first embodiment or the semiconductor device 181 according to the second embodiment is applied to the second semiconductor chip 202B.

[0377] 24, semiconductor module 201 includes a housing 203 that houses first semiconductor chip 202A and second semiconductor chip 202B. Housing 203 includes a resin case 204 and a support substrate 205. Support substrate 205 is a substrate that supports first semiconductor chip 202A and second semiconductor chip 202B.

[0378] Resin case 204 includes a bottom wall 206 and side walls 207A, 207B, 207C, and 207D. Bottom wall 206 is formed in a quadrangular shape (rectangular shape in this embodiment) in a plan view seen from the normal direction thereof.

[0379] A through hole 208 is formed in the bottom wall 206. The through hole 208 is formed in a region spaced apart from the periphery toward the inner region of the bottom wall 206. In this embodiment, the through hole 208 is formed in a quadrangular shape (rectangular shape in this embodiment) in plan view.

[0380] The side walls 207A to 207D stand from the periphery of the bottom wall 206 toward the opposite side to the bottom wall 206. The side walls 207A to 207D define an opening 209 on the opposite side to the bottom wall 206. The side walls 207A to 207D define an internal space 210 between themselves and the bottom wall 206.

[0381] Side wall 207A and side wall 207C extend along the short side direction of bottom wall 206. Side wall 207A and side wall 207C face each other in the long side direction of bottom wall 206. Side wall 207B and side wall 207D extend along the long side direction of bottom wall 206. Side wall 207B and side wall 207D face each other in the short side direction of bottom wall 206.

[0382] Bolt insertion holes 211, 212, 213, and 214 are formed at four corners of the internal space 210. The internal space 210 is closed by a cover member (not shown). The cover member is fastened to the bolt insertion holes 211, 212, 213, and 214 by bolts.

[0383] Resin case 204 includes a plurality of terminal support portions 215, 216, 217, and 218. In this embodiment, terminal support portions 215-218 include a first terminal support portion 215, a second terminal support portion 216, a third terminal support portion 217, and a fourth terminal support portion 218.

[0384] The first terminal support portion 215 and the second terminal support portion 216 are attached to the outer wall of the side wall 207A. In this embodiment, the first terminal support portion 215 and the second terminal support portion 216 are integrally formed with the outer wall of the side wall 207A.

[0385] The first terminal support portion 215 and the second terminal support portion 216 are formed at an interval from each other in the short side direction. The first terminal support portion 215 and the second terminal support portion 216 are each formed in a block shape. The first terminal support portion 215 and the second terminal support portion 216 each protrude outward in the longitudinal direction from the outer wall of the side wall 207A.

[0386] The third terminal support portion 217 and the fourth terminal support portion 218 are attached to the side wall 207C. In this embodiment, the third terminal support portion 217 and the fourth terminal support portion 218 are integrally formed with the outer wall of the side wall 207C.

[0387] The third terminal support portion 217 and the fourth terminal support portion 218 are formed at an interval from each other in the short side direction. The third terminal support portion 217 and the fourth terminal support portion 218 are each formed in a block shape. The third terminal support portion 217 and the fourth terminal support portion 218 each protrude outward in the longitudinal direction from the side wall 207C.

[0388] First terminal support portion 215, second terminal support portion 216, third terminal support portion 217, and fourth terminal support portion 218 each have a support wall 219. Each support wall 219 is located in a region closer to opening 209 than bottom wall 206. Each support wall 219 is formed in a quadrangular shape in a plan view.

[0389] A first bolt insertion hole 221 is formed in the region between first terminal support portion 215 and second terminal support portion 216. A second bolt insertion hole 222 is formed in the region between third terminal support portion 217 and fourth terminal support portion 218.

[0390] Support substrate 205 includes heat sink 225, insulating material 226, and circuit section 227. Support substrate 205 is attached to the outer surface of resin case 204 such that circuit section 227 is exposed from through hole 208 in bottom wall 206. Support substrate 205 may be attached to the outer surface of resin case 204 by adhering heat sink 225 to the outer surface of resin case 204.

[0391] The heat sink 225 may be a metal plate. The heat sink 225 may be an insulating plate coated with a metal film. The heat sink 225 is formed in a quadrangular shape (rectangular shape in this embodiment) in a plan view seen from the normal direction.

[0392] The insulating material 226 is formed on the heat sink 225. The insulating material 226 may be a mounting substrate including an insulating material. The insulating material 226 may be an insulating film formed on the heat sink 225 in a film shape.

[0393] Circuit section 227 is formed on heat sink 225 via insulating material 226. Circuit section 227 includes a plurality of wirings 231, 232, 233, first semiconductor chip 202A, and second semiconductor chip 202B. In this embodiment, wirings 231 to 233 include first collector wiring 231, second collector wiring 232, and emitter wiring 233.

[0394] The first collector wiring 231 is formed in a plate or film shape. The first collector wiring 231 is formed in a quadrangular shape in a plan view. The first collector wiring 231 is disposed in an area on one side in the longitudinal direction (sidewall 207A side) and one side in the lateral direction (sidewall 207D side) of the heat sink 225.

[0395] The second collector wiring 232 is formed in a plate or film shape. The second collector wiring 232 is formed in a quadrangular shape in a plan view. The second collector wiring 232 is spaced apart from the first collector wiring 231 and is disposed in the heat sink 225 in the other longitudinal side (side wall 207C side) and one lateral side (side wall 207D side).

[0396] The emitter wiring 233 is formed in a plate or film shape. The emitter wiring 233 is formed in a quadrangular shape in a plan view. In this embodiment, the emitter wiring 233 is formed in a rectangular shape extending along the longitudinal direction of the heat sink 225.

[0397] The emitter wiring 233 is spaced apart from the first collector wiring 231 and the second collector wiring 232 and is disposed in a region on the other short side of the heat sink 225 (the side of the sidewall 207B).

[0398] The first semiconductor chip 202A is disposed on the first collector wiring 231 with the collector terminal electrode 32 facing the heat sink. The collector terminal electrode 32 of the first semiconductor chip 202A is joined to the first collector wiring 231 via a conductive bonding material.

[0399] As a result, the collector terminal electrode 32 of the first semiconductor chip 202A is electrically connected to the first collector wiring 231. The conductive bonding material may include solder or a conductive paste.

[0400] The second semiconductor chip 202B is disposed on the second collector wiring 232 with the collector terminal electrode 32 facing the heat sink. The collector terminal electrode 32 of the second semiconductor chip 202B is joined to the second collector wiring 232 via a conductive bonding material.

[0401] As a result, the collector terminal electrode 32 of the second semiconductor chip 202B is electrically connected to the second collector wiring 232. The conductive bonding material may include solder or a conductive paste.

[0402] The semiconductor module 201 includes a plurality of terminals 234, 235, 236, and 237. The plurality of terminals 234 to 237 include a collector terminal 234, a first emitter terminal 235, a common terminal 236, and a second emitter terminal 237.

[0403] The collector terminal 234 is disposed on the first terminal support portion 215. The collector terminal 234 is electrically connected to the first collector wiring 231. The collector terminal 234 includes a first region 238 and a second region 239. The first region 238 of the collector terminal 234 is located outside the internal space 210. The second region 239 of the collector terminal 234 is located within the internal space 210.

[0404] A first region 238 of the collector terminal 234 is supported by a support wall 219 of the first terminal support portion 215. A second region 239 of the collector terminal 234 is drawn out from the first region 238 into the internal space 210 through the side wall 207A. The second region 239 of the collector terminal 234 is electrically connected to the first collector wiring 231.

[0405] The first emitter terminal 235 is disposed on the second terminal support portion 216. The first emitter terminal 235 is electrically connected to the emitter wiring 233. The first emitter terminal 235 includes a first region 240 and a second region 241. The first region 240 of the first emitter terminal 235 is located outside the internal space 210. The second region 241 of the first emitter terminal 235 is located within the internal space 210.

[0406] The first region 240 of the first emitter terminal 235 is supported by the support wall 219 of the second terminal support portion 216. The second region 241 of the first emitter terminal 235 is drawn out from the first region 240 into the internal space 210 through the side wall 207A. The second region 241 of the first emitter terminal 235 is electrically connected to the emitter wiring 233.

[0407] The common terminal 236 is disposed on the third terminal support portion 217. The common terminal 236 is electrically connected to the second collector wiring 232. The common terminal 236 includes a first region 242 and a second region 243. The first region 242 of the common terminal 236 is located outside the internal space 210. The second region 243 of the common terminal 236 is located within the internal space 210.

[0408] The first region 242 of the common terminal 236 is supported by the support wall 219 of the second terminal support portion 216. The second region 243 of the common terminal 236 is drawn out from the first region 240 into the internal space 210 through the side wall 207C. The second region 243 of the common terminal 236 is electrically connected to the second collector wiring 232.

[0409] The second emitter terminal 237 is disposed on the fourth terminal support portion 218. The second emitter terminal 237 is electrically connected to the emitter wiring 233. The second emitter terminal 237 includes a first region 244 and a second region 245. The first region 244 of the second emitter terminal 237 is located outside the internal space 210. The second region 245 of the second emitter terminal 237 is located within the internal space 210.

[0410] The first region 244 of the second emitter terminal 237 is supported by the support wall 219 of the fourth terminal support portion 218. The second region 245 of the second emitter terminal 237 is drawn out from the first region 244 through the side wall 207C into the internal space 210. The second region 245 of the second emitter terminal 237 is electrically connected to the emitter wiring 233.

[0411] The semiconductor module 201 includes a plurality of (six in this embodiment) sidewall terminals 246A to 246H. The sidewall terminals 246A to 246H are arranged in the internal space 210 at intervals along the sidewall 207D.

[0412] Each of the side wall terminals 246A to 246H includes an internal connection portion 247 and an external connection portion 248. The internal connection portion 247 is disposed on the bottom wall 206. The external connection portion 248 extends in a line from the internal connection portion 247 along the side wall 207D and is drawn out to the outside of the internal space 210.

[0413] The multiple sidewall terminals 246A to 246H include three sidewall terminals 246A to 246D for the first semiconductor chip 202A and three sidewall terminals 246E to 246H for the second semiconductor chip 202B.

[0414] The sidewall terminals 246A to 246D face the first collector wiring 231 along the short side direction. The sidewall terminal 246A is formed as a gate terminal connected to the gate terminal electrode 14 of the first semiconductor chip 202A.

[0415] The sidewall terminals 246B to 246D are formed as terminals connected to the first sense terminal electrode 15, the second sense terminal electrode 16, and the current detection terminal electrode 17 of the first semiconductor chip 202A, respectively. At least one of the sidewall terminals 246B to 246D may be an open terminal.

[0416] The sidewall terminals 246E to 246H face the second collector wiring 232 along the short side direction. The sidewall terminal 246E is formed as a gate terminal connected to the gate terminal electrode 14 of the second semiconductor chip 202B.

[0417] The sidewall terminals 246F to 246H are formed as terminals connected to the first sense terminal electrode 15, the second sense terminal electrode 16, and the current detection terminal electrode 17 of the second semiconductor chip 202B, respectively. At least one of the sidewall terminals 246F to 246H may be an open terminal.

[0418] The semiconductor module 201 includes a plurality of conductive wires 249A-249J. Each of the plurality of conductive wires 249A-249J may include at least one of gold, silver, copper, and aluminum. Each of the conductive wires 249A-249J may include a bonding wire. Each of the conductive wires 249A-249J may include a conductive plate.

[0419] The multiple conductive wires 249A-249J include a first conductive wire 249A, a second conductive wire 249B, a third conductive wire 249C, a fourth conductive wire 249D, a fifth conductive wire 249E, a sixth conductive wire 249F, a seventh conductive wire 249G, an eighth conductive wire 249H, a ninth conductive wire 249I, and a tenth conductive wire 249J.

[0420] The first conductive wire 249A connects the collector terminal 234 and the first collector wiring 231. The second conductive wire 249B connects the first emitter terminal 235 and the emitter wiring 233. The third conductive wire 249C connects the common terminal 236 and the second collector wiring 232.

[0421] The fourth conducting wire 249D connects the second emitter terminal 237 and the emitter wiring 233. The fifth conducting wire 249E connects the emitter terminal electrode 13 of the first semiconductor chip 202A and the second collector wiring 232. The sixth conducting wire 249F connects the emitter terminal electrode 13 of the second semiconductor chip 202B and the emitter wiring 233.

[0422] The seventh conducting wire 249G connects the gate terminal electrode 14 of the first semiconductor chip 202A and the sidewall terminal 246A. The eighth conducting wire 249H connects the gate terminal electrode 14 of the second semiconductor chip 202B and the sidewall terminal 246E.

[0423] The ninth conducting wire 249I connects the first sense terminal electrode 15, the second sense terminal electrode 16 and the current detection terminal electrode 17 of the first semiconductor chip 202A to the sidewall terminals 246B to 246D.

[0424] The tenth conducting wire 249J connects the first sense terminal electrode 15, the second sense terminal electrode 16 and the current detection terminal electrode 17 of the second semiconductor chip 202B to the sidewall terminals 246F to 246H.

[0425] FIG. 25 is a circuit diagram showing the electrical structure of the semiconductor module 201 shown in FIG.

[0426] 25, a semiconductor module 201 includes a half-bridge circuit 250. The half-bridge circuit 250 includes a first semiconductor chip 202A and a second semiconductor chip 202B.

[0427] The first semiconductor chip 202A constitutes a high-voltage side arm of the half-bridge circuit 250. The second semiconductor chip 202B constitutes a low-voltage side arm of the half-bridge circuit 250.

[0428] A gate terminal (sidewall terminal 246A) is connected to the gate terminal electrode 14 of the first semiconductor chip 202A. A collector terminal 234 is connected to the collector terminal electrode 32 of the first semiconductor chip 202A.

[0429] A collector terminal electrode 32 of the second semiconductor chip 202B is connected to the emitter terminal electrode 13 of the first semiconductor chip 202A. A common terminal 236 is connected to the connection portion of the emitter terminal electrode 13 of the first semiconductor chip 202A and the collector terminal electrode 32 of the second semiconductor chip 202B.

[0430] A gate terminal (sidewall terminal 246D) is connected to the gate terminal electrode 14 of the second semiconductor chip 202B. A first emitter terminal 235 (second emitter terminal 237) is connected to the emitter terminal electrode 13 of the second semiconductor chip 202B.

[0431] A gate driver IC or the like may be connected to the gate terminal electrode 14 of the first semiconductor chip 202A via a gate terminal (sidewall terminal 246A). A gate driver IC or the like may be connected to the gate terminal electrode 14 of the second semiconductor chip 202B via a gate terminal (sidewall terminal 246D).

[0432] The semiconductor module 201 may be an inverter module that drives any one of the U phase, V phase, and W phase in a three-phase motor having U phase, V phase, and W phase. An inverter device that drives the three-phase motor may be configured by three semiconductor modules 201 corresponding to the U phase, V phase, and W phase of the three-phase motor.

[0433] In this case, a DC power supply is connected to the collector terminal 234 and the first emitter terminal 235 (second emitter terminal 237) of each semiconductor module 201. Also, any one of the U-phase, V-phase, and W-phase of a three-phase motor is connected to the common terminal 236 of each semiconductor module 201 as a load.

[0434] In the inverter device, the first semiconductor chip 202A and the second semiconductor chip 202B are driven and controlled with a predetermined switching pattern, whereby the DC voltage is converted into a three-phase AC voltage, and the three-phase motor is driven with a sine wave.

[0435] The present invention may be embodied in other forms.

[0436] In each of the above-described embodiments, the semiconductor layer 2 is - Instead of the p-type semiconductor substrate 31, a p-type semiconductor substrate and an n-type semiconductor substrate formed on the semiconductor substrate are used. - In this case, the p-type semiconductor substrate corresponds to the collector region 34. - The epitaxial layer of the type corresponds to the drift region 30 .

[0437] The p-type semiconductor substrate may be made of silicon. -The mold epitaxial layer may be made of silicon. - The epitaxial layer is formed by epitaxially growing silicon from the main surface of a p-type semiconductor substrate.

[0438] In each of the above-described embodiments, a structure in which the conductivity type of each semiconductor portion is inverted may be adopted, that is, a p-type portion may be formed as an n-type, and an n-type portion may be formed as a p-type.

[0439] In a semiconductor device including an IGBT region and a diode region, there is a problem that the forward voltage VF of the diode varies before and after application of a bias voltage to the IGBT. This is because the amount of carriers flowing from the IGBT region to the diode region varies before and after application of a bias voltage to the IGBT.

[0440] To solve this problem, it is possible to form the diode region in only one place. This limits the path through which carriers can flow, suppressing fluctuations in the diode's forward voltage VF. However, in this case, the breakdown resistance decreases due to current concentration (overcurrent) in the diode region.

[0441] Examples of features extracted from this specification and the drawings are shown below. The following item provides a semiconductor device that can improve the breakdown voltage while suppressing the fluctuation of the forward voltage VF of the diode before and after application of a bias voltage to the IGBT.

[0442] [A1] A semiconductor device including: a semiconductor layer including a first main surface on one side and a second main surface on the other side; a drift region of a first conductivity type formed in the semiconductor layer; a diode region including a first impurity region of a second conductivity type formed in a surface layer portion of the first main surface and a second impurity region of the first conductivity type formed in a surface layer portion of the second main surface; a FET structure including a body region of the second conductivity type formed in the first main surface, an emitter region of the first conductivity type formed in a surface layer portion of the body region, and a gate electrode layer facing the body region and the emitter region via a gate insulating layer; and an IGBT region including a collector region of the second conductivity type formed in the surface layer portion of the second main surface and having a pull-out region pulled out to the diode region.

[0443] According to this semiconductor device, during reverse recovery operation of the diode, the carrier density in the vicinity of the boundary between the IGBT region and the diode region can be reduced. This makes it possible to suppress the retention of carriers in the vicinity of the boundary between the IGBT region and the diode region, thereby suppressing the reverse recovery current. As a result, it is possible to reduce recovery loss.

[0444] [A2] The semiconductor device according to A1, wherein the drawn-out region faces the first impurity region in a normal direction of the first main surface.

[0445] [A3] The semiconductor device according to A1, wherein the diode region includes a plurality of the first impurity regions formed at intervals, and the extraction region faces at least one of the plurality of first impurity regions in a normal direction of the first main surface.

[0446] [A4] The semiconductor device according to any one of A1 to A3, wherein the diode region includes a trench in the first main surface that defines the first impurity region, and the drawn-out region faces the trench in a direction normal to the first main surface.

[0447] [A5] The semiconductor device according to A4, wherein the diode region includes a plurality of the trenches, and the drawn-out region faces at least one of the plurality of trenches in a normal direction of the first main surface.

[0448] [A6] The semiconductor device according to any one of A1 to A5, wherein an overlap width of the drawn region with respect to the diode region is not less than 1 μm and not more than 200 μm in plan view.

[0449] [A7] The semiconductor layer includes an active region, a plurality of the diode regions are formed in the active region, and a plurality of the IGBT regions are formed in the active region, the total length of the plurality of the diode regions and the boundary lines between the plurality of the IGBT regions is L, the total area of ​​the plurality of the diode regions is SD, and the dispersion degree of the plurality of the diode regions with respect to the active region is Log e (L 2 The semiconductor device according to any one of A1 to A6, wherein the dispersity is 2 or more and 15 or less when defined by the formula: (a) / SD.

[0450] [A8] The semiconductor device according to any one of A1 to A7, further including: an insulating layer covering the IGBT region on the first main surface, having a diode opening exposing the diode region, wherein an angle formed between an inner wall of the diode opening and the first main surface within a covering portion covering the first main surface is 45° or more and 90° or less; and a main surface electrode extending into the diode opening from above the insulating layer and electrically connected to the diode region.

[0451] [A9] The semiconductor device according to any one of A1 to A7, further including: an insulating layer formed on the first main surface and having a diode opening exposing the diode region; and a main surface electrode directly connected to the first impurity region within the diode opening.

[0452] [A10] The semiconductor device according to A9, wherein the first impurity region has a second-conductivity-type impurity concentration that is less than a second-conductivity-type impurity concentration of the body region.

[0453] [A11] The semiconductor device according to A9 or A10, wherein an angle formed between an inner wall of the diode opening in the insulating layer and the first main surface is equal to or greater than 45° and equal to or less than 90°.

[0454] [B1] A semiconductor device including: a semiconductor layer having a first main surface on one side and a second main surface on the other side; an IGBT region formed in the semiconductor layer; a diode region formed in the semiconductor layer adjacent to the IGBT region; an insulating layer covering the IGBT region on the first main surface and having a diode opening exposing the diode region, wherein an angle formed by an inner wall of the diode opening and the first main surface within a covering portion covering the first main surface is between 45° and 90°; and a main surface electrode extending into the diode opening from above the insulating layer and electrically connected to the diode region.

[0455] When the angle θ of the inner wall of the diode opening is less than 45°, a thin film portion is formed in the insulating layer in a portion covering the diode region. When a thin film portion is formed in the insulating layer, the principal surface electrode faces the first principal surface with the thin film portion of the insulating layer sandwiched therebetween. In this case, an electric field is concentrated in the thin film portion of the insulating layer, and as a result, the dielectric breakdown resistance may decrease starting from the thin film portion of the insulating layer.

[0456] Therefore, in this semiconductor device, the inner wall of the diode opening is formed so that the angle θ of the inner wall of the diode opening is 45° or more and 90° or less, thereby preventing the formation of a thin film portion in the insulating layer, thereby preventing a decrease in the dielectric breakdown resistance caused by undesired electric field concentration.

[0457] [B2] The semiconductor device according to B1, further comprising a drift region of a first conductivity type formed in the semiconductor layer.

[0458] [B3] The semiconductor device according to B2, wherein the diode region includes a first impurity region of a second conductivity type formed in a surface layer portion of the first main surface, and a second impurity region of the first conductivity type formed in a surface layer portion of the second main surface.

[0459] [B4] The semiconductor device according to B3, wherein the insulating layer includes a portion covering the first impurity region.

[0460] [B5] The semiconductor device according to B3 or B4, wherein the diode region includes a diode region isolation structure that partitions the first impurity region in the first main surface.

[0461] [B6] The semiconductor device according to B5, wherein the insulating layer includes a portion covering the diode region isolation structure.

[0462] [B7] The semiconductor device according to B5 or B6, wherein the diode region isolation structure includes a trench formed in the first main surface.

[0463] [B8] A semiconductor device according to any one of B2 to B7, wherein the IGBT region includes a FET structure including a body region of a second conductivity type formed on the first main surface, an emitter region of a first conductivity type formed in a surface layer portion of the body region, and a gate electrode layer facing the body region and the emitter region via a gate insulating layer, and a collector region of the second conductivity type formed in a surface layer portion of the second main surface.

[0464] [B9] The semiconductor device according to B8, further including a plug electrode embedded in the insulating layer and electrically connected to the emitter region, the main surface electrode being electrically connected to the emitter region via the plug electrode on the insulating layer.

[0465] [B10] The semiconductor device according to B8 or B9, wherein the IGBT region is adjacent to the FET structure in a surface layer portion of the first main surface and includes a floating region of a second conductivity type formed in an electrically floating state.

[0466] [B11] The semiconductor device according to B10, wherein the IGBT region includes a plurality of the FET structures formed at intervals from each other, and the floating region formed in a region between the plurality of adjacent FET structures in a surface layer portion of the first main surface.

[0467] [B12] The semiconductor device according to B10 or B11, wherein the IGBT region includes a region isolation structure in the first main surface that separates the floating region from the FET structure.

[0468] [B13] The semiconductor device according to any one of B8 to B12, wherein the FET structure has a trench gate structure including a gate trench formed in the first main surface, and the gate electrode layer in the gate trench facing the body region and the emitter region via the gate insulating layer.

[0469] [B14] The semiconductor device according to any one of B1 to B13, further comprising an RC-IGBT array including a plurality of the IGBT regions and a plurality of the diode regions arranged alternately along one direction, and the insulating layer has a plurality of the diode openings exposing the plurality of the diode regions, respectively.

[0470] [B15] The semiconductor device according to B14, wherein a plurality of the RC-IGBT arrays are formed at intervals from each other along an intersecting direction intersecting the one direction.

[0471] [B16] The semiconductor device described in B15, wherein the multiple IGBT regions are arranged in a matrix at intervals along the one direction and the intersecting direction, and the multiple diode regions are arranged in a matrix at intervals along the one direction and the intersecting direction so as to be interposed in a region between two of the IGBT regions adjacent to each other in the one direction.

[0472] [B17] The semiconductor device according to any one of B1 to B16, wherein the IGBT region is formed in a quadrangular shape in a planar view, and the diode region is formed in a quadrangular shape in a planar view.

[0473] [B18] The semiconductor device according to any one of B1 to B17, further including a second main surface electrode formed on the second main surface and electrically connected to the IGBT region and the diode region.

[0474] [C1] A semiconductor device including a semiconductor layer including a first main surface on one side and a second main surface on the other side, a drift region of a first conductivity type formed in the semiconductor layer, a body region of a second conductivity type formed on the first main surface, an emitter region of the first conductivity type formed in a surface layer of the body region, an FET structure including a gate electrode layer facing the body region and the emitter region via a gate insulating layer, an IGBT region including a collector region of a second conductivity type formed in a surface layer of the second main surface, a first impurity region of a second conductivity type formed in the surface layer of the first main surface and having a second conductivity type impurity concentration less than the second conductivity type impurity concentration of the body region, and a diode region including a second impurity region of a first conductivity type formed in the surface layer of the second main surface, and a main surface electrode connected to the first impurity region on the first main surface. This semiconductor device can suppress recovery loss.

[0475] [C2] The semiconductor device according to C1, wherein the principal surface electrode is directly connected to the first impurity region. With this semiconductor device, it is possible to suppress recovery loss while suppressing an increase in forward voltage.

[0476] [C3] The semiconductor device according to C1 or C2, further comprising an insulating layer formed on the first main surface and having a diode opening exposing the diode region, the main surface electrode being connected to the first impurity region within the diode opening.

[0477] [C4] The semiconductor device described in C3, further including a plug electrode embedded in the insulating layer and electrically connected to the emitter region, wherein the main surface electrode extends into the diode opening from above the insulating layer and is electrically connected to the emitter region above the insulating layer via the plug electrode.

[0478] [C5] The semiconductor device according to C4, wherein the plug electrode has a laminated structure including a barrier electrode layer in contact with the insulating layer, and a main electrode layer embedded in the insulating layer with the barrier electrode layer sandwiched therebetween.

[0479] [C6] The semiconductor device according to C5, wherein the barrier electrode layer has a single-layer structure including a titanium layer or a titanium nitride layer, or a laminated structure including a titanium layer and a titanium nitride layer.

[0480] [C7] The semiconductor device according to C5 or C6, wherein the main electrode layer contains tungsten.

[0481] [C8] The semiconductor device described in any one of C4 to C7, wherein the FET structure includes an emitter trench exposing the emitter region at the first main surface, and the plug electrode penetrates the insulating layer and is embedded in the emitter trench.

[0482] [C9] The semiconductor device described in C8, wherein the FET structure includes a second conductivity type contact region formed in a region along a bottom wall of the emitter trench in a surface portion of the body region and having a second conductivity type impurity concentration that exceeds the second conductivity type impurity concentration of the body region.

[0483] [C10] The semiconductor device according to C8 or C9, wherein the emitter trench penetrates the emitter region.

[0484] [C11] The semiconductor device according to any one of C1 to C10, wherein the diode region is adjacent to the IGBT region.

[0485] [C12] The semiconductor device according to any one of C1 to C11, further including an RC-IGBT arrangement including a plurality of the IGBT regions and a plurality of the diode regions arranged alternately along one direction.

[0486] [C13] The semiconductor device according to C12, wherein a plurality of the RC-IGBT arrays are formed at intervals from each other along an intersecting direction intersecting the one direction.

[0487] [C14] The semiconductor device described in C13, wherein the multiple IGBT regions are arranged in a matrix at intervals along the one direction and the intersecting direction, and the multiple diode regions are arranged in a matrix at intervals along the one direction and the intersecting direction so as to be interposed in a region between two IGBT regions adjacent in the one direction.

[0488] [C15] The semiconductor device according to any one of C1 to C14, wherein the IGBT region is formed in a quadrangular shape in a planar view, and the diode region is formed in a quadrangular shape in a planar view.

[0489] [C16] The semiconductor device according to any one of C1 to C15, wherein the FET structure has a trench gate structure including a gate trench formed in the first main surface, and the gate electrode layer in the gate trench facing the body region and the emitter region via the gate insulating layer.

[0490] [C17] The semiconductor device according to any one of C1 to C16, wherein the IGBT region is adjacent to the FET structure in a surface layer portion of the first main surface and includes a floating region of a second conductivity type formed in an electrically floating state.

[0491] [C18] The semiconductor device according to C17, wherein the IGBT region includes a plurality of the FET structures formed at intervals from each other, and the floating region formed in a region between the plurality of adjacent FET structures in a surface layer portion of the first main surface.

[0492] [C19] The semiconductor device according to C17 or C18, wherein the IGBT region includes a region isolation structure in the first main surface that separates the floating region from the FET structure.

[0493] [C20] The semiconductor device according to any one of C1 to C19, wherein the diode region includes a diode region isolation structure that partitions the first impurity region in the first main surface.

[0494] [C21] The semiconductor device according to any one of C1 to C20, wherein the principal surface electrode contains at least one of aluminum, copper, an aluminum-silicon-copper alloy, an aluminum-silicon alloy, and an aluminum-copper alloy.

[0495] [C22] The semiconductor device according to any one of C1 to C21, further including a second main surface electrode formed on the second main surface and electrically connected to the collector region and the second impurity region.

[0496] [D1] A semiconductor device comprising: a semiconductor layer having a main surface; a first RC-IGBT array formed in the semiconductor layer including a first IGBT region and a first diode region arranged adjacent to each other; a second RC-IGBT array formed in the semiconductor layer including a second IGBT region and a second diode region arranged adjacent to each other and spaced apart from the first RC-IGBT array; a temperature sensor formed in the semiconductor layer so as to be located in a region between the first RC-IGBT array and the second RC-IGBT array in a planar view; gate wiring formed in the region between the first RC-IGBT array and the second RC-IGBT array on the main surface and transmitting a gate signal to one or both of the first IGBT and the second IGBT; and sensor wiring formed in the region between the first RC-IGBT array and the second RC-IGBT array on the main surface and transmitting a control signal for the temperature sensor.

[0497] According to this semiconductor device, the area for forming wiring can be reduced while improving the accuracy of temperature detection by the temperature sensor. This makes it possible to suppress a reduction in the area in which an RC-IGBT array can be formed while improving the accuracy of temperature detection by the temperature sensor.

[0498] [D2] The semiconductor device according to D1, wherein the sensor wiring is formed to run parallel to the gate wiring in a region between the first RC-IGBT array and the second RC-IGBT array.

[0499] [D3] The semiconductor device according to D1 or D2, wherein the sensor wiring includes a first sensor wiring connected to one end of the temperature sensor, and a second sensor wiring connected to the other end of the temperature sensor.

[0500] [D4] The semiconductor device according to D3, wherein the second sensor wiring is formed to run parallel to the first sensor wiring in a region between the first RC-IGBT array and the second RC-IGBT array.

[0501] [D5] The semiconductor device according to any one of D1 to D4, wherein the first RC-IGBT array extends along one direction, and the second RC-IGBT array extends along the one direction.

[0502] [D6] The semiconductor device according to any one of D1 to D5, wherein the first RC-IGBT arrangement includes a plurality of the first IGBT regions and a plurality of the first diode regions arranged alternately.

[0503] [D7] The semiconductor device according to any one of D1 to D6, wherein the second RC-IGBT arrangement includes a plurality of the second IGBT regions and a plurality of the second diode regions arranged alternately.

[0504] [D8] A semiconductor device according to any one of D1 to D7, wherein the semiconductor layer includes an active region and an outer region outside the active region, and the first RC-IGBT array, the second RC-IGBT array and the temperature sensor are formed in the active region.

[0505] [D9] The semiconductor device described in any one of D1 to D8, further including: a gate terminal electrode formed on the main surface in the outer region and electrically connected to the gate wiring; and a sensor terminal electrode formed on the main surface in the outer region at a distance from the gate terminal electrode and electrically connected to the sensor wiring.

[0506] [E1] A semiconductor layer having a first main surface on one side and a second main surface on the other side, the semiconductor layer including an active region, a plurality of IGBT regions formed in the active region, and a plurality of diode regions formed in the active region adjacent to the plurality of IGBT regions, wherein a total extension of boundaries between the plurality of IGBT regions and the plurality of diode regions is represented by L, a total area of ​​the plurality of diode regions is represented by SD, and a dispersion degree of the plurality of diode regions with respect to the active region is represented by Log e (L 2 / SD), the dispersity is 2 or more and 15 or less.

[0507] [E2] The semiconductor device according to E1, wherein a ratio of a total area of ​​the plurality of diode regions to an area of ​​the active region is equal to or less than a ratio of a total area of ​​the plurality of IGBT regions to an area of ​​the active region.

[0508] [E3] The semiconductor device according to E1 or E2, wherein a ratio of a total area of ​​the plurality of diode regions to an area of ​​the active region is 0.4 or less.

[0509] [E4] The semiconductor device according to any one of E1 to E3, wherein the dispersity is 2 or more and 7 or less.

[0510] [E5] The semiconductor device according to any one of E1 to E3, wherein the dispersity is 7 or more and 12 or less.

[0511] [E6] The semiconductor device according to any one of E1 to E5, further including an RC-IGBT arrangement including a plurality of the IGBT regions and a plurality of the diode regions arranged alternately along one direction.

[0512] [E7] The semiconductor device according to E6, wherein a plurality of the RC-IGBT arrays are formed at intervals from each other along an intersecting direction intersecting the one direction.

[0513] [E8] The semiconductor device described in E7, wherein the multiple IGBT regions are arranged in a matrix at intervals along the one direction and the intersecting direction, and the multiple diode regions are arranged in a matrix at intervals along the one direction and the intersecting direction so as to be interposed in a region between two IGBT regions adjacent in the one direction.

[0514] [E9] The semiconductor device according to any one of E1 to E8, wherein the IGBT regions are formed in a quadrangular shape in a planar view, and the diode regions are formed in a quadrangular shape in a planar view.

[0515] [E10] The semiconductor device according to any one of E1 to E9, further including a drift region of a first conductivity type formed in the semiconductor layer, wherein the plurality of IGBT regions each include a body region of a second conductivity type formed in the first main surface, an emitter region of the first conductivity type formed in a surface layer portion of the body region, an FET structure including a gate electrode layer facing the body region and the emitter region via a gate insulating layer, and a collector region of the second conductivity type formed in a surface layer portion of the second main surface, and the plurality of diode regions each include a first impurity region of the second conductivity type formed in the surface layer portion of the first main surface, and a second impurity region of the first conductivity type formed in the surface layer portion of the second main surface.

[0516] [E11] The semiconductor device according to E10, wherein the first impurity region has a second conductive type impurity concentration less than a second conductive type impurity concentration of the body region.

[0517] [E12] The semiconductor device according to E10 or E11, further including a first main surface electrode formed on the first main surface and electrically connected to the emitter region and the first impurity region.

[0518] [E13] The semiconductor device according to E12, further comprising an insulating layer on the first main surface covering each of the IGBT regions and having a plurality of diode openings exposing each of the diode regions, the first main surface electrode being electrically connected to the first impurity region within the plurality of diode openings.

[0519] [E14] The semiconductor device according to E13, further comprising a plug electrode embedded in the insulating layer and electrically connected to the emitter region, the first main surface electrode being electrically connected to the emitter region via the plug electrode on the insulating layer.

[0520] [E15] The semiconductor device according to E13 or E14, wherein an angle formed between an inner wall of each of the diode openings in the insulating layer and the first main surface is greater than or equal to 45° and less than or equal to 90°.

[0521] [E16] The semiconductor device according to any one of E12 to E15, wherein the first main surface electrode is directly connected to the first impurity region.

[0522] [E17] The semiconductor device according to any one of E10 to E16, further including a second main surface electrode formed on the second main surface and electrically connected to the collector region and the second impurity region.

[0523] [E18] The semiconductor device according to any one of E10 to E17, wherein the IGBT region is adjacent to the FET structure in a surface layer portion of the first main surface and includes a floating region of a second conductivity type formed in an electrically floating state.

[0524] [E19] The semiconductor device according to E18, wherein the IGBT region includes a plurality of the FET structures formed at intervals from each other, and the floating region formed in a region between the plurality of adjacent FET structures in a surface layer portion of the first main surface.

[0525] [E20] The semiconductor device according to E18 or E19, wherein the IGBT region includes a region isolation structure in the first main surface that separates the floating region from the FET structure.

[0526] [E21] The semiconductor device according to any one of E10 to E20, wherein the FET structure has a trench gate structure including a gate trench formed in the first main surface, and the gate electrode layer in the gate trench facing the body region and the emitter region via the gate insulating layer.

[0527] [F1] A semiconductor layer having a first main surface on one side and a second main surface on the other side, the semiconductor layer including an active region, a plurality of IGBT regions formed in the active region, and a plurality of diode regions formed in the active region adjacent to the plurality of IGBT regions, wherein a total extension of a boundary line between the plurality of IGBT regions and the plurality of diode regions is represented by L, a total area of ​​the plurality of diode regions is represented by SD, and a dispersion degree of the plurality of diode regions with respect to the active region is represented by Log e (L 2 / SD), the dispersity is 7 or more and 12 or less.

[0528] [F2] The semiconductor device according to F1, wherein the active region further includes a sensor region in which a temperature sensor is formed, the sensor region being formed in a central portion of the active region in a plan view.

[0529] [F3] The semiconductor device described in F2, wherein the semiconductor layer includes the active region and an outer region that is an area outside the active region and surrounds the active region along a periphery of the active region in a planar view, and includes a plurality of terminal electrodes formed in the outer region.

[0530] [F4] The semiconductor device according to F3, wherein at least two of the plurality of terminal electrodes are terminal electrodes for transmitting a control signal for controlling the sensor region.

[0531] [F5] The semiconductor device according to any one of F1 to F4, wherein the proportion of the total area of ​​the plurality of diode regions to the area of ​​the active region is equal to or less than the proportion of the total area of ​​the plurality of IGBT regions to the area of ​​the active region.

[0532] [F6] The semiconductor device according to F5, wherein a ratio of a total area of ​​the plurality of diode regions to an area of ​​the active region is 0.4 or less.

[0533] [F7] The semiconductor device according to any one of F1 to F6, further including an RC-IGBT arrangement including a plurality of the IGBT regions and a plurality of the diode regions arranged alternately along one direction.

[0534] [F8] The semiconductor device according to F7, wherein a plurality of the RC-IGBT arrays are formed at intervals from each other along an intersecting direction intersecting the one direction.

[0535] [F9] The semiconductor device described in F8, wherein the multiple IGBT regions are arranged in a matrix at intervals along the one direction and the intersecting direction, and the multiple diode regions are arranged in a matrix at intervals along the one direction and the intersecting direction so as to be interposed in a region between two of the IGBT regions adjacent in the one direction.

[0536] [F10] The semiconductor device according to any one of F1 to F9, wherein the IGBT regions are formed in a quadrangular shape in a planar view, and the diode regions are formed in a quadrangular shape in a planar view.

[0537] [F11] The semiconductor device according to any one of F1 to F10, further including a drift region of a first conductivity type formed in the semiconductor layer, wherein the plurality of IGBT regions each include a body region of a second conductivity type formed in the first main surface, an emitter region of the first conductivity type formed in a surface layer portion of the body region, an FET structure including a gate electrode layer facing the body region and the emitter region via a gate insulating layer, and a collector region of the second conductivity type formed in a surface layer portion of the second main surface, and the plurality of diode regions each include a first impurity region of the second conductivity type formed in the surface layer portion of the first main surface, and a second impurity region of the first conductivity type formed in the surface layer portion of the second main surface.

[0538] [F12] The semiconductor device according to F11, wherein the first impurity region has a second conductivity type impurity concentration that is less than a second conductivity type impurity concentration of the body region.

[0539] [F13] The semiconductor device according to F11 or F12, further comprising a first main surface electrode formed on the first main surface and electrically connected to the emitter region and the first impurity region.

[0540] [F14] The semiconductor device according to F13, further including an insulating layer on the first main surface covering each of the IGBT regions and having a plurality of diode openings exposing each of the diode regions, the first main surface electrode being electrically connected to the first impurity region within the plurality of diode openings.

[0541] [F15] The semiconductor device according to F14, further including a plug electrode embedded in the insulating layer and electrically connected to the emitter region, the first main surface electrode being electrically connected to the emitter region via the plug electrode on the insulating layer.

[0542] [F16] The semiconductor device according to F14 or F15, wherein an angle formed between an inner wall of each of the diode openings in the insulating layer and the first main surface is equal to or greater than 45° and equal to or less than 90°.

[0543] [F17] The semiconductor device according to any one of F13 to F16, wherein the first main surface electrode is directly connected to the first impurity region.

[0544] [F18] The semiconductor device according to any one of F11 to F17, further including a second main surface electrode formed on the second main surface and electrically connected to the collector region and the second impurity region.

[0545] [F19] The semiconductor device according to any one of F11 to F18, wherein the IGBT region is adjacent to the FET structure in a surface layer portion of the first main surface and includes a floating region of a second conductivity type formed in an electrically floating state.

[0546] [F20] The semiconductor device according to F19, wherein the IGBT region includes a plurality of the FET structures formed at intervals from one another, and the floating region formed in a region between the plurality of adjacent FET structures in a surface layer portion of the first main surface.

[0547] [F21] The semiconductor device according to F19 or F20, wherein the IGBT region includes a region isolation structure in the first main surface that separates the floating region from the FET structure.

[0548] [F22] The semiconductor device according to any one of F11 to F21, wherein the FET structure has a trench gate structure including a gate trench formed in the first main surface, and the gate electrode layer in the gate trench facing the body region and the emitter region via the gate insulating layer.

[0549] [F23] The semiconductor device according to F11, wherein the collector region is formed in the entire surface layer portion of the second main surface except for the diode region.

[0550] The aforementioned [A1] to [A11], the aforementioned [B1] to [B18], the aforementioned [C1] to

[22] , the aforementioned [D1] to [D9], the aforementioned [E1] to [E21], and the aforementioned [F1] to [F23] may be combined in any manner therebetween.

[0551] This application corresponds to Japanese Patent Application No. 2018-196511 filed with the Japan Patent Office on October 18, 2018, the entire disclosure of which is incorporated herein by reference. Although the embodiments of the present invention have been described in detail, these are merely specific examples used to clarify the technical content of the present invention, and the present invention should not be interpreted as being limited to these specific examples, and the scope of the present invention is limited only by the scope of the appended claims. [Explanation of symbols]

[0552] 1 Semiconductor device 2. Semiconductor layer 3 First main surface 4 Second main surface 6 Active Area 8 IGBT area 9 Diode Region 12 RC-IGBT array 13 Emitter terminal electrode 30 Drift Region 32 Collector terminal electrode 34 Collector Region 35 FET structure 36 Trench gate structure 39 Gate Trench 40 Gate insulating layer 41 Gate electrode layer 45 Body Region 46 Emitter Area 52 Floating Areas 53 Region isolation trench structure 61 Cathode Region 62 Anode Region 79 Interlayer insulation layer 84 Diode Aperture 91 Emitter plug electrode 181 Semiconductor devices D Dispersity L Total length SA Active Area SD Diode Area SI IGBT area θ Angle of the inner wall of the diode aperture X 1st direction Y Second direction

Claims

1. a semiconductor layer having a first main surface on one side and a second main surface on the other side, the semiconductor layer including an active region; an IGBT region formed on the first main surface; a diode region formed outside the IGBT region in the first main surface; an insulating layer selectively covering the IGBT region and the diode region on the first main surface; an emitter terminal covering the insulating layer and having a portion connected to the semiconductor layer in the diode region; a total extension of boundaries between the IGBT regions and the diode regions is represented by L, a total area of ​​the diode regions is represented by SD, and a dispersion of the diode regions with respect to the active region is defined by the formula Log e (L2 / SD), the dispersion being 7 or more and 12 or less.

2. the diode region includes a p-type anode region formed in a surface layer portion of the first main surface, The semiconductor device according to claim 1 , wherein said emitter terminal is electrically connected to said anode region.

3. the insulating layer has a diode opening exposing the diode region; 3. The semiconductor device according to claim 1, wherein an angle between an inner wall of said diode opening and said first main surface in said insulating layer is equal to or greater than 45 degrees and equal to or less than 90 degrees.

4. the IGBT region includes a trench electrode type gate structure formed on the first main surface, 4. The semiconductor device according to claim 1, wherein the diode region includes a trench electrode type isolation structure formed in the first main surface.

5. the gate structure has a depth of 4 μm to 5 μm, 5 μm to 6 μm, or 6 μm to 7 μm; 5. The semiconductor device according to claim 4, wherein the isolation structure has a depth of 4 [mu]m to 5 [mu]m, 5 [mu]m to 6 [mu]m, or 6 [mu]m to 7 [mu]m.

6. the gate structure has a width of 0.5 μm to 1 μm, or 1 μm to 1.5 μm; 6. The semiconductor device according to claim 4, wherein the isolation structure has a width of 0.5 μm to 1 μm, or 1 μm to 1.5 μm.

7. 7. The semiconductor device according to claim 4, wherein the isolation structure has a depth equal to a depth of the gate structure.

8. 8. The semiconductor device according to claim 4, wherein the isolation structure has a width equal to a width of the gate structure.

9. the IGBT region includes a plurality of the gate structures formed at intervals on the first main surface, 9. The semiconductor device according to claim 4, wherein the diode region includes a plurality of the isolation structures formed at intervals on the first main surface.

10. the IGBT region is formed in a surface layer portion of the second main surface and includes a p-type collector region facing a plurality of the gate structures in a thickness direction of the semiconductor layer; 10. The semiconductor device according to claim 9, wherein the diode region includes an n-type cathode region formed in a surface layer portion of the second main surface and facing a plurality of the isolation structures in a thickness direction of the semiconductor layer.

11. the plurality of isolation structures includes an outermost isolation structure adjacent to the IGBT region, The semiconductor device according to claim 10 , wherein the cathode region has an outermost portion facing the isolation structure in a thickness direction of the semiconductor layer.

12. The semiconductor device according to any one of claims 4 to 11, wherein the IGBT region includes a p-type body region formed in a surface layer portion of the first main surface along the gate structure, and an n-type emitter region formed in a surface layer portion of the body region along the gate structure.

13. 13 . The semiconductor device according to claim 12 , wherein said body region is formed at a distance from a center position of said gate structure in a depth direction toward said first main surface.

14. A plurality of the IGBT regions are formed at intervals on the first main surface, 14. The semiconductor device according to claim 1, wherein the diode region is formed in a region between a plurality of the IGBT regions on the first main surface.

15. The semiconductor device according to claim 14 , wherein a plurality of said diode regions are formed at intervals on said first main surface.

16. The semiconductor device according to claim 15 , wherein the plurality of diode regions and the plurality of IGBT regions are arranged alternately.

17. 17. The semiconductor device according to claim 15, wherein a ratio of a total area of ​​the plurality of diode regions is equal to or smaller than a ratio of a total area of ​​the plurality of IGBT regions.

18. The semiconductor device according to claim 1, further comprising a temperature sensor formed on the first main surface.

19. 19. The semiconductor device according to claim 1, further comprising a gate terminal disposed on said insulating layer and spaced from said emitter terminal.

20. The semiconductor device according to claim 1 , further comprising a collector terminal covering the second main surface.

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