Semiconductor parts

Abstract

To provide a semiconductor component that includes higher efficiency, and is adopted to a high-frequency and a high power related electronic component while improving a high-frequency power gain.SOLUTION: In a semiconductor component 1 comprising a semiconductor layer 100, a barrier layer 109, a leak current suppression layer 101, ohmic contact layers 103 and 104, and electrode layers 105 and 106, the semiconductor layer includes a projection part 100P and top surfaces T1 and T2 that are adjacent to the projection part. The projection part contains a top surface T3 and two side surfaces S1 and S2. The barrier layer is provided onto the top surfaces of the projection part. The leak current suppression layer 101 is provided onto the top surface of the semiconductor layer. Each ohmic contact layer is provided onto the leak current suppression layer, is contacted to the side surface of the projection part and the side surface of the barrier layer, and is not contacted to the top surface of the semiconductor layer. Each electrode layer is provided onto each ohmic contact layer.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to semiconductor components. [Background technology]

[0002] Due to application environments requiring high operating frequencies and high output power, semiconductor components are required to have characteristics such as high breakdown voltage and high saturation carrier velocity. Gallium nitride has wide band gap characteristics. In addition, the polarization difference occurring at the interface of a heterostructure formed by gallium nitride and n-type aluminum gallium nitride induces two-dimensional electron gas, which is the mechanism of high electron mobility transistors (HEMT). Therefore, components based on gallium nitride materials are suitable for applications in high frequency, high power, radiation resistance, and high temperature environments.

[0003] The information disclosed in this Background is merely intended to enhance understanding of the described technology and may therefore include information that does not constitute prior art known to those of skill in the art. Moreover, the information disclosed in this Background does not imply that one or more problems to be solved by one or more embodiments of the present invention are recognized by those of skill in the art. Summary of the Invention [Problem to be solved by the invention]

[0004] When high frequency components are working, a small amount of current leaks downward from the ohmic contact layer under the source and drain electrodes to the buffer layer. Therefore, how to solve the above problem is a concern in the industry. [Means for solving the problem]

[0005] The present invention provides a semiconductor component that prevents current from leaking downward into the buffer layer.

[0006] According to one embodiment of the present invention, there is provided a semiconductor component including a semiconductor layer, a barrier layer, two leakage current suppression layers, two ohmic contact layers, and two electrode layers. The semiconductor layer has a protrusion on one side of the semiconductor layer and two top surfaces of the semiconductor layer. The two top surfaces of the semiconductor layer are adjacent to the protrusion, and the protrusion includes a top surface and two side surfaces. One of the two side surfaces of the protrusion is adjacent between the top surface of the protrusion and one of the two top surfaces of the semiconductor layer. The other of the two side surfaces of the protrusion is adjacent between the top surface of the protrusion and the other of the two top surfaces of the semiconductor layer. The barrier layer is provided on the top surface of the protrusion, and the barrier layer includes two side surfaces. The two leakage current suppression layers are provided on the two top surfaces of the semiconductor layer, respectively. The two ohmic contact layers are provided on the two leakage current suppression layers, respectively, the two ohmic contact layers contact the two side surfaces of the protrusion and the two side surfaces of the barrier layer, and the two ohmic contact layers do not contact the two top surfaces of the semiconductor layer. The two electrode layers are provided on the two ohmic contact layers, respectively. Effect of the Invention

[0007] Based on the above, in the semiconductor component provided by the embodiment of the present invention, a leakage current suppression layer is provided between the ohmic contact layer and the semiconductor layer, and the ohmic contact layer is used to reduce the contact resistance, thereby increasing the high frequency power gain. The leakage current suppression layer prevents current from leaking downward to the buffer layer or substrate of the semiconductor component during the operation of the semiconductor component, thereby reducing power consumption. Therefore, the semiconductor component can have higher efficiency while improving the high frequency power gain. The semiconductor component is suitable for high frequency and high power related electronic products, such as B5G / 6G communication products.

[0008] Other objects, features, and advantages of the present invention will be further understood from the additional technical features disclosed in the embodiments of the present invention, which have been shown and described in detail with reference to preferred embodiments of the present invention, simply by way of illustration of the best mode for carrying out the present invention. [Brief description of the drawings]

[0009] The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification, illustrating embodiments of the invention and, together with the description, serve to explain the principles of the invention. [Figure 1A] 1 is a schematic diagram of a method for manufacturing a semiconductor component according to one embodiment of the present invention. [Figure 1B] 1 is a schematic diagram of a method for manufacturing a semiconductor component according to one embodiment of the present invention. [Figure 1C] 1 is a schematic diagram of a method for manufacturing a semiconductor component according to one embodiment of the present invention. [Figure 1D] 1 is a schematic diagram of a method for manufacturing a semiconductor component according to one embodiment of the present invention. [Figure 1E] 1 is a schematic diagram of a method for manufacturing a semiconductor component according to one embodiment of the present invention. [Figure 2A] 1 is a schematic diagram of a method for manufacturing a semiconductor component according to one embodiment of the present invention. [Figure 2B] 1 is a schematic diagram of a method for manufacturing a semiconductor component according to one embodiment of the present invention. [Figure 2C] 1 is a schematic diagram of a method for manufacturing a semiconductor component according to one embodiment of the present invention. [Diagram 3] 1 is a schematic diagram of a partial structure of a semiconductor component according to one embodiment of the present invention. [Figure 4] 1 is a schematic diagram of a partial structure of a semiconductor component according to one embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] In the following detailed description of the preferred embodiment, reference is made to the accompanying drawings, which form a part hereof, and which show, by way of illustration, specific embodiments in which the invention may be practiced. In this context, directional terms such as "upper", "lower", "front", "rear" and the like are used with reference to the orientation of the figures being described. Components of the invention can be arranged in a number of different orientations. As such, directional terms are used for purposes of explanation and in no way limiting. However, the drawings are merely schematic, and the sizes of components may be exaggerated for clarity. It is to be understood that other embodiments may be utilized and structural changes may be made without departing from the scope of the present invention. It is also to be understood that the phraseology and terminology used herein are for purposes of explanation and in no way limiting. The use of "including", "comprising", or "having" and variations thereof herein is meant to encompass the items listed thereafter and equivalents thereof, as well as additional items. Unless otherwise limited, the terms "connected", "coupled", and "mounted" and variations thereof herein are used broadly and encompass both direct and indirect connections, couplings, and mountings. Similarly, the terms "facing," "facing," and variations thereof herein are used broadly to include directly and indirectly facing, and "adjacent" and variations thereof herein are used broadly to include directly and indirectly "adjacent." Thus, a description herein of component "A" facing component "B" may include a situation in which component "A" faces component "B" directly, or where there are one or more additional components between component "A" and component "B." Also, a description herein of component "A" being "adjacent" component "B" may include a situation in which component "A" is directly "adjacent" component "B," or where there are one or more additional components between component "A" and component "B." Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as limiting.

[0011] Reference is made to Figures 1A-1E, which are schematic illustrations of a method for manufacturing a semiconductor component according to one embodiment of the present invention.

[0012] 1A, a substrate 10 is provided, which may include, for example, a semiconductor layer such as a silicon layer, a silicon carbide layer, a SOI (silicon-on-insulator) layer, a QST (Qromis substrate technology) ceramic layer, or a combination thereof.

[0013] Next, an aluminum nitride layer 300 is formed on the substrate 10. Generally, when the aluminum nitride layer 300 is formed in a high temperature process, the aluminum contained therein may diffuse into the underlying film layers. Therefore, in some preferred embodiments, a wide band gap diffusion buffer layer is formed on the side of the substrate 10 close to the aluminum nitride layer 300 to prevent the aluminum in the aluminum nitride layer 300 from diffusing into the semiconductor layers of the substrate 10, which prevents current leakage during operation in the fabricated semiconductor component.

[0014] Next, a buffer layer 200 and a semiconductor layer 100 are sequentially formed on the aluminum nitride layer 300. The buffer layer 200 is an aluminum gallium nitride (AlGaN) layer, and the semiconductor layer 100 is a wide band gap gallium nitride (GaN) layer. The difference in lattice constant between the substrate 10 and the GaN layer (semiconductor layer 100) thereon causes stress, which affects the quality of the epitaxial layer on the substrate 10. Therefore, the buffer layer 200 is formed between the substrate 10 and the semiconductor layer 100 to balance the stress between the substrate 10 and the semiconductor layer 100 formed on the substrate 10.

[0015] Then, a barrier layer 109 is formed on the semiconductor layer 100. The barrier layer 109 is an aluminum gallium nitride layer, and the wide band gap gallium nitride (GaN) of the semiconductor layer 100 and the barrier layer 109 form a heterostructure (AlGaN / GaN heterostructure).

[0016] 1B, an etching process is performed on the barrier layer 109 and the semiconductor layer 100 to form a protrusion 100P and two top surfaces T1 and T2 on the top of the semiconductor layer 100. The barrier layer 109 is located on the protrusion 100P.

[0017] 1C, leakage current suppression layers 101, 102, and 107 are formed on two top surfaces T1 and T2 of the semiconductor layer 100 and a top surface 109T of the barrier layer 109, respectively. In some embodiments, the material of the leakage current suppression layers 101, 102, and 107 is SiO 2 , SiN, Ga 2 O 3 , (Al x Ga 1-x ) 2 O 3 , Al 2 O 3 , AlN, BN, or similar wide band gap materials, but the invention is not limited thereto.

[0018] Referring to FIG. 1D, ohmic contact layers 103 and 104 are formed on the leakage current suppressing layers 101 and 102, respectively. The ohmic contact layer 103 contacts the side surface S1 of the protrusion 100P, and the ohmic contact layer 104 contacts the side surface S2 of the protrusion 100P.

[0019] Referring to FIG. 1E, electrode layers 105, 106, and 108 are formed on the ohmic contact layers 103 and 104 and the leakage current suppression layer 107, respectively, to form the semiconductor component 1.

[0020] Reference is now made to Figures 1A, 1B, 2A, 2B and 2C, which show schematic diagrams of a method for manufacturing a semiconductor component according to one embodiment of the present invention. The steps shown in Figures 1A and 1B have been described in the above embodiment, and will not be repeated.

[0021] 2A and 2B, first, the leakage current suppression layer 107 is formed on the top surface 109T of the barrier layer 109, and then, in order to form high resistance layers 101R, 102R, and 107R, the two top surfaces T1 and T2 of the semiconductor layer 100 and the leakage current suppression layer 107 are simultaneously implanted with ions.

[0022] 2C, ohmic contact layers 103 and 104 are formed on the high-resistance layers 101R and 102R, respectively, with the ohmic contact layer 103 in contact with the side surface S1 of the protrusion 100P and the ohmic contact layer 104 in contact with the side surface S2 of the protrusion 100P. Finally, electrode layers 105, 106, and 108 are formed on the ohmic contact layers 103 and 104 and the high-resistance layer 107R, respectively, thereby completing the semiconductor component 2.

[0023] For a detailed understanding of the structure and function of the semiconductor component in the above-mentioned embodiment, please refer to Fig. 3. The semiconductor component 1 includes a substrate 10, a semiconductor layer 100, a buffer layer 200, an aluminum nitride layer 300, two leakage current suppression layers 101, 102, two ohmic contact layers 103, 104, electrode layers 105, 106, 108, and a barrier layer 109. The two electrode layers 105 and 106 are disposed on the two ohmic contact layers 103 and 104, respectively.

[0024] On one side of the semiconductor layer 100, there is a protrusion 100P and two top surfaces T1, T2 of the semiconductor layer 100 adjacent to the protrusion 100P. The protrusion 100P includes a top surface T3 and two side surfaces S1, S2. The side surface S1 of the protrusion 100P is adjacent to the top surface T3 and the top surface T1 of the protrusion 100P, and the side surface S2 of the protrusion 100P is adjacent to the top surface T3 and the top surface T2 of the protrusion 100P. The barrier layer 109 is provided on the top surface T3 of the protrusion 100P, and the barrier layer 109 includes two side surfaces S3, S4.

[0025] The leakage current suppression layer 101 is provided on the top surface T1, and the leakage current suppression layer 102 is provided on the top surface T2. The ohmic contact layer 103 is provided on the leakage current suppression layer 101, and is in contact with a side surface S1 of the protrusion 100P and a side surface S3 of the barrier layer 109. The ohmic contact layer 104 is provided on the leakage current suppression layer 102, and is in contact with a side surface S2 of the protrusion 100P and a side surface S4 of the barrier layer 109.

[0026] In some embodiments, the semiconductor component 1 is implemented as a high frequency device, and the substrate 10 is one of a silicon substrate, a silicon carbide substrate, an SOI substrate, and a QST substrate. The buffer layer 200 is an aluminum gallium nitride (AlGaN) layer. The barrier layer 109 is an aluminum gallium nitride layer. The semiconductor layer 100 is a wide band gap gallium nitride (GaN) layer. The semiconductor layer 100 and the barrier layer 109 form a heterostructure (AlGaN / GaN heterostructure). The electrode layers 105, 106, and 108 are used as source, drain, and gate electrodes, respectively. The material of the electrode layers 105, 106, and 108 includes Ag, Au, TiN, Au / Ti, Au / Mo / Ti, Au / Si / Ti, etc. In some embodiments, the material of the electrode layers 105, 106, and 108 includes Ti / Al / Ni / Au with thicknesses of 30 nm / 200 nm / 40 nm / 10 nm, respectively. In some embodiments, the material of the electrode layers 105, 106, 108 includes Ti / Al / Ni / Au with respective thicknesses of 20 nm / 220 nm / 55 nm / 45 nm. In some embodiments, the material of the electrode layers 105, 106, 108 includes Ti / Al / Mo / Au with respective thicknesses of 15 nm / 60 nm / 35 nm / 50 nm. In some embodiments, the material of the electrode layers 105, 106, 108 includes Ta / Si / Ti / Al / Ni / Ta with respective thicknesses of 5 nm / 20 nm / 120 nm / 40 nm / 30 nm. In some embodiments, the material of the electrode layers 105, 106, 108 includes Ta / Ti / Al / Mo / Au with respective thicknesses of 10 nm / 30 nm / 90 nm / 40 nm / 25 nm. In some embodiments, the material of the electrode layers 105, 106, 108 includes Si / Ti / Al / Ni / Au, with the thickness of the Si layer being 3 nm or 6 nm, in some embodiments, the material of the electrode layers 105, 106, 108 includes Ti / Al / Ti / Au, with the thicknesses of 30 nm / 200 nm / 30 nm / 10 nm, respectively.

[0027] Ohmic contact layers 103 and 104 are provided on the semiconductor component 1 to reduce the contact resistance between the source electrode 105 and the drain electrode 106 and to increase the high frequency power gain. In some embodiments, the material of the ohmic contact layers 103 and 104 may include N-type gallium nitride, N-type indium nitride, ZnO, SiC, AlInGaN, Ti, Al, Cr, or a metal with a work function less than 4.49 eV. In some embodiments, the ohmic contact layers 103 and 104 are doped with silicon or germanium, with a doping concentration of 10 18 cm -3 ~10 21 cm -3 Therefore, the contact resistance is further reduced.

[0028] The top surface T3 of the protrusion 100P is located between the top surfaces 103T and 104T of the ohmic contact layers 103 and 104 and the top surfaces 101T and 102T of the leakage current suppression layers 101 and 102. A two-dimensional electron gas having a low resistance value is formed at the heterointerface (i.e., the top surface T3 of the protrusion 100P), and the two-dimensional electron gas serves as the channel layer 100C. That is, the side surfaces of the channel layer 100C are in contact with the ohmic contact layers 103 and 104. Therefore, the contact resistance is further reduced.

[0029] It should be particularly noted that the semiconductor components in some comparative examples are not provided with the leakage current suppression layers 101 and 102. That is, the ohmic contact layer 103 contacts the top surface T1, and the ohmic contact layer 104 contacts the top surface T2. In this manner, when the semiconductor component is in operation, a small amount of current leaks downward to the buffer layer 200 or the substrate 10. In contrast, the semiconductor component 1 according to the embodiment of the present invention is provided with the leakage current suppression layers 101 and 102. Therefore, the ohmic contact layer 103 does not directly contact the top surface T1, and the ohmic contact layer 104 does not directly contact the top surface T2. The semiconductor component 1 of the present invention does not suffer from the current leakage situation in the comparative examples described above. In some embodiments of the present invention, the material of the leakage current suppression layers 101 and 102 is SiO 2 , SiN, Ga2 O 3 , (Al x Ga 1-x ) 2 O 3 , Al 2 O 3 , AlN, BN, or similar wide band gap materials, although the invention is not so limited.

[0030] 3, the semiconductor component 1 further includes a leakage current suppression layer 107, in which a barrier layer 109, a leakage current suppression layer 107, and an electrode layer 108 are stacked in this order. However, the present invention is not limited thereto. In some embodiments, the electrode layer 108 may be provided directly on the barrier layer 109.

[0031] 3, in this embodiment, the ohmic contact layer 103 has a hypotenuse surface 103S away from the side surface S1 of the protrusion 100P. The hypotenuse surface 103S is inclined with respect to the leakage current suppression layer 101 and contacts the electrode layer 105. The ohmic contact layer 104 has a hypotenuse surface 104S away from the side surface S2 of the protrusion 100P. The hypotenuse surface 104S is inclined with respect to the leakage current suppression layer 102 and contacts the electrode layer 106. The top surface 109T of the barrier layer 109 is located between the top surfaces 103T and 104T of the ohmic contact layers 103 and 104 and the top surface T3 of the protrusion 100P.

[0032] In contrast, referring to FIG. 4, which shows a partial structural diagram of a semiconductor component 3 according to another embodiment of the present invention, the top surfaces 103T and 104T of the ohmic contact layers 103 and 104 of the semiconductor component 3 are located between the top surface 109T of the barrier layer 109 and the top surface T3 of the protrusion 100P.

[0033] 3 and 4, in the semiconductor component 1, the area of ​​the bottom surface 103B of the ohmic contact layer 103 is equal to the area of ​​the top surface 101T of the leakage current suppression layer 101, and the area of ​​the bottom surface 104B of the ohmic contact layer 104 is equal to the area of ​​the top surface 102T of the leakage current suppression layer 102. However, the present invention is not limited thereto. In the semiconductor component 3, as shown in FIG. 4, the area of ​​the bottom surface 103B of the ohmic contact layer 103 may be smaller than the area of ​​the top surface 101T of the leakage current suppression layer 101, and the area of ​​the bottom surface 104B of the ohmic contact layer 104 may be smaller than the area of ​​the top surface 102T of the leakage current suppression layer 102.

[0034] In summary, in the semiconductor component of the embodiment of the present invention, a leakage current suppression layer is provided between the ohmic contact layer and the semiconductor layer, and the ohmic contact layer is used to reduce the contact resistance so as to increase the high frequency power gain. The leakage current suppression layer prevents the current from leaking downward to the buffer layer or the substrate when the semiconductor component is operating. Therefore, the semiconductor component can have a higher efficiency due to the high frequency power gain.

[0035] The above description of the preferred embodiment of the present invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form or exemplary embodiments disclosed. Thus, the above description should be considered as illustrative and not limiting. Of course, many modifications and variations will be apparent to those skilled in the art. The embodiments have been selected and described to best explain the principles of the invention and the practical application of its best mode, so that those skilled in the art can understand the invention with its various embodiments and various modifications suited to the particular use or implementation contemplated. The scope of the present invention is defined by the appended claims and their equivalents, and all terms are intended to have their broadest reasonable meaning unless otherwise indicated. Thus, the terms "the present invention", "the present invention", and the like do not necessarily limit the scope of the claims to any particular embodiment, and reference to a particularly preferred exemplary embodiment of the present invention is not meant to limit the invention, and no such limitation is intended. The present invention is limited only by the spirit and scope of the appended claims. Furthermore, these claims may refer to the use of "first", "second", and the like following a noun or element. Such terms should be understood as nomenclature and should not be construed as limiting the number of elements modified by such nomenclature unless a specific number is specified. The Abstract of the Invention is provided to comply with the rules requiring abstracts, which will allow the searcher to quickly identify the subject matter of the technical disclosure of any patent issued from this disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. The advantages and benefits described do not apply to all embodiments of the invention. Those skilled in the art will understand that changes can be made to the described embodiments without departing from the scope of the invention as defined by the claims. Furthermore, elements and components of the invention are not intended to be made available to the public, regardless of whether the elements or components are expressly recited in the claims. [Industrial Applicability]

[0036] The semiconductor component of the present invention can be applied to high frequency devices. [Explanation of symbols]

[0037] 1, 2, 3: Semiconductor parts 10: Substrate 100: Semiconductor layer 100C: Channel layer 100P:Protrusion 101, 102, 107: Leakage current suppression layer 101T, 102T, 103T, 104T, 109T, T1, T2, T3: Top surface 101R, 102R, 107R: High resistance layer 103, 104: Ohmic contact layers 103B, 104B: Bottom 103S, 104S: hypotenuse surface 105, 106, 108: Electrode layer 109: Barrier layer 200: Buffer layer 300: Aluminum nitride layer S1, S2, S3, S4: Side

Claims

1. a semiconductor layer having a protrusion on one side and two top surfaces; a barrier layer including two sides; two leakage current suppression layers provided on the two top surfaces of the semiconductor layer, respectively; two ohmic contact layers provided on the two leakage current suppression layers, respectively; Two electrode layers provided on the two ohmic contact layers, respectively; Including, the two top surfaces of the semiconductor layer are adjacent to the protrusion, the protrusion has a top surface and two side surfaces, one of the two side surfaces of the protrusion is adjacent between the top surface of the protrusion and one of the two top surfaces of the semiconductor layer, and the other of the two side surfaces of the protrusion is adjacent between the top surface of the protrusion and the other of the two top surfaces of the semiconductor layer; the barrier layer is provided on the top surface of the protrusion; the two ohmic contact layers contact the two side surfaces of the protrusion and the two side surfaces of the barrier layer, and the two ohmic contact layers do not contact the two top surfaces of the semiconductor layer; The bottom surfaces of the two ohmic contact layers are in contact with the two leakage current suppression layers and are smaller than the top surfaces of the two leakage current suppression layers. Semiconductor components.

2. the top surface of the protrusion is provided between the top surfaces of the two ohmic contact layers and the top surfaces of the two leakage current suppression layers; The semiconductor component according to claim 1 .

3. The material of the two leakage current suppression layers is SiO ２ , SiN, Ga ２ O ３ , (Al ｘ G １－ｘ ) ２ O ３ , Al ２ O ３ , AlN, or BN; The semiconductor component according to claim 1 .

4. The two ohmic contact layers include at least one of N-type gallium nitride, N-type indium nitride, ZnO, SiC, AlInGaN, Ti, Al, and Cr; The semiconductor component according to claim 1 .

5. The two ohmic contact layers are made of silicon or germanium. １８ cm －３ ~10 ２１ cm －３ doped with a doping concentration between The semiconductor component according to claim 4.

6. The semiconductor layer includes a channel layer, and the two ohmic contact layers contact side surfaces of the channel layer. The semiconductor component according to claim 1 .

7. Further comprising a buffer layer provided on the other side of the semiconductor layer. The semiconductor component according to claim 1 .

8. Further comprising a substrate; The buffer layer is disposed between the substrate and the semiconductor layer, and the substrate is one of a silicon substrate, a silicon carbide substrate, an SOI substrate, and a QST substrate. The semiconductor component according to claim 7.

9. the two leakage current suppression layers are a first leakage current suppression layer and a second leakage current suppression layer, the two electrode layers are a first electrode layer and a second electrode layer, The semiconductor component further includes a third leakage current suppression layer and a third electrode layer, the barrier layer, the third leakage current suppression layer, and the third electrode layer are stacked in this order; The semiconductor component according to claim 1 .

10. the two ohmic contact layers have two side surfaces away from the two side surfaces of the protrusion, the two side surfaces of the two ohmic contact layers are inclined with respect to the two leakage current suppression layers, and the first electrode layer and the second electrode layer are in contact with the two side surfaces of the two ohmic contact layers, respectively.

10. The semiconductor component according to claim 9.

11. The two ohmic contact layers include a metal having a work function of less than 4.49 eV. The semiconductor component according to claim 1 .

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