Sustainable DRAM with a main power supply voltage unified with a logic circuit

Abstract

To disclose a sustainable DRAM having a main power supply voltage unified with an external logic circuit.SOLUTION: A DRAM circuit is configured to be coupled to an external logic circuit and a main power supply voltage source. The DRAM circuit has a first maintenance voltage generator and a DRAM core circuit. The first maintenance voltage generator generates a first voltage level higher than a voltage level corresponding to a signal ONE used in the DRAM circuit. The DRAM core circuit has a DRAM cell having an access transistor and a storage capacitor, and the storage capacitor of the DRAM cell is configured to be selectively coupled to the first maintenance voltage generator. The voltage level of the main power supply voltage source to the DRAM circuit is equal to or substantially equal to the voltage level of the main power supply voltage source to the external logic circuit.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present invention relates to dynamic memories, and more particularly to sustainable dynamic memories having a main power supply voltage that is unified or compatible with an external logic circuit.

Background Art

[0002] The most widely used DRAM cell has one access transistor whose source is connected to a storage capacitor and whose drain is connected to a bit line. The bit line is connected to a first-stage cross-coupled sense amplifier, which transfers the signal read (READ) from the cell array to a second-stage sense amplifier connected to an I / O line (also known as a data line) via a column switch. In a write (WRITE) operation, the signal is driven by an I / O buffer so as to be kept constant on the data line in order to write the correct signal to the storage capacitor via the access transistor, and the data line further keeps the data constant on the first-stage sense amplifier. The access transistor is responsible for the READ operation or the WRITE operation of correct data to the storage capacitor while the access transistor is in the active mode (i.e., the access transistor is ON), but also avoids loss of the stored signal when the access transistor is in the non-active mode (i.e., the access transistor is OFF).

[0003] The access transistor is designed to have a high threshold voltage to minimize the leakage current in the transistor. However, this results in the drawback of degrading its performance when the access transistor is turned on. As a result, in order to enable the access transistor to have a high driving ability for writing a signal to the storage capacitor, it is necessary to bootstrap the word line or connect it to a high VPP (usually from the word line voltage source). Such a high VPP is loaded onto the word line or the gate of the access transistor through the word line driver. Since VPP is a high voltage stress on the access transistor, the dielectric material of the transistor (e.g., oxide layer or high-k material) has to be designed thicker than that used for transistors in other support circuits or peripheral circuits of the DRAM (such as command decoders, address decoders, and other I / O circuits, etc.). Therefore, the design of the access transistor faces the dilemma of maintaining either high performance or high reliability, presenting a difficult trade-off between reliability and performance. Widely used access transistor designs focus more on achieving high reliability, but at the expense of the performance of the access transistor.

[0004] Briefly summarized, for conventional access transistor designs, they have a high threshold voltage to reduce leakage current to help with the long retention time of holding charge in the storage capacitor, have a thick gate dielectric material to withstand high word line voltages such as VPP, and sacrifice the performance of the access transistor. As a result, writing or reading a signal ONE (1), which usually refers to the VCC level, takes longer or the signal ONE cannot be fully restored. That is, the WRITE time becomes even longer to satisfy fully writing the full signal VCC to the storage capacitor.

[0005] A commonly used design of a DRAM cell can be shown in FIG. 1A. The DRAM cell includes an access transistor 11 and a capacitor 12. The gate of the access transistor 11 is coupled to a word line (WL), and a cross-coupled sense amplifier 20 is coupled to the access transistor 11 via a bit line (BL). The DRAM cell uses the access transistor 11 as a switch to control the charge so that it is stored from the bit line (BL) to the capacitor in the WRITE mode or transferred to the bit line in the READ mode, and a plurality of DRAM cells are respectively connected to the bit line. In this example, in the READ mode, the signal ONE (assumed to be 1.2V, and the signal ONE usually corresponds to the voltage level of VCCSA provided by the cross-coupled sense amplifier 20) and the signal ZERO (assumed to be 0V, and the signal ZERO usually corresponds to the voltage level of VSS provided by the cross-coupled sense amplifier 20) latched by the cross-coupled sense amplifier by amplifying the signal transferred onto the bit line by the cell signal exist, or these signals ONE and ZERO are externally written so as to twist the sense amplifier to store the correct signal in the cell in the WRITE mode.

[0006] FIG. 1B shows the signal waveforms related to the access (READ or WRITE) operation of most current DRAMs. For example, a 25-nanometer DRAM cell generally has the following parameters related to (and surrounded by) the array design: the bit line ONE voltage is 1.2V, the word line ON has a VPP reaching 2.7V, the word line OFF has a voltage of about -0.3V, the threshold voltage of the cell is in the range of about 0.7 - 0.9V, the dielectric of the access transistor must withstand the electric field strength below 2.7V (this number goes up to 3.4V for an acceptable reliability margin under the power-on test stress), and the word line driver device also has to use a thick gate dielectric, resulting in sacrificing performance.

[0007] As shown in FIG. 1B, initially, the storage capacitor of the DRAM is in the standby mode or the inactive mode (i.e., the access transistor is OFF), and the voltage level of the word line coupled to the gate of the access transistor is the standby negative voltage (-0.3V). The bit line (BL) and the bit line bar (BLB) are equalized at a voltage level that is half of VCCSA between the ONE level at VCCSA = 1.2V and the ZERO level at 0V. When the DRAM cell enters the active mode (i.e., the access transistor turns ON), the voltage level of the word line is raised from the standby negative voltage (-0.3V) and pulled up to a high level VPP (e.g., 2.7V, etc.) that is much higher than the sum of VCCSA (1.2V) and the threshold voltage VT of the access transistor (which can be 0.7 or 0.8V), providing a drive large enough to exceed the gate-source voltage of the access transistor (e.g., 2.7V - 1.2V - 0.8V = 0.7V). The bit line is coupled to the storage capacitor. The word line remains continuously ON at such a high voltage VPP for an access operation (e.g., READ or WRITE, etc.). Following the access operation, the RESTORE phase is advanced. During the RESTORE phase, the cross-coupled sense amplifier will recharge the storage capacitor based on the signal ONE or ZERO in the storage capacitor. After the RESTORE phase, the word line is pulled down from VPP to the voltage of the word line in the standby mode (-0.3V), and the access transistor becomes in the inactive mode.

[0008] This high VPP voltage stress causes the access transistor to be designed with a thicker gate oxide or gate insulator than those used for transistors in the peripheral circuit, which degrades access transistor performance, such as degradation of the short-channel effect, the ON-OFF ratio of the transistor current, and the swing gradient. Further, although the threshold voltage is designed to be higher than that used for transistors in the peripheral circuit, the leakage current in the access transistor in standby mode or non-active mode remains high, reducing the amount of stored charge for sensing. When VCCSA becomes lower in a 12 nm or 7 nm process (e.g., 0.6 V, etc.), the leakage problem in standby mode or non-active mode will deteriorate. Therefore, the main power supply voltage to the DRAM or the VCCSA voltage in transitional DRAM should be maintained at a certain voltage level.

[0009] On the other hand, an IC system for high-performance computing or artificial intelligence (AI) systems is composed of a plurality of DRAM chips and logic chips. Logic chips are now sometimes fabricated within a silicon die using a 10 nanometer process node or a 7 nanometer process node and are moving towards a 5 nanometer process node. These process nodes basically follow Moore's law through a device scaling design that doubles the number of transistors within a specified area for each process node. However, an important contribution enabling compliance with Moore's law is due to the invention and implementation of 3D transistor structures (e.g., gate-all-around, tri-gate, or FINFET). Transistors with a 3D shape or 3D structure deliver high performance, low leakage, high reliability, etc.

[0010] However, DRAM technology scaling has slowed after the 45-nanometer process node, and the introduction of 1Xnm after the 25-nanometer process node takes much longer than two years per process node that has occurred in the history of DRAM according to Moore's Law prediction. The major reason is that DRAM uses a stacked capacitor structure that requires a high-temperature processing step after the transistor structure is formed, and therefore it is difficult to control the source and drain junctions of the transistor to the shallowness required by the transistor scaling rules. As a result, most DRAM products do not use the same process technology as that widely used in logic processes for sub-20-nanometer process nodes.

[0011] Even worse, when logic / SOC performance can be highly accelerated by sub-10-nanometer processing and design technologies, especially by the use and improvement of 3D trigate transistor structures, the migration of the decelerated DRAM technology exacerbates the well-known Memory-Wall (actually DRAM-Wall) effect that reduces the data transfer speed between logic and memory. Both data bandwidth and random access time become an increasingly large performance gap, and conventional DRAM cannot function as a memory vehicle to provide or store data in logic / SOC chips.

[0012] To solve the memory wall problem, DRAM technology development has been led to 3D-DRAM technology called High-bandwidth DRAM (HBM). However, in the HBM standard issued by the Joint Electron Device Engineering Council (JEDEC), the main power supply voltage or main supply voltage Vdd of the DRAM chip is set at 1.2V. Such a main power supply voltage is outside the DRAM chip. On the other hand, the main power supply voltage of the tri-gate transistor used in the logic chip is in the range of 0.6 - 0.7V. As shown in FIG. 1C, the DRAM circuit 100 includes an I / O circuit 110 (including a signal level conversion circuit, a drive impedance adjustment circuit, etc.), a peripheral circuit 120 (including a command / address decoder, etc.), and a DRAM core circuit 130 (including a cell array, etc.). To communicate with the logic circuit 300 (such as a memory controller, etc.), there is a physical layer circuit (sometimes called the PHY layer) 200 between the DRAM 100 and the logic circuit 300, and the physical layer circuit 200 further includes an I / O physical circuit 210 (also including a signal level conversion circuit, a drive impedance adjustment circuit, etc.) and a logic physical circuit 220 that communicates with the logic circuit 300. Due to the decelerated DRAM technology migration and leakage problems in the DRAM circuit 100, the external main power supply voltage Va to the DRAM circuit 100 can be in the range of 2.5V - 1.1V, while the external main power supply voltage Va' to the logic circuit 300 can be in the range of 0.9V - 0.6V, for example. The main power supply voltage Va is outside the DRAM circuit 100 and can be used by the DRAM circuit 100 to generate various voltage sources such as the aforementioned voltage sources VCCSA, 1 / 2VCCSA, VPP, etc. The level of VCCSA may be the same as or different from the level of Va.

[0013] Due to the difference between the main power supply voltage Va to the DRAM circuit 100 and the main power supply voltage Va' to the logic circuit 300, as shown in FIG. 1D, in the transitional DRAM circuit, the I / O circuit 110 of the DRAM circuit 100 includes an output level conversion circuit for increasing or decreasing the voltage level of the output signal from the DRAM circuit 100 to a predetermined level acceptable by the I / O physical circuit 210 of the physical layer circuit 200. Further, the I / O 110 further includes an input comparator that compares the input signal from the physical layer circuit 200 with the reference voltage Vref and converts it into a corresponding signal. Similarly, as shown in FIG. 1E, the I / O physical circuit 210 of the physical layer circuit 200 also includes an output level conversion circuit for increasing or decreasing the voltage level of the output signal from the physical layer circuit 200 to a predetermined level acceptable by the I / O circuit 110 of the DRAM circuit 100, and further includes an input comparator that compares the input signal from the DRAM circuit 100 with another reference voltage Vref' and converts it into a corresponding signal. These mismatches in the main power supply voltage between the DRAM chip and the logic chip lead to difficulties in optimizing energy efficiency and performance synchronization.

[0014] Also, refer to FIG. 1F showing a conventional low-power DRAM circuit block. Input write data XIO (e.g., signal ONE or signal High) is received by data input circuit DI and then passed to global I / O path GIO with a heavy load. The voltage level of the write data on global I / O path GIO is, for example, 1.1V (such as VCCSA used in the sense amplifier of the DRAM array). Next, the write data on global I / O path GIO is sent to data line sense amplifier 70 that transfers the write data to the main data line path (i.e., data line DL). However, the main data line path still has a heavy load as well, and the voltage level of the write data on data line DL can also be 1.1V. Then, the write data on data line DL is sent to memory array 75, and within memory array 75, the write data is stored in the corresponding storage node via bit line BL. Usually, as shown in FIG. 1F, the voltage level of the write data on bit line BL is 1.1V. Here, global I / O path GIO and data line DL are part of the data path. To meet low power consumption, the voltage levels of the write data on global I / O path GIO, data line DL, and bit line BL should be made as low as possible, for example, 1.1V. However, if the voltage stored in the corresponding storage node is low, it can be troubled by serious leakage problems and cause data damage. SUMMARY OF THE INVENTION

[0015] Accordingly, the present invention is to introduce a sustainable DRAM chip having a main power supply voltage unified with an external logic circuit. According to one aspect of the present invention, the DRAM chip has a first maintenance voltage generator and a DRAM core circuit. The first maintenance voltage generator generates a first voltage level higher than the voltage level corresponding to the signal ONE used in the DRAM chip. The DRAM core circuit has DRAM cells each having an access transistor and a storage capacitor, and the storage capacitor of the DRAM cell is configured to be selectively coupled to the first maintenance voltage generator. The voltage level of the main power supply voltage source to the DRAM chip is the same as or substantially the same as the voltage level of the main power supply voltage source to the external logic circuit.

[0016] According to one aspect of the present invention, the voltage level of the external main power supply voltage source to the DRAM chip is 0.9V or less. For example, the voltage level of the external main power supply voltage source to the DRAM chip is between 0.9V and 0.5V or lower.

[0017] According to one aspect of the present invention, the DRAM chip further has an I / O circuit and a peripheral circuit between the I / O circuit and the DRAM core circuit, and the I / O circuit does not have an input comparison circuit and an output level conversion circuit.

[0018] According to one aspect of the present invention, the operating supply voltage to the drain side of the transistor in the peripheral circuit is the same as the voltage level of the main power supply voltage source to the DRAM chip. Also, the operating supply voltage to the drain side of the transistor in the DRAM core circuit other than the access transistor is the same as the voltage level of the main power supply voltage source to the DRAM chip. Furthermore, the voltage level corresponding to the signal ONE used in the DRAM chip is the same as the voltage level of the main power supply voltage source to the DRAM chip.

[0019] According to one aspect of the present invention, the DRAM chip further has an I / O circuit and a peripheral circuit between the I / O circuit and the DRAM core circuit. The output data signal from the peripheral circuit to the I / O circuit is not leveled up or down by the I / O circuit, and the input data signal from the external logic circuit to the DRAM chip is not compared with a reference voltage by the I / O circuit to generate a corresponding signal.

[0020] According to one aspect of the present invention, the DRAM chip further has a word line coupled to the gate terminal of the access transistor. The word line is selected to turn on the access transistor over a first period and a second period after the first period. The first voltage generator is electrically coupled to the storage capacitor of the DRAM cell during the second period. Also, the first period is an access operation period, and the second period is a restore phase period. Further, during the access operation period, a kicking charge source is electrically coupled to the bit line of the DRAM chip.

[0021] According to another object of the present invention, the present invention provides a DRAM chip configured to be coupled to an external logic circuit and a main power supply voltage source. The DRAM chip has a DRAM core circuit, an I / O circuit, and a peripheral circuit between the I / O circuit and the DRAM core circuit. The DRAM core circuit has DRAM cells having access transistors and storage capacitors, and the I / O circuit is configured to be coupled to the external logic circuit. The voltage level of the main power supply voltage source to the DRAM chip is the same as or substantially the same as the voltage level of the main power supply voltage source to the external logic circuit, and the voltage level of the main power supply voltage source to the DRAM chip is 0.9V or less.

[0022] According to one aspect of the present invention, the operating supply voltage to the drain side of the transistors in the peripheral circuit is the same as the voltage level of the main power supply voltage source to the DRAM chip. Also, the operating supply voltage to the drain side of the transistors in the DRAM core circuit that are not access transistors is the same as the voltage level of the main power supply voltage source to the DRAM chip. Further, the voltage level corresponding to the signal ONE used in the DRAM chip is the same as the voltage level of the main power supply voltage source to the DRAM chip. Also, the I / O circuit excludes or omits the input comparator circuit and the output level conversion circuit.

[0023] According to one aspect of the present invention, the DRAM chip further includes a first retention voltage generator and a word line coupled to the gate terminal of the access transistor. The first retention voltage generator generates a first voltage level higher than the voltage level corresponding to the signal ONE used in the DRAM chip. The word line is selected to turn on the access transistor over a first period and a second period after the first period, and the first retention voltage generator is electrically coupled to the storage capacitor of the DRAM cell during the second period. Also, the first period is an access operation period, and the second period is a restore phase period.

[0024] Another object of the present invention is to provide a memory system having a unified supply power voltage, which includes a DRAM chip and a logic chip electrically coupled to the DRAM chip. The voltage level of the main power supply voltage source to the DRAM chip is the same as or substantially the same as the voltage level of the main power supply voltage source to the logic chip, and the voltage level of the main power supply voltage source to the DRAM chip is 0.9V or less.

[0025] According to one aspect of the present invention, the DRAM chip includes a DRAM circuit, and the logic chip includes a logic circuit and a physical layer circuit. The main power supply voltage source to the DRAM chip is supplied to the DRAM circuit, and the main power supply voltage source to the logic chip is supplied to the logic circuit and the physical layer circuit.

[0026] According to one aspect of the present invention, a memory system having a unified supply power voltage further includes a base chip electrically coupled to a DRAM chip. The voltage level of the main power supply source to the DRAM chip is the same as or substantially the same as the voltage level of the main power supply source to the base chip.

[0027] According to one aspect of the present invention, the DRAM chip includes a DRAM circuit, the logic chip includes a logic circuit, and the base chip includes a physical layer circuit. The main power supply source to the DRAM chip supplies the DRAM circuit, the main power supply source to the logic chip supplies the logic circuit, and the main power supply source to the base chip supplies the physical layer circuit.

[0028] According to one aspect of the present invention, the DRAM chip has a DRAM cell and a first retention voltage generator. The DRAM cell has a storage capacitor and an access transistor, and the first retention voltage generator generates a first voltage level higher than the voltage level corresponding to the signal ONE used in the DRAM chip. The first retention voltage generator is coupled to the storage capacitor of the DRAM cell before the access transistor of the DRAM cell is turned off.

[0029] According to one aspect of the present invention, the DRAM chip further has an I / O circuit and a peripheral circuit between the I / O circuit and the DRAM cell, and the I / O circuit does not have an input comparison circuit and an output level conversion circuit.

[0030] According to one aspect of the present invention, the physical layer circuit of the memory system has an I / O physical circuit, and the I / O physical circuit does not have an input comparison circuit and an output level conversion circuit.

[0031] Another embodiment of the present invention provides a DRAM chip. The DRAM chip includes a DRAM cell having an access transistor and a storage capacitor, a sense amplifier coupled to the DRAM cell via a bit line, and a data path coupled to the sense amplifier. In the process of writing signal ONE into the storage capacitor, the voltage level of signal ONE on the data path is different from the voltage level of signal ONE stored in the storage capacitor.

[0032] According to one aspect of the present invention, the voltage level of signal ONE on the data path is lower than the voltage level of signal ONE stored in the storage capacitor.

[0033] According to one aspect of the present invention, the voltage level of signal ONE on the data path is between 0.9 - 0.6V.

[0034] According to another aspect of the present invention, the voltage level of signal ONE is stored in the storage capacitor only after the end of period tWR defined by JEDEC.

[0035] According to another aspect of the present invention, the data path includes a global I / O path and a data line, and the voltage level of signal ONE on the global I / O path or the data line is between 0.7 - 0.5V.

[0036] Another object of the present invention is to provide a DRAM chip, which includes a DRAM cell having an access transistor and a storage capacitor, a sense amplifier coupled to the DRAM cell via a bit line, and a data path coupled to the sense amplifier. The voltage level of the read data corresponding to signal ONE on the data path is higher than the voltage level of the write data corresponding to another signal ONE on the data path.

[0037] According to one aspect of the present invention, the voltage level of the read data corresponding to signal ONE on the data path is between 1.2 - 1.0V, and the voltage level of the write data corresponding to another signal ONE on the data path is between 0.8 - 0.5V.

[0038] According to another aspect of the present invention, the write data is stored in a storage capacitor, and the voltage level of the write data stored in the storage capacitor is higher than the voltage level of the write data on the data path.

[0039] According to another aspect of the present invention, the voltage level of signal ONE is stored in the storage capacitor only after the end of period tWR defined by JEDEC.

[0040] The present invention further provides a DRAM chip having a DRAM cell having an access transistor and a storage capacitor, a sense amplifier coupled to the DRAM cell via a bit line, and a data path coupled to the sense amplifier. The voltage swing on the global I / O path or data line during the read operation is greater than the voltage swing on the global I / O path or data line during the write operation.

[0041] According to another aspect of the present invention, the voltage swing on the global I / O path or data line during the read operation is between 1.2 - 1.0V, and the voltage swing on the global I / O path or data line during the write operation is between 0.8 - 0.6V.

[0042] According to another aspect of the present invention, the voltage swing of the control signal and address signal for DRAM operation is greater than the voltage swing on the global I / O path or data line during the write operation. The DRAM chip according to claim 30.

[0043] After reading the following detailed description of the preferred embodiments shown in the various figures and drawings, these and other objects of the present invention will become apparent to those skilled in the art.

Brief Description of the Drawings

[0044]

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Embodiments for Carrying Out the Invention

[0045] The following detailed description of the embodiments described below of the disclosed apparatus and method is presented herein by way of example and not limitation with reference to the drawings. Although specific embodiments are illustrated and described in detail, it should be understood that various modifications and changes can be made without departing from the scope of the appended claims. The scope of the present invention is not limited to the number, materials, shapes, relative arrangements, etc. of these constituent components, and is simply disclosed as an example of embodiments of the present invention.

[0046] This invention discloses a DRAM having a sustainable storage architecture, in which a sustaining voltage source is electrically coupled to the storage capacitor of the DRAM cell before the access transistor turns off, and the voltage level of the sustaining voltage source is higher than the voltage level of a normal signal ONE, or the voltage level of the sustaining voltage source is lower than the voltage level of a normal signal ZERO. DRAM operations (such as auto-precharge operations, RESTORE phases, and precharge phases, etc.) turn on the access transistor for the selected DRAM cell. Thus, by coupling the sustaining voltage source to the storage capacitor of the DRAM cell during the turn-on stage of the access transistor, after the turn-off stage of the access transistor, even if there is a leakage current in the access transistor, the storage capacitor can be sustained for a longer period compared to conventional DRAM structures.

[0047] Figure 2 shows the signal waveforms related to the access (READ or WRITE) operation of a DRAM cell according to an embodiment of this invention. Starting from the standby mode of the DRAM, the word line WL is biased to -0.3V to completely turn off the access transistor 11. In this embodiment, VCCSA is set to 1.2V and VSS is set to 0V. In this example, the level of signal ONE is 1.2V and the level of signal ZERO is 0V (GND). The bit lines (BL and BLB) are equalized at a voltage level of 0.6V between the signal ONE level at VCCSA = 1.2V and the signal ZERO level at VSS = 0V.

[0048] At T0, the word line voltage ramps up from -0.3V to 2.7V which is much higher than the VCCSSA of 1.2V and the threshold voltage of the access transistor of 0.8V, turning on the access transistor 11 to provide sufficient drive for transferring either signal ONE or ZERO to the bit line. Until the signal develops to a certain magnitude, the sense amplifier 20 is activated to amplify the signal across the bit line (BL) and the bit line bar (BLB). After T1, either a READ operation (by amplifying the signal transmitted by the cell signal on the bit line) or a WRITE operation (where these signals ONE and ZERO are externally written to twist the sense amplifier 20 and store the correct signal in the DRAM cell) can be executed. Naturally, in addition to READ or WRITE, other DRAM operations may be executed after T1. That is, during the period between T1 and T2, the DRAM cell is accessible.

[0049] In the RESTORE phase after T2, the dielectric of access transistor 11 can still have VPP applied from the word line over a suitably short restore time. In this RESTORE phase, a first sustain voltage source is intentionally coupled to the capacitor of the DRAM cell. The voltage level of the first sustain voltage source is higher than 1.2V VCCSA (or the voltage level of signal ONE). As shown in FIG. 3A, which shows a schematic circuit of sense amplifier 20 selectively coupled to the first sustain voltage source, this can be done by connecting or coupling the first sustain voltage source (VCCSA+M1) to sense amplifier 20 (e.g., by turning on switch 13). During this RESTORE phase, as shown in FIG. 3A, the original VCCSA voltage source is disconnected from the sense amplifier (e.g., by turning off switch 14), and the first sustain voltage source (VCCSA+M1) is connected to sense amplifier 20. M1 can be a positive number such that the first sustain voltage source (VCCSA+M1) is higher than VCCSA. In one example, M1 can be in the range from 1 / 3 of VCCSA to 2 / 3 of VCCSA, e.g., 0.6V. For example, when signal ONE is originally in the storage capacitor, during this RESTORE phase, a voltage level of 1.2V+0.6V from the first sustain voltage source is supplied to storage capacitor 12 via sense amplifier 20. That is, before the turn-off of access transistor 11 at T3 in FIG. 2 (i.e., the word line WL is pulled down from 2.7V VPP to the word line voltage in standby mode of -0.3V), a voltage level of the first sustain voltage source higher than the voltage level of the normal signal ONE (VCCSA) is supplied to storage capacitor 12. Thus, after the turn-off of access transistor 11, even if there is a leakage current in access transistor 11, storage capacitor 12 can be sustained over a longer period compared to a conventional DRAM structure. In one embodiment, after the turn-off of access transistor 11 or after the RESTORE phase, the first sustain voltage source (VCCSA+M1) can be disconnected from sense amplifier 20.In addition, as shown in FIG. 2, the bit line (BL) can be coupled to a bit line voltage source having a voltage level of Vbl such that the voltage level of the bit line (BL) is reset to Vbl. The switches 13 and 14 shown in FIG. 3A are PMOS transistors, and from the perspective of layout, it is necessary to prepare additional N wells for accommodating these PMOS transistors. To simplify the layout, the switches 13 and 14 may be MNOS transistors such that these NMOS transistors are located within the p substrate. However, doing so requires a higher voltage to fully turn on the NMOS transistors.

[0050] In another embodiment, during the RESTORE phase after T2, a second hold voltage source is intentionally coupled to the capacitor of the DRAM cell during the RESTORE phase. The voltage level of the second hold voltage source is lower than the voltage source VSS (0V or the voltage level of signal ZERO). This can be done by connecting the second hold voltage source (VSS-M2) to the sense amplifier 20 (e.g., by turning on switch 23), as shown in FIG. 3B. FIG. 3B shows a schematic circuit of a sense amplifier selectively coupled to a second hold voltage source (VSS-M2) lower than VSS, and M2 can be a positive number. In one example, M2 can be in the range of 0.4V - 0.8V, such as 0.6V for example. Of course, when the second hold voltage source is coupled to the sense amplifier 20 during the RESTORE phase, the voltage source VSS is disconnected from the sense amplifier 20 (e.g., by turning off switch 24). When signal ZERO is originally in the storage capacitor 12, a voltage level of -0.6V is supplied to the storage capacitor during this RESTORE phase. That is, before the access transistor 11 in T3 of FIG. 2 is turned off (i.e., the word line WL is pulled down from VPP to the word line voltage in standby mode), a voltage level of the second hold voltage source lower than the normal voltage level of signal ZERO (VSS) is supplied to the storage capacitor 12. In one embodiment, after the access transistor 11 is turned off or after the RESTORE phase, the second hold voltage source (VSS-M2) can be disconnected from the sense amplifier 20.

[0051] Of course, in another embodiment, both the first and second hold voltage sources can be intentionally coupled to the capacitor of the DRAM cell during the RESTORE phase. Thus, before the word line WL is pulled down from VPP to the word line voltage in standby mode, if signal ONE is originally in the storage capacitor, a voltage level of 1.2V + 0.6V is stored in the storage capacitor, and if signal ZERO is originally in the storage capacitor, a voltage level of -0.6V is stored in the storage capacitor.

[0052] In order to maintain the stored charge without leakage through the access transistor, a design is usually carried out to give the access transistor a very high threshold voltage to reduce the leakage current. When VCCSA is lowered to 0.6V, tri-gate or FinFET transistors with a 7nm or 5nm process are adopted in the peripheral circuits of the DRAM design, and accordingly, the threshold voltages of these transistors can be scaled, for example, down to 0.3V. In this embodiment, the threshold voltage of the access transistor can be intentionally increased to 0.5 - 0.6V. Thus, the leakage current from the storage capacitor decreases sharply by at least 3 to 4 decades (=0.6 - 0.3~0.3V, when the S factor is 68mV / decade, the leakage can be reduced by 4 decades compared to that of the peripheral tri-gate device, and when the threshold voltage is increased to 0.5V, the leakage current should be 2 to 3 decades). It is proposed to increase the threshold voltage close to VCCSA or at least more than 80% of 0.6V. In the embodiment, the gate dielectric thickness of the access transistor (such as a finFET or a tri-gate transistor, etc.) can be maintained at that of the peripheral transistor without increasing its thickness, and the high-performance merit of using the tri-gate structure can be maintained.

[0053] Figure 4 shows the signal waveforms related to a DRAM cell according to another embodiment of the present invention. In this example, the level of signal ONE is 0.6V and the level of signal ZERO is 0V (GND). During the RESTORE phase after T2, a first holding voltage source is intentionally coupled to the capacitor of the DRAM cell during the RESTORE phase. The voltage level of the first holding voltage source is higher than VCCSA of 0.6V (or the voltage level of signal ONE). This can be done by connecting the first holding voltage source (VCCSA + K) to the sense amplifier, where K can be a positive number. In one example, K can be in the range from 1 / 3 of VCCSA to 2 / 3 of VCCSA, such as 0.3V or 0.4V for example. Thus, when signal ONE of 0.6V is originally in the storage capacitor, during this RESTORE phase, a voltage level of 0.6V + 0.4V is supplied to the storage capacitor. That is, before the access transistor in Figure 4 is turned off at T3 (i.e., the word line WL is pulled down from VPP to the word line voltage in standby mode), a voltage level of the first holding voltage source higher than the normal voltage level of signal ONE (VCCSA of 0.6V) is supplied to the storage capacitor. Therefore, after the word line WL is pulled up to VPP and before the word line is pulled down to standby mode or non - active mode, a voltage level of 1V is stored in the storage capacitor when signal ONE is originally in the storage capacitor. In one embodiment, after the RESTORE phase, as shown in Figure 4, the bit line (BL) and the bit line bar (BLB) can be coupled to a bit line voltage source having a voltage level of Vbl such that the voltage levels of the bit line (BL) and the bit line bar (BLB) are reset to Vbl.

[0054] Of course, as described above, before the word line WL is pulled down from VPP to the word line voltage in standby mode, if the signal ZERO was originally in the storage capacitor, the voltage level of the second holding voltage source can be stored in the storage capacitor, and the voltage level of the second holding voltage source is lower than the voltage level of the signal ZERO, for example, -0.4V or the like.

[0055] FIG. 5 shows another embodiment regarding the circuit and functional block diagram for the precharge operation. In this embodiment, VCCSA is set to 0.6V and VSS is set to 0V. In the precharge operation, all DRAM cells connected to the selected word line(s) within the memory section 5 (“Sec5”) are precharged, and the DRAM cells connected to the unselected word lines within other memory sections (e.g., “Sec4”, “Sec6”, etc.) are in an idle state.

[0056] The sense amplifiers 41 and 42 coupled to the DRAM cells connected to the selected word line(s) are kicked to the third holding voltage source VHSA (0.6V + K) by the precharge kicker 30, and as a result, a stronger drain-source electric field can accelerate the signal restoration to the cell. The third holding voltage source VHSA is higher than VCCSA (0.6V) by approximately several hundred mV, for example, 0.3V or 0.4V. Further, before the selected word line(s) is turned off (i.e., the access transistor of the DRAM cell coupled to the selected word line(s) is turned off), a voltage level of 0.6V + 0.4V, which is higher than the voltage level of the original signal ONE, can be stored in the storage capacitor. On the other hand, the sense amplifiers coupled to the DRAM cells connected to the unselected word line(s) are not kicked up and remain coupled to VCCSA.

[0057] FIG. 6 illustrates the operation of the sense amplifier for the precharge phase, and the meanings of the symbols used in FIG. 6 are as follows: VCCSA: Bit line sense amplifier voltage VHSA: Third maintenance voltage source LSLP: Selected bit line sense amplifier High voltage LSLN: Selected bit line sense amplifier Low voltage Vpl: Plate voltage SN: Storage node WL: Word line BL: Bit line Vsg1, Vsg2: Source-gate voltages of P1, P2 Vgs3, Vgs4: Gate-source voltages of N3, N4 Vsg5, Vsg6: Source-gate voltages of P5, P6 Vgs7, Vgs8: Gate-source voltages of N7, N8.

[0058] Referring to FIG. 6, word line WL100 is coupled to a plurality of storage nodes such as SN1 and SN9. When a signal ONE (0.6V) is stored in storage node SN1 connected to word line WL100, after a precharge command is issued and word line WL100 is selected (i.e., the word line is turned ON), LSLP of the sense amplifier is coupled to VHSA (1.0V). Thus, LSLP is kicked from 0.6V to 1.0V and LSLN remains at 0V. Accordingly, transistor P1 of the sense amplifier is OFF and Vsg1 = 0V. Also, transistor P2 of the sense amplifier is ON and Vsg2 is kicked from 0.6V to 1.0V, and 1.0V is fully charged to storage node SN1 via bit line BL1. On the other hand, transistor N3 of the sense amplifier is ON and Vgs3 is also kicked from 0.6V to 1.0V. Also, transistor N4 of the sense amplifier is OFF and Vgs4 is 0V.

[0059] When a signal ZERO (0V) is stored in the storage node SN9 connected to the word line WL100, after a precharge command is issued and the word line WL100 is selected, the sense amplifier is coupled to VHSA (1.0V). Thus, LSLP is kicked from 0.6V to 1.0V and LSLN remains at 0V. Accordingly, the transistor P5 of the sense amplifier is ON and Vsg5 is kicked from 0.6V to 1.0V. Also, the transistor P6 of the sense amplifier is OFF and Vsg2 is 0V. On the other hand, the transistor N7 of the sense amplifier is OFF and Vgs7 is 0V. Also, the transistor N8 of the sense amplifier is ON and Vgs8 is kicked from 0.6V to 1.0V, and 0V is strongly restored to the storage node SN9 via the bit line BL9. Naturally, as described above, when the signal ZERO is originally in the storage capacitor, LSLN can be coupled to another holding voltage source VLSN (0V - K) during the precharge phase. VLSN is lower than the voltage level of the signal ZERO, and in this case, VLSN can be -0.4V. Then, during the precharge phase, -0.4V is strongly restored to the storage node SN9 via the bit line BL9.

[0060] In another embodiment, as shown in FIG. 7, after T0, the word line voltage is ramped up to turn on the access transistor of the DRAM cell. And there is an active command to be executed in a normal READ or WRITE access of the DRAM. To reduce tRCD defined by JEDEC, during the execution of the active command, a corresponding voltage slightly higher than VCCSA (e.g., VCCSA+ΔN, etc.) can be connected to the sense amplifier (by turning off switch 14 shown in FIG. 3A and turning on switch 13). Such a voltage level or voltage source is coupled to the bit line during the period between T1 and T2 (i.e., the access operation period). Therefore, the corresponding voltage (VCCSA+ΔN) can be connected to the sense amplifier according to the active command. Thus, the signal of the bit line is pumped (or kicked) to at least VCCSA+ΔN during the execution of the active command. Such a pump or kick in the bit line signal can be called an active kick. Such an active kick to the bit line speeds up signal sensing. After the execution of the active command or active kick, the normal voltage source VCCSA is connected to the sense amplifier, and in the subsequent READ or WRITE operation, the signal of the bit line returns to VCCSA. Similarly, in the RESTORE (or precharge) phase after T2, a first holding voltage source VCCSA+M1 (or a different holding voltage higher than VCCSA) is re-coupled to the capacitor of the DRAM cell during this RESTORE phase. That is, during this RESTORE (or precharge) phase, the original VCCSA voltage source is disconnected from the sense amplifier (e.g., by turning off switch 14 shown in FIG. 3A), and the first holding voltage source VCCSA+M1 is connected to the sense amplifier 20 (e.g., by turning on switch 13 shown in FIG. 3A). The signal of the bit line is pumped (or kicked) to at least VCCSA+M1. Such a pump or kick in the bit line signal can be called a restore kick.Thus, before the word line WL is pulled down to completely turn off the access transistor of the DRAM cell, a voltage level of a first holding voltage source higher than the voltage level of a normal signal ONE (VCCSA) is supplied to the storage capacitor of the DRAM cell, and even if there is a leakage current in the access transistor, the storage capacitor of the DRAM cell can be sustained over a longer period compared to the conventional DRAM structure.

[0061] In one embodiment, the corresponding voltage (VCCSA + ΔN) used for the active kick is lower than the first holding voltage (VCCSA + M1) used for the restore kick. In another embodiment, the corresponding voltage (VCCSA + ΔN) used for the active kick is the same as or substantially the same as the first holding voltage (VCCSA + M1) used for the restore kick. The corresponding voltage (VCCSA + ΔN) and the first holding voltage (VCCSA + M1) can be generated from two different voltage sources, respectively. Alternatively, the corresponding voltage (VCCSA + ΔN) used for the active kick to kick the voltage of the bit line can be generated from the first holding voltage source (VCCSA + M1), but the duration of connecting the first holding voltage source (VCCSA + M1) to the bit line is adjusted so that the bit line is only pumped or kicked to the corresponding voltage (VCCSA + ΔN) instead of (VCCSA + M1). Of course, in the present invention, the voltage (VCCSA + M1), the voltage (VCCSA + ΔN), and the voltage (VCCSA) may be generated or converted inside the DRAM, or supplied or converted from other voltage sources outside the DRAM chip. Also, raising the bit line to the voltage level VCCSA + ΔN or VCCSA + M1 during the active kick can be performed by a bootstrap circuit, and the charge of the capacitor in the bootstrap circuit is coupled to the bit line. Whether it is a voltage source or a bootstrap circuit, it can be regarded as a charge source, and thus, during the active kick, the bit line can be kicked or pumped to the voltage level VCCSA + ΔN or VCCSA + M1 by the charge source.

[0062] Figure 8A shows the related signal waveforms regarding the operation of a DRAM cell according to another embodiment of this invention. During the period between T1 and T2, there is an active command to be executed, and the corresponding first hold voltage source (VCCSA+M1) can be connected to the sense amplifier during the active operation. Therefore, the signals on the bit lines are pumped (or kicked) to at least VCCSA+M1 during the active command. After the execution of the active command, the normal voltage source VCCSA is connected to the sense amplifier, and the signals on the bit lines return to VCCSA. After the active command, one (or more) read commands can be executed before T2, and the first hold voltage source (VCCSA+M1) can be reconnected to the sense amplifier during the read command so that the signals on the bit lines are pumped (or kicked) to at least VCCSA+M1 during the read command. After the execution of the read command, the normal voltage source VCCSA is reconnected to the sense amplifier (by turning off switch 13 and turning on switch 14 as shown in Figure 3A), and the signals on the bit lines return to VCCSA. Such a kick to the bit lines during the read command improves the signal propagation time. For example, when VCCSA is 1.1V and M1 is 0.2V, the signal propagation time with a kick during the read command is about 20%-30% faster than that without a kick.

[0063] Similarly, in the RESTORE phase after T2, the original VCCSA voltage source is disconnected from the sense amplifier, the first hold voltage source VCCSA+M1 is connected to the sense amplifier 20, and the signals on the bit lines are pumped (or kicked) to at least VCCSA+M1. Therefore, the voltage level of the first hold voltage source higher than the normal signal ONE voltage level (VCCSA) is supplied to the storage capacitor of the DRAM cell. However, in another embodiment, as shown in Figure 8B, in the RESTORE phase after T2, the original VCCSA voltage source (instead of VCCSA+M1) is still connected to the sense amplifier.

[0064] In another embodiment, during an active command, the signal on the bit line is not kicked to VCCSA+M1, but during a read command, the signal on the bit line is kicked to VCCSA+M1. As shown in FIG. 8C, during the RESTORE phase after T2, a first holding voltage source VCCSA+M1 is connected to the sense amplifier so that the signal on the bit line is pumped (or kicked) to at least VCCSA+M1.

[0065] FIG. 8D shows the relevant signal waveforms for the operation of a DRAM cell according to another embodiment of the present invention. Similar to FIG. 8A, during the period between T1 and T2, there is an active command to be executed and at least one read command following the active command, and during the active operation and the read command, the corresponding first holding voltage source (VCCSA+M1) can be connected to the sense amplifier (by turning on switch 13 shown in FIG. 3A). Further, during the active operation and the read command, the corresponding second holding voltage source (VSS-M2) can be connected to the sense amplifier (by turning on switch 23 shown in FIG. 3B). Therefore, during the active command and the read command, the signal on the bit line (BL) is pumped (or kicked) to at least VCCSA+M1, and the signal on the bit line bar (BLB) is pumped (or kicked) to at least VSS-M2. After the execution of the active command and the read command, the normal voltage source VCCSA is connected to the sense amplifier (by turning off switch 13 shown in FIG. 3A and turning on switch 14) and the normal voltage source VSS is connected to the sense amplifier (by turning off switch 23 shown in FIG. 3B and turning on switch 24), and the signal on the bit line returns to VCCSA and the signal on the bit line bar returns to VSS.

[0066] Similarly, in the RESTORE phase after T2, the original VCCSA and VSS voltage sources are disconnected from the sense amplifier (e.g., by turning off switches 14 and 24 in FIGS. 3A and 3B, respectively), the first maintenance voltage source VCCSA+M1 is connected to the sense amplifier 20 (by turning on switch 13 in FIG. 3A), and the second maintenance voltage source VSS-M2 is connected to the sense amplifier 20 (by turning on switch 23 in FIG. 3B). Then, the signals on the bit lines are pumped (or kicked) to at least VCCSA+M1, and the signals on the complementary bit lines are pumped (or kicked) to at least VSS-M2.

[0067] FIG. 8E shows the relationship between the kick period and the signals on the bit lines in the operation of a DRAM cell. The kick period of the signals on the bit lines corresponding to the RESTORE phase (or precharge) K4 can be longer than that corresponding to the active command K1, or longer than that corresponding to the read commands K2 or K3. Also, the kick period of the signals on the bit lines corresponding to the active command K1 is equal to that corresponding to the read commands K2 or K3. Naturally, during the periods of K1-K3, raising the signals on the bit lines to the voltage level VCCSA+M1 or another voltage level (e.g., VCCSA+ΔN, where ΔN<M1, etc.) can be done by a bootstrap circuit, and the charge of the capacitor in the bootstrap circuit is coupled to the bit lines. Whether it is a voltage source or a bootstrap circuit, it can be regarded as a charge source. Therefore, the signals on the bit lines can be kicked or pumped to the voltage level VCCSA+M1 or VCCSA+ΔN by the charge source. The same is true for the signals on the bit lines kicked to VSS-M2 (or VSS-ΔN, where ΔN<M2).

[0068] Of course, in another embodiment, VCCSA can be in the range of 0.9V - 0.5V (for example, 0.9V, 0.8V, 0.7V, or 0.6V, etc.) or lower, and the kick voltage VCCSA+M1 can still be in the range of 1.1V - 2.5V (for example, 1.1V, 1.2V, 1.35V, 1.5V, 1.8V, or 2.5V, etc.) to solve the leakage problem and maintain an acceptable retention time in the DRAM cell. Therefore, since the leakage problem in the DRAM circuit is reduced according to the present invention, even if there is a slowdown in DRAM technology migration, the main power supply voltage to the DRAM chip can be reduced to 1.0V - 0.5V or lower. Thus, the main power supply voltage to the DRAM chip can be the same as or substantially the same as the main power supply voltage to the logic circuit chip.

[0069] As shown in FIG. 9A, the DRAM circuit 500 includes an I / O circuit 510, a peripheral circuit 520, and a DRAM core circuit 530. There is a physical layer circuit 400 between the DRAM 500 and the logic circuit 300. The physical layer circuit 400 further includes an I / O physical circuit 410 and a logic physical circuit 420. Usually, the DRAM circuit 500 is within a DRAM chip, and the physical layer circuit 400 and the logic circuit 300 are located in other chips (such as a logic chip, etc.) separate from the DRAM chip. For example, the logic chip includes a memory controller which is the logic circuit 300, and also includes a physical layer circuit (or PHY circuit) 400 that interacts with the DRAM chip and the memory controller.

[0070] In another embodiment, the physical layer circuit 400 and the logic circuit 300 may be located in two separate chips respectively. For example, the DRAM circuit 500 may include a plurality of stacked DRAM chips. And the stacked DRAM chips are positioned on a base chip (or interposer) including the physical layer circuit (or PHY layer) 400. The logic circuit 300 is a digital circuit or a memory controller located in a logic chip separate from the base chip.

[0071] According to the present invention, the main power supply voltage Vnew to the DRAM circuit 500 can be in the range of 1.0V - 0.5V (or 0.9V - 0.5V) or less, which is exactly the same as the main power supply voltage Va' to the logic chip or circuit 300 that has already been in the range of 1.0V - 0.5V (or 0.9V - 0.5V) or less due to the high-speed scale-down logic technology migration. The main power supply voltage Vnew is external to the DRAM circuit 500 and can be used by the DRAM circuit 500 to generate various voltage sources used in the peripheral circuit 520 or the DRAM core circuit 530, such as the aforementioned voltage sources VCCSA, VCCSA + M1, 1 / 2VCCSA, VPP, etc. The level of VCCSA may be the same as or different from the level of the main power supply voltage Vnew to the DRAM circuit. Also, another supply voltage V high may exist outside the DRAM circuit 100, and another supply voltage V high is higher than the main power supply voltage Vnew and can be used to generate the voltage source Vpp or VCCSA + M1 for the purpose of conversion efficiency.

[0072] Also, since the value of the main power supply voltage Vnew to the DRAM circuit 500 is the same as or substantially the same as the value of the main power supply voltage Va' to the logic circuit 300, the output level conversion circuit (which levels up or down the voltage level of the output signal) and the input comparator in the I / O circuit 110 of the traditional DRAM circuit 100 can be removed or omitted. Therefore, according to the present invention shown in FIG. 9B, the I / O circuit 510 of the DRAM circuit 500 does not include the aforementioned output level conversion circuit and input comparator, and the input / output data signals to or from other DRAM circuits (such as the peripheral circuit 520, etc.) are not necessarily converted or compared by the I / O circuit 510. Also, the signal swing of the input / output data signals to or from other DRAM circuits can be set to the level of the main power supply voltage Vnew.

[0073] As described above, the DRAM circuit 500 includes an I / O circuit 510, a peripheral circuit 520, and a DRAM core circuit 530. The peripheral circuit 520 has at least a command / address decoder and / or other circuits including transistors, and the DRAM core circuit 530 has at least a cell array and / or other related circuits including transistors. Based on the present invention, the operating supply voltage to the drain side of the transistors in the peripheral circuit can be the same as the voltage level of the main power supply voltage source Vnew to the DRAM chip. Also, the operating supply voltage to the drain side of the transistors in the DRAM core circuit that are not access transistors can be the same as the voltage level of the main power supply voltage source to the DRAM chip. Naturally, the voltage level corresponding to the signal ONE or the signal High used in the DRAM chip can be the same as the voltage level of the main power supply voltage source Vnew to the DRAM chip.

[0074] Similarly, according to the present invention shown in FIG. 9C, the I / O physical circuit 410 of the physical layer circuit 400 can also remove the aforementioned output level conversion circuit (for level - up or level - down of the voltage level of the output signal) and the input comparator. The signals of the input / output data to or from other physical layer circuits (such as the logic physical circuit 420, etc.) are not necessarily converted or compared by the I / O circuit 410 of the physical layer circuit 400. Also, the signal swing of the input / output data to or from other physical layer circuits can be set to the level of the main power supply voltage Va’ (i.e., Vnew).

[0075] Therefore, based on the present invention, the levels of the main power supply voltage to the logic circuit 300, the physical layer circuit 400, and the DRAM circuit 500 can all be the same. When the DRAM circuit 500 is located within the DRAM chip and the physical layer circuit 400 and the logic circuit 300 are located within other logic chips separate from the DRAM chip, the level of the main power supply voltage to the DRAM chip is the same as the level of the main power supply voltage to the logic chip.

[0076] The I / O physical circuit 410 of the physical layer circuit 400 and the DRAM circuit 500 are located within the DRAM chip, and the logic physical circuit 420 and the logic circuit 300 of the physical layer circuit 400 can be located within another logic chip. Even in this case, the level of the main power supply voltage to the DRAM chip is the same as the level of the main power supply voltage to the logic chip.

[0077] In another case, when the logic circuit 300, the physical layer circuit 400, and the DRAM circuit 500 are located within a logic chip, a base chip (or an interposer), and a DRAM chip, respectively, the level of the main power supply voltage to the DRAM chip is the same as the level of the main power supply voltage to the base chip and is also the same as the level of the main power supply voltage to the logic chip.

[0078] As described above, in low-power applications, it is necessary to lower the voltage levels of the data path of the DRAM cell, the bit line, and / or the write data on the storage node. However, if the voltage stored in the corresponding storage node is low, it will suffer from serious leakage problems and may cause data corruption. Kicking up the voltage level of the bit line during the restore phase according to the present invention can be applied to the data write operation for power saving. FIG. 10 shows the related signal waveforms in the WRITE operation of a DRAM cell according to another embodiment of the present invention, and FIG. 11 shows a schematic circuit of a sense amplifier selectively coupled to two separate voltage sources VCCSA and VCCSAh in the WRITE operation of a DRAM cell, where the voltage level of VCCSAh is higher than that of VCCSA. When the write data XIO (e.g., signal ONE or signal High) shown in FIG. 1F is input to the global I / O path GIO via the data input circuit DI, the voltage level of the write data on the global I / O path GIO is maintained as VCCSA (e.g., 0.7V, etc.) for power saving. However, the voltage level of the write data XIO corresponding to the signal ONE (or signal High) can be higher than VCCSA, such as VSSCAh, for example. Then, the write data on the global I / O path GIO is passed to the data line DL via the data line sense amplifier. As shown in FIG. 10, the voltage level of the write data on the data line DL is also maintained as the voltage level VCCSA by the data line sense amplifier 70. In this embodiment of FIG. 10, for power saving, the voltage level of VCCSA is set to 0.7V (but not limited to this). Then, the write data on the data line DL is passed to the corresponding bit line BL in the memory array. As shown in FIG. 11, in the memory array 75, when the word line WL66 corresponding to the storage node SN is selected to turn on the access transistor 66, two separate voltage sources, VCCSA (e.g., 0.7V) and VCCSAh (e.g., 1.1V) higher than VCCSA, are selectively coupled to the cross-coupled sense amplifier 80 at different times.After word line WL66 is selected, first, voltage source VCCSA is coupled to cross-coupled sense amplifier 80, and bit switch BS100 is turned on to write data (i.e., signal ONE) to access transistor 66. Therefore, the voltage level of bit line BL also rises to VCCSA. On the other hand, as should be understood by those skilled in the art, signals EN1 and EN2 are enabled, and signal EN3 is disabled. As shown in FIG. 10 with respect to the signal waveforms, the voltage level of bit line BL is maintained at VCCSA for a while, but after the end of period tWR (write recovery time), during the restoration phase, the voltage level on the bit line is kicked up to VCCSAh (or called "restore kick"). Period tWR can refer to the DRAM specification defined by JEDEC (Joint Electron Device Engineering Council), which is the rising edge of the Last Write CLK for the precharge command. This tWR (write recovery time) ensures that the restore kick from the precharge command can only start after the write cycle is completed.

[0079] Therefore, as shown in FIG. 10, after the end of period tWR, the voltage level of bit line BL is kicked up to VCCSAh (i.e., restore kick). In this embodiment of FIG. 10, the voltage level of VCCSAh is equal to 1.1V, which is higher than VCCSA (however, it is not limited to this). On the other hand, referring to FIGS. 10 and 11 simultaneously, before word line WL66 corresponding to storage node SN is turned off, voltage source VCCSAh is coupled to cross-coupled sense amplifier 80, bit line BL, and thus storage node SN. As a result, even if the voltage levels of global I / O path GIO and data line DL during the WRITE operation are VCCSA, the voltage level of bit line BL is kicked up from VCCSA to VCCSAh, and sufficient charge is stored in storage node SN based on the restore kick to VCCSAh.

[0080] Since the voltage level of the bit line BL is kicked up from VCCSA (0.7V or another voltage level lower than 1.1V) to VCCSAh (1.1V), the present invention can clearly solve the leakage problem of the prior art. That is, even if the voltage levels of the write data on the global I / O path GIO, the data line DL, and the bit line BL are lowered to 0.7V, 0.6V, or lower, the corresponding storage node can store sufficient charge based on the restoration kick to VCCSAh, so the present invention will still not be troubled by the leakage problem and data damage. As shown in FIG. 12, in the write operation, the voltage levels of the write data on the global I / O path GIO, the data line DL, and the bit line BL can be lowered to 0.7V (even further to 0.6V or lower), and as a result, the operating current is also lowered. For example, when the voltage levels of the write data on the global I / O path GIO, the data line DL, and the bit line BL are reduced (35% reduction) from 1.1V to 0.7V, the operating current will be reduced from 141mA to 35mA. Here, the operating current of 141mA corresponds to the case where the voltage levels of the write data on the global I / O path GIO, the data line DL, and the bit line BL are maintained at 1.1V.

[0081] On the other hand, in the read operation, when the read data corresponds to the signal ONE (or the signal High), in one embodiment of the present invention, the voltage levels of the read data on the global I / O path GIO and the data line DL can be made higher than VCCSA, such as VSSCAh for example. For example, as shown in FIG. 12, the voltage levels of the read data (corresponding to the signal ONE) on the global I / O path GIO and the data line DL are set to 1.1V, which is higher than the voltage levels of the write data (corresponding to the signal ONE) on the global I / O path GIO and the data line DL set to VCCSA (for example, 0.7V). Similarly, the voltage levels of the control signal and / or the address signal for the DRAM operation are also set to 1.1V, which is higher than the voltage levels of the write data (corresponding to the signal ONE) on the global I / O path GIO and the data line DL (when corresponding to the signal ONE).

[0082] Therefore, the voltage swings on the global I / O path GIO and the data line DL (or data path) in the read operation are different from those on the global I / O path GIO and the data line DL (or data path) in the write operation. In particular, the voltage swing of the read data set (including signal ONE and signal ZERO) on the global I / O path GIO and / or the data line DL is higher than the voltage swing of the write data set (including signal ONE and signal ZERO) on the global I / O path GIO and / or the data line DL. Also, the voltage swings of the control signals and address signals for DRAM operations (such as read operations, write operations, or other operations) according to the present invention are different from or higher than the voltage swing on the data path in the write operation.

[0083] Summarizing the above description, this invention discloses a sustainable DRAM having a unified main power supply voltage unified with a logic circuit. Before the access transistor of the DRAM storage cell is turned off (or the word line coupled to the DRAM storage cell is turned off), a first holding voltage higher than the voltage level of signal ONE (or signal high) can be restored or stored in the DRAM storage cell. After the access transistor is turned off, even if there is a leakage current in the access transistor, the storage capacitor can last for a long period compared to the conventional DRAM structure. Since the leakage problem in the DRAM circuit is reduced, even if there is a slowdown in the DRAM technology transition, the main power supply voltage to the DRAM chip can be reduced to 1.0V - 0.5V or lower. Therefore, the main power supply voltage to the DRAM chip can be the same as or substantially the same as the main power supply voltage to the logic circuit chip. Also, the compatibility of the power supply voltage between the DRAM chip and the logic chip leads to the optimization of energy efficiency and performance synchronization, not only increasing the operating speed but also saving die area and power. Furthermore, the voltage swing of the write data on the data path is lower than the voltage swing of the read data on the data path, and thus the current or power for the write operation is reduced.

[0084] As will be immediately apparent to those skilled in the art, numerous changes and modifications of the apparatus and method can be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as being limited only by the scope of the appended claims.

Claims

1. 1. A DRAM chip configured for coupling to an external logic circuit and for coupling to a main power supply voltage source, comprising: a first sustain voltage generator for generating a first voltage level higher than a voltage level corresponding to a signal ONE used in the DRAM chip; a DRAM core circuit having a DRAM cell having an access transistor and a storage capacitor; having the storage capacitor of the DRAM cell is configured to be selectively coupled to the first sustain voltage generator; the voltage level of the main power supply voltage to the DRAM chip is the same or substantially the same as the voltage level of the main power supply voltage to the external logic circuitry external to the DRAM chip, the voltage level of the main power supply voltage to the DRAM chip being between 0.9V-0.5V; DRAM chip.

2. 2. The DRAM chip of claim 1, further comprising I / O circuitry and peripheral circuitry between the I / O circuitry and the DRAM core circuitry, wherein an operating supply voltage to a drain side of a transistor in the peripheral circuitry is the same as the voltage level of the main power supply voltage source to the DRAM chip.

3. 3. The DRAM chip of claim 2, wherein an operating supply voltage to the drain side of transistors in said DRAM core circuitry that are not said access transistors is the same as said voltage level of said main power supply voltage source to said DRAM chip.

4. 4. The DRAM chip of claim 3, wherein the voltage level corresponding to the signal ONE used in the DRAM chip is the same as the voltage level of the main power supply voltage source to the DRAM chip.

5. 2. The DRAM chip of claim 1, further comprising an I / O circuit and a peripheral circuit between the I / O circuit and the DRAM core circuit, the I / O circuit not including an input comparison circuit and an output level conversion circuit.

6. 2. The DRAM chip of claim 1, further comprising a word line coupled to a gate terminal of the access transistor, the word line being selected to turn on the access transistor for a first period and a second period after the first period, and the first sustain voltage generator being electrically coupled to the storage capacitor of the DRAM cell during the second period.

7. 7. The DRAM chip of claim 6, wherein the first period is an access operation period and the second period is a restore phase period.

8. 8. The DRAM chip of claim 7, wherein a kick charge source is electrically coupled to a bit line of the DRAM chip during the access operation.

9. 1. A DRAM chip configured to couple to an external logic circuit and to a main power supply voltage source, comprising: a DRAM core circuit having a DRAM cell having an access transistor and a storage capacitor; an I / O circuit configured to couple to the external logic circuit; a peripheral circuit between the I / O circuit and the DRAM core circuit; having a voltage level of the main power supply voltage source to the DRAM chip is the same or substantially the same as a voltage level of a main power supply voltage source to the external logic circuit, the voltage level of the main power supply voltage source to the DRAM chip being 0.9V or less; the external logic circuit is located on a logic chip separate from the DRAM chip; DRAM chip.

10. 10. The DRAM chip of claim 9, wherein an operating supply voltage to the drain side of transistors in the peripheral circuitry is the same as the voltage level of the main power supply voltage source to the DRAM chip.

11. 11. The DRAM chip of claim 10, wherein an operational supply voltage to the drain side of transistors in said DRAM core circuitry that are not said access transistors is the same as said voltage level of said main power supply voltage source to said DRAM chip.

12. 12. The DRAM chip of claim 11, wherein a voltage level corresponding to signal ONE used in the DRAM chip is the same as the voltage level of the main power supply voltage source to the DRAM chip.

13. 10. The DRAM chip of claim 9, wherein the I / O circuit does not include an input comparison circuit and an output level conversion circuit.

14. a first sustain voltage generator for generating a first voltage level higher than a voltage level corresponding to a signal ONE used in the DRAM chip; 10. The DRAM chip of claim 9, further comprising: a word line coupled to a gate terminal of the access transistor, the word line being selected to turn on the access transistor for a first period and a second period after the first period; and the first sustain voltage generator being electrically coupled to the storage capacitor of the DRAM cell during the second period.

15. 15. The DRAM chip of claim 14, wherein the first period is an access operation period and the second period is a restore phase period.

16. A DRAM chip; a logic chip electrically coupled to the DRAM chip; having a voltage level of a main power supply voltage source to the DRAM chip is the same or substantially the same as a voltage level of a main power supply voltage source to the logic chip, and the voltage level of the main power supply voltage source to the DRAM chip is 0.9V or less; Memory system.

17. 17. The memory system of claim 16, wherein the DRAM chip includes a DRAM circuit, the logic chip includes a logic circuit and a physical layer circuit, the main power supply voltage source to the DRAM chip is supplied to the DRAM circuit, and the main power supply voltage source to the logic chip is supplied to the logic circuit and the physical layer circuit.

18. 17. The memory system of claim 16, further comprising a base chip electrically coupled to the DRAM chip, wherein the voltage level of the main power supply voltage source to the DRAM chip is the same or substantially the same as the voltage level of the main power supply voltage source to the base chip.

19. 20. The memory system of claim 18, wherein the DRAM chip includes a DRAM circuit, the logic chip includes a logic circuit, the base chip includes a physical layer circuit, the main power supply voltage source to the DRAM chip is supplied to the DRAM circuit, the main power supply voltage source to the logic chip is supplied to the logic circuit, and the main power supply voltage source to the base chip is supplied to the physical layer circuit.

20. 17. The memory system of claim 16, wherein the DRAM chip comprises a DRAM cell and a first sustain voltage generator, the DRAM cell having a storage capacitor and an access transistor, the first sustain voltage generator generating a first voltage level higher than a voltage level corresponding to a signal ONE used in the DRAM chip, the first sustain voltage generator being coupled to the storage capacitor of the DRAM cell before the access transistor of the DRAM cell is turned off.

21. 21. The memory system of claim 20, wherein the DRAM chip further comprises I / O circuitry and peripheral circuitry between the I / O circuitry and the DRAM cells, the I / O circuitry not including input comparison circuitry and output level translation circuitry.

22. 20. The memory system of claim 16, further comprising a physical layer circuit having an I / O physical circuit, the I / O physical circuit not including an input compare circuit and an output level translation circuit.

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