Drive circuit for bridge circuit, motor drive device using the same, and electronic apparatus

Abstract

To provide a drive circuit capable of versatilely correcting the influence of dead time.SOLUTION: A high-side driver circuit 450 sources an ON current IHG_ON of a predetermined current volume when a high-side control signal HGCTL is at an ON level and a first feedback signal S1 is asserted, and sinks an OFF current IHG_OFF from a gate of a high-side transistor MH when the high-side control signal HGCTL is at an OFF level. A correction circuit 460 measures a pulse width Ta of an input signal PWMIN in a first mode. After the lapse of a time Ta / 2 that is 1 / 2 the pulse width Ta from when a second feedback signal S2 is asserted, the correction circuit 460 changes the high-side control signal HGCTL to the OFF level.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present disclosure relates to a drive circuit for a bridge circuit.

Background Art

[0002] In motor driver circuits, DC / DC converters, power conversion devices, etc., half-bridge circuits, H-bridge circuits, and three-phase bridge circuits (hereinafter collectively referred to as bridge circuits) using power transistors are frequently used.

[0003] A bridge circuit includes an upper arm and a lower arm provided in series between a power supply terminal and a ground terminal. The upper arm includes a high-side transistor and a flywheel diode connected in parallel. The lower arm includes a low-side transistor and a flywheel diode connected in parallel.

[0004] The bridge circuit can be switched between a high output state in which the high-side transistor is on and the low-side transistor is off, and a low output state in which the high-side transistor is off and the low-side transistor is on. When transitioning between the high output state and the low output state, if the high-side transistor and the low-side transistor are turned on simultaneously, an undesirable through current flows. To prevent this, the bridge circuit passes through a high impedance state in which both the high-side transistor and the low-side transistor are off during the transition between the high output state and the low output state. The period during which this bridge circuit is in the high impedance state is called dead time.

[0005] Consider the PWM (Pulse Width Modulation) control of the bridge circuit. Ideally, when the command value of the duty cycle of the PWM signal is d (0 ≦ d ≦ 1), the effective output voltage (time average) V OUT of the bridge circuit is V OUT = V IN × d …(1) where V INis the input voltage of the bridge circuit.

[0006] However, when dead time is inserted, the effective output voltage V of the bridge circuit OUT deviates from the value of Equation (1). Patent Document 1 discloses a technique for correcting the error in the effective value of the output voltage V OUT caused by dead time.

Prior Art Documents

Patent Documents

[0007]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0008] The technique described in Patent Document 1 was premised on the fact that the off-time of the high-side transistor and the off-time of the low-side transistor are equal, and that the gate voltages of the high-side transistor and the low-side transistor each transition with a constant slope.

[0009] However, depending on the configuration of the drive circuit of the bridge circuit, these premises may not hold.

[0010] The present disclosure has been made in view of such problems, and an exemplary object of one aspect thereof is to provide a drive circuit that can generally correct the influence of dead time.

Means for Solving the Problems

[0011] Certain aspects of the present disclosure relate to a drive circuit for driving a bridge circuit having a high-side transistor connected between a power line and an output line and a low-side transistor connected between the output line and a ground line. The drive circuit includes a first sensor that generates a first feedback signal that is asserted when the low-side transistor is off, a second sensor that generates a second feedback signal that is asserted in response to a change in the output voltage of the bridge circuit, a correction circuit that receives an input signal indicating the output of the bridge circuit, the first feedback signal, and the second feedback signal and generates an actual drive signal, and a high-side driver circuit configured to source an on-current of a predetermined current amount to the gate of the high-side transistor when the actual drive signal is at an on-level and the first feedback signal is asserted, and to sink an off-current of a predetermined current amount from the gate of the high-side transistor when the actual drive signal is at an off-level.

[0012] The correction circuit supports at least one of a first mode to a third mode.

[0013] In the first mode, when the input signal transitions to an on-level, the correction circuit changes the actual drive signal to an on-level, measures the pulse width Ta of the input signal, and changes the actual drive signal to an off-level after a lapse of Ta / 2, which is half of the pulse width Ta, after the second feedback signal is asserted.

[0014] When supporting the second mode or the third mode, the drive circuit may be provided with a third sensor that generates a third feedback signal that is asserted when the high-side transistor is fully on.

[0015] In the second mode, when the input signal transitions to the on level, the correction circuit changes the actual drive signal to the on level, measures the time Tb from when the input signal transitions to the on level until the second feedback signal is asserted, and when the time from when the second feedback signal is asserted until the third feedback signal is asserted is Tc, after the input signal transitions to the off level and after the elapse of the time Tb - Tc, the correction circuit changes the actual drive signal to the off level.

[0016] In the third mode, when the input signal transitions to the on level, the correction circuit changes the actual drive signal to the on level, measures the time Td from when the input signal transitions to the on level until the second feedback signal is asserted, when the time from when the second feedback signal is asserted until the input signal transitions to the off level is Te, and when the time from when the input signal transitions to the off level until the third feedback signal is asserted is Tf, after the high-side transistor is fully on and after the elapse of the time Td - Te - 2Tf, the correction circuit changes the actual drive signal to the off level.

[0017] In addition, combinations of the above components arbitrarily, and those in which components and expressions are mutually replaced among methods, apparatuses, systems, etc. are also effective as aspects of the present invention.

Advantages of the Invention

[0018] According to an aspect of the present disclosure, it is possible to generally correct the influence of dead time.

Brief Description of the Drawings

[0019]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Embodiments for Carrying Out the Invention

[0020] (Overview of the Embodiment) The overview of some exemplary embodiments of the present disclosure will be described. This overview is for the purpose of providing a basic understanding of the embodiments as a prelude to the detailed description to follow, and simplifies and explains some concepts of one or more embodiments. It does not limit the scope of the invention or the disclosure. For convenience, "one embodiment" may be used to refer to one embodiment (example or variation) or a plurality of embodiments (examples or variations) disclosed in this specification.

[0021] This summary is not an extensive overview of all possible embodiments, nor is it intended to identify key elements of all embodiments or to delineate the scope of some or all aspects. Its sole purpose is to present, in a simplified form, some concepts of one or more embodiments as a prelude to the more detailed description that follows.

[0022] A drive circuit according to an embodiment drives a bridge circuit having a high-side transistor connected between a power supply line and an output line and a low-side transistor connected between the output line and a ground line. The drive circuit includes a first sensor that generates a first feedback signal asserted when the low-side transistor turns off, a second sensor that generates a second feedback signal asserted in response to a change in the output voltage of the bridge circuit, a correction circuit that receives an input signal indicating the output of the bridge circuit, the first feedback signal, and the second feedback signal and generates an actual drive signal, and a high-side driver circuit configured to source a predetermined amount of on-current to the gate of the high-side transistor when the actual drive signal is at an on-level and the first feedback signal is asserted, and to sink a predetermined amount of off-current from the gate of the high-side transistor when the actual drive signal is at an off-level. In the first mode, when the input signal transitions to the on-level, the correction circuit changes the actual drive signal to the on-level, measures the pulse width Ta of the input signal, and changes the actual drive signal to the off-level after a lapse of time Ta / 2, which is half of the pulse width Ta, after the second feedback signal is asserted.

[0023] According to this configuration, in a case where the pulse width of the input signal is very narrow and the input signal transitions to the off-level before the output voltage of the bridge circuit changes, the influence of dead time can be corrected.

[0024] In one embodiment, the drive circuit may further include a third sensor that generates a third feedback signal that is asserted when the high-side transistor is fully on. In the second mode, when the input signal transitions to the on level, the correction circuit changes the actual drive signal to the on level, measures the time Tb from when the input signal transitions to the on level until the second feedback signal is asserted, and when the time from when the second feedback signal is asserted until the third feedback signal is asserted is Tc, after the input signal transitions to the off level, the correction circuit may change the actual drive signal to the off level after the elapse of time Tb - Tc.

[0025] According to this configuration, in a case where the output voltage of the bridge circuit changes and further, after the high-side transistor is fully on, the input signal transitions to the off level, the influence of the dead time can be corrected.

[0026] In one embodiment, in the third mode, when the input signal transitions to the on level, the correction circuit changes the actual drive signal to the on level, measures the time Td from when the input signal transitions to the on level until the second feedback signal is asserted, when the time from when the second feedback signal is asserted until the input signal transitions to the off level is Te, and when the time from when the input signal transitions to the off level until the third feedback signal is asserted is Tf, after the high-side transistor is fully on, the correction circuit may change the actual drive signal to the off level after the elapse of time Td - Te - 2Tf.

[0027] According to this configuration, after the output voltage V of the bridge circuit changes and before the high-side transistor is fully on, in a case where the input signal transitions to the off level, the influence of the dead time can be corrected. OUT

[0028] In one embodiment, the first sensor may assert the first feedback signal when the gate voltage of the low-side transistor falls below the first threshold voltage.

[0029] ​ In one embodiment, the second sensor may assert a second feedback signal when the output voltage exceeds a second threshold voltage.

[0030] In one embodiment, the third sensor may assert a third feedback signal when the gate voltage of the high-side transistor exceeds a third threshold voltage.

[0031] In one embodiment, the correction circuit may include a timer circuit that generates a turn-off trigger for transitioning the actual drive signal to an off level.

[0032] In one embodiment, the timer circuit includes a capacitor, a charging circuit that charges the capacitor with a first current, a discharging circuit that discharges the capacitor with a second current, where the second current can be switched between the same first current amount as the first current and a current amount twice the first current amount, and a comparison circuit that compares the voltage of the capacitor with a threshold voltage corresponding to the initialization voltage of the capacitor and generates a turn-off trigger.

[0033] In one embodiment, the comparison circuit may include an impedance element provided on the path of the first current and a voltage comparator. The timer circuit may apply an initialization voltage based on the voltage drop of the impedance element to the capacitor prior to the start of the timer operation, and the voltage comparator may compare the voltage of the capacitor with a threshold voltage based on the voltage drop of the impedance element.

[0034] In one embodiment, the voltage comparator may be configured such that the input offset voltage is adjustable. Thereby, the influence of the propagation delay can be canceled according to the input offset voltage.

[0035] In one embodiment, the comparison circuit may include a first field-effect transistor whose gate is connected to a capacitor, and a second field-effect transistor that is of the same type as the first field-effect transistor and whose gate and drain are connected. The timer circuit may apply, to the capacitor, an initialization voltage based on the voltage drop of the second field-effect transistor in a state where a first current flows through the second field-effect transistor prior to the start of the timer operation.

[0036] (Embodiment) Hereinafter, preferred embodiments will be described with reference to the drawings. The same or equivalent components, members, and processes shown in each drawing are denoted by the same reference numerals, and redundant descriptions are omitted as appropriate. Further, the embodiments are illustrative and not restrictive of the invention, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention.

[0037] In this specification, the phrase "member A is in a state of being connected to member B" includes not only the case where member A and member B are physically and directly connected, but also the case where member A and member B are indirectly connected via other members that do not substantially affect their electrical connection state or impair the functions and effects achieved by their connection.

[0038] Similarly, the phrase "member C is provided between member A and member B" includes not only the case where member A and member C, or member B and member C are directly connected, but also the case where they are indirectly connected via other members that do not substantially affect their electrical connection state or impair the functions and effects achieved by their connection.

[0039] Note that the vertical and horizontal axes of the waveform diagrams and time charts referred to in this specification are appropriately enlarged or reduced for ease of understanding, and each waveform shown is also simplified, exaggerated, or emphasized for ease of understanding.

[0040] FIG. 1 is a circuit diagram of a switching circuit 100 according to an embodiment. The switching circuit 100 includes a bridge circuit 110 and a drive circuit 400. Here, only the configuration of one phase of the switching circuit 100 is shown, but the switching circuit 100 may have three phases or may be an H-bridge circuit.

[0041] The bridge circuit 110 includes an upper arm 112 provided between an input line (power supply line) 102 and an output terminal (output line) 104, and a lower arm 114 provided between the output line 104 and a ground line 106. The upper arm 112 includes a high-side transistor MH and a flywheel diode (freewheeling diode) Di connected in parallel. The lower arm 114 includes a low-side transistor ML and a flywheel diode Di connected in parallel. In the present embodiment, the high-side transistor MH and the low-side transistor ML are N-channel MOSFETs, and their respective body diodes also serve as flywheel diodes Di.

[0042] The drive circuit 400 controls the upper arm 112 and the lower arm 114 of the bridge circuit 110. The drive circuit 400 switches between two states: a high output state φ where the upper arm 112 is on and the lower arm 114 is off H and a low output state φ where the upper arm 112 is off and the lower arm 114 is on. L The bridge circuit 110 may take a high impedance state φ where both the upper arm 112 and the lower arm 114 are off. HZ

[0043] The drive circuit 400 includes four sensors 410, 420, 430, 440, a high-side driver circuit 450, a correction circuit 460, and a low-side driver circuit 490, and is a functional IC integrated on a single semiconductor substrate.

[0044] The first sensor is the low-side off-sensor 410, which generates a first feedback signal S1 that is asserted when the low-side transistor ML turns off. For example, the low-side off-sensor 410 asserts the first feedback signal S1 when the gate-source voltage (gate voltage) of the low-side transistor ML is below a first threshold voltage V TH1 determined according to the threshold voltage of the MOSFET.

[0045] The second sensor is the output sensor 420, which generates a second feedback signal S2 that is asserted in response to a change in the output voltage V OUT of the bridge circuit 110. For example, the output sensor 420 compares the output voltage V OUT with a second threshold voltage V TH2 and asserts the second feedback signal S2 when the output voltage V OUT exceeds the second threshold voltage V TH2 .

[0046] The third sensor is the high-side full-on sensor 430, which generates a third feedback signal S3 that is asserted when the high-side transistor MH turns fully on. For example, the high-side full-on sensor 430 asserts the third feedback signal S3 when the gate voltage of the high-side transistor MH exceeds a third threshold voltage V TH3 . The third threshold voltage V TH3 is set slightly lower than the supply voltage V H of the high-side driver circuit 450. In other words, the third feedback signal S3 is asserted when the gate-source voltage V GS of the high-side transistor MH exceeds a threshold voltage V H -V IN determined to be slightly lower than V TH3 '.

[0047] The fourth sensor is the high-side off sensor 440, which generates a fourth feedback signal S4 that is asserted when the high-side transistor MH turns off. For example, the high-side off sensor 440 asserts the fourth feedback signal S4 when the gate-source voltage of the high-side transistor MH falls below a fourth threshold voltage V TH4 TH4 .

[0048] The correction circuit 460 receives an input signal PWMIN, a second feedback signal S2, and a third feedback signal S3 generated by a controller (not shown), and generates a high-side control signal HGCTL, which is an actual drive signal.

[0049] The high-side driver circuit 450 receives the high-side control signal HGCTL and the first feedback signal S1. The output node of the high-side driver circuit 450 is connected to the gate of the high-side transistor MH.

[0050] The high-side driver circuit 450 becomes active when the high-side control signal HGCTL is at an on level (e.g., high) and the first feedback signal S1 is asserted (high), and sources an on current I HG_ON HG_ON of a predetermined current amount to the gate of the high-side transistor MH. Thereby, the gate-source voltage V GS GS of the high-side transistor MH is increased at a constant slope to turn on the high-side transistor MH.

[0051] Also, the high-side driver circuit 450 becomes active when the high-side control signal HGCTL is at an off level (low), and is configured to sink an off current I HG_OFF HG_OFF from the gate of the high-side transistor MH. Thereby, the gate-source voltage V GS GS of the high-side transistor MH is decreased at a constant slope to turn off the high-side transistor MH.

[0052] Here, the off current I HG_OFF HG_OFF and the on current IHG_ON The same current amount is used. This ensures that the turn-on time and turn-off time of the high-side transistor MH are equal.

[0053] The low-side driver circuit 490 is also configured in the same manner as the high-side driver circuit 450. The low-side driver circuit 490 receives a low-side control signal (referred to as an actual drive signal) LGCTL and a fourth feedback signal S4. The output node of the low-side driver circuit 490 is connected to the gate of the low-side transistor ML.

[0054] The low-side driver circuit 490 becomes active when the low-side control signal LGCTL is at the on level (e.g., high) and the fourth feedback signal S4 is asserted (high), and sources an on current I of a predetermined current amount to the gate of the low-side transistor ML. Thereby, the voltage V between the gate and source of the low-side transistor ML is increased at a constant slope to turn on the low-side transistor ML. LG_ON The low-side driver circuit 490 becomes active when the low-side control signal LGCTL is at the off level (low), and is configured to sink an off current I from the gate of the low-side transistor ML. Thereby, the voltage V between the gate and source of the low-side transistor ML is decreased at a constant slope to turn off the low-side transistor ML. GS

[0055] Here, the off current I LG_OFF and the on current I GS are set to the same current amount. This ensures that the turn-on time and turn-off time of the low-side transistor ML are equal.

[0056] Here, the off current I LG_OFF and the on current I LG_ON are set to the same current amount. This ensures that the turn-on time and turn-off time of the low-side transistor ML are equal.

[0057] ​The correction circuit 460 supports at least one of the first to third modes. The first to third modes are modes that assume a case where the duty cycle of the input signal PWMIN is small.

[0058] (First mode) In the first mode, the pulse width of the input signal PWMIN is very narrow, and the output voltage V OUT This is applicable to the case where the input signal PWMIN transitions to the off level before V changes.

[0059] When the input signal PWMIN transitions to the on level, the correction circuit 460 changes the high-side control signal HGCTL to the on level.

[0060] The correction circuit 460 measures the pulse width Ta of the input signal PWMIN (referred to as sampling). Then, the correction circuit 460 detects the pulse width Ta of the input signal PWMIN when the second feedback signal S2 is asserted (the output voltage V OUT After a time Ta / 2, which is half the pulse width Ta, has elapsed since the high side control signal HGCTL is changed, the high side control signal HGCTL is changed to the off level.

[0061] (Second mode) In the second mode, the output voltage V OUT This is applicable to a case where, after the high-side transistor MH is fully turned on, the input signal PWMIN transitions to the off level.

[0062] When the input signal PWMIN transitions to the on level, the correction circuit 460 changes the high-side control signal HGCTL to the on level, and measures (samples) the time Tb from when the input signal PWMIN transitions to the on level to when the second feedback signal S2 is asserted.

[0063] Then, the second feedback signal S2 is asserted (the output voltage V OUTWhen the time from when it changes until the third feedback signal S3 is asserted (the high-side transistor MH is fully on) is Tc, after the input signal PWMIN transitions to the off level, after a lapse of time Tb - Tc, the high-side control signal HGCTL is changed to the off level.

[0064] (Third mode) The third mode is applicable to a case where, after the output voltage V of the bridge circuit 110 changes and before the high-side transistor MH is fully on, the input signal PWMIN transitions to the off level. OUT

[0065] When the input signal PWMIN transitions to the on level, the correction circuit 460 changes the high-side control signal HGCTL to the on level. And after the input signal PWMIN transitions to the on level, the correction circuit 460 measures the time Td from when the second feedback signal S2 is asserted (the output voltage V OUT changes).

[0066] When the time from when the second feedback signal S2 is asserted until the input signal PWMIN transitions to the off level is Te, and the time from when the input signal PWMIN transitions to the off level until the third feedback signal S3 is asserted (the high-side transistor MH is fully on) is Tf, the correction circuit 460 changes the high-side control signal HGCTL to the off level after a lapse of time Td - Te - 2Tf from when the high-side transistor MH is fully on.

[0067] The above is the configuration of the switching circuit 100. Subsequently, its operation will be described for each of the first mode to the third mode.

[0068] FIG. 2 is a waveform diagram for explaining the operation of the first mode of the switching circuit 100. At time t 10 ​The input signal PWMIN transitions to the on level. In response, the high-side control signal HGCTL transitions to the on level and the low-side control signal LGCTL transitions to the off level. When the low-side control signal LGCTL becomes the off level, the low-side driver circuit 490 sinks a constant current from the gate of the high-side transistor MH, and the gate voltage V LG decreases with time. At time t 11 , when the gate voltage V LG falls below the first threshold voltage V TH1 , the first feedback signal S1 is asserted.

[0069] When the first feedback signal S1 is asserted, the high-side driver circuit 450 starts to source the drive current I HG_ON . As a result, the voltage between the gate and source of the high-side transistor MH (V HG - V OUT ) increases with a constant slope.

[0070] At time t 12 , the input signal PWMIN transitions to the off level. The time Ta (t 10 ~ t 12 ) during which the input signal PWMIN was at the on level is measured by the correction circuit 460.

[0071] When the voltage between the gate and source of the high-side transistor MH exceeds the threshold of the MOSFET, the high-side transistor MH turns on and the output voltage V OUT starts to rise.

[0072] At time t 13 , when the output voltage V OUT exceeds the second threshold voltage V TH2 , the second feedback signal S2 is asserted.

[0073] The correction circuit 460 transitions the high-side control signal HGCTL to the off level at time t 13 after the elapse of time Ta / 2 from time t 14 . Also, the low-side control signal LGCTL transitions to the on level.

[0074] When the high-side control signal HGCTL becomes the off level, the high-side driver circuit 450 starts to sink the drive current I HG_OFF . As a result, the voltage between the gate and source of the high-side transistor MH (V HG - V OUT ) decreases with a constant slope. When the voltage between the gate and source (V HG - V OUT ) becomes lower than the gate threshold voltage of the MOSFET, the high-side transistor MH turns off. At this stage, the low-side transistor ML is not yet on, but when current flows through the flywheel diode Di of the lower arm 114, the output voltage V OUT changes towards -Vf. And at time t 15 , when the output voltage V OUT becomes lower than the second threshold voltage V TH2 , the second feedback signal S2 is negated.

[0075] And at time t 16 , when the voltage between the gate and source of the high-side transistor MH (V HG - V OUT ) falls below the fourth threshold voltage V TH4 , the fourth feedback signal S4 is asserted. When the fourth feedback signal S4 is asserted, the low-side driver circuit 490 becomes active and sources an on-current I LG_OFF of the same amount as the off-current I LG_ON to the gate of the low-side transistor ML. As a result, the voltage between the gate and source of the low-side transistor ML, V GS , rises with a constant slope, turning on the low-side transistor ML.

[0076] The above is the operation of the first mode. Subsequently, its advantages will be explained.

[0077] The on-current I HG_ON and off-current I HG_OFF generated by the high-side driver circuit 450Since they are of the same amount, the voltage V between the gate and source of the high-side transistor MH HG -V OUT becomes a waveform symmetric about the time t 14 . Here, the pulse width of the second feedback signal S2 can be regarded as equal to the pulse width of the output voltage V OUT . And since the voltages V HG , V OUT can be regarded as having waveforms symmetric about the time t 14 , the length of t 14 ~t 15 is equal to the length of t 13 ~t 14 . As described above, since the length of t 13 ~t 14 is Ta / 2, the length of t 13 ~t 15 , that is, the pulse width of the output voltage V OUT becomes Ta / 2×2 = Ta, which is equal to the pulse width of the original input signal PWMIN.

[0078] Thus, according to the first mode, an output voltage V OUT having a pulse width substantially equal to the input signal PWMIN can be generated without being affected by the dead time.

[0079] Subsequently, the operation of the second mode will be described.

[0080] FIG. 3 is a waveform diagram for explaining the operation of the second mode of the switching circuit 100. Note that the scales of the horizontal axes in FIGS. 2 and 3 are different.

[0081] At the time t 20 , the input signal PWMIN transitions to the on level. In response to this, the high-side control signal HGCTL transitions to the on level and the low-side control signal LGCTL transitions to the off level. When the low-side control signal LGCTL becomes the off level, the low-side driver circuit 490 sinks a constant current from the gate of the high-side transistor MH, and the gate voltage V LG decreases with time. And at the time t 21When the gate voltage V LG is lower than the first threshold voltage V TH1 , the first feedback signal S1 is asserted.

[0082] When the first feedback signal S1 is asserted, the high-side driver circuit 450 starts to source the drive current I HG_ON . As a result, the voltage between the gate and source of the high-side transistor MH (V HG -V OUT ) increases with a constant slope. Thereby, the high-side transistor MH turns on, and the output voltage V OUT starts to rise. And at time t 22 , when the output voltage V OUT exceeds the second threshold voltage V TH2 , the second feedback signal S2 is asserted. The correction circuit 460 measures (samples) the time Tb (= t 20 ~t 22 ) from when the input signal PWMIN transitions to the on level until the second feedback signal S2 is asserted.

[0083] Thereafter, the voltage between the gate and source of the high-side transistor MH V HG -V OUT further increases, and at time t 23 , when it exceeds the third threshold voltage V TH3 , the third feedback signal S3 is asserted. Let the time from when the second feedback signal S2 is asserted (the output voltage V OUT changes) until the third feedback signal S3 is asserted (the high-side transistor MH is fully on) be Tc.

[0084] Thereafter, at time t 24 , the input signal PWMIN transitions to the off level. The correction circuit 460 changes the high-side control signal HGCTL to the off level at time t 24 after the elapse of time (Tb - Tc) from time t 25 . Also, the low-side control signal LGCTL transitions to the on level.

[0085] When the high-side control signal HGCTL becomes the off level, the high-side driver circuit 450 starts to sink the drive current I HG_OFF . As a result, the voltage between the gate and source of the high-side transistor MH (V HG - V OUT ) decreases with a constant slope. At time t 26 , when the voltage between the gate and source (V HG - V OUT ) becomes lower than the third threshold voltage V TH3 , that is, when the full-on state is released, the third feedback signal S3 is negated.

[0086] And when the voltage between the gate and source (V HG - V OUT ) becomes lower than the gate threshold voltage of the MOSFET, the high-side transistor MH turns off. At this stage, the low-side transistor ML is not yet on, but current flows through the flywheel diode Di of the lower arm 114, causing the output voltage V OUT to change towards -Vf. And at time t 27 , when the output voltage V OUT becomes lower than the second threshold voltage V TH2 , the second feedback signal S2 is negated.

[0087] And at time t 28 , when the voltage between the gate and source of the high-side transistor MH (V HG - V OUT ) falls below the fourth threshold voltage V TH4 , the fourth feedback signal S4 is asserted. When the fourth feedback signal S4 is asserted, the low-side driver circuit 490 becomes active and sources the same amount of on-current I LG_OFF as the off-current I LG_ON to the gate of the low-side transistor ML. As a result, the voltage between the gate and source of the low-side transistor ML, V GS , is increased with a constant slope to turn on the low-side transistor ML.

[0088] The above is the operation of the second mode. Next, its advantages will be described.

[0089] The third threshold voltage V TH3 is set close to the maximum value of the gate-source voltage of the high-side transistor MH (V H -V IN ), then the time difference between time t 25 and time t 26 can be made small. Here, it is assumed that time t 25 and t 26 are substantially simultaneous.

[0090] Since the on-current I HG_ON generated by the high-side driver circuit 450 and the off-current I HG_OFF are of the same amount, the waveform of the gate-source voltage V HG -V OUT of the high-side transistor MH is symmetric about the rising slope section (t 21 ~t 23 ) and the falling slope section (after t 26 until it becomes zero).

[0091] Here, the pulse width of the second feedback signal S2 can be regarded as equal to the pulse width of the output voltage V OUT . And since the voltages V HG , V OUT have the same waveform for the rising slope and the falling slope, the length of t 26 ~t 27 is equal to the length Tc of t 22 ~t 23 . The rising edge t OUT of the second feedback signal S2 (output voltage V 22 ) lags behind the rising edge t 20 of the input signal PWMIN by Tb, and the falling edge t OUT of the second feedback signal S2 (output voltage V 27 ) lags behind the falling edge t 24 of the input signal PWMIN by (Tb - Tc)+Tc = Tb. That is, the pulse width of the output voltage V OUT is equal to the pulse width of the input signal PWMIN.

[0092] (Mode 3) Next, the operation of Mode 3 will be described.

[0093] FIG. 4 is a waveform diagram for explaining the operation of the switching circuit 100 in Mode 3. Note that the scale of the horizontal axis in FIG. 4 is different from that in FIGS. 2 and 3.

[0094] Time t 30 At, the input signal PWMIN transitions to the on level. In response to this, the high-side control signal HGCTL transitions to the on level and the low-side control signal LGCTL transitions to the off level. When the low-side control signal LGCTL becomes the off level, the low-side driver circuit 490 sinks a constant current from the gate of the high-side transistor MH, and the gate voltage V LG decreases with time. Then at time t 31 , when the gate voltage V LG falls below the first threshold voltage V TH1 , the first feedback signal S1 is asserted.

[0095] When the first feedback signal S1 is asserted, the high-side driver circuit 450 starts to source the drive current I HG_ON . As a result, the voltage between the gate and source of the high-side transistor MH (V HG -V OUT ) increases with a constant slope. Thereby, the high-side transistor MH turns on, and the output voltage V OUT starts to rise. Then at time t 32 , when the output voltage V OUT exceeds the second threshold voltage V TH2 , the second feedback signal S2 is asserted.

[0096] The correction circuit 460 measures (samples) the time Td from when the input signal PWMIN transitions to the on level until the second feedback signal S2 is asserted (the output voltage V OUT changes).

[0097] Subsequent time t 33 The input signal PWMIN transitions to the off level. Thereafter, the voltage V between the gate and source of the high-side transistor MH HG -V OUT further rises, and when it exceeds the third threshold voltage V 34 at time t TH3 , the third feedback signal S3 is asserted.

[0098] Let the time from when the second feedback signal S2 is asserted until the input signal PWMIN transitions to the off level be Te, and the time from when the input signal PWMIN transitions to the off level until the third feedback signal S3 is asserted (the high-side transistor MH is fully on) be Tf.

[0099] The correction circuit 460 changes the high-side control signal HGCTL to the off level at time t 34 when the high-side transistor MH is fully on, after the elapse of time (Td - Te - 2Tf) at time t 35 . Also, the low-side control signal LGCTL transitions to the on level.

[0100] When the high-side control signal HGCTL becomes the off level, the high-side driver circuit 450 starts to sink the drive current I HG_OFF . As a result, the voltage (V HG -V OUT ) between the gate and source of the high-side transistor MH decreases with a constant slope. At time t 36 , when the voltage (V HG -V OUT ) between the gate and source becomes lower than the third threshold voltage V TH3 , that is, when the fully-on state is released, the third feedback signal S3 is negated.

[0101] And the voltage (V HG -V OUT) is lower than the gate threshold voltage of the MOSFET, the high-side transistor MH turns off. At this stage, although the low-side transistor ML is not yet on, current flows through the flywheel diode Di of the lower arm 114, causing the output voltage V OUT to change towards -Vf. And at time t 37 , when the output voltage V OUT is lower than the second threshold voltage V TH2 , the second feedback signal S2 is negated.

[0102] And at time t 38 , when the voltage between the gate and source of the high-side transistor MH (V HG - V OUT ) is lower than the fourth threshold voltage V TH4 , the fourth feedback signal S4 is asserted. When the fourth feedback signal S4 is asserted, the low-side driver circuit 490 becomes active and sources an on-current I LG_OFF of the same amount as the off-current I LG_ON to the gate of the low-side transistor ML. This causes the voltage between the gate and source of the low-side transistor ML, V GS , to rise at a constant slope, turning on the low-side transistor ML.

[0103] The above is the operation of the third mode. Subsequently, its advantages will be explained.

[0104] If the third threshold voltage V TH3 is set close to the maximum value of the voltage between the gate and source of the high-side transistor MH (V H - V IN ), the time difference between time t 35 and time t 36 can be made small. Here, it is assumed that time t 35 and t 36 are substantially simultaneous.

[0105] The on-current I HG_ON and off-current I HG_OFFSince they are of the same amount, the voltage V between the gate and source of the high-side transistor MH HG -V OUT has a waveform that is symmetric about the rising slope section (t 31 ~t 34 ) and the falling slope section (after t 35 until it becomes zero).

[0106] Here, the pulse width of the second feedback signal S2 can be considered equal to the pulse width of the output voltage V OUT . And since the voltages V HG , V OUT have the same waveform for the rising and falling slopes, the length of t 36 ~t 37 is equal to the length Te + Tf of t 32 ~t 34 .

[0107] The rising edge t OUT of the second feedback signal S2 (output voltage V 32 ) lags behind the rising edge t 30 of the input signal PWMIN by Td. The falling edge t OUT of the second feedback signal S2 (output voltage V t37 ) lags behind the falling edge t 33 of the input signal PWMIN by Tf+(Td - Te - 2Tf)+(Te + Tf)=Td. That is, the pulse width of the output voltage V OUT is equal to the pulse width of the input signal PWMIN.

[0108] Subsequently, a specific configuration example of the drive circuit 400 will be described.

[0109] FIG. 5 is a block diagram showing a configuration example of the correction circuit 460. The correction circuit 460 includes an event-driven logic circuit 462 and a timer circuit 470.

[0110] In addition to the input signal PWMIN, feedback signals S1 to S3 are input to the logic circuit 462. The logic circuit 462 includes a state machine and undergoes state transitions according to the input signal PWMIN and the feedback signals S1 to S3.

[0111] The timer circuit 470 is controlled by the logic circuit 462 and generates a turn-off trigger that transitions the high-side drive signal HGCTL to the off level. The logic circuit 462 measures time using the timer circuit 470 for each state. The logic circuit 462 transitions the high-side drive signal HGCTL to the off level in response to the turn-off trigger TURN_OFF from the timer circuit 470.

[0112] The logic circuit 462 selects the mode of the correction circuit 460 according to the timing of the negative edge of the input signal PWMIN and the timing of the assertion of each of the first feedback signal S1 to the third feedback signal S3.

[0113] That is, as shown in FIG. 2, when the negative edge of the input signal PWMIN precedes the assertion of the first feedback signal S1, it is the first mode.

[0114] As shown in FIG. 3, when the negative edge of the input signal PWMIN is after the assertion of the third feedback signal S3, it is the second mode.

[0115] As shown in FIG. 4, when the negative edge of the input signal PWMIN occurs after the assertion of the second feedback signal and before the assertion of the third feedback signal S3, it is the third mode.

[0116] When the input signal PWMIN transitions to the on level, that is, when triggered by the positive edge of the input signal PWMIN, the logic circuit 462 activates the timer circuit 470 and samples time Ta in the first mode, time Tb in the second mode, and time Td in the third mode. That is, in the first mode, the logic circuit 462 stops the timer circuit 470 triggered by the negative edge of the input signal PWMIN and samples time Ta. In the second and third modes, the logic circuit 462 stops the timer circuit 470 triggered by the assertion of the second feedback signal S2 and samples time Tb or Td.

[0117] And in the first mode, the logic circuit 462 starts the timer circuit 470 triggered by the negative edge of the input signal PWMIN. The timer circuit 470 generates a turn-off trigger TURN_OFF after the elapse of time Ta / 2 from the start.

[0118] In the second mode, the logic circuit 462 starts the timer circuit 470 in response to the assertion of the second feedback signal S2 and measures the time Tc until the assertion of the third feedback signal S3. Further, the logic circuit 462 restarts the timer circuit 470 in response to the negative edge of the input signal PWMIN. The timer circuit 470 generates a turn-off trigger TURN_OFF after the elapse of time (Tb - Tc).

[0119] In the third mode, the logic circuit 462 starts the timer circuit 470 in response to the assertion of the second feedback signal S2 and measures the time Te until the negative edge of the input signal PWMIN. Further, the logic circuit 462 restarts the timer circuit 470 in response to the negative edge of the input signal PWMIN and measures the time Tf until the assertion of the third feedback signal S3. Then, in response to the assertion of the third feedback signal S3, the timer circuit 470 is restarted, and the timer circuit 470 generates a turn-off trigger TURN_OFF after the elapse of time (Td - Te - 2Tf).

[0120] The configuration of the timer circuit 470 is not particularly limited, and it may be configured with an analog timer or a digital timer (counter).

[0121] FIG. 6 is a circuit diagram showing a specific configuration example of the correction circuit 460. The timer circuit 470 is an analog timer and includes a capacitor C1, a charging circuit 472, a discharging circuit 474, and a comparison circuit 476.

[0122] Prior to sampling, an initialization voltage V INIT is applied to the capacitor C1 to initialize the charge.

[0123] The logic circuit 462 turns on the switch SW11 and enables the charging circuit 472 as an instruction to start sampling. The logic circuit 462 turns off the switch SW11 and disables the charging circuit 472 as an instruction to end sampling. The charging circuit 472 charges the capacitor C1 with a constant current Ic while it is enabled. If the length of the charging period is T SMP , the voltage V C1 of the capacitor C1 at the end of sampling is V SMP =V INIT +T SMP ×Ic / C1 . T SMP is either Ta, Tb or Td.

[0124] Also, the logic circuit 462 turns on the switch SW12 and enables the discharging circuit 474 as an instruction to start / reset the timer, turns off the switch SW12 and disables the discharging circuit 474 as an instruction to stop the timer. Also, the logic circuit 462 sets the current amount generated by the discharging circuit 474 to either Ic or 2×Ic. During the timer operation of the timer circuit 470, the voltage V C1 of the capacitor C1 decreases at a slope of Ic / C1 or 2×Ic / C1.

[0125] The comparison circuit 476 compares the voltage V of the capacitor C1 with the threshold voltage V corresponding to the initialization voltage V C1 and outputs a turn-off trigger TURN_OFF when the voltage V INIT drops to the voltage V TH C1 is lower than the voltage V TH .

[0126] The timer operations in the first to third modes will be described with reference to FIGS. 7 to 9

[0127] FIG. 7 is an operation waveform diagram of the correction circuit 460 in the first mode of FIG. 6. The time in FIG. 7 corresponds to the time in FIG. 2

[0128] The logic circuit 462 enables the charging circuit 472 and starts sampling at time t 10 and disables the charging circuit 472 and ends sampling at time t 12 . The capacitor voltage V at the end of sampling is C1 V SMP = V INIT + Ta × Ic / C1 .

[0129] At time t 13 , the logic circuit 462 enables the discharge circuit 474 in response to the assertion of the second feedback signal S2 and starts the timer. The current amount of the discharge circuit 474 at this time is set to 2 × Ic

[0130] During the discharge period, since the voltage V of the capacitor C1 drops from V C1 to V SMP to V TH , the voltage change width ΔV is ΔV = V SMP - V TH = V INIT + Ta × Ic / C1 - V INIT = Ta × Ic / C1 . Let the time from the start of discharge until the turn-off trigger TURN_OFF is output be t DIS , then​​ t DIS ×2×Ic / C1 = Ta×Ic / C1 holds. Therefore, t DIS = Ta / 2. The turn-off trigger TURN_OFF is asserted at the time t after the elapse of time Ta / 2 from the timer start 14 is asserted.

[0131] Figure 8 is an operation waveform diagram of the second mode of the correction circuit 460 in FIG. 6. The time in FIG. 8 corresponds to the time in FIG. 3.

[0132] The logic circuit 462 enables the charging circuit 472 at the time t 20 and starts sampling, and disables the charging circuit 472 at the time t 22 to end sampling. The capacitor voltage V at the end of sampling C1 is V SMP = V INIT + Tb×Ic / C1 becomes.

[0133] At the time t 22 , the logic circuit 462 enables the discharge circuit 474 in response to the assertion of the second feedback signal S2, starts the timer, and at the time t when the third feedback signal S3 is asserted 23 , disables the discharge circuit 474 and pauses the timer. The current amount of the discharge circuit 474 at this time is set to Ic.

[0134] At the time t 23 in, the voltage V of the capacitor C1 C1 is V C1 = V SMP - Tc×Ic / C1 = V INIT + Tb×Ic / C1 - Tc×Ic / C1 becomes.

[0135] At the time t 24Upon this, in response to the negative edge of the input signal PWMIN, the logic circuit 462 enables the discharge circuit 474 and restarts the timer. The current amount of the discharge circuit 474 at this time is also set to Ic.

[0136] The turn-off trigger TURN_OFF is asserted at the time t after the elapse of Tb - Tc after the restart. 25 is asserted.

[0137] Figure 9 is an operation waveform diagram of the third mode of the correction circuit 460 in Figure 6. The time in Figure 9 corresponds to the time in Figure 4.

[0138] At time t, the logic circuit 462 enables the charging circuit 472, starts sampling, and at time t 30 disables the charging circuit 472 and ends sampling. The capacitor voltage V 32 at the end of sampling is C1 is V SMP = V INIT + Td × Ic / C1 becomes.

[0139] At time t 32 in response to the assertion of the second feedback signal S2, the logic circuit 462 enables the discharge circuit 474, starts the timer, and at the time t 33 when the third feedback signal S3 is asserted, disables the discharge circuit 474 and temporarily stops the timer. The current amount of the discharge circuit 474 at this time is set to Ic.

[0140] At time t 33 the voltage V C1 of the capacitor C1 is V C1 = V SMP - Te × Ic / C1

[0141] At time t 33At the negative edge of the input signal PWMIN, the logic circuit 462 enables the discharge circuit 474 and restarts the timer. The current amount of the discharge circuit 474 at this time is set to 2×Ic.

[0142] And at time t 34 At time t, in response to the assertion of the third feedback signal S3, the logic circuit 462 enables the discharge circuit 474 and restarts the timer. The current amount of the discharge circuit 474 at this time is set to Ic. The voltage V of the capacitor C1 at time t 34 is C1 V V C1 =V SMP -Te×Ic / C1 - Tf×2×Ic / C1 becomes.

[0143] The turn-off trigger TURN_OFF is asserted at time t 34 after the restart at time t and after the elapse of Td - Te - 2×Tf at time t 35 .

[0144] FIG. 10 is a circuit diagram of a specific configuration example (470A) of the timer circuit 470. In the timer circuit 470A, the comparison circuit 476 includes a MOS (Metal Oxide Semiconductor) transistor M11 and a constant current source CS11.

[0145] The initialization circuit 478 includes a MOS transistor M12 and a switch SW13. The transistor M12 is a replica of the same type as the MOS transistor M11, and the size of the transistor M11 is twice the size of the transistor M12. When initializing the capacitor C1, the switches SW13 and SW11 are turned on. Thereby, the capacitor C1 is charged with an initialization voltage V GS(th) corresponding to the threshold voltage V INIT of the transistor M11.

[0146] During sampling, the switch SW11 is turned on, and the capacitor voltage V C1 becomes the initialization voltage VINIT rises from. During the timer operation, switch SW12 turns on, and the capacitor voltage V C1 decreases with time. When the capacitor voltage V C1 drops to the gate threshold voltage V GS(th) of transistor M11, a turn-off trigger TURN_OFF is output.

[0147] FIG. 11 is a circuit diagram of a specific configuration example (470B) of the timer circuit 470. In the timer circuit 470B, the comparison circuit 476 includes a two-input voltage comparator COMP1.

[0148] The initialization circuit 478 includes switches SW14, SW15, and an impedance element. In this example, the impedance element is a MOSFET with its gate and drain connected, but it is not limited to this. An element that generates a constant voltage drop when a constant current Ic flows can be used, for example, a resistor or a diode.

[0149] When initializing the capacitor C1, switches SW11 and SW15 turn on. At this time, an initialization voltage V GS(th) corresponding to the gate threshold voltage V INIT of transistor M13 is applied to the capacitor C1.

[0150] During sampling, switch SW11 turns on, and the capacitor voltage V C1 rises from the initialization voltage V INIT During the timer operation, switch SW12 turns on, and the capacitor voltage V C1 decreases with time. Also during the timer operation, switch SW14 turns on, and a threshold voltage V GS(th) corresponding to the gate threshold voltage V TH of transistor M13 is supplied to the voltage comparator COMP1.

[0151] The configuration of FIG. 11 has the following advantages compared to the configuration of FIG. 10. The configuration of FIG. 10 has an initialization voltage V INIT and a threshold voltage VTH An offset is likely to occur, and the propagation delay is large. In contrast, the configuration of FIG. 11 can reduce the propagation delay by configuring the comparison circuit 476 with a high-speed voltage comparator COMP1. Also, in the configuration of FIG. 11, the offset between the initialization voltage V INIT and the threshold voltage V TH does not occur in principle.

[0152] The voltage comparator COMP1 in FIG. 11 preferably has an adjustable input offset voltage V OFS . By adjusting the input offset voltage V OFS of the voltage comparator COMP1, the timing of the turn-off trigger TURN_OFF can be finely adjusted, and the influence of the propagation delay occurring in other paths can be canceled.

[0153] FIG. 12 is a circuit diagram showing a configuration example of a high-side driver circuit 450 and a high-side full-on sensor 430.

[0154] The high-side full-on sensor 430 includes a PMOS transistor 432 and a resistor 434. The PMOS transistor 432 and the resistor 434 are connected in series between a power supply line 402 where a high-level voltage V H is generated and a constant voltage line 404 stabilized at a voltage ΔV lower than that, and the gate of the PMOS transistor 432 is connected to the gate of the high-side transistor MH via the HG pin.

[0155] The third feedback signal S3 is asserted when V H -V HG is smaller than the gate threshold voltage V GS(th) of the PMOS transistor 432.

[0156] The high-side driver circuit 450 includes a source current source CS31, a sink current source CS32, and switches SW31 to SW34.

[0157] The source current source CS31 is a reference current I REF generated by a constant current source CS33It is composed of a current mirror circuit that folds back. The switch SW31 turns on during the period when the on-current I HG_ON is to be output. Similarly, the sink current source CS32 is also composed of a current mirror circuit that folds back the reference current I REF . The switch SW32 turns on during the period when the off-current I HG_OFF is to be output. According to this configuration, an on-current I HG_ON and an off-current I HG_OFF of equal current amount can be generated.

[0158] The strong-on switch SW33 is turned on after the high-side transistor MH is fully on. After the high-side transistor MH is fully on, the switch SW31 can be turned off.

[0159] Conversely, the strong-off switch SW34 is turned on after the high-side transistor MH is completely off. After the high-side transistor MH is off, the switch SW32 can be turned off.

[0160] Subsequently, the use of the switching circuit 100 will be described. The switching circuit 100 can be suitably used in a drive circuit for a motor.

[0161] FIG. 13 is a circuit diagram of a motor drive device 300 including the switching circuit 100 according to the embodiment. The motor drive device 300 drives a three-phase motor 302 as a load and controls its rotational state.

[0162] The motor drive device 300 includes a bridge circuit 110 and a drive circuit 200. The bridge circuit 110 is a three-phase inverter and has legs for the U-phase, V-phase, and W-phase, and each phase leg has an upper arm and a lower arm.

[0163] The drive circuit 200 includes a control circuit 210, high-side driver circuits 220U to 220W, and low-side driver circuits 260U to 260W. The control circuit 210 generates control signals indicating the states of the six arms constituting the bridge circuit 110 based on the state of the three-phase motor 302, which is the load.

[0164] The high-side driver circuits 220U to 220W are configured with the architecture of the high-side driver circuit 450 described above and can correct the influence of the duty cycle error caused by the dead time.

[0165] Here, a three-phase motor is taken as an example, but a single-phase motor may also be used. In this case, the bridge circuit 110 becomes an H-bridge circuit.

[0166] Subsequently, the applications of the motor drive device 300 will be described. The motor drive device 300 can be used for controlling the spindle motor of a hard disk and for controlling the lens drive motor of an imaging device. Alternatively, it can be used for driving the head drive motor or the paper feed motor of a printer. Alternatively, the motor drive device 300 can be used for driving motors in electric vehicles, hybrid vehicles, and the like.

[0167] It should be understood by those skilled in the art that the embodiments are illustrative, and various modifications are possible for the combinations of their respective components and processing processes, and such modifications are also within the scope of the present disclosure or the present invention. Hereinafter, such modifications will be described.

[0168] (Modification 1) In the embodiment, the bridge circuit 110 is composed of discrete components, but not limited thereto, and the bridge circuit 110 may be integrated into the drive circuit 400.

[0169] (Modification 2) The upper arm 112 and the lower arm 114 may be composed of IGBTs (Insulated Gate Bipolar Transistors).

[0170] (Modification Example 3) In the embodiment, three modes can be selected, but only any of them may be implemented. When only the first mode is implemented, the high-side full-on sensor 430 may be omitted.

[0171] (Modification Example 4) The application of the switching circuit 100 is not limited to the motor drive device 300. For example, the switching circuit 100 can be suitably used for a switching regulator (DC / DC converter), various power conversion devices (inverters and converters), an inverter for lighting a discharge lamp, a digital audio amplifier, and the like. Therefore, the switching circuit 100 can be used in consumer devices including electronic devices and home appliances, automobiles and in-vehicle parts, industrial vehicles and industrial machines.

[0172] The embodiment only shows the principle and application of the present invention, and many modifications and arrangement changes are possible in the embodiment without departing from the idea of the present invention defined in the claims.

Description of Reference Numerals

[0173] 100 Switching circuit 102 Input line 104 Output line 106 Ground line 110 Bridge circuit 112 Upper arm 114 Lower arm MH High-side transistor ML Low-side transistor Di Flywheel diode HGCTL High-side control signal LGCTL Low-side control signal 400 Drive circuit 410 Low-side off sensor 420 Output sensor 430 High-side full-on sensor 440 High-side off sensor 450 High-side driver circuit 460 Correction Circuit 490 Low-Side Driver Circuit S1 First Feedback Signal S2 Second Feedback Signal S3 Third Feedback Signal S4 Fourth Feedback Signal 300 Motor Drive Device 302 Three-Phase Motor 462 Logic Circuit 470 Timer Circuit C1 Capacitor 472 Charging Circuit 474 Discharging Circuit 476 Comparison Circuit 478 Initialization Circuit 432 PMOS Transistor

Claims

1. A drive circuit for driving a bridge circuit having a high-side transistor connected between a power line and an output line and a low-side transistor connected between the output line and a ground line, a first sensor that generates a first feedback signal that is asserted when the low-side transistor turns off; a second sensor that generates a second feedback signal that is asserted in response to a change in the output voltage of the bridge circuit; a correction circuit that receives an input signal indicating the output of the bridge circuit, the first feedback signal, and the second feedback signal and generates an actual drive signal; a high-side driver circuit configured to source an on-current of a predetermined current amount to the gate of the high-side transistor when the actual drive signal is at an on-level and the first feedback signal is asserted, and to sink the off-current of the predetermined current amount from the gate of the high-side transistor when the actual drive signal is at an off-level; comprising: In a first mode applicable when the input signal transitions to an off-level before the output voltage of the bridge circuit changes, the correction circuit changes the actual drive signal to an on-level when the input signal transitions to an on-level, measures the pulse width Ta of the input signal, and changes the actual drive signal to an off-level after a time Ta / 2, which is half of the pulse width Ta, has elapsed after the second feedback signal is asserted. A drive circuit.

2. further comprising a third sensor that generates a third feedback signal that is asserted when the high-side transistor is fully on; In a second mode, the correction circuit changes the actual drive signal to an on-level when the input signal transitions to an on-level, measures the time Tb from when the input signal transitions to an on-level until the second feedback signal is asserted, and changes the actual drive signal to an off-level after a time Tb - Tc has elapsed after the input signal transitions to an off-level, when the time from when the second feedback signal is asserted until the third feedback signal is asserted is Tc. The drive circuit according to claim 1.

3. In a third mode, the correction circuit changes the actual drive signal to an on-level when the input signal transitions to an on-level, Measure the time Td from when the input signal transitions to the on level until the second feedback signal is asserted. When the time from when the second feedback signal is asserted until the input signal transitions to the off level is Te, and the time from when the input signal transitions to the off level until the third feedback signal is asserted is Tf, after the high-side transistor is fully on and after a lapse of time Td - Te - 2Tf, change the actual drive signal to the off level. The drive circuit according to claim 2.

4. The drive circuit according to any one of claims 1 to 3, wherein the first sensor asserts the first feedback signal when the gate voltage of the low-side transistor falls below a first threshold voltage.

5. The drive circuit according to any one of claims 1 to 4, wherein the second sensor asserts the second feedback signal when the output voltage exceeds a second threshold voltage.

6. The drive circuit according to claim 2 or 3, wherein the third sensor asserts the third feedback signal when the gate voltage of the high-side transistor exceeds a third threshold voltage.

7. The drive circuit according to any one of claims 1 to 6, wherein the correction circuit includes a timer circuit that generates a turn-off trigger for transitioning the actual drive signal to the off level.

8. The timer circuit includes a capacitor, a charging circuit that charges the capacitor with a first current, a discharging circuit that discharges the capacitor with a second current, wherein the second current can be switched between the same first current amount as the first current and a current amount twice the first current amount, and a comparison circuit that compares the voltage of the capacitor with a threshold voltage corresponding to the initialization voltage of the capacitor and generates the turn-off trigger. The drive circuit according to claim 7.

9. The comparison circuit includes an impedance element provided on the path of the first current, a voltage comparator, and the timer circuit applies the initialization voltage based on the voltage drop of the impedance element to the capacitor prior to the start of the timer operation. The voltage comparator compares the voltage of the capacitor with the threshold voltage based on the voltage drop of the impedance element. The drive circuit according to claim 8.

10. ​ The voltage comparator is configured such that the input offset voltage is adjustable, and the drive circuit according to claim 9.

11. The comparison circuit a first field effect transistor whose gate is connected to the capacitor, a second field effect transistor that is of the same type as the first field effect transistor and has its gate and drain connected, and includes The timer circuit applies the initialization voltage based on the voltage drop of the second field effect transistor in a state where the first current flows through the second field effect transistor to the capacitor prior to the start of timer operation, and the drive circuit according to claim 8.

12. A bridge circuit including a high-side transistor and a low-side transistor, a drive circuit according to any one of claims 1 to 11 for driving the bridge circuit, and a motor drive device comprising the same.

13. A motor, a motor drive device according to claim 12 for driving the motor, and an electronic device comprising the same.

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