Semiconductor device

Abstract

To provide a semiconductor device capable of improving a measurement accuracy of a noise.SOLUTION: A semiconductor device comprises: a potential supply terminal T31 to which a potential is supplied; a terminal T21 (an I / O terminal) that is for transmitting / receiving signals to / from the outside; an I / O current detection load circuit 110 that is electrically connected with the potential supply terminal T31 and the terminal T21; and a current sensor circuit 210 that detects an I / O current IIO flowing through the I / O current detection load circuit 110. The current sensor circuit 210 acquires a sensor current IOUT proportional to the I / O current IIO, and outputs the acquired sensor current IOUT as output information. The I / O current IIO is an abnormal current flowing through the I / O terminal by at least one of an electrostatic discharge and an electromagnetic sensibility, and is a current larger than a predetermined current so as to be an abnormal state.SELECTED DRAWING: Figure 11

Description

Technical Field

[0001] The present invention relates to a semiconductor device.

Background Art

[0002] For example, healthcare products having terminals that directly touch the human body, industrial motor products and industrial sensor products in which cables are long and large noise is generated, and in-vehicle products that place greater emphasis on safety than ever before due to autonomous driving, etc., require strict noise tolerance for the mounted ICs from the viewpoints of functional safety and safety.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Non-Patent Documents

[0004]

Non-Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] These noises are called Electro Static Discharge (ESD) and Electromagnetic Susceptibility (EMS), and noise current flows into the IC from input / output terminals (I / O terminals) for communicating signals with the outside of the substrate on which the IC is mounted. The said noise current is also called I / O current. The said noise current (I / O current) is larger than the normal operating current of the IC, and is a current that causes the IC to enter an abnormal state such as IC destruction or malfunction, greatly compromising the safety of the product on which the IC is mounted. Therefore, by detecting the noise current (I / O current) generated by these ESDs and EMSs inside the IC, it becomes possible to detect and warn of abnormal states of the IC such as IC destruction or malfunction, or to use a function that improves the robustness against IC destruction or malfunction based on the detection results, ensuring the safety of the product against the noise current of ESDs and EMSs. Therefore, improvement in the detection accuracy and measurement accuracy of this noise current (I / O current) is desired.

[0006] Other problems and novel features will become apparent from the description of this specification and the accompanying drawings.

Means for Solving the Problems

[0007] According to one embodiment, a semiconductor device includes a potential supply terminal to which a potential is supplied, an I / O terminal for communicating signals with the outside, an I / O current detection load circuit electrically connected to the potential supply terminal and the I / O terminal, and a current sensor circuit that detects an I / O current, which is the current flowing through the I / O current detection load circuit. The first current sensor circuit acquires a sensor current proportional to the I / O current and outputs the acquired sensor current as output information. The current flowing through the I / O current detection load circuit is the same as the said noise current and the I / O current.

Effects of the Invention

[0008] According to the above-described embodiment, a semiconductor device capable of improving the measurement accuracy of noise current can be provided.

Brief Description of the Drawings

[0009]

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Embodiments for Carrying Out the Invention

[0010] For the sake of clarity of explanation, the following descriptions and drawings are appropriately omitted and simplified. Also, in each drawing, the same reference numerals are assigned to the same elements, and duplicate explanations are omitted as necessary.

[0011] Before explaining the semiconductor device according to the embodiment, the semiconductor device and problems according to the comparative example will be explained. This makes the semiconductor device according to the embodiment clearer. Note that the semiconductor device according to the comparative example is also included in the scope of the technical idea of the embodiment.

[0012] (Comparative Example) FIG. 1 is a configuration diagram illustrating a semiconductor device according to a comparative example. As shown in FIG. 1, the semiconductor device 1001 according to the comparative example includes a substrate 10. On the substrate 10, a terminal T11, a terminal T12, an IC (Integrated Circuit) 20, a potential supply wiring LSU, a ground wiring LGR, a substrate load circuit 11, a substrate load circuit 12, a signal line 13, and a signal line 14 are formed. Note that several wirings, signal lines, and circuits may be further formed on the substrate 10.

[0013] Terminal T11 is, for example, the input / output terminal (I / O terminal) described above and is for communicating signals with the outside. The input / output terminal is also referred to as the I / O terminal. Terminal T11 is connected to signal line 13. Terminal T12 is, for example, the input / output terminal (I / O terminal) described above and is for communicating signals with the outside. Terminal T12 is connected to signal line 14. The potential supply wiring LSU is connected to a potential supply source. Therefore, a predetermined potential is supplied to the potential supply wiring LSU. The predetermined potential is referred to as the first potential. The predetermined potential is, for example, the power supply potential. The ground wiring LGR is connected to the ground. Therefore, a ground potential (grounding potential) having a potential different from the first potential is supplied to the ground wiring LGR. The ground potential is referred to as the second potential. The ground potential may be, for example, 0V.

[0014] The substrate load circuit 11 is electrically connected to the potential supply wiring LSU and the ground wiring LGR. That is, one terminal of the substrate load circuit 11 is connected to the potential supply wiring LSU, and the other terminal is connected to the ground wiring LGR. The substrate load circuit 12 is electrically connected to the signal line 14 and the ground wiring LGR. That is, one terminal of the substrate load circuit 12 is connected to the signal line 14, and the other terminal is connected to the ground wiring LGR. The substrate load circuit 11 and the substrate load circuit 12 are predetermined circuits formed on the substrate 10.

[0015] IC20 includes an I / O current detection load circuit 110, an I / O current detection load circuit 120, an I / O current detection load circuit 130, an I / O current detection load circuit 140, a current sensor circuit 1210, a current sensor circuit 1220, an information processing circuit 310, an information processing circuit 320, a power supply load circuit 21, a power supply load circuit 22, signal lines 23 and 24, terminals T21, T22, T31, and T32, wiring L11, L12, L21, and L22. Note that several wirings, signal lines, and circuits may be further formed in IC20.

[0016] The signal line 13 formed on the substrate 10 is connected to the terminal T21. Also, the signal line 23 formed on the IC 20 is connected to the terminal T21. Therefore, the signal input to the terminal T11 is input to the signal line 23 via the signal line 13 and the terminal T21. The terminal T21 is a terminal for communicating signals with the outside. The terminal T21 is also called an input / output terminal (I / O terminal). The signal line 14 formed on the substrate 10 is connected to the terminal T22. Also, the signal line 24 formed on the IC 20 is connected to the terminal T22. Therefore, the signal input to the terminal T12 is input to the signal line 24 via the signal line 14 and the terminal T22. The terminal T22 is a terminal for communicating signals with the outside. The terminal T22 is also called an input / output terminal (I / O terminal).

[0017] The potential supply wiring LSU is connected to the wiring L11 via the terminal T31. Therefore, the first potential is supplied to the terminal T31 and the wiring L11. The terminal T31 is also called the first potential supply terminal SU. The wiring L12 is connected to a potential supply wiring (not shown), and a predetermined potential SU3 is supplied. The ground wiring LGR is connected to the wiring L21 via the terminal T32. Therefore, the second potential is supplied to the terminal T32 and the wiring L21. The terminal T32 is also called the second potential supply terminal or the ground terminal GR. The wiring L22 is connected to the wiring L21. Therefore, the second potential is supplied to the wiring L22 via the wiring L21 and the terminal T32.

[0018] The I / O current detection load circuit 110 is connected to the wiring L11 and the signal line 23. Since the wiring L11 is connected to the terminal T31 and the signal line 23 is connected to the terminal T21, the I / O current detection load circuit 110 is electrically connected to the terminal T31 and the terminal T21. Specifically, the I / O current detection load circuit 110 has two terminals 111 and 112, one terminal 111 is connected to the wiring L11, and the other terminal 112 is connected to the signal line 23.

[0019] The I / O current detection load circuit 120 is connected to the wiring L22 and the signal line 23. Since the wiring L22 is connected to the terminal T32 and the signal line 23 is connected to the terminal T21, the I / O current detection load circuit 120 is electrically connected to the terminal T32 and the terminal T21. Specifically, the I / O current detection load circuit 120 has two terminals 121 and 122, one terminal 121 is connected to the signal line 23, and the other terminal 122 is connected to the wiring L22.

[0020] The I / O current detection load circuit 130 is connected to the wiring L12 and the signal line 24. Since the wiring L12 is connected to the terminal T33 (see FIG. 2, referred to as the potential supply terminal SU3) and the signal line 24 is connected to the terminal T22, the I / O current detection load circuit 130 is electrically connected to the terminal T33 and the terminal T22. Specifically, the I / O current detection load circuit 130 has two terminals 131 and 132, one terminal 131 is connected to the wiring L12, and the other terminal 132 is connected to the signal line 24.

[0021] The I / O current detection load circuit 140 is connected to the wiring L21 and the signal line 24. Since the wiring L21 is connected to the terminal T32 and the signal line 24 is connected to the terminal T22, the I / O current detection load circuit 140 is electrically connected to the terminal T32 and the terminal T22. Specifically, the I / O current detection load circuit 140 has two terminals 141 and 142, one terminal 141 is connected to the signal line 24, and the other terminal 122 is connected to the wiring L21.

[0022] The current sensor circuit 1210 detects the I / O current, which is the current flowing through the I / O current detection load circuit 110. Specifically, the current sensor circuit 1210 has two terminals 211 and 212, one terminal 211 is connected to one terminal 111 of the I / O current detection load circuit 110, and the other terminal 212 is connected to the other terminal 112 of the I / O current detection load circuit 110. The current sensor circuit 1210 obtains a sensor current proportional to the I / O current flowing through the I / O current detection load circuit 110 and outputs the obtained sensor current as output information.

[0023] Also, the current sensor circuit 1210 detects the I / O current, which is the current flowing through the I / O current detection load circuit 120. Specifically, the current sensor circuit 1210 further has two terminals 213 and 214. One terminal 213 is connected to one terminal 121 of the I / O current detection load circuit 120, and the other terminal 214 is connected to the other terminal 122 of the I / O current detection load circuit 120. The current sensor circuit 1210 obtains a sensor current proportional to the I / O current flowing through the I / O current detection load circuit 120 and outputs the obtained sensor current as output information.

[0024] The current sensor circuit 1220 detects the I / O current, which is the current flowing through the I / O current detection load circuit 130. Specifically, the current sensor circuit 1220 has two terminals 221 and 222. One terminal 221 is connected to one terminal 131 of the I / O current detection load circuit 130, and the other terminal 222 is connected to the other terminal 132 of the I / O current detection load circuit 130. The current sensor circuit 1220 obtains a sensor current proportional to the I / O current flowing through the I / O current detection load circuit 130 and outputs the obtained sensor current as output information.

[0025] Also, the current sensor circuit 1220 detects the I / O current, which is the current flowing through the I / O current detection load circuit 140. Specifically, the current sensor circuit 1220 further has two terminals 223 and 224. One terminal 223 is connected to one terminal 141 of the I / O current detection load circuit 140, and the other terminal 224 is connected to the other terminal 142 of the I / O current detection load circuit 140. The current sensor circuit 1220 obtains a sensor current proportional to the I / O current flowing through the I / O current detection load circuit 140 and outputs the obtained sensor current as output information.

[0026] The I / O current is an abnormal current flowing through the I / O terminal due to at least one of electrostatic discharge and electromagnetic susceptibility, and is a current larger than a predetermined current that causes an abnormal state of the semiconductor device 1001.

[0027] The information processing circuit 310 is electrically connected to the current sensor circuit 1210. The information processing circuit 310 processes the output information output from the current sensor circuit 1210. The information processing circuit 320 is connected to the current sensor circuit 1220. The information processing circuit 320 processes the output information output from the current sensor circuit 1220. When at least either the output information output from the current sensor circuit 1210 or the output information output from the current sensor circuit 1220 exceeds a predetermined threshold value, the information processing circuits 310 and 320 output an abnormal signal indicating that an abnormal current has flowed through at least any one of the terminals T31 (potential supply terminal SU), terminal T21 (input / output terminal, also referred to as I / O terminal), terminal T22 (input / output terminal, also referred to as I / O terminal), and terminal T32 (ground terminal GR).

[0028] The power supply load circuit 21 has, for example, two terminals, one of which is connected to the wiring L11 and the other is connected to the wiring L21. The power supply load circuit 22 has, for example, two terminals, one of which is connected to the wiring L12 and the other is connected to the wiring L21.

[0029] With such a configuration, the semiconductor device 1001 measures, by the current sensor circuits 1210 and 1220, the ESD / EMS current that enters the IC 20 through the terminals T21 and T22 (input / output terminals, also referred to as I / O terminals) from the terminals T11 and T12 that exit outside the substrate 10. The information processing circuits 310 and 320 grasp the current stress amount of each of the terminals T11 and T12 by processing the measured current amount. Then, the information processing circuits 310 and 320 detect whether there is a possibility of IC destruction or malfunction based on the grasped information.

[0030] FIG. 2 is a configuration diagram illustrating a semiconductor device 1001 according to a comparative example. As shown in FIG. 2, the current sensor circuit 1210 is electrically connected to the potential supply wiring LSU2 and the ground wiring LGR. Specifically, the current sensor circuit 1210 further has two terminals 215 and 216, one terminal 215 is connected to the potential supply wiring LSU2, and the other terminal 216 is connected to the ground wiring LGR.

[0031] The current sensor circuit 1220 is electrically connected to the potential supply wiring LSU2 and the ground wiring LGR. Specifically, the current sensor circuit 1220 further has two terminals 225 and 226, one terminal 225 is connected to the potential supply wiring LSU2, and the other terminal 226 is connected to the ground wiring LGR.

[0032] The reason why the current sensor circuits 1210 and 1220 use the potential supply wiring LSU2 is to maintain the compatibility with the power supply voltages of the A / D conversion circuit 350, the memory circuit 360, and the CPU circuit 370, which are configured with low withstand voltage, even if other power supplies (SU, SU3) are high withstand voltage terminals.

[0033] The current sensor circuit 1210 further has two terminals 217 and 218. The two terminals 217 and 218 are connected to the information processing circuit 330. The current sensor circuit 1210 outputs output information to the information processing circuit 330 via the two terminals 217 and 218. The current sensor circuit 1220 further has two terminals 227 and 228. The two terminals 227 and 228 are connected to the information processing circuit 330. The current sensor circuit 1220 outputs output information to the information processing circuit 330 via the two terminals 227 and 228.

[0034] The information processing circuit 330 shows the aforementioned information processing circuits 310 and 320 individually. The information processing circuit 330 may include a temporary holding circuit 340, an A / D conversion circuit 350, a memory circuit 360, and a CPU circuit 370. The information processing circuit 330 is electrically connected to the potential supply wiring LSU2 and the ground wiring LGR. Specifically, each component of the information processing circuit 330 is electrically connected to the potential supply wiring LSU2 and the ground wiring LGR.

[0035] The temporary holding circuit 340 has two terminals 341 and 342. One terminal 341 is connected to the potential supply wiring LSU2, and the other terminal 342 is connected to the ground wiring LGR. Also, the temporary holding circuit 340 is connected to the current sensor circuit 1210 by terminals 217 and 218. The temporary holding circuit 340 is connected to the current sensor circuit 1220 by terminals 227 and 228. The temporary holding circuit 340 temporarily holds the amount of current measured by the current sensor circuits 1210 and 1220. Since the response speed of the A / D conversion circuit 350 is not fast enough for the speed of ESD, the temporary holding circuit 340 holds the amount of current measured by the current sensor circuits 1210 and 1220 for a time longer than the time when the response speed of the A / D conversion circuit 350 is sufficient.

[0036] The A / D conversion circuit 350 has two terminals 351 and 352. One terminal 351 is connected to the potential supply wiring LSU2, and the other terminal 352 is connected to the ground wiring LGR. Also, the A / D conversion circuit 350 is connected to the temporary holding circuit 340. Specifically, the A / D conversion circuit 350 further has two terminals 353 and 354, and each of the terminals 353 and 354 is connected to the temporary holding circuit 340. Furthermore, the A / D conversion circuit 350 has two terminals 355 and 356, and each of the terminals 355 and 356 is connected to the temporary holding circuit 340. The A / D conversion circuit 350 performs A / D conversion on the amount of current measured by the current sensor circuits 1210 and 1220.

[0037] The memory circuit 360 has two terminals 361 and 362. One terminal 361 is connected to the potential supply wiring LSU2, and the other terminal 362 is connected to the ground wiring LGR. Also, the memory circuit 360 is connected to the A / D conversion circuit 350 via the terminal 363. Furthermore, the memory circuit 360 is connected to the CPU circuit 370 via the terminal 373. The memory circuit 360 stores the A / D converted current amount. The memory circuit 360 outputs the stored current amount to the CPU circuit 370 as needed. When long-term storage of the current amount is required, the memory circuit 360 uses a non-volatile memory.

[0038] The CPU circuit 370 has two terminals 371 and 372. One terminal 371 is connected to the potential supply wiring LSU2, and the other terminal 372 is connected to the ground wiring LGR. The CPU circuit 370 reads the current amount stored in the memory circuit 360 and executes operations such as those shown in the practical example.

[0039] When the semiconductor device 1001 is provided in an industrial motor, for example, as a practical example, if the current amount measured by the current sensor circuits 1210 and 1220 exceeds a certain value, it is determined that there is a possibility of destruction or malfunction of the IC20, and the industrial motor is notified of this. Thereby, the semiconductor device 1001 can prompt safety operations such as motor stop and rotation speed reduction. Specifically, in the semiconductor device 1001, the information processing circuit 330, by having the above-described configuration, temporarily holds the current amount measured by the current sensor circuits 1210 and 1220 in the temporary holding circuit 340, A / D converts it in the A / D conversion circuit 350, and then stores it in the memory circuit 360. Then, the information processing circuit 330 reads the current amount stored in the memory circuit 360 with the CPU circuit 370 and executes operations such as those shown in the practical example.

[0040] FIG. 3 is a configuration diagram illustrating the I / O current detection load circuits 110 and 120 and the current sensor circuit 1210 in the semiconductor device 1001 according to the comparative example. As shown in FIG. 3, the current sensor circuit 1210 detects the I / O current flowing through the I / O current detection load circuits 110 and 120. Specifically, the current sensor circuit 1210 has the following functions. That is, when an I / O current flows through the I / O current detection load circuit 110 on the potential supply terminal SU side (potential supply wiring LSU side), the measurement result of the current sensor circuit 1210 is output to the information processing circuit 330 via the terminal 217 (OUTP). When an I / O current flows through the I / O current detection load circuit 120 on the ground terminal GR side (ground wiring LGR side), the measurement result of the current sensor circuit 1210 is output to the information processing circuit 330 via the terminal 218 (OUTN).

[0041] FIG. 4 is a configuration diagram illustrating the current sensor circuit 1210 in the semiconductor device 1001 according to the comparative example. As shown in FIG. 4, the current sensor circuit 1210 includes proportional circuits 410 and 420. When an I / O current flows through the I / O current detection load circuit 110 on the potential supply terminal SU side (potential supply wiring LSU side), the proportional circuit 410 that outputs to the terminal 217 (OUTP) responds. Specifically, the current measurement result of the proportional circuit 410 is output to the information processing circuit 330 via the terminal 217 (OUTP). When a current flows through the I / O current detection load circuit 120 on the ground terminal GR side (ground wiring LGR side), the proportional circuit 420 that outputs to the terminal 218 (OUTN) responds. Specifically, the current measurement result of the proportional circuit 420 is output to the information processing circuit 330 via the terminal 218 (OUTN).

[0042] Since the same problem occurs in both the case of the potential supply terminal SU side (potential supply wiring LSU side) and the ground terminal GR side (ground wiring LGR side), hereinafter, for example, the potential supply terminal SU side (potential supply wiring LSU side) will be focused on for explanation.

[0043] FIG. 5 is a configuration diagram illustrating an I / O current detection load circuit 110 and a proportional circuit 410 in a semiconductor device 1001 according to a comparative example. As shown in FIG. 5, when an I / O current IIO flows through the I / O current detection load circuit 110, let the input voltage input to the proportional circuit 410 be VIO. The input voltage VIO is the voltage between terminals 111 and 112 of the I / O current detection load circuit 110. When an I / O current flows through the I / O current detection load circuit 110, the I / O current detection load circuit 110 generates an input voltage VIO between a terminal 112 into which the I / O current of the I / O current detection load circuit 110 flows and a terminal 111 from which the I / O current of the I / O current detection load circuit 110 flows out. The input voltage VIO is input to the proportional circuit 410 by terminals 211 and 212. In this case, an attempt is made to estimate the I / O current IIO flowing through the I / O current detection load circuit 110 using the output voltage VOUT output by the proportional circuit 410.

[0044] FIG. 6 is a graph illustrating the I-V conversion coefficient α of the I / O current detection load circuit 110 in the semiconductor device 1001 according to the comparative example. The horizontal axis represents the input voltage VIO between terminals 111 and 112, and the vertical axis represents the I / O current IIO flowing through the I / O current detection load circuit 110. As shown in FIG. 6, the I-V conversion coefficient α of the I / O current detection load circuit 110 is represented as ΔIIO / ΔVIO as the slope of the graph. That is, the I-V conversion coefficient α is represented by Equation (1). The I-V conversion coefficient α is a fixed value.

[0045] α = (ΔIIO / ΔVIO) (1)

[0046] On the other hand, the proportional circuit 410 has a proportionality constant β of the output voltage VOUT with respect to the input voltage VIO. That is, the proportionality constant β is represented by Equation (2). The proportionality constant β is a fixed value.

[0047] β = (ΔVIO / ΔVOUT) (2)

[0048] FIG. 7 is a diagram illustrating the transition of the I-V conversion coefficient α of the I / O current detection load circuit 110 and the proportionality constant β of the proportional circuit 410 in the semiconductor device 1001 according to the comparative example. As shown in FIG. 7, the I / O current IIO flowing through the I / O current detection load circuit 110 is obtained by multiplying the input voltage VIO by the I-V conversion coefficient α. That is, the I / O current IIO is represented by Equation (3).

[0049] IIO = α × VIO (3)

[0050] The input voltage VIO input to the proportional circuit 410 is obtained by multiplying the output voltage VOUT output from the proportional circuit 410 by the proportionality constant β. That is, the input voltage VIO is represented by Equation (4).

[0051] VIO = β × VOUT (4)

[0052] Therefore, using the I-V conversion coefficient α of the I / O current detection load circuit 110 and the proportionality constant β of the proportional circuit 410, the I / O current IIO flowing through the I / O current detection load circuit 110 can be obtained from the output voltage VOUT of the proportional circuit 410 by the following Equation (5).

[0053] IIO = α × β × VOUT (5)

[0054] In order to obtain such an I / O current IIO, it is necessary to specify the I-V conversion coefficient α of the I / O current detection load circuit 110 and the proportionality constant β of the proportional circuit 410. However, the characteristics of the I / O current detection load circuit 110 vary greatly depending on the speed and waveform shape of the IIO current. For this reason, it is difficult to uniquely specify the I-V conversion coefficient α of the I / O current detection load circuit 110.

[0055] FIG. 8 is a graph illustrating the characteristics added to the I-V conversion coefficient α of the I / O current detection load circuit 110 in the semiconductor device 1001 according to the comparative example. The horizontal axis represents the input voltage VIO between the terminal 111 and the terminal 112, and the vertical axis represents the I / O current IIO flowing through the I / O current detection load circuit 110. As shown in FIG. 8, the characteristics A1 and A2 are added to the I-V conversion coefficient α according to the speed and shape of the I / O current IIO flowing through the I / O current detection load circuit 110. Therefore, a current measurement error for a specific difficult offset may occur, and the current measurement accuracy of the proportional circuit 410 may deteriorate.

[0056] FIG. 9 is a diagram illustrating the transition of the I-V conversion coefficient α of the I / O current detection load circuit 110 and the proportionality constant β of the proportional circuit 410 in the semiconductor device 1001 according to the comparative example. As shown in FIG. 9, since an offset Offset is added to the I-V conversion coefficient α, the I / O current IIO flowing through the I / O current detection load circuit 110 is the product of the input voltage VIO and the I-V conversion coefficient (Offset + α). That is, the I / O current IIO is represented by Equation (6).

[0057] IIO = (Offset + α) × VIO (6)

[0058] The input voltage VIO input to the proportional circuit 410 is the product of the proportionality constant β and the output voltage VOUT output by the proportional circuit 410. That is, the input voltage VIO is represented by Equation (7).

[0059] VIO = β × VOUT (7)

[0060] Therefore, using the I-V conversion coefficient (Offset + α) of the I / O current detection load circuit 110 and the proportionality constant β of the proportional circuit 410, the I / O current IIO flowing through the I / O current detection load circuit 110 can be obtained from the output voltage VOUT of the proportional circuit 410 by the following Equation (8).

[0061] IIO = (Offset + α) × β × VOUT (8)

[0062] When an offset is included and the current measurement accuracy of the proportional circuit 410 deteriorates, a new problem has been discovered that it is difficult to establish the mechanism for obtaining the I / O current IIO described above. That is, the I / O current detection load circuit 110 has a first coefficient that is the ratio of the I / O current IIO to the input voltage VIO, and the first coefficient is not constant with respect to the I / O current IIO, and the I / O current IIO and the input voltage VIO are not proportional. Therefore, even when the I / O current IIO flowing through the I / O current detection load circuit 110 is small, it may be misrecognized that a large amount of the I / O current IIO is flowing, and terminals T21 etc. that are not originally stressed may be erroneously detected as being stressed by an ESD / EMS current or the like. Also, even when a large amount of the I / O current IIO flows through the I / O current detection load circuit 110, it may be misrecognized that only a small amount of the I / O current IIO is flowing, and terminals T21 etc. that are originally stressed may be overlooked. For these reasons, it is desired to improve the measurement accuracy of currents such as noise currents.

[0063] (Embodiment 1) Next, a semiconductor device according to Embodiment 1 will be described. This embodiment improves the current measurement accuracy of the proportional circuit 410 shown in the comparative example and enables the mechanism for obtaining the current IIO flowing through the I / O current detection load circuit 110 to function.

[0064] FIG. 10 is a configuration diagram illustrating a semiconductor device according to Embodiment 1. As shown in FIG. 10, the semiconductor device 1 of this embodiment includes current sensor circuits 210 and 220 instead of the current sensor circuits 1210 and 1220 in the comparative example. The other configurations are the same as those of the semiconductor device 1001 in the comparative example. Hereinafter, after explaining <the configuration of the proportional circuit and the proportional current acquisition load circuit>, will be explained. And <the size reduction of the proportional current acquisition load circuit> for solving another problem will be explained.

[0065] <Configuration of the proportional circuit and the proportional current acquisition load circuit> FIG. 11 is a configuration diagram illustrating an I / O current detection load circuit 110 and a current sensor circuit 210 in the semiconductor device 1 according to Embodiment 1. As shown in FIG. 11, the current sensor circuit 210 of the present embodiment includes a proportional circuit 410 and a proportional current acquisition load circuit 510. The proportional current acquisition load circuit 510 is electrically connected to the proportional circuit 410.

[0066] The proportional circuit 410 is connected to terminals 211 and 212. Therefore, when an I / O current IIO flows through the I / O current detection load circuit 110 on the potential supply terminal SU side (potential supply wiring LSU side), the proportional circuit 410 outputs a current measurement result to terminal 217 (OUTP). The proportionality constant β of the proportional circuit 410 is set to be 1-fold. Note that 1-fold means not strictly 1-fold but approximately 1-fold including an inevitable range such as a measurement error. The same applies to 1-fold described later.

[0067] The proportional current acquisition load circuit 510 is connected to terminal 217 and the ground wiring LGR. Specifically, the proportional current acquisition load circuit 510 has two terminals 511 and 512, and one terminal 511 is connected to terminal 217. The other terminal 512 is connected to the ground wiring LGR. The proportional current acquisition load circuit 510 uses the same load circuit as the I / O current detection load circuit 110.

[0068] The proportional current acquisition load circuit 510 is a load circuit for acquiring a current proportional to the I / O current IIO. In other words, it can also be said to be a load circuit for canceling the current measurement error caused by the change in the I-V conversion coefficient α due to the influence of the speed and shape of the I / O current IIO flowing through the I / O current detection load circuit 110. The configurations of the I / O current detection load circuit 110 and the proportional current acquisition load circuit 510 include, for example, a PN junction diode, a MOS transistor, etc., which will be described later. Note that the configuration of the load circuit is not limited to these.

[0069] As described above, in the semiconductor device 1 of the present embodiment, the current sensor circuit 210 doubles the proportionality constant β of the proportional circuit 410 and uses the same load circuit as the I / O current detection load circuit 110 as the proportional current acquisition load circuit 510. As a result, the current sensor circuit 210 can acquire an output current IOUT proportional to the I / O current IIO flowing through the I / O current detection load circuit 110. The output current IOUT is also referred to as the sensor current. When the proportionality constant β of the proportional circuit 410 is set to double, the output current IOUT (sensor current) is equivalent to the I / O current IIO. That is, the proportional circuit 410 takes the input voltage as an input and outputs a voltage obtained by multiplying the input voltage by approximately 2 as the output voltage. The proportional circuit 410 inputs the output voltage to the proportional current acquisition load circuit 510 and causes the output current IOUT (sensor current) to flow through the proportional current acquisition load circuit 510. The proportional current acquisition load circuit 510 has an output voltage VOUT input between a terminal 511 into which the output current IOUT flows and a terminal 512 from which the output current IOUT flows out. The current sensor circuit 210 outputs the acquired output current IOUT as output information to the information processing circuit 310.

[0070] FIG. 12 is a diagram illustrating the transition of the I-V conversion coefficient α of the I / O current detection load circuit 110 and the proportionality constant β of the proportional circuit 410 in the semiconductor device according to Embodiment 1. As shown in FIG. 12, since an offset Offset is added to the I-V conversion coefficient α, the I / O current IIO flowing through the I / O current detection load circuit 110 is the product of the input voltage VIO and the I-V conversion coefficient (Offset + α). That is, the I / O current IIO is represented by Equation (9).

[0071] IIO = (Offset + α) × VIO (9)

[0072] The output current IOUT flowing through the proportional current acquisition load circuit 510 is the product of the output voltage VOUT of the proportional circuit 410 and the I-V conversion coefficient (Offset + α). That is, the output current IOUT is represented by Equation (10).

[0073] IOUT = (Offset + α) × VOUT (10)

[0074] Equations (9) and (10) can be transformed into equations (11) and (12).

[0075] VIO = IIO / (Offset + α) (11) VOUT = IOUT / (Offset + α) (12)

[0076] Here, since the proportionality constant β = 1, equation (13) holds. This is because the proportional circuit 410 operates according to equation (7): VIO = β × VOUT.

[0077] VIO = VOUT (13)

[0078] From equation (13), using equations (11) and (12), equation (14) is derived.

[0079] IIO = IOUT (14)

[0080] In this embodiment, the same voltages, namely the input voltage VIO and the output voltage VOUT, are applied to the I / O current detection load circuit 110 and the proportional current acquisition load circuit 510 of the same load circuit, respectively. Therefore, it is characterized in that the current IIO is equivalent to the output current IOUT.

[0081] In other words, the proportional current acquisition load circuit 510 has a second coefficient that is the ratio of the output current IOUT (sensor current) to the output voltage VOUT. The ratio of the first coefficient to the second coefficient is approximately 1-fold and equivalent. The I / O current IIO is the product of the first coefficient and the input voltage VIO. The output current IOUT (sensor current) is the product of the second coefficient and the output voltage VOUT. Since the ratio of the input voltage VIO to the output voltage VOUT is approximately 1-fold, the input voltage VIO and the output voltage VOUT are equivalent. Since the ratio of the first coefficient to the second coefficient is approximately 1-fold, the first coefficient and the second coefficient are equivalent. The I / O current IIO can be replaced with the product of the second coefficient and the output voltage VOUT. The output current IOUT (sensor current) can be replaced with the product of the first coefficient and the input voltage VIO. The ratio of the I / O current IIO to the output current IOUT becomes approximately 1-fold, and the I / O current IIO and the output current IOUT (sensor current) are proportional.

[0082] In this way, the semiconductor device of the present embodiment measures at least one of the ESD current and the EMS current that enters the IC 20 from the terminals that come out of the substrate 10 using the current sensor circuit 210 in the IC 20. The current sensor circuit 210 can cancel the offset of the I-V conversion coefficient α of the proportional circuit 410 by the proportional current acquisition load circuit 510. Thereby, the measurement accuracy of the amount of current such as noise can be improved. Then, by processing the measured amount of current in the information processing circuit 330, the current stress amount of each terminal can be grasped, and based on that information, it is possible to detect whether there is a possibility of destruction or malfunction of the IC 20. In this way, destruction and malfunction of the IC 20 can be appropriately suppressed.

[0083] <Specific circuit example of proportional circuit> Next, a specific circuit example of the proportional circuit 410 will be described. First, a circuit example for measuring the I / O current IIOP flowing from the terminal T21 (also referred to as an input / output terminal, I / O terminal) to the potential supply wiring LSU side (potential supply terminal SU side) will be described. The I / O current IIOP is referred to as a positive current in the present embodiment.

[0084] FIG. 13 is a circuit diagram illustrating a current sensor circuit in the semiconductor device 1 according to Embodiment 1. As shown in FIG. 13, the current sensor circuit 210P includes a proportional circuit 410P and a proportional current acquisition load circuit 510P. The proportional circuit 410P includes a P-type transistor PT, an N-type transistor NT, and a resistor R.

[0085] The gate of the P-type transistor PT is connected to the potential supply wiring LSU. The source of the P-type transistor PT is connected to the terminal T21 via the terminal 212 and the signal line 23. The drain of the P-type transistor PT is connected to one end of the resistor R.

[0086] One end of the resistor R is connected to the drain of the P-type transistor PT. The other end of the resistor R is connected to the ground wiring LGR via the terminal 213.

[0087] The gate of the N-type transistor NT is connected to the drain of the P-type transistor PT and one end of the resistor R. The source of the N-type transistor NT is connected to the terminal 511 of the proportional current acquisition load circuit 510P. The drain of the N-type transistor NT is connected to the source of the P-type transistor and the terminal 212. The terminal 512 of the proportional current acquisition load circuit 510P is connected to the ground wiring LGR via the other end of the resistor and the terminal 213.

[0088] Here, the I / O current flowing through the I / O current detection load circuit 110 is called IIOP, the input voltage of the proportional circuit 410P is called VIOP, the output voltage of the proportional circuit 410P is called VOUTP, and the output current (sensor current) of the proportional circuit 410P is called IOUTP. The I-V conversion coefficient of the I / O current detection load circuit 110 is Offset (fluctuation value) + α (fixed value). The proportionality constant of the proportional circuit 410P is β (fixed value), which is ΔVIOP / ΔVOUTP.

[0089] The proportional circuit 410P acquires an output current IOUTP equivalent to the positive current IIOP flowing through the I / O current detection load circuit 110 by the following operation.

[0090] Operation 1. When a positive current IIOP flows through the input / output terminal (also referred to as terminal T21 or I / O terminal), an input voltage VIOP is generated between the input / output terminal and the potential supply terminal SU.

[0091] Operation 2. The proportional circuit 410P operates with a proportional constant β ≈ 1 times. That is, Equation (15) holds in the same way as Equation (13).

[0092] VIOP = VOUTP (15)

[0093] Operation 3. Since the I / O current detection load circuit 110 and the proportional current acquisition load circuit 510P are the same load circuit, the following equations (16) to (20) hold in the same way as the above (9) to (12), (14).

[0094] IIOP = (Offset + α) × VIOP (16) IOUTP = (Offset + α) × VOUTP (17) VIOP = IIOP / (Offset + α) (18) VOUTP = IOUTP / (Offset + α) (19) From the relationship of Equation (15), the following Equation (20) is obtained. IIOP = IOUTP (20)

[0095] Next, a circuit example for measuring the I / O current IION flowing from the terminal T32 (ground terminal GR) on the ground wiring LGR side to the terminal T21 (input / output terminal, also referred to as I / O terminal) will be described. The I / O current IION is referred to as a negative current in this embodiment.

[0096] FIG. 14 is a circuit diagram illustrating a current sensor circuit in the semiconductor device 1 according to Embodiment 1. As shown in FIG. 14, the current sensor circuit 210N includes a proportional circuit 410N and a proportional current acquisition load circuit 510N. The proportional circuit 410N includes an N-type transistor NT, a P-type transistor PT, and a resistor R.

[0097] The gate of the N-type transistor NT is connected to the ground wiring LGR. The source of the N-type transistor NT is connected to the terminal T21 via the terminal 212 and the signal line 23. The drain of the N-type transistor NT is connected to one end of the resistor R.

[0098] One end of the resistor R is connected to the drain of the N-type transistor NT. The other end of the resistor R is connected to the potential supply wiring LSU2.

[0099] The gate of the P-type transistor PT is connected to the drain of the N-type transistor NT and one end of the resistor R. The source of the P-type transistor PT is connected to the terminal 512 of the proportional current acquisition load circuit 510N. The drain of the P-type transistor PT is connected to the terminal T21 via the source of the N-type transistor NT and the terminal 212. The terminal 511 of the proportional current acquisition load circuit 510N is connected to the potential supply wiring LSU2.

[0100] Here, the I / O current flowing through the I / O current detection load circuit 120 is called IION, the input voltage of the proportional circuit 410N is called VION, the output voltage of the proportional circuit 410N is called VOUTN, and the output current of the proportional circuit 410N is called IOUTN. The I-V conversion coefficient of the I / O current detection load circuit 120 is Offset (fluctuating value) + α (fixed value). The proportional constant of the proportional circuit 410N is β (fixed value), which is ΔVION / ΔVOUTN.

[0101] The proportional circuit 410N acquires an I / O current IOUTN equivalent to the negative I / O current IION flowing through the I / O current detection load circuit 120 by the following operation.

[0102] Operation 1. When a negative current IION flows through the input / output terminal (also called the terminal T21, I / O terminal), an input voltage VION is generated between the input / output terminal and the ground terminal GR.

[0103] Operation 2. The proportional circuit 410N operates with a proportional constant β ≒ 1 times. That is, the equation (21) holds in the same way as the equation (15).

[0104] VION = VOUTN (21)

[0105] Since the I / O current detection load circuit 120 and the proportional current acquisition load circuit 510N are the same load circuit, the following equations (22) to (26) hold in the same manner as in the above (16) to (20).

[0106] IION = (Offset + α) × VION (22) IOUTN = (Offset + α) × VOUTN (23) VION = IION / (Offset + α) (24) VOUTN = IOUTN / (Offset + α) (25) From the relationship of equation (21), the following equation (26) is obtained. IION = IOUTN (26)

[0107] In the semiconductor device described above, in actual use, the following two points may become problems. One is an increase in the layout area. An increase in area equivalent to that of a protection circuit, a driver circuit, etc. can be considered on the IC20. The other is a concern about chip internal breakdown due to an increase in the chip internal current of the IC20. The I / O current IIOP flowing through the I / O current detection load circuit 110 and the I / O current IION flowing through the I / O current detection load circuit 120 are up to several amperes. If the same current flows inside the chip of the IC20, there is a possibility of chip internal breakdown. Due to such problems, it is desirable that the proportional current acquisition load circuits 510P and 510N be the same size as or smaller than the I / O current detection load circuits 110 and 120.

[0108] <Reduction in the size of the proportional current acquisition load circuit> FIG. 15 is a circuit diagram illustrating a current sensor circuit in the semiconductor device 1 according to Embodiment 1. As shown in FIG. 15, the current sensor circuit 210PS has a proportional circuit 410P and a proportional current acquisition load circuit 510PS. The proportional current acquisition load circuit 510PS is the same size as or smaller than the I / O current detection load circuit 110.

[0109] Here, a method for reducing the size of the proportional current acquisition load circuit 510PS is shown below. First, the case of a circuit for measuring the I / O current IIOP flowing from the input / output terminal (also called terminal T21 or I / O terminal) to the potential supply wiring LSU side will be described. Through the following operations 1 to 4, an output current IOUTP (sensor current) proportional to the I / O current IIOP flowing through the I / O current detection load circuit 110 is obtained.

[0110] Operation 1. When a positive current IIOP flows through the input / output terminal (terminal T21), an input voltage VIOP is generated between the input / output terminal and the potential supply terminal SU.

[0111] Operation 2. The proportional circuit 410P operates with a proportional constant β ≈ 1 times. That is, the following equation (15) holds.

[0112] Operation 3. The I / O current detection load circuit 110 and the proportional current acquisition load circuit 510PS are the same load circuit, and the proportional current acquisition load circuit 510PS is smaller in size than the I / O current detection load circuit 110. Therefore, the following equation (27) holds.

[0113] Size of I / O current detection load circuit 110: Size of proportional current acquisition load circuit 510PS = 1:N (1 > N) (27)

[0114] Operation 4. The following equations (28) to (32) hold.

[0115] IIOP = (Offset + α) × VIOP (28) IOUTP = (Offset + α) × VOUTP × N (29) VIOP = IIOP / (Offset + α) (30) VOUTP = IOUTP / (Offset + α) × 1 / N (31) Based on the relationship of equation (15), the following equation (32) is obtained. IIOP = IOUTP × 1 / N (32)

[0116] Next, a circuit for measuring the I / O current IION flowing from the terminal T32 (ground terminal GR) connected to the ground wiring LGR to the input / output terminal (also referred to as the terminal T21 or the I / O terminal) will be described. FIG. 16 is a circuit diagram illustrating a current sensor circuit in the semiconductor device 1 according to Embodiment 1. As shown in FIG. 16, the current sensor circuit 210NS includes a proportional circuit 410N and a proportional current acquisition load circuit 510NS. The proportional current acquisition load circuit 510NS is smaller in size than the I / O current detection load circuit 120. The following operations 1 to 4 are used to acquire a current IOUTN proportional to the current IION flowing through the I / O current detection load circuit 120.

[0117] Operation 1. When a negative current IION flows through the input / output terminal (terminal T21), an input voltage VION is generated between the input / output terminal and the ground terminal GR.

[0118] Operation 2. The proportional circuit 410N operates with a proportionality constant β≈1 times. That is, the following equation (21) holds.

[0119] Operation 3. The I / O current detection load circuit 120 and the proportional current acquisition load circuit 510NS are the same load circuit, and the proportional current acquisition load circuit 510NS is smaller in size than the I / O current detection load circuit 120. Therefore, the following equation (33) holds.

[0120] Size of the I / O current detection load circuit 120: Size of the proportional current acquisition load circuit 510NS =1:N (1 > N) (33)

[0121] Operation 4. The following equations (34) to (38) hold.

[0122] IION = (Offset + α) × VION (34) IOUTN = (Offset + α) × VOUTN × N (35) VION = IION / (Offset + α) (36) VOUTN = IOUTN / (Offset + α) × 1 / N (37) Based on the relationship of equation (21), the following equation (38) is obtained. IION = IOUTN × 1 / N (38)

[0123] In this way, when the sizes of the I / O current detection load circuits 110 and 120 and the proportional current acquisition load circuit 510 are different, for example, even when the size of the proportional current acquisition load circuit 510 is small, the I / O current and the output current (sensor current) are in a proportional relationship. Therefore, the ratio of the first coefficient to the second coefficient is approximately a constant multiple. The I / O current is the product of the first coefficient and the input voltage. The sensor current is the product of the second coefficient and the output voltage. Since the ratio of the input voltage to the output voltage is approximately 1 times, the input voltage and the output voltage are equivalent. Since the ratio of the first coefficient to the second coefficient is approximately a constant multiple, the first coefficient and the second coefficient are proportional. The I / O current is proportional to the product of the second coefficient and the output voltage. The sensor current is proportional to the product of the first coefficient and the input voltage. The I / O current and the sensor current are proportional.

[0124] By adopting such a configuration, an increase in the layout area of the semiconductor device 1 can be suppressed, and an increase in area can be suppressed as compared with a protection circuit, a driver circuit, etc. Also, an increase in the internal current of the chip of the IC20 can be suppressed, and internal breakdown of the chip can be suppressed.

[0125] (Embodiment 2) Next, a semiconductor device according to Embodiment 2 will be described. The semiconductor device of this embodiment includes a conversion circuit that outputs the output currents IOUTP and IOUTN of the proportional circuit 410 as voltages. First, a case of a circuit that measures the I / O current IIOP flowing from the input / output terminal (also called terminal T21, I / O terminal) to the potential supply wiring LSU side will be described.

[0126] FIG. 17 is a circuit diagram illustrating a current sensor circuit in the semiconductor device according to Embodiment 2. As shown in FIG. 17, in the semiconductor device 2 of the present embodiment, the current sensor circuit 230P includes a proportional circuit 430P, a proportional current acquisition load circuit 510P, and a conversion circuit 610P. The proportional circuit 430P includes a P-type transistor PT, an N-type transistor NT, a resistor Rs, and a bias Vb. The conversion circuit 610P includes a current mirror MR1, a current mirror MR2, and a resistor Ro. The conversion circuit 610P converts the output current IOUTP of the proportional circuit 430P into an output voltage. The output current IOUTP is also referred to as a sensor current, and the output voltage is also referred to as a sensor voltage. The conversion circuit 610P outputs the converted output voltage as output information to the information processing circuit 310.

[0127] The gate of the P-type transistor PT is connected to the potential supply wiring LSU. The source of the P-type transistor PT is connected to the terminal T21 via the terminal 212 and the signal line 23. The drain of the P-type transistor PT is connected to one end of the resistor Rs.

[0128] One end of the resistor Rs is connected to the drain of the P-type transistor PT. The other end of the resistor Rs is connected to the positive terminal of the bias Vb. The negative terminal of the bias Vb is connected to the ground wiring LGR via the terminal 213.

[0129] The gate of the N-type transistor NT is connected to the drain of the P-type transistor PT and one end of the resistor R. The source of the N-type transistor NT is connected to the terminal 511 of the proportional current acquisition load circuit 510P. The drain of the N-type transistor NT is connected to the terminal T21 via the source of the P-type transistor PT and the terminal 212.

[0130] The current mirror MR1 includes two N-type transistors NT. The gates of each N-type transistor NT are connected to each other, and the sources of each N-type transistor NT are connected to each other. The drain and gate of one N-type transistor NT in the current mirror MR1 are connected. The drain of one N-type transistor NT of the current mirror MR1 is connected to the terminal 512 of the proportional current acquisition load circuit 510P. The source of each N-type transistor NT of the current mirror MR1 is connected to the ground wiring LGR via the negative terminal of the bias Vb and the terminal 213.

[0131] The current mirror MR2 includes two P-type transistors PT. The gates of each P-type transistor PT are connected to each other, and the sources of each P-type transistor PT are connected to each other. The drain and gate of one P-type transistor PT in the current mirror MR2 are connected. The drain of one P-type transistor PT in the current mirror MR2 is connected to the drain of the other N-type transistor NT in the current mirror MR1. The source of each P-type transistor PT of the current mirror MR2 is connected to the potential supply wiring LSU2. The drain of the other P-type transistor PT in the current mirror MR2 is connected to one end of the resistor Ro. The other end of the resistor Ro is connected to the ground wiring LGR via the source of each N-type transistor NT in the current mirror MR1, the negative terminal of the bias Vb, and the terminal 213.

[0132] The current sensor circuit 230P of this embodiment connects current mirrors MR1 and MR2 to the path through which the output current IOUTP (sensor current) flows. By flowing the current obtained by mirroring the output current IOUTP through the resistor Ro, an output voltage VOUTP1 proportional to the output current IOUTP is obtained. In this way, by converting the output current IOUTP into the output voltage VOUTP1, the output current IOUTP can be output as the output voltage VOUTP1. In this case, a bias Vb is required to cancel the voltage drop generated by the diode-connected MOS in which the transistor is connected in the current mirror MR1. A transistor with its drain and gate connected is generally called a diode-connected MOS. A diode-connected MOS can be treated as equivalent to a voltage source when its output resistance is small compared to the resistance values of other circuits.

[0133] FIG. 18 is a circuit diagram illustrating another current sensor circuit in the semiconductor device 2 according to Embodiment 2. As shown in FIG. 18, another current sensor circuit 250P includes a proportional circuit 450P, a proportional current acquisition load circuit 510P, and a conversion circuit 610P. The proportional circuit 450P has a diode-connected multi-stage stack 3NT instead of the resistor Rs and the bias Vb. Specifically, instead of the resistor Rs and the bias Vb, three N-type transistors NT are connected. The gate and drain of the first N-type transistor NT are connected to the drain of the P-type transistor PT in the proportional circuit 450P. The gate and drain of the second N-type transistor are connected to the source of the first N-type transistor NT. The gate and drain of the third N-type transistor are connected to the source of the second N-type transistor NT. The source of the third N-type transistor NT is connected to the ground wiring LGR via the terminal 213.

[0134] In this way, the proportional circuit 450P in the current sensor circuit 250P generates the functions of the resistor Rs and the bias Vb using the diode-connected multi-stage stack 3NT. This utilizes the fact that in the linear region, the diode-connected multi-stage stack 3NT is equivalent to the resistor Rs and the bias Vb.

[0135] Next, a case of a circuit that measures an I / O current IION flowing from a terminal T32 connected to a ground wiring LGR to an input / output terminal (also referred to as a terminal T21 or an I / O terminal) among circuits that output output currents IOUTP and IOUTN of current sensor circuits 230P and 230N as voltages will be described.

[0136] FIG. 19 is a circuit diagram illustrating a current sensor circuit in a semiconductor device according to Embodiment 2. As shown in FIG. 19, the current sensor circuit 230N includes a proportional circuit 430N, a proportional current acquisition load circuit 510N, and a conversion circuit 610N. The proportional circuit 430N includes an N-type transistor NT, a P-type transistor PT, a resistor Rs, and a bias Vb. The conversion circuit 610N includes a current mirror MR3 and a resistor Ro. The conversion circuit 610N converts the output current IOUTN of the proportional circuit 430N into an output voltage. The output current IOUTN is also referred to as a sensor current, and the output voltage is also referred to as a sensor voltage. The conversion circuit 610N outputs the converted output voltage to the information processing circuit 310 as output information.

[0137] The gate of the N-type transistor NT is connected to the ground wiring LGR. The source of the N-type transistor NT is connected to the terminal T21 via the terminal 212 and the signal line 23. The drain of the N-type transistor NT is connected to the negative terminal of the bias Vb and the gate of the P-type transistor PT.

[0138] The positive terminal of the bias Vb is connected to one end of the resistor Rs. The other end of the resistor Rs is connected to the potential supply wiring LSU2.

[0139] The gate of the P-type transistor PT is connected to the drain of the N-type transistor NT and the negative terminal of the bias Vb. The source of the P-type transistor PT is connected to the terminal 512 of the proportional current acquisition load circuit 510N. The drain of the P-type transistor PT is connected to the terminal T21 via the source of the N-type transistor NT and the terminal 212.

[0140] The current mirror MR3 includes two P-type transistors PT. The gates of the P-type transistors PT are connected to each other, and the sources of the P-type transistors PT are connected to each other. The drain and the gate of one of the P-type transistors PT in the current mirror MR3 are connected. The drain of one of the P-type transistors PT in the current mirror MR3 is connected to the terminal 511 of the proportional current acquisition load circuit 510N. The source of each P-type transistor PT of the current mirror MR3 is connected to the potential supply wiring LSU2 together with the other end of the resistor Rs. The drain of the other P-type transistor PT in the current mirror MR3 is connected to one end of the resistor Ro. The other end of the resistor Ro is connected to the ground wiring LGR.

[0141] The current sensor circuit 230N of the present embodiment connects the current mirror MR3 to the path through which the output current IOUTN (sensor current) flows. By flowing the current obtained by mirroring the output current IOUTN through the resistor Ro, an output voltage VOUTN1 proportional to the output current IOUTN is obtained. In this way, by converting the output current IOUTN into the output voltage VOUTN1, the output current IOUTN can be output as the output voltage VOUTN1. In this case, a bias Vb is required to cancel the voltage drop generated in the diode-connected MOS in which the transistor is connected in the current mirror MR3. As described above, a transistor having its drain and gate connected is generally called a diode-connected MOS. The diode-connected MOS can be treated as equivalent to a voltage source when the output resistance is small compared to the resistance values of other circuits.

[0142] FIG. 20 is a circuit diagram illustrating another current sensor circuit in the semiconductor device 2 according to Embodiment 2. As shown in FIG. 20, another current sensor circuit 250N has a diode-connected multi-stage stacked 3PT instead of the resistor Rs and the bias Vb. Specifically, instead of the resistor Rs and the bias Vb, three P-type transistors PT are connected. The source of the first P-type transistor PT is connected to the potential supply wiring LSU2. The gate and drain of the first P-type transistor PT are connected to the source of the second P-type transistor PT. The gate and drain of the second P-type transistor PT are connected to the source of the third P-type transistor PT. The gate and drain of the third P-type transistor PT are connected to the drain of the N-type transistor NT in the proportional circuit 450N and the gate of the P-type transistor PT in the proportional circuit 450N.

[0143] In this way, the current sensor circuit 250N generates the functions of the resistor Rs and the bias Vb with the diode-connected multi-stage stacked 3PT. This uses the fact that the diode-connected multi-stage stacked 3PT is equivalent to the resistor Rs and the bias Vb in the linear region.

[0144] FIG. 21 is a circuit diagram illustrating the I / O current detection load circuits 110 and 120 and the current sensor circuit 250 in the semiconductor device 2 according to Embodiment 2. FIG. 22 is a configuration diagram illustrating the current sensor circuit 250 in the semiconductor device 2 according to Embodiment 2.

[0145] As shown in FIGS. 21 and 22, the current sensor circuit 250 may include a proportional circuit 450P and a proportional circuit 450N. The proportional circuit 450P measures the positive current IIOP flowing through the I / O current detection load circuit 110 on the potential supply wiring LSU side. The proportional circuit 450N measures the negative current IION flowing through the I / O current detection load circuit 120 on the ground wiring LGR side. The ground wiring LGR in the proportional circuit 450P is connected to the ground wiring LGR in the proportional circuit 450N. The potential supply wiring LSU2 in the proportional circuit 450P is connected to the potential supply wiring LSU2 in the proportional circuit 450N.

[0146] According to the semiconductor device 2 of this embodiment, the current sensor circuit 250 can measure the positive current IIOP flowing through the I / O current detection load circuit 110 and the negative current IION flowing through the I / O current detection load circuit 120.

[0147] (Embodiment 3) Next, a semiconductor device according to Embodiment 3 will be described. The semiconductor device of this embodiment detects that an ESD and / or EMS current has flowed by a certain amount or more, and uses the detection signal as a trigger to prevent malfunction of the IC20.

[0148] FIG. 23 is a configuration diagram illustrating a semiconductor device according to Embodiment 3. As shown in FIG. 23, the semiconductor device 3 includes I / O current detection load circuits 110 and 120, a current sensor circuit 210, a comparison circuit 700, and an information processing circuit 330. The information processing circuit 330 includes, for example, an IP380 and a CPU370. The comparison circuit 700 is connected to the current sensor circuit 210. Specifically, the comparison circuit 700 is provided at the subsequent stage of the current sensor circuit 210. The comparison circuit 700 is connected to an information processing circuit 330 such as the IP380 and the CPU370.

[0149] The comparison circuit 700 compares whether the amount of the I / O current IIO flowing through the I / O current detection load circuits 110 and 120 measured by the current sensor circuit 210 is greater than a reference value REF. The reference value REF is, for example, set in advance. When the amount of current is greater than the reference value REF, the comparison circuit 700 activates the malfunction prevention example shown below to suppress malfunction of the information processing circuit 330 such as the IP380 and the CPU370.

[0150] Malfunction prevention example 1. During the period when the ESD and / or EMS current amount exceeds the reference value REF, increase the malfunction tolerance of the information processing circuit 330. For example, increase the malfunction tolerance of the IP380 in the information processing circuit 330.

[0151] Example of malfunction prevention 2. During the period when the ESD and / or EMS current exceeds the reference value REF, the data handled by the information processing circuit 330 is invalidated. For example, the data handled by the CPU 370 in the information processing circuit 330 is invalidated.

[0152] In this way, when a current equal to or greater than the reference value REF is input from the input / output terminal, the comparison circuit 700 notifies the IP 380, CPU 370, etc. in the information processing circuit 330 that the ESD and / or EMS current has been detected, and executes the malfunction prevention example.

[0153] The differences between the above-described comparative example and the present embodiment are as follows. That is, the comparative example has a function of storing the measured current amount in the memory circuit 360 for a long time and having the CPU 370 process the information to determine whether there is a possibility of destruction or malfunction of the IC 20. On the other hand, in the present embodiment, the comparison circuit 700 has a function of detecting that the measured current amount has exceeded the reference value REF even temporarily, notifying abnormalities to the IP 380, CPU 370, etc. in the IC 20, and preventing malfunctions.

[0154] When the current sensor circuit 210 of the present embodiment is not used and the current measurement accuracy is degraded, malfunction of the information processing circuit 330 such as the IP 380 and CPU 370 cannot be suppressed. Even when the I / O current IIO flowing through the I / O current detection load circuits 110 and 120 is small, if it is erroneously recognized that a large amount of current is flowing, it is thus erroneously recognized that the reference value REF is exceeded, and the malfunction prevention examples 1 and 2 are operated. Also, even when the I / O current IIO flowing through the I / O current detection load circuit 110 is large, if it is erroneously recognized that only a small amount of current is flowing, it is thus erroneously recognized that the reference value REF is not exceeded, and the malfunction prevention examples 1 and 2 are not operated. In contrast, in the present embodiment, by using the current sensor circuit 210, the current measurement accuracy can be improved, and malfunction of the information processing circuit 330 such as the IP 380 and CPU 370 can be suppressed.

[0155] Next, examples of the I / O current detection load circuit 110 and the proportional current acquisition load circuit 510 will be described. The I / O current detection load circuit 110 and the proportional current acquisition load circuit 510 include the same load circuit. Therefore, hereinafter, the I / O current detection load circuit 110 will be described.

[0156] FIGS. 24 and 25 are diagrams illustrating the I / O current detection load circuit 110 in the semiconductor devices of Embodiments 1 to 3. As shown in FIG. 24, the I / O current detection load circuit 110 may include a PN junction diode. Further, as shown in FIG. 25, the I / O current detection load circuit 110 may include a MOS transistor. Thus, the I / O current detection load circuit 110 and the proportional current acquisition load circuit 510 may include at least one of a PN junction diode and a MOS transistor. Note that the I / O current detection load circuit 110 may include a circuit other than a PN junction diode and a MOS transistor as long as it can detect the I / O current flowing from the input / output terminal (also referred to as the I / O terminal) to the potential supply wiring LSU or / and the ground wiring LGR. For example, it may include a bipolar transistor.

[0157] Next, the structure of the above-described I / O current detection load circuit 110 will be described. FIGS. 26 to 31 are cross-sectional views illustrating the I / O current detection load circuit 110 in the semiconductor devices of Embodiments 1 to 3. As shown in FIG. 26, the MOS transistor may include an N layer serving as a drain disposed on a P layer (P-type Layer), an N layer serving as a source disposed on the P layer, a STI disposed on the N layer serving as the drain, a gate covering the STI, the N layer serving as the drain, the P layer, and the N layer serving as the source, and a back gate connecting the P layer and the source.

[0158] Also, as shown in FIG. 27, the MOS transistor may include a P layer serving as a drain disposed on an N layer, a P layer serving as a source disposed on the N layer, a shallow trench isolation (STI) disposed on the P layer serving as the drain, a gate covering the STI, the P layer serving as the drain, the N layer, and the P layer serving as the source, and a back gate connecting the N layer and the source.

[0159] Also, as shown in FIG. 28, the MOS transistor may include an N layer serving as a drain disposed on a P layer, an N layer serving as a source disposed on the P layer, a gate covering the N layer serving as the drain, the P layer, and the N layer serving as the source, and a back gate connected to the N layer.

[0160] Also, as shown in FIG. 29, the MOS transistor may include a P layer serving as a drain disposed on an N layer, a P layer serving as a source disposed on the N layer, a gate covering the P layer serving as the drain, the N layer, and the P layer serving as the source, and a back gate connected to the N layer.

[0161] Also, as shown in FIG. 30, the MOS transistor may include a P substrate (P-substrate), an N buried layer (N-Buried) disposed on the P substrate, an N well (N-well) disposed on the N buried layer, a P+ layer serving as a source disposed on the N well, an N+ layer disposed adjacent to the P+ layer serving as the source on the N well, a P drift layer (P-drift) disposed on the N well, a P well (P-well) disposed on the P drift layer, a shallow trench isolation (STI) disposed on the P drift layer and the P well so as to be in contact with the P drift layer and the P well, a P+ layer serving as a drain disposed on the P well adjacent to the STI, a gate (Gate) covering the P+ layer serving as the source, the N well, the P drift layer, and the STI, and a back gate connecting the P+ layer serving as the source and the N+ layer.

[0162] Also, as shown in FIG. 31, the MOS transistor includes a P substrate, an N-embedded layer disposed on the P substrate, a P-epitaxial layer (P-EPI) disposed on the N-embedded layer, a P well disposed on the P-EPI layer, an N+ layer serving as a source disposed on the P well, a P+ layer disposed adjacent to the N+ layer serving as a source on the P well, an N-drift layer (N-drift) disposed on the P-EPI layer, an N well disposed on the N-drift layer, a shallow trench isolation (STI) disposed on the N-drift layer and the N well so as to be in contact with the N-drift layer and the N well, an N+ layer serving as a drain disposed on the N well so as to be adjacent to the STI, a gate (Gate) covering the N+ layer serving as a source, the P well, the P-EPI layer, the N-drift layer and the STI, and a back gate connecting the N+ layer serving as a source and the P+ layer.

[0163] The I / O current detection load circuit 110 and the like may include MOS transistors as shown in FIGS. 26 to 31. The N layers (N-type Layer, N-buried, N-well, N-drift, N+, etc.) refer to N-type diffusion layers, and the P layers (P-type Layer, P-substrate, P-drift, P-well, P-EPI, P+, etc.) refer to P-type diffusion layers. Regardless of what impurities are mixed in and what the impurity concentration is, anything corresponding to a P-type diffusion layer is regarded as a P layer, and anything corresponding to an N-type diffusion layer is regarded as an N layer.

[0164] As shown in FIGS. 26, 28, and 31, in the case of an N-type MOS transistor, an N layer is electrically connected to the drain, and a P layer is electrically connected to the back gate. There is a parasitic diode in which the P layer and the N layer are combined between the back gate and the drain.

[0165] As shown in FIGS. 27, 29, and 30, in the case of a P-type MOS transistor, a P layer is electrically connected to the drain, and an N layer is electrically connected to the back gate. There is a parasitic diode formed by the combination of the P layer and the N layer between the drain and the back gate. Therefore, the diode described above includes at least one of the PN junction diode and the parasitic diode generated between the drain and the back gate of the MOS transistor. In FIG. 25, between T31 and T21 is a P-type MOS transistor as shown in FIGS. 27, 29, and 30, and between T21 and T32 is an N-type MOS transistor as shown in FIGS. 26, 28, and 31. However, this is not the only case. An N-type MOS transistor may be used between T31 and T21, and a P-type MOS transistor may be used between T21 and T32.

[0166] The I / O current detection load circuit 110 etc. and the proportional current acquisition load circuit 510 etc. are diodes, and the diodes have the same cross-sectional structure. Here, the same cross-sectional structure means that, as shown in FIGS. 26 to 31, the cross-sectional structures are the same. That is, the same cross-sectional structure means that differences within the normal distribution such as manufacturing variations and process variations are regarded as the same cross-sectional structure. Also, the same cross-sectional structure means that even when the sizes of the P layer, N layer, and STI are different, it is still regarded as the same cross-sectional structure. Further, the same cross-sectional structure means that even when there are differences in the positions of the drain, gate, source, and back gate terminals, it is still regarded as the same cross-sectional structure.

[0167] As described above, the invention made by the present inventor has been specifically described based on the embodiments. However, it goes without saying that the present invention is not limited to the above embodiments and can be variously modified without departing from the gist thereof. Also, combinations of the configurations of Embodiments 1 to 3 are also within the scope of the technical idea.

[0168] (Appendix 21) The first proportional current acquisition load circuit has the same size as the first I / O current detection load circuit or is smaller in size than the first I / O current detection load circuit. The second proportional current acquisition load circuit has the same size as the second I / O current detection load circuit or a smaller size than the second I / O current detection load circuit. The semiconductor device according to Supplementary Note 19. (Supplementary Note 22) The first current sensor circuit further includes a first conversion circuit that converts the first sensor current into a first sensor voltage. The second current sensor circuit further includes a second conversion circuit that converts the second sensor current into a second sensor voltage. The first conversion circuit outputs the converted first sensor voltage as the first output information. The second conversion circuit outputs the converted second sensor voltage as the second output information. The semiconductor device according to Supplementary Note 19. (Supplementary Note 23) The first conversion circuit and the second conversion circuit include a current mirror circuit and a resistor. The semiconductor device according to Supplementary Note 22. (Supplementary Note 24) The first proportional circuit and the second proportional circuit include a transistor, a resistor, and a bias. The semiconductor device according to Supplementary Note 23. (Supplementary Note 25) The first proportional circuit and the second proportional circuit include a transistor and a diode-connected multi-stage stack of transistors. The semiconductor device according to Supplementary Note 23. (Supplementary Note 26) It further has a comparison circuit that compares the first sensor current and the second sensor current with a reference value. When at least one of the first sensor current and the second sensor current is greater than the reference value, the comparison circuit increases the malfunction tolerance of the information processing circuit. The semiconductor device according to Supplementary Note 19. (Supplementary Note 27) It further has a comparison circuit that compares the first sensor current and the second sensor current with a reference value. When at least one of the first sensor current and the second sensor current is greater than the reference value, the comparison circuit invalidates the data processed by the information processing circuit. The semiconductor device according to Supplementary Note 19. (Supplementary Note 28) The first I / O current detection load circuit, the first proportional current acquisition load circuit, the second I / O current detection load circuit, and the second proportional current acquisition load circuit include at least one of a PN junction diode, a bipolar transistor, and a MOS transistor. The semiconductor device according to Supplementary Note 19.

Explanation of Reference Signs

[0169] 1, 2, 3 Semiconductor device 10 Substrate 11, 12 Substrate load circuit 13, 14 Signal line 20 IC 21, 22 Power supply load circuit 23, 24 Signal line 110, 120, 130, 140 I / O current detection load circuit 111, 112, 121, 122, 131, 132, 141, 142 Terminal 210, 220 Current sensor circuit 210P, 210N, 210PS, 210NS Current sensor circuit 230P, 230N, 250P, 250N Current sensor circuit 211, 212, 213, 214, 215, 216, 217, 218 Terminal 221, 222, 223, 224, 225, 226, 227, 228 Terminal 310, 320, 330 Information processing circuit 340 Temporary holding circuit 341, 342 Terminal 350 A / D conversion circuit 351, 352, 353, 354, 355, 356 Terminal 360 Memory circuit 361, 362, 363 Terminal 370 CPU circuit Terminals 371, 372, 373 Ratio circuits 410, 420 Ratio circuits 410P, 410N, 430P, 430N, 450P, 450N Ratio current acquisition load circuits 510, 510P, 510N, 510PS, 510NS Terminals 511, 512 Conversion circuits 610P, 610N Comparison circuit 700 Semiconductor device 1001 Current sensor circuits 1210, 1220 Characteristics A1, A2 GR ground terminal I / O currents IIO, IIOP, IION Output currents IOUT, IOUTP, IOUTN Wiring L11, L12 Wiring L21, L22 LGR ground wiring Potential supply wirings LSU, LSU2 Current mirrors MR1, MR2, MR3 N-type transistor NT Offset Reference value REF P-type transistor PT Resistors R, Rs, Ro Potential supply terminals SU, SU2, SU3 Terminals T11, T12, T21, T22, T31, T32, T33 Bias Vb Input voltages VIO, VIOP, VOIN Output voltages VOUT, VOUTP, VOUTP1, VOUTN, VOUTN1

Claims

1. A potential supply terminal to which a potential is supplied, an I / O terminal for communicating signals with the outside, an I / O current detection load circuit electrically connected to the potential supply terminal and the I / O terminal, a current sensor circuit for detecting an I / O current flowing through the I / O current detection load circuit, comprising: the current sensor circuit acquires a sensor current proportional to the I / O current and outputs the acquired sensor current as output information, the I / O current is an abnormal current flowing through the I / O terminal due to at least one of electrostatic discharge and electromagnetic susceptibility, and is a current larger than a predetermined current that causes an abnormal state, when the I / O current flows through the I / O current detection load circuit, the I / O current detection load circuit generates an input voltage between a terminal into which the I / O current flows and a terminal from which the I / O current flows out of the I / O current detection load circuit, the I / O current detection load circuit has a first coefficient that is a ratio of the I / O current to the input voltage, and the first coefficient is not constant with respect to the I / O current and the I / O current and the input voltage are not proportional, a semiconductor device.

2. the current sensor circuit has a proportional circuit and a proportional current acquisition load circuit electrically connected to the proportional circuit, the proportional circuit takes the input voltage as an input, outputs a voltage obtained by multiplying the input voltage by approximately 1 as an output voltage, inputs the output voltage to the proportional current acquisition load circuit, and causes the sensor current to flow through the proportional current acquisition load circuit, the proportional current acquisition load circuit has the output voltage input between a terminal into which the sensor current flows and a terminal from which the sensor current flows out, the proportional current acquisition load circuit has a second coefficient that is a ratio of the sensor current to the output voltage, and a ratio of the first coefficient to the second coefficient is approximately 1 and equivalent, the I / O current is a product of the first coefficient and the input voltage, the sensor current is a product of the second coefficient and the output voltage, the input voltage and the output voltage are equivalent because a ratio of the input voltage to the output voltage is approximately 1, and the first coefficient and the second coefficient are equivalent because a ratio of the first coefficient to the second coefficient is approximately 1, The I / O current can be replaced with the product of the second coefficient and the output voltage, the sensor current can be replaced with the product of the first coefficient and the input voltage, the ratio of the I / O current to the sensor current becomes approximately 1 times, and the I / O current and the sensor current are proportional. The semiconductor device according to claim 1.

3. The current sensor circuit includes a proportional circuit and a proportional current acquisition load circuit electrically connected to the proportional circuit. The proportional circuit takes the input voltage as an input, outputs a voltage obtained by multiplying the input voltage by approximately 1 as an output voltage, inputs the output voltage to the proportional current acquisition load circuit, and causes the sensor current to flow through the proportional current acquisition load circuit. The proportional current acquisition load circuit has the output voltage input between a terminal into which the sensor current flows and a terminal from which the sensor current flows out. The proportional current acquisition load circuit includes a second coefficient that is the ratio of the sensor current to the output voltage, and the ratio of the first coefficient to the second coefficient is approximately a constant multiple. The I / O current is the product of the first coefficient and the input voltage, the sensor current is the product of the second coefficient and the output voltage, and since the ratio of the input voltage to the output voltage is approximately 1, the input voltage and the output voltage are equivalent. Since the ratio of the first coefficient to the second coefficient is approximately a constant multiple, the first coefficient and the second coefficient are proportional. The I / O current is proportional to the product of the second coefficient and the output voltage, the sensor current is proportional to the product of the first coefficient and the input voltage, and the I / O current and the sensor current are proportional. The semiconductor device according to claim 1.

4. The I / O current detection load circuit and the proportional current acquisition load circuit are diodes, and the diodes have the same cross-sectional structure. The diode includes at least one of a PN junction diode and a parasitic diode generated between the drain and the back gate of a MOS transistor. The semiconductor device according to claim 2.

5. The I / O current detection load circuit and the proportional current acquisition load circuit are diodes, and the diodes have the same cross-sectional structure. The diode includes at least one of a PN junction diode and a parasitic diode generated between the drain and the back gate of a MOS transistor. The semiconductor device according to claim 3.

6. Further comprising an information processing circuit that is electrically connected to the current sensor circuit and processes the output information output from the current sensor circuit. The semiconductor device according to claim 1.

7. When the output information exceeds a predetermined threshold value, the information processing circuit outputs an abnormal signal indicating that the abnormal current has flowed through at least one of the potential supply terminal and the I / O terminal. The semiconductor device according to claim 6.

8. The potential is a power supply potential or a ground potential. The semiconductor device according to claim 1.

9. The proportional circuit includes a transistor and a resistor. The semiconductor device according to claim 2.

10. The proportional current acquisition load circuit has the same size as the I / O current detection load circuit or a size smaller than that of the I / O current detection load circuit. The semiconductor device according to claim 2.

11. The current sensor circuit further includes a conversion circuit that converts the sensor current into a sensor voltage. The conversion circuit outputs the converted sensor voltage as the output information. The semiconductor device according to claim 2.

12. The conversion circuit includes a current mirror and a resistor. The semiconductor device according to claim 11.

13. The proportional circuit includes a transistor, a resistor, and a bias. The semiconductor device according to claim 12.

14. The proportional circuit includes a transistor and a diode-connected multi-stage stack of transistors. The semiconductor device according to claim 12.

15. Further comprising a comparison circuit that compares the sensor current with a reference value. When the sensor current is greater than the reference value, the comparison circuit increases the malfunction tolerance of the information processing circuit. The semiconductor device according to claim 6.

16. Further comprising a comparison circuit that compares the sensor current with a reference value. When the sensor current is greater than the reference value, the comparison circuit invalidates the data handled by the information processing circuit. The semiconductor device according to claim 6.

17. The I / O current detection load circuit and the proportional current acquisition load circuit include at least one of a PN junction diode, a bipolar transistor, and a MOS transistor. The semiconductor device according to claim 2.

18. A first potential supply terminal to which a first potential is supplied, An I / O terminal for communicating signals with the outside, A first I / O current detection load circuit electrically connected to the first potential supply terminal and the I / O terminal, A first current sensor circuit that detects a first I / O current flowing through the first I / O current detection load circuit; A second potential supply terminal to which a second potential having a potential different from the first potential is supplied; A second I / O current detection load circuit electrically connected to the second potential supply terminal and the I / O terminal; A second current sensor circuit that detects a second I / O current flowing through the second I / O current detection load circuit; Comprising: The first current sensor circuit acquires a first sensor current proportional to the first I / O current, and outputs the acquired first sensor current as first output information; The second current sensor circuit acquires a second sensor current proportional to the second I / O current, and outputs the acquired second sensor current as second output information; At least one of the first I / O current and the second I / O current is an abnormal current flowing through the I / O terminal due to at least one of electrostatic discharge and electromagnetic susceptibility, and is a current larger than a predetermined current that causes an abnormal state. A semiconductor device.

19. The semiconductor device according to claim 18, further comprising an information processing circuit electrically connected to the first current sensor circuit and the second current sensor circuit, and processing at least one of the first output information and the second output information. The semiconductor device according to claim 18.

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