Asymmetrically Inclined Gate Structure and Method of Manufacturing the Same

Abstract

A high electron mobility transistor (HEMT) includes a substrate (104), a source (16) on the substrate, a drain (14) on the substrate spaced apart from the source, and a gate (102) between the source and drain, the gate having a stem in contact with the substrate, the stem having a source side surface and a drain side surface, a source side angle defined between the source side surface and a top planar surface of the substrate, and a drain side angle defined between the drain side surface and a top planar surface of the substrate, the source side angle and the drain side angle being different. A method of fabricating the HEMT is also disclosed.

Description

Technical Field

[0001] The present disclosure relates to high electron mobility transistors (HEMTs) and pseudomorphic high electron mobility transistors (pHEMTs), and methods of manufacturing the same.

Background Art

[0002] HEMTs, also known as heterostructure FETs (HFETs) or modulation-doped FETs (MODFETs), are field-effect transistors in which a junction between two materials with different bandgaps is incorporated. The generally used material combination is GaAs and AlGaAs, but various other materials may be used depending on the application of the device. HEMTs operate at high frequencies up to, for example, millimeter-wave frequencies and are used in high-frequency devices such as mobile phones, satellite TV receivers, voltage converters, and radar equipment, and are also applied in satellite receivers, low-power amplifiers, and the defense industry.

[0003] One aspect of the design of HEMTs and pHEMTs is the gate shape, and the gate is usually in the form of either a T-shaped structure or a V-shaped structure arranged between the source and the drain. Special attention is paid when defining the gate profile in order to optimize the capacitance and gate resistance based on a specific application. The capacitance can be minimized by making the contact of the gate with the semiconductor as small as possible and making the region of the sidewall of the gate stem adjacent to the semiconductor surface perpendicular.

[0004] The upper part of the gate has dimensions, width, and height that affect the resistance. However, in a completely vertical T-gate, a large spike may occur in the electric field at the gate edge, which may have a catastrophic effect on the device.

[0005] A conductive metal plate can be implemented on the stem, whereby the electric field can be smoothed at the expense of an increase in capacitance. These conductive metal plates are known as field plates and may be incorporated directly into the gate stem or as a completely separate layer.

[0006] Attempts have been made to incorporate an inclined field plate directly into the gate stem. However, due to the nature of known photoresist patterns, the inclinations on both sides are symmetric. This can undesirably increase the capacitance on the source side in order to achieve a field plate effect on the drain side.

[0007] The present disclosure addresses these concerns. SUMMARY OF THE INVENTION

[0008] A high electron mobility transistor (HEMT) is disclosed, the HEMT comprising a substrate, a source on the substrate, a drain on the substrate spaced apart from the source, and a gate between the source and the drain, the gate having a stem in contact with the substrate, the stem having a source-side surface and a drain-side surface, a source-side angle defined between the source-side surface and an upper plane of the substrate, a drain-side angle defined between the drain-side surface and the upper plane of the substrate, and the source-side angle and the drain-side angle being asymmetric.

[0009] In one non-limiting configuration, the source-side surface and the drain-side surface are non-linear surfaces.

[0010] In another non-limiting configuration, the non-linear surface is non-linear from a contact point with the upper plane of the substrate.

[0011] In yet another non-limiting configuration, the source-side surface and the drain-side surface are defined by a field plate.

[0012] In a further non-limiting configuration, the source-side angle is greater than the drain-side angle.

[0013] In yet a further non-limiting configuration, the source side angle is from 25° to 90°, and the drain side angle is less than the source side angle.

[0014] In another non-limiting configuration, the source side angle is from 45° to 90°.

[0015] In yet a further non-limiting configuration, the source side angle is from 70° to 90°.

[0016] In a further non-limiting configuration, the drain side angle is from 25° to 70°.

[0017] In yet a further non-limiting configuration, the drain side angle is from 25° to 50°.

[0018] In another non-limiting configuration, the gate is a metal structure formed of one or more metals selected from the group consisting of gold, platinum, nickel, and combinations and alloys thereof.

[0019] In another non-limiting configuration, a method of manufacturing a transistor is provided, the method including applying a photoresist layer to a substrate coated with an ohmic material defining a source and a drain, removing a portion of the photoresist to define a central space between a first photoresist strip and a second photoresist strip, the first strip and the second strip having different widths, reflowing the photoresist to form reflow angles on both sides of the central space, and applying a gate metal to the central space.

[0020] In a non-limiting configuration, the method further includes, after the reflow step, applying an additional photoresist layer over the photoresist layer; removing a portion of the additional layer to expose the central space; applying gate metal to the additional layer and the central space; and removing the photoresist layer and the additional photoresist layer to create a substrate having a source and a drain and a gate, the gate having a stem in contact with the substrate, a source-side field plate, and a drain-side field plate, wherein the source-side field plate and the drain-side field plate are defined by non-linear surfaces, a source-side angle is defined between the source-side field plate and an upper plane of the substrate, a drain-side angle is defined between the drain-side field plate and the upper plane of the substrate, and the source-side angle and the drain-side angle are asymmetric.

[0021] In another non-limiting configuration, the removing step includes removing a central portion of the photoresist layer to define a central space, removing a source-side portion of the photoresist layer to define a source-side photoresist strip having a first width, and removing a drain-side portion of the photoresist layer to define a drain-side photoresist strip having a second width.

[0022] In yet another non-limiting configuration, the photoresist is a material selected from the group consisting of polymethyl methacrylate (PMMA), phenolic formaldehyde resin, and combinations thereof.

[0023] In a further non-limiting configuration, the reflow step includes exposing the photoresist layer to a temperature of 100°C to 200°C for a period of 1 minute to 10 minutes, whereby the photoresist melts and flows to form a shape according to the surface tension of the photoresist.

[0024] In yet a further non-limiting configuration, a method of manufacturing a transistor is provided, the method comprising applying a photoresist layer to a substrate coated with an ohmic material defining a source and a drain and coated with a dielectric layer; removing a portion of the photoresist so as to define a central space between a first photoresist strip and a second photoresist strip, the first strip and the second strip having different widths; reflowing the photoresist so as to form reflow angles on both sides of the central space; etching the dielectric layer through the central space so as to define a dielectric central space having side surfaces forming an angle defined by the reflow angle; and applying a gate metal to the dielectric central space.

[0025] In another non-limiting configuration, the method further comprises, after the reflowing step, applying a further photoresist layer over the photoresist layer; and removing a portion of the further layer so as to expose the central space.

[0026] In yet another non-limiting configuration, the method further comprises, after the etching step, stripping a further photoresist layer and the photoresist layer from the dielectric layer; applying an additional photoresist layer over the dielectric layer and the dielectric central space; removing a portion of the additional photoresist layer so as to expose the dielectric central space; applying a gate metal to the additional layer and the dielectric central space; and removing an additional layer gate metal over the additional layer so as to create a substrate having a source and a drain and a gate, the gate having a stem in contact with the substrate, a source-side surface of the stem, and a drain-side surface of the stem, the source-side angle being defined between the source-side surface and an upper plane of the substrate, the drain-side angle being defined between the drain-side surface and the upper plane of the substrate, the source-side angle and the drain-side angle being asymmetric.

[0027] In a further non-limiting configuration, the removing step includes removing a central portion of the photoresist layer so as to define a central space, removing a source-side portion of the photoresist layer so as to define a source-side photoresist strip having a first width, and removing a drain-side portion of the photoresist layer so as to define a drain-side photoresist strip having a second width.

[0028] A detailed description of one or more embodiments of the present disclosure is set forth below with reference to the accompanying drawings.

Brief Description of the Drawings

[0029]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

Figure 15

Figure 16

Figure 17

Figure 18

Figure 19

Figure 20

Figure 21

Embodiments for Carrying Out the Invention

[0030] Like reference numerals and designations in the various drawings indicate like elements.

[0031] The present disclosure relates to high electron mobility transistors (HEMTs) and pseudomorphic high electron mobility transistors (pHEMTs), and methods for manufacturing them.

[0032] FIG. 1 schematically shows a PHEMT structure 10 including a substrate 12, a source 14, and a drain 16. As is well known and understood in the art, a gate 18 is disposed between the source 14 and the drain 16. The substrate 12 is typically a multilayer structure incorporating a junction between two materials having different bandgaps. A non-limiting example of a material suitable for the substrate 12 is gallium antimonide, i.e., a GaAs material. This material can be utilized in various forms, such as in combination with aluminum (AlGaAs) or in combination with indium (InGaAs), to produce desirable performance at the junction between materials. This structure is referred to as pseudomorphic lattice matched because the hetero material layers are so thin that they cannot maintain their own crystal lattice structure. Rather, these material layers assume the structure of the surrounding material. The disclosure described herein is applicable to both HEMT structures and PHEMT structures. Additionally, for a number of other related or additional reasons, a number of additional layers can be incorporated into the substrate 12, and all such multiple additional layer structures are considered to be included within the term "substrate" as used herein.

[0033] The source 14 is an ohmic metal layer. Non-limiting examples of suitable ohmic metals include gold, platinum, nickel, tantalum, tantalum nitride, tungsten, aluminum, and related alloys thereof.

[0034] The drain 16 is also an ohmic metal layer and can be, for example, the same type of metal as that suitable for the source. Thus, non-limiting examples of suitable ohmic metals include gold, platinum, nickel, tantalum, tantalum nitride, tungsten, aluminum, and related alloys thereof. The metal can be the same for both the source and the drain or different.

[0035] The conventional T-shaped gate 18 is shown in FIG. 1 and has a narrow stem 20 and a wide upper part 22. The stem 20 in FIG. 1 has straight side surfaces 24, 26 that are equally and oppositely inclined. The positions of the side surfaces 24, 26 with respect to the substrate surface, and the relative positions of the side surfaces 24, 26, also affect the possibility of large spikes in the electric field at the gate edge, as well as the capacitance across the gate.

[0036] As shown, the gate 18 has an upper part 22, and the lateral dimension or width of the upper part 22 is larger than the width of the stem, and the vertical dimension or height is smaller than the width. The width and height of the upper part 22 affect the resistance in the overall configuration.

[0037] The contact 28 between the bottom surface of the stem 20 and the upper surface of the substrate 12 is preferably as small as possible. Further, the side surfaces 24, 26 at the contact with the substrate 12 are usually kept as close to vertical as possible. However, as described above, in a completely vertical T-shaped gate, large spikes may occur in the electric field at the gate edge, and these large spikes can have a devastating effect on the device.

[0038] FIGS. 2 and 3 show some non-limiting configurations of the PHEMT 100 according to the present disclosure. A gate 102 is shown on a substrate 104 and has a source-facing side surface 106 and a drain-facing side surface 108. The side surfaces 106, 108 are non-linear. In the configurations shown in FIGS. 2 and 3, the side surfaces 106, 108 are curved along an arc.

[0039] The side surfaces 106, 108 are arranged asymmetrically with respect to the substrate 104. In this case, the source-facing side surface 106 has an angle closer to vertical than the drain-facing side surface 108. This enables the side surface 106 to have an angle closer to vertical on the source side, reducing the capacitance, and at the same time, since the side surface 108 has a shallower angle on the drain side, a smoothing field plate effect occurs as desired. Achieving this configuration using conventional manufacturing methods is difficult because, in the resist materials and photoresist materials used to define the gate space or gap, a contrasting inclination as shown in FIG. 1 occurs.

[0040] FIGS. 2 and 3 show a gate 102 having photoresist strips 110, 112, and it should be understood that the photoresist strips 110, 112 are used to form the gate 102 according to the method further described below. Additionally, it should be understood that the photoresists 110, 112 can be removed after the formation of the gate 102.

[0041] Figure 3 is an enlarged view of a part of Figure 2, and further shows the specific details of the configuration, shape, and angle of sides 106 and 108 in a configuration of a gate according to the present disclosure. Side 106 in this configuration is non-linear, specifically a concave curved surface that generally faces the source. The overall curved surface 106 forms an angle, i.e., is inclined, with respect to the substrate 104, specifically with respect to the upper plane 114 of the substrate 104. Since sides 106 and 108 in this embodiment are formed around the curved surface of an adjacent photoresist, it may be best to measure the contact angle of the photoresist that defines the shape of the sides to obtain the angles of sides 106 and 108. Thus, when side 106 is formed by deposition onto a photoresist having a contact angle of 80° with the surface 114, the angle A of side 106 with respect to the substrate 104 is considered to be 80°. Similarly, side 108 is non-linear and, in this configuration, is generally a concave curved surface that faces the drain. Side 108 is also formed by deposition onto a photoresist having a contact angle with the surface 114 of the substrate 104. Thus, the angle B of side 108 is considered to be the contact angle of the photoresist on which side 108 is deposited. For example, if this photoresist has / had a contact angle of 40°, the angle B of side 108 referred to in this specification is considered to be 40°. The contact angles A and B in the embodiment of Figure 3 are shown with respect to lines X, Y, and plane 114.

[0042] In a non-limiting configuration, the source-side angle A is greater than the drain-side angle B. The angle A can be from 25° to 90°. In a further non-limiting configuration, the angle A can be from 45° to 90°, and further can be from 70° to 90°. The angle B can also generally be from 25° to 90°, but in one configuration can be from 25° to 70°, and further can be from 25° to 50°. Within these ranges, still, the angle A is greater than the angle B. As described above, this helps to achieve the field plate effect on the drain side while still providing a desirable low capacitance.

[0043] The angles mentioned in this embodiment are contact angles. However, in other configurations, the side surfaces 106, 108 may be straight lines. In this case, it should be understood that the angle is simply the angle of the straight side surface with respect to the upper surface of the substrate. Such configurations will be discussed further below. In any of these configurations, it is advantageous for the drain side angle B to be less than 90°.

[0044] Figures 4 to 10 show a non-limiting example of a method capable of forming the gate structure shown in Figures 2 and 3. Figure 4 shows a substrate or wafer 104 pre-coated with an ohmic metal for forming what will become the source 14 and drain 16. According to known techniques, a layer 116 of resist or photoresist is applied or spin-coated onto the surface 114 of the substrate 104 and may also be applied onto the source 14 and drain 16.

[0045] Next, the layer 116 is exposed and patterned to create the stem channel 118, i.e., the central space, and at least two external channels 120, 122. This combination of channels creates photoresist strips 110, 112 having different widths. These strips are referred to as auxiliary shapes, and this configuration is shown in Figure 5. This step can be achieved using any known combination of resist materials or photoresist materials and methods for removing or etching them. For example, materials suitable for photoresist can be selected from the group consisting of polymethyl methacrylate (PMMA), phenolic formaldehyde resin, and combinations thereof.

[0046] Referring to FIG. 6, the structure of FIG. 5 can be exposed to heat, for example, in a photoresist baking step, causing the photoresist material to reflow, thereby generating the shapes of strips 110 and 112 between the channels as shown in FIG. 6. The shape obtained with the reflowed photoresist depends on the surface tension of the material and the starting width of the photoresist strip. For this reason, the outer channels 120 and 122 are formed as external auxiliary shapes that generate photoresist strips with different widths on one side of the stem channel 118 from the photoresist strip on the other side. When the width of the photoresist strip is narrower, the contact angle of the gate stem formed in the stem channel becomes steeper, and when the width of the photoresist strip is wider, the contact angle of the gate stem formed in this way becomes shallower. Therefore, it may be advantageous to configure the photoresist strip 112 on the drain side to be wider than the photoresist strip 110 on the source side.

[0047] Referring to FIG. 7, a second photoresist layer 124 can be applied or spin-coated over the top of the first layer 116 and within the channels 118, 120, and 122. The second layer 124 can be made from the same photoresist material, but it may be advantageous to make it from a photoresist that is more sensitive to the etching force than the first material. This enables the partial removal, i.e., etching removal, of the second layer 124, namely the channels, to a desirable extent without removing the underlying first photoresist layer 116. As shown in FIG. 8, a channel 126 is formed, i.e., etched, in the layer 124 at a position where the underlying stem channel 118 and the portion of the photoresist strip of the layer 116 that surrounds and defines the stem channel 118 are exposed.

[0048] Next, a gate metal layer 128 can be deposited over the entire structure including on the photoresist layer 124, within the stem channel 118, and on the surface of the photoresist layer 116 exposed within the channel 126. Alternatively, the gate metal can be deposited only at the location of the stem channel 118. This gate metal can be deposited, for example, using evaporation or sputtering, or other known techniques. Finally, as shown in FIG. 10, the excess metal and photoresist of layers 116 and 124 are removed, for example, by peeling from the wafer or substrate 104, leaving a gate 102 having asymmetrically sloped sides as shown. In the illustration of FIGS. 4 - 10, the steeper angle of the gate 102 is shown facing right, which is to be understood as being due to the use of a narrower photoresist strip as an auxiliary form on the right side. Thus, in this configuration, this structure has a source on the right side and a drain on the left side.

[0049] It should be understood that any combination of the source-side and drain-side angles of the stem can be created according to this method by selecting an appropriate combination of widths in the auxiliary strips on both sides of the stem channel.

[0050] FIGS. 11 - 21 show another manufacturing method for a gate for a HEMT having asymmetrically sloped sides.

[0051] Referring to FIG. 11, the substrate 104 can be provided with ohmic materials for the source 14 and drain 16 and then coated with a gate dielectric material layer 128, such as silicon carbide or a high-k material, for example. Next, a first photoresist layer 130 can be deposited over the dielectric layer 128.

[0052] FIG. 12 shows the structure after the photoresist layer 130 is exposed to form a stem channel 132 and two external channels 134, 136 spaced apart on both sides of the stem channel 132. Similar to the embodiments of FIGS. 4-10, two photoresist strips 138, 140 are disposed on both sides of the stem channel 132, and the channels 134, 136 are disposed at different intervals from the stem channel 132 such that the two strips 138, 140 have different widths.

[0053] FIG. 13 shows the structure after the photoresist is baked or reflowed such that the strips 138, 140 reach the glass transition temperature and reflow to take a round shape caused by the surface tension and other properties of the material. As shown, the wider strip produces a reflow shape with a smaller contact angle, i.e., a shallower contact angle, than the narrower strip.

[0054] FIG. 14 shows the structure after a second photoresist layer 142 is applied over the reflowed first layer 130. Next, this second layer 142 can be removed by exposure or etching to expose the stem channel 132 as shown in FIG. 15.

[0055] At this stage, the dielectric layer 128 can be etched through the stem channel 132 to form a central channel 144 within the dielectric layer 128. Since this etching is achieved through the space defined between the walls of different angles of the strips 138, 140, the central channel 144 has side surfaces 146, 148 at different angles with respect to the substrate 104. This is shown in FIG. 16.

[0056] FIG. 17 shows a structure in which a dielectric having a central channel 144 remains after the photoresist layers 116 and 124 are removed. Next, as shown in FIG. 18, a third photoresist layer 146 can be disposed or deposited over the dielectric layer 128 and the central channel 144, and then this third layer 146 can be etched or exposed so as to form an opening 148 over the central channel 144. This exposure or etching can be performed using a mask technique or any other technique, and an opening 148 wider than the central channel 144 is obtained. Further, the opening 148 can be defined by walls 150, 152 whose spacing widens as it approaches the dielectric layer 128 (see FIG. 19). Next, as shown in FIG. 20, a gate metal 150 can be deposited over the structure and within the opening 148 and the central channel 144. As a result, it is shown that a gate 152 having an expected shape is formed. Finally, as shown in FIG. 21, the third photoresist layer 146 and the excess gate metal 150 can be removed, leaving the HEMT structure 100. As can be seen from the figure, the gate 152 has a stem 154 and an upper portion 156 wider than the stem 154. Similar to the structures of FIGS. 2 and 3, the stem 154 is defined by side surfaces 158, 160 that make different angles with respect to the substrate 104. It may be advantageous for the different angles of these side surfaces to be within the ranges of the aforementioned angle A and angle B. However, in this configuration, the side surfaces 158, 160 are substantially linear. Further, in this case, the gate 152 is formed such that both sides of its stem contact the dielectric layer 128, rather than being defined within the substrate.

[0057] One or more embodiments of the present disclosure have been described. However, it will be understood that various changes may be made without departing from the spirit and scope of the invention. For example, different materials and configurations may be utilized, and transistor structures having different shapes or configurations may also benefit from the present disclosure. Accordingly, other embodiments are within the scope of the following claims.

Claims

1. A high electron mobility transistor, comprising: a substrate; a source on the substrate; a drain on the substrate spaced apart from the source; a gate between the source and the drain; wherein the gate has a stem in contact with the substrate, the stem having a source-side surface and a drain-side surface; a source-side angle is defined between the source-side surface and an upper plane of the substrate, and a drain-side angle is defined between the drain-side surface and the upper plane of the substrate; the source-side angle and the drain-side angle are asymmetric; the source-side surface extends from a contact point with the upper plane of the substrate so as to be completely concave toward the source, and the drain-side surface extends from a contact point with the upper plane of the substrate so as to be completely concave toward the drain; a transistor.

2. The transistor according to claim 1, wherein the source-side surface and the drain-side surface are defined by a field plate.

3. The transistor according to claim 1, wherein the source-side angle is larger than the drain-side angle.

4. The transistor according to claim 1, wherein the source-side angle is 25° to 90°, and the drain-side angle is smaller than the source-side angle.

5. The transistor according to claim 4, wherein the source-side angle is 45° to 90°.

6. The transistor according to claim 4, wherein the source-side angle is 70° to 90°.

7. The transistor according to claim 4, wherein the drain-side angle is 25° to 70°.

8. The transistor according to claim 4, wherein the drain-side angle is 25° to 50°.

9. The transistor according to claim 1, wherein the gate is a metal structure formed of one or more metals selected from the group consisting of gold, platinum, nickel, combinations thereof, and alloys thereof.

10. A method of manufacturing a transistor, comprising: applying a layer of photoresist to a substrate coated with an ohmic material defining a source and a drain; Removing a portion of the photoresist so as to define a central space between a first photoresist strip and a second photoresist strip, wherein the first photoresist strip and the second photoresist strip have different widths, the removing step; Reflowing the photoresist so as to form a reflow angle on both sides of the central space, wherein each of the reflowed first photoresist strip and the second photoresist strip extends in a curved shape in a direction away from the central space from an upper plane of the substrate, and the reflow angle is defined between the upper plane of the substrate and each curved surface of the first photoresist strip and the second photoresist strip, the reflowing step; Applying gate metal to the central space; A method comprising.

11. The method further comprises After the reflowing step, applying a further photoresist layer on the layer of the photoresist; Removing a part of the further photoresist layer so as to expose the central space; Applying gate metal to the further photoresist layer and the central space; Removing the layer of the photoresist and the further photoresist layer so as to create a substrate having the source and the drain and a gate, wherein the gate has a stem in contact with the substrate, a source-side field plate, and a drain-side field plate, the removing step; Including The source-side field plate and the drain-side field plate are defined by a non-linear surface, A source-side angle is defined between the source-side field plate and the upper plane of the substrate, and a drain-side angle is defined between the drain-side field plate and the upper plane of the substrate, The source-side angle and the drain-side angle are asymmetric, The method according to claim 10.

12. The removing step is Removing a central portion of the layer of the photoresist so as to define the central space; Removing a source-side portion of the layer of the photoresist so as to define a source-side photoresist strip having a first width; Removing a drain-side portion of the layer of photoresist so as to define a drain-side photoresist strip having a second width; The method according to claim 10, comprising:

13. The method according to claim 10, wherein the photoresist is a material selected from the group consisting of polymethyl methacrylate (PMMA), phenolic formaldehyde resin, and combinations thereof.

14. The step of reflowing includes exposing the layer of photoresist to a temperature of 100° C. to 200° C. for a period of 1 minute to 10 minutes, wherein the photoresist melts and flows to form a shape according to the surface tension of the photoresist. The method according to claim 10.

15. A method of manufacturing a transistor, comprising: Applying a layer of photoresist to a substrate coated with an ohmic material defining a source and a drain and coated with a dielectric layer; Removing a portion of the photoresist so as to define a central space between a first photoresist strip and a second photoresist strip, wherein the first photoresist strip and the second photoresist strip have different widths. The removing step; Reflowing the photoresist so as to form a reflow angle on both sides of the central space, wherein each of the reflowed first photoresist strip and the second photoresist strip extends in a curved shape from an upper plane of the dielectric layer in a direction away from the central space, and the reflow angle is defined between the upper plane of the dielectric layer and each curved surface of the first photoresist strip and the second photoresist strip. The reflowing step; Etching the dielectric layer through the central space so as to define a dielectric central space having a side surface forming an angle defined by the reflow angle; Applying a gate metal to the dielectric central space; A method comprising:

16. After the step of reflowing, applying an additional photoresist layer on the layer of photoresist; Removing a portion of the additional photoresist layer so as to expose the central space; The method according to claim 15, further comprising:

17. The method further comprises: After the step of etching, a step of peeling the additional photoresist layer and the layer of the photoresist from the dielectric layer; A step of applying an additional photoresist layer on the dielectric layer and the central space of the dielectric; A step of removing a part of the additional photoresist layer so as to expose the central space of the dielectric; A step of applying an additional layer gate metal to the additional photoresist layer and the central space of the dielectric; A step of removing the additional layer gate metal on the additional photoresist layer so as to create a substrate having the source and the drain and a gate, wherein the gate has a stem contacting the substrate, a source-side surface of the stem, and a drain-side surface of the stem; comprising; A source-side angle is defined between the source-side surface and an upper plane of the substrate, and a drain-side angle is defined between the drain-side surface and the upper plane of the substrate; The source-side angle and the drain-side angle are asymmetric; The method according to claim 16.

18. The step of removing comprises: Removing a central portion of the layer of the photoresist so as to define the central space; Removing a source-side portion of the layer of the photoresist so as to define a source-side photoresist strip having a first width; Removing a drain-side portion of the layer of the photoresist so as to define a drain-side photoresist strip having a second width; The method according to claim 15, comprising.

19. A method of manufacturing a transistor, comprising: A step of applying a layer of photoresist to a substrate coated with an ohmic material defining a source and a drain and coated with a dielectric layer; A step of removing a portion of the photoresist so as to define a central space between a first photoresist strip and a second photoresist strip, wherein the first photoresist strip and the second photoresist strip have different widths; A step of reflowing the photoresist so as to form a reflow angle on both sides of the central space; A step of etching the dielectric layer through the central space so as to define a dielectric central space having side surfaces forming an angle defined by the reflow angle; Applying a gate metal to the dielectric central space; including; the method further comprises; after the step of reflowing, applying an additional photoresist layer on the layer of the photoresist; removing a part of the additional photoresist layer so as to expose the central space; after the step of etching, stripping the additional photoresist layer and the layer of the photoresist from the dielectric layer; applying an additional photoresist layer on the dielectric layer and the dielectric central space; removing a part of the additional photoresist layer so as to expose the dielectric central space; applying an additional layer of gate metal to the additional photoresist layer and the dielectric central space; removing the additional layer of gate metal on the additional photoresist layer so as to create the substrate having the source and the drain and a gate, wherein the gate has a stem contacting the substrate, a source-side surface of the stem, and a drain-side surface of the stem, the removing step; including; a source-side angle is defined between the source-side surface and the upper plane of the substrate, and a drain-side angle is defined between the drain-side surface and the upper plane of the substrate; the source-side angle and the drain-side angle are asymmetric; method.

Images