Semiconductor device and method for manufacturing the same

Abstract

To improve the reliability of a semiconductor device.SOLUTION: A gate electrode GE1 is formed inside a trench via a gate insulating film GI. The gate insulating film GI formed over a semiconductor substrate is removed. An insulating film IF1 is formed over the semiconductor substrate. A p-type base region PB is formed in the semiconductor substrate. An n-type emitter region NE is formed in the base region PB. Hydrogen annealing is applied to the semiconductor substrate. A boundary 10 between the base region PB and the emitter region NE is positioned deeper than the insulating film IF1 formed between the side surface of the trench and the gate insulating film GI.SELECTED DRAWING: Figure 18

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device having a gate electrode inside a trench and a method for manufacturing the same.

Background Art

[0002] As an IGBT (Insulated Gate Bipolar Transistor) with low on-resistance, a trench gate type IGBT is widely used.

[0003] For example, Patent Document 1 discloses an IGBT having a GGEE structure. In such an IGBT, trenches are formed in an n-type semiconductor substrate, and a gate electrode is embedded inside the trenches via a gate insulating film. Further, a p-type base region is formed in the semiconductor substrate, and an n-type emitter region is formed on the upper part of the base region. The base region and the emitter region are formed by performing ion implantation in a state where an insulating film different from the gate insulating film is formed on the semiconductor substrate.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] Conventionally, a gate insulating film is formed inside the trench and on the semiconductor substrate, a polycrystalline silicon film is deposited on the gate insulating film, and a dry etching process is performed on the polycrystalline silicon film, so that the polycrystalline silicon film on the semiconductor substrate is removed and the polycrystalline silicon film is embedded inside the trench. When performing ion implantation on the semiconductor substrate, in order to reduce damage to the semiconductor substrate, the gate insulating film on the semiconductor substrate is used as a through film.

[0006] However, since the thickness of the gate insulating film is relatively thick, variations in the thickness of the gate insulating film are likely to occur during the formation of the gate insulating film and during the dry etching process of the polycrystalline silicon film. Therefore, the gate insulating film on the semiconductor substrate is removed and re-oxidation treatment is performed to newly form another silicon oxide film. By performing ion implantation using this silicon oxide film as a through film, the base region and the emitter region are formed. Note that the re-oxidation treatment is a thermal oxidation treatment using oxygen gas, which is a so-called dry oxidation treatment.

[0007] Here, as a result of investigations by the inventors of the present application, it has been found that when re-oxidation treatment is performed, interface states increase and hydrogen ions are formed in the gate insulating film, deteriorating PBTI (Positive Bias Temperature Instability). When PBTI deteriorates, a problem occurs in that the threshold voltage fluctuates over time. That is, the reliability of the semiconductor device decreases.

[0008] The main object of the present application is to improve the reliability of a semiconductor device by suppressing the deterioration of PBTI. Other problems and novel features will become apparent from the description of this specification and the accompanying drawings.

Means for Solving the Problems

[0009] Among the embodiments disclosed in the present application, the outline of a representative one will be briefly described as follows.

[0010] A method for manufacturing a semiconductor device according to an embodiment includes: (a) a step of preparing a semiconductor substrate of a first conductivity type; (b) a step of forming a trench in the semiconductor substrate after the step (a); (c) a step of forming a gate insulating film inside the trench and on the semiconductor substrate after the step (b); (d) a step of forming a first conductive film on the gate insulating film so as to fill the inside of the trench after the step (c); (e) a step of forming a gate electrode made of the first conductive film inside the trench by removing the first conductive film formed outside the trench after the step (d); (f) a step of removing the gate insulating film formed on the semiconductor substrate after the step (e); (g) a step of forming a first insulating film on the semiconductor substrate after the step (f); (h) a step of forming a first impurity region of a second conductivity type, which is opposite to the first conductivity type, in the semiconductor substrate so that the bottom thereof is shallower than the bottom of the trench after the step (g); (i) a step of forming a second impurity region of the first conductivity type in the first impurity region after the step (h); (j) a step of performing a hydrogen annealing process on the semiconductor substrate after the step (i). Here, in the step (g), the first insulating film is also formed between the side surface of the trench and the gate insulating film, and the boundary between the first impurity region and the second impurity region is located at a position deeper than the first insulating film formed between the side surface of the trench and the gate insulating film.

[0011] In one embodiment, a semiconductor device includes a semiconductor substrate of a first conductivity type, a trench formed in the semiconductor substrate, a gate insulating film formed inside the trench, a gate electrode formed on the gate insulating film so as to fill the inside of the trench, a first impurity region of a second conductivity type, which is formed in the semiconductor substrate and has a conductivity type opposite to the first conductivity type, such that the bottom thereof is shallower than the bottom of the trench, and a second impurity region of the first conductivity type, which is formed in the first impurity region. Here, a first distance between the gate electrode and the second impurity region above a boundary between the first impurity region and the second impurity region is wider than a second distance between the gate electrode and the first impurity region below the boundary, the first distance becomes wider as it approaches the upper surface of the gate electrode, and a difference between the first distance and the second distance at a position of the upper surface of the gate electrode is 30 nm or more and 100 nm or less.

Advantages of the Invention

[0012] According to one embodiment, the reliability of the semiconductor device can be improved.

Brief Description of the Drawings

[0013]

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Mode for Carrying Out the Invention

[0014] Hereinafter, embodiments will be described in detail with reference to the drawings. In all the drawings for explaining the embodiments, members having the same function are denoted by the same reference numerals, and repeated description thereof is omitted. Further, in the following embodiments, description of the same or similar parts is not repeated in principle unless particularly necessary.

[0015] Also, in the present application, when a numerical range such as "1 to 10 μm" is described, it means "1 μm or more and 10 μm or less". The same applies to other numerical values and other units.

[0016] (Embodiment 1) <Structure of Semiconductor Device> The structure of the semiconductor device 100 in Embodiment 1 will be described below with reference to FIGS. 1 and 2. The main features of Embodiment 1 are the structure near the upper part of the gate electrodes GE1 and GE2 embedded inside the trench TR and its manufacturing method. Such features will be described in detail later with reference to FIGS. 12 to 20. Before that, the overall structure and manufacturing method of the semiconductor device 100 will be described.

[0017] FIG. 1 is a plan view showing a semiconductor chip which is the semiconductor device 100. As shown in FIG. 1, most of the semiconductor device 100 is covered with the emitter electrode EE. A gate wiring GW is formed on the outer periphery of the emitter electrode EE. The region surrounded by the broken line in the emitter electrode EE is the emitter pad EP, and the region surrounded by the broken line in the gate wiring GW is the gate pad GP.

[0018] A part of each of the emitter electrode EE and the gate wiring GW is covered with a protective film (not shown). The regions exposed from this protective film are the emitter pad EP and the gate pad GP. External connection terminals such as wire bonding or clips (copper plates) are connected onto the emitter pad EP and the gate pad GP, whereby the semiconductor device 100 is electrically connected to other semiconductor chips or wiring boards.

[0019] FIG. 2 is a cross-sectional view corresponding to the cell region 1A shown in FIG. 1. A semiconductor element such as an IGBT is formed in the cell region 1A. The IGBT shown in FIG. 2 is an IGBT of the GGEE structure and is an IE-type IGBT capable of utilizing the IE (Injection Enhancement) effect.

[0020] The IE effect is a technology that increases the concentration of charges accumulated in the drift region NV by making it difficult for holes to be discharged from the emitter electrode EE side when the IGBT is in the on state. For this reason, the semiconductor device 100 has an active cell AC for performing the main operation of the IGBT and an inactive cell IAC other than the active cell AC. The gate electrode GE1 of the active cell AC is electrically connected to the gate wiring GW, and a gate potential is supplied during the operation of the IGBT. The gate electrode GE2 of the inactive cell IAC is electrically connected to the emitter electrode EE, and an emitter potential is supplied during the operation of the IGBT.

[0021] The semiconductor device 100 includes a semiconductor substrate SUB having a low-concentration n-type drift region NV. Here, the n-type semiconductor substrate SUB itself constitutes the drift region NV. Note that the drift region NV may be a laminate of an n-type silicon substrate and a semiconductor layer grown while introducing phosphorus (P) by an epitaxial growth method on the silicon substrate. In the present application, such a laminate will also be described as the semiconductor substrate SUB.

[0022] On the back side of the semiconductor substrate SUB, an n-type field stop region (impurity region) NS is formed in the semiconductor substrate SUB. The field stop region NS is provided to suppress the depletion layer extending from the pn junction on the surface TS side of the semiconductor substrate SUB from reaching the p-type collector region PC when the IGBT is turned off.

[0023] On the back side of the semiconductor substrate SUB, a p-type collector region (semiconductor region) PC is formed in the semiconductor substrate SUB. The collector region PC is located below the field stop region NS.

[0024] A collector electrode CE is formed on the back surface of the semiconductor substrate SUB. The collector electrode CE is electrically connected to the collector region PC and supplies a collector potential to these regions. The collector electrode CE is made of a metal film such as an AlSi film, a Ti film, a NiV film, and an Au film.

[0025] On the surface side of the semiconductor substrate SUB, a trench TR is formed in the semiconductor substrate SUB. The trench TR penetrates through an emitter region NE and a base region PB, which will be described later, and reaches the semiconductor substrate SUB. The depth of the trench TR is, for example, 2 to 3 μm.

[0026] A gate insulating film GI is formed inside the trench TR. Gate electrodes GE1 and GE2 are formed on the gate insulating film GI so as to fill the inside of the trench TR. The gate insulating film GI is, for example, a silicon oxide film, and the gate electrodes GE1 and GE2 are, for example, polycrystalline silicon films into which n-type impurities are introduced.

[0027] In the active cell AC, a hole barrier region (impurity region) NHB is formed in the semiconductor substrate SUB between a pair of gate electrodes GE1. A p-type base region (impurity region) PB is formed in the hole barrier region NHB. An n-type emitter region (impurity region) NE is formed in the p-type base region PB. The bottom of the base region PB is shallower than the bottom of the trench TR, and the bottom of the emitter region NE is shallower than the bottom of the base region PB.

[0028] In the inactive cell IAC, a hole barrier region NHB is formed in the semiconductor substrate SUB between a pair of gate electrodes GE2. Also, a p-type floating region (impurity region) PF is formed in the semiconductor substrate SUB between the gate electrode GE1 and the gate electrode GE2. A p-type base region PB is formed in the floating region PF. The floating region PF is preferably formed to a position deeper than the bottom of the trench TR in order to enhance the high breakdown voltage characteristics, and more preferably formed so as to cover the bottom of the trench TR.

[0029] An interlayer insulating film IL is formed on a semiconductor substrate SUB. The interlayer insulating film IL includes an insulating film IF1 formed on the semiconductor substrate SUB and an insulating film IF2 formed on the insulating film IF1. The insulating film IF1 is a silicon oxide film. The insulating film IF2 is a silicon oxide film containing boron and phosphorus, and is a BPSG (Boro Phospho Silicate Glass) film.

[0030] In an active cell AC, a contact hole CH penetrates through the interlayer insulating film IL and the emitter region NE and reaches the base region PB. The contact hole CH is formed so as to be in contact with the emitter region NE and the base region PB. A plug PG fills the inside of the contact hole CH and is electrically connected to the emitter region NE and the base region PB. The configuration of the contact hole CH and the plug PG in an inactive cell IAC is substantially the same as that of the active cell AC except that the emitter region NE is absent. Although not shown, the contact hole CH and the plug PG are also formed on a part of the gate electrodes GE1 and GE2.

[0031] The contact hole CH is composed of a first contact hole CH1 and a second contact hole CH2 communicating with the first contact hole CH1. The first contact hole CH1 is formed in the semiconductor substrate SUB, penetrates through the emitter region NE, and reaches the base region PB. The second contact hole CH2 is formed in the insulating film IF1 and the insulating film IF2.

[0032] The opening width of the second contact hole CH2 is larger than that of the first contact hole CH1. Therefore, when forming the plug PG, the aspect ratio is improved, making it easier to embed the plug PG well inside the contact hole CH. Also, since the opening width of the second contact hole CH2 is large, the upper surface of the emitter region NE is also exposed. Accordingly, the plug PG not only contacts the side surface of the emitter region NE but also contacts the upper surface of the emitter region NE inside the contact hole CH. Thereby, the contact resistance between the plug PG and the emitter region NE can be reduced.

[0033] The plug PG is composed of a laminated film of a barrier metal film and a conductive film. The barrier metal film is composed of, for example, a laminated film of a titanium film and a titanium nitride film formed on the titanium film. The conductive film is composed of, for example, a tungsten film.

[0034] A p-type high-concentration diffusion region (impurity region) PR is formed around the bottom of the first contact hole CH1. The high-concentration diffusion region PR is provided to lower the contact resistance with the plug PG and to prevent latch-up.

[0035] Note that the impurity concentration of the drift region NV is 1×10 13 ~2×10 14 cm -3 . The impurity concentration of the field stop region NS is higher than that of the drift region NV, and is 5×10 16 ~5×10 17 cm -3 . The impurity concentration of the hole barrier region NHB is higher than that of the drift region NV, and is 1×10 16 ~1×10 17 cm -3 . The impurity concentration of the emitter region NE is higher than that of the hole barrier region NHB, and is 1×10 18 ~1×10 21 cm -3 . The impurity concentration of the collector region PC is 1×10 17 ~1×10 21 cm-3 It is. The impurity concentration in the floating region PF is 1×10 15 ~1×10 16 cm -3 . The impurity concentration in the base region PB is higher than that in the floating region PF and is 1×10 16 ~1×10 18 cm -3 . The impurity concentration in the high-concentration diffusion region PR is higher than that in the base region PB and is 1×10 18 ~1×10 21 cm -3 .

[0036] An emitter electrode EE is formed on the interlayer insulating film IL. The emitter electrode EE is electrically connected to the emitter region NE, the base region PB, the high-concentration diffusion region PR, and the gate electrode GE2 via a plug PG, and supplies an emitter potential to these regions. Although not shown here, a gate wiring GW formed in the same process as the emitter electrode EE is also formed on the interlayer insulating film IL. The gate wiring GW is electrically connected to the gate electrode GE1 via a plug PG and supplies a gate potential to the gate electrode GE1. Such an emitter electrode EE and gate wiring GW are composed of, for example, a TiW film and an aluminum film formed on the TiW film. The aluminum film is the conductor film of the emitter electrode EE and the gate wiring and is sufficiently thicker than the TiW film.

[0037] <Method for manufacturing a semiconductor device> The manufacturing method of the semiconductor device 100 in Embodiment 1 will be described below with reference to FIGS. 3 to 11.

[0038] As shown in FIG. 3, first, a semiconductor substrate SUB having an n-type drift region NV is prepared. Next, an n-type hole barrier region NHB and a p-type floating region PF are formed in the semiconductor substrate SUB by photolithography and ion implantation.

[0039] As shown in FIG. 4, a trench TR is formed in the semiconductor substrate SUB. First, an insulating film made of, for example, a silicon oxide film is formed on the semiconductor substrate SUB, and a hard mask is formed by patterning the insulating film by photolithography and dry etching processes. Next, an anisotropic etching process is performed on the semiconductor substrate SUB using the hard mask as a mask to form a trench TR in the semiconductor substrate SUB. Thereafter, the hard mask is removed by a wet etching process or the like.

[0040] As shown in FIG. 5, first, the semiconductor substrate SUB is subjected to a heat treatment at, for example, 1000 to 1200 ° C. to diffuse the impurities contained in the hole barrier region NHB and the floating region PF. By this heat treatment, the hole barrier region NHB diffuses to near the bottom of the trench TR, and the floating region PF diffuses to a position deeper than the bottom of the trench TR so as to cover the bottom of the trench TR.

[0041] Next, a gate insulating film GI is formed inside the trench TR and on the semiconductor substrate SUB. The gate insulating film GI is formed by a thermal oxidation process (wet oxidation process) using water vapor in an atmosphere of 950 ° C. The thickness of the gate insulating film GI is, for example, 1000 Å. Next, a conductive film PL such as a polycrystalline silicon film into which an n-type impurity is introduced is formed on the gate insulating film GI by, for example, a CVD method so as to fill the inside of the trench TR.

[0042] As shown in FIG. 6, first, the conductive film PL formed outside the trench TR is removed by a dry etching process. The conductive film PL formed inside the trench TR remains as gate electrodes GE1 and GE2. Next, the gate insulating film GI formed outside the trench TR is removed by an anisotropic etching process and an isotropic etching process.

[0043] As shown in FIG. 7, an insulating film IF1 made of a silicon oxide film is formed on a semiconductor substrate SUB. The insulating film IF1 is formed by a thermal oxidation process (dry oxidation process) using oxygen gas in an atmosphere of 950°C. The thickness of the insulating film IF1 is, for example, 200 to 500 Å.

[0044] Next, using the insulating film IF1 as a through-film, a p-type base region PB is formed in the semiconductor substrate SUB (floating region PF and hole barrier region NHB) by photolithography and ion implantation. Next, an n-type emitter region NE is formed in the base region PB of the active cell AC by photolithography and ion implantation. Thereafter, for example, a heat treatment at 950°C for 30 seconds is performed to activate the impurities contained in each impurity region.

[0045] As shown in FIG. 8, an insulating film IF2 is formed on the insulating film IF1 by, for example, the CVD method. The insulating film IF2 is a silicon oxide film containing boron and phosphorus, and is a BPSG film. The insulating film IF1 and the insulating film IF2 each constitute a part of the interlayer insulating film IL. The thickness of the insulating film IF2 is thicker than the thickness of the insulating film IF1, and is, for example, 1000 nm. Next, a heat treatment (reflow treatment) at, for example, 950°C for 30 minutes is performed on the insulating film IF2. By this reflow treatment, the insulating film IF2 is softened and the upper surface of the insulating film IF2 is flattened.

[0046] As shown in FIG. 9, a first contact hole CH1 is formed in the insulating film IF2, the insulating film IF1, the emitter region NE, and the base region PB by photolithography and dry etching. The bottom of the first contact hole CH1 is located in the base region PB.

[0047] Next, by means of photolithography and ion implantation, a p-type high-concentration diffusion region PR is formed at the bottom of the first contact hole CH1. Then, a heat treatment is performed to activate each impurity region. The ion implantation for the high-concentration diffusion region PR is carried out in two steps. The first ion implantation is performed using boron, with an energy of 60 keV and a dose of 3×10 15 cm 2 . The second ion implantation is performed using boron difluoride, with an energy of 80 keV and a dose of 5×10 15 cm 2 . Then, a heat treatment is performed, for example, at 950°C for 30 seconds to activate the impurities contained in each impurity region.

[0048] As shown in FIG. 10, by performing an isotropic etching process on the insulating film IF2 and the insulating film IF1, the insulating film IF2 and the insulating film IF1 are recessed. For this isotropic etching process, an aqueous solution containing, for example, hydrofluoric acid is used. Thereby, a second contact hole CH2 is formed in the insulating film IF2 and the insulating film IF1. The opening width of the second contact hole CH2 is larger than the opening width of the first contact hole CH1. Note that the recession amount of the insulating film IF2 and the insulating film IF1 due to the isotropic etching process is about 130 nm.

[0049] As shown in FIG. 11, a plug PG is formed inside the contact hole CH. First, a titanium film is formed inside the contact hole CH and on the interlayer insulating film IL by, for example, sputtering, and a titanium nitride film is formed on the titanium film by, for example, sputtering to form a barrier metal film. Next, a tungsten film, for example, is formed on the barrier metal film by, for example, CVD so as to fill the inside of the contact hole CH. Next, the tungsten film and the barrier metal film formed outside the contact hole CH are removed by dry etching. Thereby, a plug PG that is embedded inside the contact hole CH and is electrically connected to the emitter region NE and the base region PB is formed.

[0050] Next, an emitter electrode EE is formed on the interlayer insulating film IL. First, for example, by a sputtering method, a TiW film is formed on the interlayer insulating film IL, and an aluminum film is formed on the TiW film by, for example, a sputtering method. Next, the emitter electrode EE is formed by patterning the TiW film and the aluminum film by a photolithography method and a dry etching process. Although not shown here, the gate wiring GW is also formed in the same process as the process of forming the emitter electrode EE.

[0051] After forming the metal film by the sputtering method, a hydrogen annealing process is performed to form a metal alloy. The hydrogen annealing process is performed, for example, in a hydrogen atmosphere at 400 to 600 °C for 30 minutes.

[0052] Thereafter, a field stop region NS, a collector region PC, and a collector electrode CE are formed on the back surface side of the semiconductor substrate SUB, whereby the structure of FIG. 2 is obtained.

[0053] First, an n-type field stop region NS and a p-type collector region PC are formed by performing ion implantation from the back surface side of the semiconductor substrate SUB. The ion implantation of the field stop region NS is performed using phosphorus, with an energy of 700 to 1600 keV and a dose of 2×10 12 cm 2 under the conditions. The ion implantation of the collector region PC is performed using boron, with an energy of 60 keV and a dose of 2×10 13 cm 2 under the conditions. Further, after these ion implantations, laser annealing is performed to activate the impurities contained in the field stop region NS and the collector region PC.

[0054] Next, a metal film such as an AlSi film, a Ti film, a NiV film, and an Au film is formed on the collector region PC exposed on the back surface side of the semiconductor substrate SUB by, for example, a sputtering method. This metal film becomes the collector electrode CE.

[0055] As described above, the semiconductor device 100 in the first embodiment is manufactured.

[0056] <Examination by the inventors of the present application> As described above, since the thickness of the gate insulating film GI is relatively thick, variations in the thickness of the gate insulating film GI are likely to occur during the formation of the gate insulating film GI and during the dry etching process of the conductive film PL. Therefore, the insulating film IF1 with a uniform and thin thickness is re-formed and applied as a through-film for ion implantation.

[0057] Also, a wet oxidation process is used for the formation of the gate insulating film GI, and a dry oxidation process is used for the formation of the insulating film IF1. In the wet oxidation process, the solubility of water vapor is high and the diffusion rate of H 2 O molecules is high, so the oxidation rate is faster than that of the dry oxidation process. Although the oxidation rate is slow in the dry oxidation process, in terms of forming a film with a uniform thickness, it is suitable to use the dry oxidation process for the formation of the insulating film IF1.

[0058] According to the examination by the inventors of the present application, it was found that when the dry oxidation process is performed, the interface states increase, hydrogen ions are formed, and PBTI deteriorates. Originally, the interface states are in a state where the SiH bonds at the interface are broken. Since the wet oxidation process is performed in an H 2 O atmosphere, the interface states are likely to recombine with the hydrogen in H 2 O, and the SiH bonds are likely to be regenerated. Therefore, it is presumed that the wet oxidation process is likely to reduce the interface states. On the other hand, since the dry oxidation process is performed in an oxygen gas atmosphere, it is difficult to regenerate the SiH bonds. Therefore, it is presumed that the dry oxidation process is difficult to reduce the interface states.

[0059] Also, the hydrogen annealing process is used to form a metal alloy, but it is presumed that hydrogen ions are formed by combining with the re-oxidation process (dry oxidation process).

[0060] FIG. 12 is a graph showing the results of analyzing PBTI degradation in the study example. FIG. 13 is a schematic diagram showing a model of PBTI degradation in the study example.

[0061] The prior art (〇) shown in FIG. 12 does not perform removal of the gate insulating film GI and dry oxidation treatment, and uses the gate insulating film GI as a through-film for ion implantation. Note that the emitter region NE in the study example is formed shallower than the emitter region NE in Embodiment 1. Ion implantation for forming the emitter region NE in the study example is performed using arsenic, with an energy of 100 keV and a dose of 1×10 15 ~5×10 15 cm 2 under the conditions described above.

[0062] As shown in FIG. 12, in the study example, due to PBTI degradation (●), the threshold voltage fluctuates over time. The inventors of the present application have clarified that PBTI degradation (●) includes an interface level component (▲) and a trap component (■) due to hydrogen ions in the gate insulating film, using the component separation method.

[0063] Hydrogen ions diffused by PBTI stress terminate the interface level, and the threshold voltage decreases. On the other hand, when hydrogen ions, which are positive charges, approach the interface between the gate insulating film GI and the base region PB, it is presumed that the hydrogen ions function as traps in the film and the threshold voltage decreases. That is, if the channel region is used at the location where the interface level exists and the location where hydrogen ions are distributed, fluctuations in the threshold voltage will occur.

[0064] <Main features of Embodiment 1> Hereinafter, the main features of Embodiment 1 will be described with reference to FIGS. 14 to 21. FIGS. 14 to 19 are enlarged cross-sectional views showing the details of the manufacturing process described in FIGS. 6 and 7.

[0065] FIG. 14 shows a state in which after forming the gate insulating film GI and the conductive film PL, the conductive film PL formed outside the trench TR is removed and the gate electrode GE1 is formed. Here, the periphery of the gate electrode GE1 will be described, but the same processes are performed around the gate electrode GE2 except for the formation of the emitter region NE.

[0066] As shown in FIG. 15, by performing anisotropic etching treatment, the thickness of the gate insulating film GI is made thinner. On the semiconductor substrate SUB, the etching progresses rapidly and the gate insulating film GI tends to become thinner, but the gate insulating film GI inside the trench TR is not etched much. Here, if all the gate insulating film GI on the semiconductor substrate SUB is to be removed by anisotropic etching treatment, etching damage will occur in the semiconductor substrate SUB during over-etching. Therefore, most of the gate insulating film GI is removed by anisotropic etching treatment, but the remaining gate insulating film GI is removed by isotropic etching treatment.

[0067] As shown in FIG. 16, by performing isotropic etching treatment, the gate insulating film GI formed outside the trench TR is removed. At this time, since etching also progresses from the upper surface side of the gate electrode GE1, a part of the gate insulating film GI in contact with the side surface of the gate electrode GE1 inside the trench TR is also removed. As a result, a part of the side surface of the gate electrode GE1 is exposed. That is, the upper part of the gate electrode GE1 is exposed.

[0068] As shown in FIG. 17, an insulating film IF1 made of a silicon oxide film is formed on the semiconductor substrate SUB. The formation of the insulating film IF1 is performed by thermal oxidation treatment (dry oxidation treatment) using oxygen gas in an atmosphere of 950°C. Also, the thickness of the insulating film IF1 formed on the semiconductor substrate SUB is thinner than the thickness of the gate insulating film GI formed on the semiconductor substrate SUB in FIG. 14 and is less than half of the thickness of the gate insulating film GI, for example, 200 to 500 Å.

[0069] By the above dry oxidation treatment, the insulating film IF1 is formed not only between the side surface of the trench TR and the gate insulating film GI like bird's beak but also on a part of the side surface of the exposed gate electrode GE1. That is, the upper part of the gate electrode GE1 is oxidized, and the corner part composed of the upper surface and the side surface of the gate electrode GE1 is oxidized. Although the gate insulating film GI and the insulating film IF1 are integrated, here they are separately illustrated for easy understanding.

[0070] Next, as shown in FIG. 18, a base region PB is formed in the semiconductor substrate SUB and an emitter region NE is formed in the base region PB by photolithography and ion implantation. These ion implantations are performed using the insulating film IF1 as a through-film. The ion implantation for the base region PB is performed using boron, with an energy of 110 keV and a dose of 1×10 13 ~2×10 13 cm 2 under the conditions. Then, for example, a heat treatment at 1000 °C for 100 to 200 minutes is performed to diffuse the impurities contained in the base region PB.

[0071] The ion implantation for the emitter region NE is performed in two steps. The first ion implantation is performed using arsenic, with an energy of 100 keV and a dose of 1×10 15 ~5×10 15 cm 2 under the conditions. The second ion implantation is performed using phosphorus, with an energy of 70 keV and a dose of 1×10 14 ~1×10 15 cm 2 under the conditions.

[0072] In the study example, the ion implantation of the emitter region NE was performed once and was carried out using arsenic. In Embodiment 1, the emitter region NE is formed by ion-implanting both arsenic and phosphorus. Therefore, the emitter region NE of Embodiment 1 is formed deeper than the emitter region NE of the study example. For example, the boundary 10 between the base region PB and the emitter region NE is located at a position of 300 nm or more and 500 nm or less from the upper surface of the semiconductor substrate SUB.

[0073] Reference sign D1 indicates the depth position of the insulating film IF1 formed between the side surface of the trench TR and the gate insulating film GI. Reference sign D2 indicates the depth position of the insulating film IF1 formed on a part of the side surface of the gate electrode GE1. The boundary 10 is located at a position deeper than the depths D1 and D2 of these insulating films IF1. Also, as shown in FIG. 19, the boundary 10 is located at a position deeper than a part (depth D3) of the side surface of the gate electrode GE1 exposed in FIG. 16. Note that the depth D3 is substantially the same as the depth D2.

[0074] The fact that the boundary 10 is located at a position deeper than the insulating film IF1 can also be rephrased as follows, for example. As shown in FIGS. 18 and 19, by dry oxidation treatment, the distance L1 between the gate electrode GE1 and the emitter region NE above the boundary 10 is wider than the distance L2 between the gate electrode GE1 and the base region PB below the boundary 10. Also, the distance L1 becomes wider as it approaches the upper surface of the gate electrode GE1. In other words, above the boundary 10, the width of the gate electrode GE1 becomes narrower as it approaches the upper surface of the gate electrode GE1. The difference between the distance L1 at the position of the upper surface of the gate electrode GE1 and the distance L2 is 30 nm or more and 100 nm or less.

[0075] By thus making the position of the boundary 10 deeper, as shown in FIG. 20, it is possible to use, for the channel region, a portion where the variation in the threshold voltage is less likely to occur due to PBTI degradation, rather than a portion where PBTI degradation is likely to occur. Therefore, the reliability of the semiconductor device 100 can be improved.

[0076] FIG. 21 is a graph showing the variation of the threshold voltage in the study example and Embodiment 1. In the study example (〇), the threshold voltage varied with the passage of time, but it can be seen that in Embodiment 1 (●), such variation was suppressed. The variation of the threshold voltage shown in FIG. 21 includes the interface level component and the trap component due to hydrogen ions in the gate insulating film as described in FIG. 12.

[0077] As described above, the present invention has been specifically described based on the embodiments. However, the present invention is not limited to these embodiments, and various modifications can be made without departing from the gist thereof.

[0078] For example, in the above embodiment, an IGBT was exemplified as the device formed in the cell region 1A. However, the technology disclosed in the above embodiment is not limited to the IGBT, and can also be applied to a power MOSFET having a vertical trench gate.

Description of Reference Numerals

[0079] 10 boundary 100 semiconductor device 1A cell region AC active cell CE collector electrode CH contact hole CH1 first contact hole CH2 second contact hole EE emitter electrode EP emitter pad GE1, GE2 gate electrode GI gate insulating film GP gate pad GW gate wiring IAC inactive cell IF1, IF2 insulating film IL interlayer insulating film NE emitter region NHB hole barrier region NS field stop region NV drift region PB base region PC collector region PF floating region PG plug PL conductive film PR high-concentration diffusion region SUB semiconductor substrate TR trench

Claims

1. (a) A step of preparing a semiconductor substrate of a first conductivity type; (b) After the step (a), a step of forming a trench in the semiconductor substrate; (c) After the step (b), a step of forming a gate insulating film inside the trench and on the semiconductor substrate; (d) After the step (c), a step of forming a first conductive film on the gate insulating film so as to fill the inside of the trench; (e) After the step (d), a step of forming a gate electrode made of the first conductive film inside the trench by removing the first conductive film formed outside the trench; (f) After the step (e), a step of removing the gate insulating film formed on the semiconductor substrate; (g) After the step (f), a step of forming a first insulating film on the semiconductor substrate; (h) After the step (g), a step of forming a first impurity region of a second conductivity type, which is of a conductivity type opposite to the first conductivity type, in the semiconductor substrate such that the bottom thereof is shallower than the bottom of the trench; (i) After the step (h), a step of forming a second impurity region of the first conductivity type in the first impurity region; (j) After the step (i), a step of performing a hydrogen annealing treatment on the semiconductor substrate; comprising: In the step (g), the first insulating film is also formed between the side surface of the trench and the gate insulating film; The boundary between the first impurity region and the second impurity region is located at a position deeper than the first insulating film formed between the side surface of the trench and the gate insulating film; In the step (f), a part of the gate insulating film in contact with the side surface of the gate electrode inside the trench is also removed, so that a part of the side surface of the gate electrode is exposed; In the step (g), a second insulating film is formed on a part of the exposed side surface of the gate electrode; The boundary is located at a position deeper than a part of the side surface of the gate electrode exposed in the step (f); In the step (f), an anisotropic etching treatment is performed on the gate insulating film, and then an isotropic etching treatment is performed on the gate insulating film. A method for manufacturing a semiconductor device.

2. (a) A step of preparing a semiconductor substrate of a first conductivity type; (b) After the step (a), a step of forming a trench in the semiconductor substrate; (c) After the step (b), a step of forming a gate insulating film inside the trench and on the semiconductor substrate; (d) After the step (c), a step of forming a first conductive film on the gate insulating film so as to fill the inside of the trench; (e) After the step (d), a step of forming a gate electrode made of the first conductive film inside the trench by removing the first conductive film formed outside the trench; (f) After the step (e), a step of removing the gate insulating film formed on the semiconductor substrate; (g) After the step (f), a step of forming a first insulating film on the semiconductor substrate; (h) After the step (g), a step of forming a first impurity region of a second conductivity type, which is opposite to the first conductivity type, in the semiconductor substrate such that the bottom thereof is shallower than the bottom of the trench; (i) After the step (h), a step of forming a second impurity region of the first conductivity type in the first impurity region; (j) After the step (i), a step of performing a hydrogen annealing process on the semiconductor substrate; comprising; In the step (g), the first insulating film is also formed between the side surface of the trench and the gate insulating film; The boundary between the first impurity region and the second impurity region is located at a position deeper than the first insulating film formed between the side surface of the trench and the gate insulating film; In the step (f), a part of the gate insulating film in contact with the side surface of the gate electrode inside the trench is also removed, so that a part of the side surface of the gate electrode is exposed; In the step (g), a second insulating film is formed on a part of the exposed side surface of the gate electrode; The boundary is located at a position deeper than a part of the side surface of the gate electrode exposed in the step (f); In the step (c), the gate insulating film is formed by a thermal oxidation process using water vapor; In the step (g), the first insulating film and the second insulating film are formed by a thermal oxidation process using oxygen gas, a method for manufacturing a semiconductor device.

3. In the method for manufacturing a semiconductor device according to any one of Claims 1 or 2, The thickness of the first insulating film formed on the semiconductor substrate is thinner than the thickness of the gate insulating film formed on the semiconductor substrate, a method for manufacturing a semiconductor device.

4. In the method for manufacturing a semiconductor device according to Claim 2, In the step (f), after an anisotropic etching process is performed on the gate insulating film, an isotropic etching process is performed on the gate insulating film, a method for manufacturing a semiconductor device.

5. In the method for manufacturing a semiconductor device according to any one of claims 1 or 2, In the step (i), a method for manufacturing a semiconductor device, in which both arsenic and phosphorus are ion-implanted to form the second impurity region.

6. In the method for manufacturing a semiconductor device according to claim 5, The method for manufacturing a semiconductor device, wherein the boundary is located at a position of 300 nm or more and 500 nm or less from the upper surface of the semiconductor substrate.

7. A semiconductor substrate of a first conductivity type, A trench formed in the semiconductor substrate, A gate insulating film formed inside the trench, A gate electrode formed on the gate insulating film so as to fill the inside of the trench, A first impurity region of a second conductivity type, which is formed in the semiconductor substrate such that the bottom thereof is shallower than the bottom of the trench and has a conductivity type opposite to that of the first conductivity type, A second impurity region of the first conductivity type formed in the first impurity region, A first insulating film formed on the semiconductor substrate and formed between the side surface of the trench and the gate insulating film, A second insulating film formed between the gate electrode and the gate insulating film, Comprising: The boundary between the first impurity region and the second impurity region is located at a position deeper than the first insulating film and the second insulating film, The interface level of the first insulating film and the second impurity region is larger than the interface level of the gate insulating film and the first impurity region, or the amount of hydrogen ions distributed at a position between the gate electrode and the second impurity region among the first insulating film, the second insulating film, and the gate insulating film is larger than the amount of hydrogen ions distributed at a position between the gate electrode and the first impurity region in the gate insulating film. A semiconductor device.

8. In the semiconductor device according to claim 7, The semiconductor device, wherein the second impurity region is configured to contain both arsenic and phosphorus.

9. In the semiconductor device according to claim 8, The semiconductor device, wherein the boundary is located at a position of 300 nm or more and 500 nm or less from the upper surface of the semiconductor substrate.

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