Doping technology

Abstract

Methods for selectively and conformally doping semiconductor materials are disclosed. Some embodiments utilize conformal dopant films selectively deposited on the semiconductor material by pyrolysis. Some embodiments relate to doping non-line-of-sight surfaces. Some implementations relate to methods for forming highly doped crystalline semiconductor layers. [Selected Figure] Figure 2

Description

Technical Field

[0001]

[0001] Embodiments of the present disclosure generally relate to methods of doping semiconductor materials. Some embodiments of the present disclosure relate to methods of selectively doping semiconductor materials with respect to oxide materials. Some embodiments of the present disclosure relate to methods for conformally doping semiconductor materials.

Background Art

[0002]

[0002] Controlling boron doping is important for p-type contact applications. Process control requires management of layer thickness, surface properties, heat balance, and etching selectivity.

[0003]

[0003] In addition, existing methods of boron doping do not provide a way to conformally dope three-dimensional structures (e.g., FINFETs). These methods (e.g., implantation) are often limited to line of sight or do not show sufficient conformality.

[0004]

[0004] Furthermore, existing methods of boron doping do not provide a way to dope only semiconductor materials. Current technologies often dope both semiconductor materials and adjacent oxide materials.

[0005]

[0005] Therefore, there is a need for a method of conformally doping semiconductor materials, particularly a method selective to the surface of the semiconductor material.

Summary of the Invention

[0006] [

[0006] ]One or more embodiments of the present disclosure are directed to a method of forming an electronic device. The method includes selectively depositing a substantially conformal dopant film onto a first surface including a semiconductor material relative to a second surface including an oxide material. The electronic device is annealed to drive dopant atoms from the dopant film into the semiconductor material such that substantially no dopant atoms are driven into the oxide material and are conformally doped into the semiconductor material.

[0007] [

[0007] ]A further embodiment of the present disclosure is directed to a method of forming an electronic device. The method includes providing a substrate having a first surface including a semiconductor material and a second surface including an oxide material. The first surface and the second surface are exposed to a boron precursor at a temperature in the range of about 700° C. to about 800° C. to selectively deposit a conformal dopant film by a non-line-of-sight pyrolysis process. The dopant film is deposited over the first surface and over the second surface. The dopant film includes boron. The electronic device is annealed at a temperature in the range of about 1150° C. to about 1200° C. by a millisecond anneal to drive boron atoms from the dopant film into the semiconductor material such that substantially no dopant atoms are driven into the oxide material and are conformally doped into the semiconductor material.

[0008] [

[0008] ]A further embodiment of the present disclosure is directed to a method of forming an electronic device. The method includes forming an amorphous boron layer over a crystalline semiconductor material. A further semiconductor material is deposited over the amorphous boron layer. The additional semiconductor material is substantially amorphous. The electronic device is annealed to crystallize the additional semiconductor material and form a boron-doped crystalline semiconductor material.

[0009]

[0009] To enable a more detailed understanding of the above features of the present disclosure, a more specific description of the present disclosure, briefly summarized above, can be provided by referring to embodiments, some of which are shown in the accompanying drawings. However, since the present disclosure may admit other equally effective embodiments, it should be noted that the accompanying drawings merely illustrate typical embodiments of the present disclosure and should not be regarded as limiting the scope of the present disclosure.

Brief Description of the Drawings

[0010]

Figure 1

[0010] Illustrates an exemplary substrate being processed according to one or more embodiments of the present disclosure.

Figure 2

[0011] Illustrates an exemplary substrate being processed according to one or more embodiments of the present disclosure.

Figure 3

[0012] Illustrates a system that can be used to process a substrate according to one or more embodiments of the present disclosure.

Modes for Carrying Out the Invention

[0011]

[0013] Before describing some exemplary embodiments of the present disclosure, it should be understood that the present disclosure is not limited to the details of the configurations or process steps described in the following description. The present disclosure is capable of other embodiments and can be implemented or executed in various ways.

[0012]

[0014] As used herein and in the appended claims, the term "substrate" refers to the surface or a portion of the surface on which the process acts. Also, it will be understood by those skilled in the art that a reference to a substrate may, in some cases, refer only to a portion of the substrate, unless the context clearly indicates otherwise. Additionally, a reference to depositing on a substrate may mean both the exposed substrate and the substrate having one or more films or features deposited or formed thereon.

[0013]

[0015] As used herein, "substrate surface" refers to any substrate or material surface formed on a substrate on which film processing is performed during the manufacturing process. For example, substrate surfaces on which processing can be performed include materials such as silicon, silicon oxide, strained silicon, silicon-on-insulator (SOI), carbon-doped silicon oxide, amorphous silicon, doped silicon, germanium, gallium arsenide, glass, sapphire, etc., and any other materials such as metals, metal nitrides, metal alloys, and other conductive materials. The substrate includes, but is not limited to, semiconductor wafers. The substrate can be exposed to a pretreatment process to polish, etch, reduce, oxidize, hydroxylate, anneal, UV-cure, electron-beam-cure, and / or bake the substrate surface. In addition to directly performing film processing on the surface of the substrate itself, in the present disclosure, any of the disclosed film processing steps may be performed on a lower layer formed on the substrate, as will be disclosed in more detail below, and the term "substrate surface" is intended to include such a lower layer as the context indicates. Thus, for example, when a film / layer or a partial film / layer is deposited on the substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface.

[0014]

[0016] Embodiments of the present disclosure relate to a method of forming an electronic device using a method including conformal and selective doping processes. Some embodiments of the present disclosure advantageously provide a method of conformally doping a semiconductor material. Some embodiments of the present disclosure advantageously provide a method for preferentially doping a semiconductor material over an oxide material. Some embodiments of the present disclosure advantageously provide a method of doping non-line-of-sight surfaces.

[0015]

[0017] As used in this specification and the appended claims, expressions such as "selectively depositing a film on one surface over another surface" mean that a first amount of the film is deposited on the first surface and a second amount of the film is deposited on the second surface, where the second amount of the film is less than the first amount of the film or no film is deposited on the second surface. The term "over" as used in this context does not mean the physical orientation of one surface over the top surface of another surface, but rather the relationship of the thermodynamic or kinetic characteristics of the chemical reaction of one surface with another surface. For example, selectively depositing a cobalt film on a copper surface over a dielectric surface means that the cobalt film is deposited on the copper surface and the cobalt film is deposited on the dielectric surface less than or not at all below it, or that the formation of the cobalt film on the copper surface is thermodynamically or kinetically more favorable than the formation of the cobalt film on the dielectric surface.

[0016]

[0018] Referring to FIG. 1, some embodiments relate to a method 100 of forming an electronic device. FIG. 1 shows a cross-sectional view of an exemplary substrate for processing by method 100. Substrate 10 includes a first surface 20 including semiconductor material 25 and a second surface 30 including oxide material 35. In some embodiments, semiconductor material 25 includes silicon or consists essentially of silicon.

[0017]

[0019] In some embodiments, semiconductor material 25 is a source / drain extension region of a transistor. In some embodiments, the electronic device includes a 3D NAND device having a plurality of alternating first surfaces 10 and second surfaces 20.

[0018]

[0020] As used in this specification and the appended claims, expressions such as "consisting essentially of" mean that the membrane or composition in question is about 95%, 98%, 99% or 99.5% or more of the stated active material. For a gas composition (e.g., a reactive gas), the expression "consisting essentially of" refers to the active component of a composition that does not contain a diluent, carrier or inert gas.

[0019]

[0021] In some embodiments, method 100 begins by selectively depositing a substantially conformal dopant film 40 over a first surface 20 and over a second surface 30. As used herein, a "substantially conformal" film refers to a film that is substantially the same in thickness throughout (e.g., over the top, center, and bottom of the sidewalls, and over the bottom of the gap). A substantially conformal film varies in thickness by about 10%, 5%, 2%, 1% or 0.5% or less.

[0020]

[0022] In some embodiments, dopant film 40 has a thickness in the range of about 2 to about 10 individual in the range of a single layer.

[0021]

[0023] In some embodiments, selectively depositing conformal film 40 is performed using a non-line-of-sight deposition process. Thus, in some embodiments, dopant film 40 conformally deposits on all exposed first surfaces regardless of their "visibility". As shown in FIG. 1, the underside of the diamond fin would typically be difficult to dope because these surfaces are not "visible" to a line-of-sight process.

[0022]

[0024] In some embodiments, selectively depositing dopant film 40 includes a pyrolysis process. In some embodiments, the pyrolysis process includes exposing the first and second surfaces to a dopant precursor at a temperature in the range of about 600°C to about 900°C or in the range of about 700°C to about 800°C.

[0023]

[0025] In some embodiments, the dopant precursor is a boron precursor and the dopant film contains boron. In some embodiments, the boron precursor is borane (BH 3 ), diborane (B 2 H 6 ), triborane (B 3 H 5 , B 3 H 7 ), tetraborane (B 4 H 6 , B 4 H 10 ), pentaborane (B 5 H 9 , B 5 H 11 ) or cyclic triborane (B 3 H 6 ) or cyclic tetraborane (B 4 H 8 ), or one or more of them, or consists essentially of them. Further examples of suitable boron precursors include boron halides such as BCl 3 , or alkyl-substituted boron compounds having the formula BHxR3-x, where each R is an independently selected C1 to C6 alkyl group and x is 0, 1 or 2. Specific examples of alkyl-substituted boron compounds include trimethylboron and triethylboron.

[0024]

[0026] In some embodiments, the dopant precursor is a phosphorus precursor and the dopant film contains phosphorus. In some embodiments, the phosphorus precursor contains phosphine (PH 3 ), or consists essentially of PH 3 . In some embodiments, the dopant precursor is an arsenic precursor and the dopant film contains arsenic. In some embodiments, the arsenic precursor contains arsine (AsH 3 ), or consists essentially of AsH 3 .

[0025]

[0027] In some embodiments, method 100 continues by annealing the electronic device to drive dopant atoms from dopant film 40 into semiconductor material 25, such that semiconductor material 25 is conformally doped and there are substantially no dopant atoms driven into oxide material 35. As shown in FIG. 1, the conformal doping of semiconductor material 25 is indicated by the thick line on the doped surface. As used herein, "substantially no dopant atoms" means that the surface of the material of interest contains less than 5%, 2%, 1%, or 0.5% dopant atoms.

[0026]

[0028] In some embodiments, annealing the electronic device includes one or more of spike annealing, laser annealing, rapid thermal annealing, millisecond annealing, or combinations thereof. In some embodiments, the annealing is performed at a temperature in the range of about 1000 °C to about 1300 °C, or in the range of about 1150 °C to about 1200 °C.

[0027]

[0029] In some embodiments, dopant atoms are driven into semiconductor material 25 to a depth of about 1 nm or more, about 2 nm or more, or about 5 nm or more. In some embodiments, the conformally doped semiconductor material has, at the surface of the semiconductor material, boron atom about 1 20 piece / cm 3 or more, boron atom about 2 20 piece / cm 3 or more, or boron atom about 5 20 piece / cm 3 or more dopant concentration.

[0028]

[0030] Referring to FIG. 2, some embodiments relate to a method 200 of forming an electronic device. FIG. 2 shows a cross-sectional view of an exemplary substrate for processing by method 200. Substrate 210 includes a crystalline semiconductor material 220.

[0029]

[0031] In some embodiments, method 200 begins by forming an amorphous boron layer 230 on a crystalline semiconductor material 220. The formation of the amorphous boron layer can be performed by any suitable process, including but not limited to the processes outlined above for depositing the dopant film 40.

[0030]

[0032] In some embodiments, method 200 continues by depositing an additional semiconductor material 240 on the amorphous boron layer 230. In some embodiments, the additional semiconductor material 240 is substantially amorphous.

[0031]

[0033] In some embodiments, method 200 continues by annealing the substrate 210 to crystallize the additional semiconductor material 240, melt the amorphous boron layer 230, and form a boron-doped crystalline semiconductor material 250. In some embodiments, the annealing process includes laser annealing. In some embodiments, the boron-doped crystalline semiconductor material 250 has the same stoichiometry as the crystalline semiconductor material 220. In some embodiments not shown, the method continues by forming a silicon compound from the boron-doped crystalline semiconductor material 250.

[0032]

[0034] In some embodiments, the crystalline semiconductor material 220 and the additional semiconductor material are composed of the same material. In some embodiments, the semiconductor material includes silicon. In some embodiments, the semiconductor material includes silicon and germanium.

[0033]

[0035] Referring to FIG. 3, a further embodiment of the present disclosure is directed to a processing tool 900 for performing the methods described herein. FIG. 3 shows a system 900 that can be used to process substrates according to one or more embodiments of the present disclosure. System 900 may be referred to as a cluster tool. System 900 includes a central transfer station 910 having a robot 912 therein. Although robot 912 is illustrated as a single blade robot, those skilled in the art will recognize that other configurations of robot 912 are within the scope of the disclosure. Robot 912 is configured to move one or more substrates between chambers coupled to central transfer station 910.

[0034]

[0036] At least one pre-cleaning / buffer chamber 920 is coupled to central transfer station 910. Pre-cleaning / buffer chamber 920 may include one or more of a heater, a radical source, or a plasma source. Pre-cleaning / buffer chamber 920 may be used as a holding area for individual semiconductor substrates or as a cassette for wafers for processing. Pre-cleaning / buffer chamber 920 can perform a pre-cleaning process, or pre-heat the substrate for processing, or simply serve as a staging area for the process sequence. In some embodiments, there are two pre-cleaning / buffer chambers 920 coupled to central transfer station 910.

[0035]

[0037] In the embodiment shown in FIG. 9, pre-cleaning chamber 920 can function as a pass-through chamber between factory interface 905 and central transfer station 910. Factory interface 905 may include one or more robots 906 for moving substrates from a cassette to pre-cleaning / buffer chamber 920. Robot 912 can then move the substrate from pre-cleaning / buffer chamber 920 to other chambers within system 900.

[0036]

[0038] The first processing chamber 930 can be connected to the central transfer station 910. The first processing chamber 930 can be configured as an anisotropic etching chamber and can be fluidly connected to one or more reactive gas sources to supply one or more flows of reactive gas to the first processing chamber 930. Substrates can be moved into and out of the deposition chamber 930 by a robot 912 passing through the isolation valve 914.

[0037]

[0039] The processing chamber 940 can also be connected to the central transfer station 910. In some embodiments, the processing chamber 940 includes an isotropic etching chamber and is fluidly connected to one or more reactive gas sources to supply a flow of reactive gas to the processing chamber 940 and perform an isotropic etching process. Substrates can be moved into and out of the deposition chamber 940 by a robot 912 passing through the isolation valve 914.

[0038]

[0040] The processing chamber 945 can also be connected to the central transfer station 910. In some embodiments, the processing chamber 945 is the same type of processing chamber 940 configured to perform the same process as the processing chamber 940. This configuration can be useful when the process performed in the processing chamber 940 takes a much longer time than the process in the processing chamber 930.

[0039]

[0041] In some embodiments, the processing chamber 960 is connected to the central transfer station 910 and is configured to function as a selective epitaxial growth chamber. The processing chamber 960 can be configured to perform one or more different epitaxial growth processes.

[0040]

[0042] In some embodiments, the anisotropic etching process is performed in the same processing chamber as the isotropic etching process. In this type of embodiment, processing chambers 930 and 960 are configured to perform etching processes simultaneously on two substrates, and processing chambers 940 and 945 may be configured to perform a selective epitaxial growth process.

[0041]

[0043] In some embodiments, each of processing chambers 930, 940, 945, and 960 is configured to perform a different part of the processing method. For example, processing chamber 930 is configured to perform an anisotropic etching process, processing chamber 940 is configured to perform an isotropic etching process, processing chamber 945 is configured to function as a measurement station or to perform a first selective epitaxial growth process, and processing chamber 960 may be configured to perform a second epitaxial growth process. Those skilled in the art will understand that the number and arrangement of the individual processing chambers on the tool can be changed, and the embodiment shown in FIG. 9 represents only one possible configuration.

[0042]

[0044] In some embodiments, processing system 900 includes one or more measurement stations. For example, the measurement station may be located within pre-cleaning / buffer chamber 920, within central transfer station 910, or within any of the individual processing chambers. The measurement station can be located at any position within system 900 that enables measurement of the distance of the recess without exposing the substrate to an oxidizing environment.

[0043]

[0045] At least one controller 950 is coupled to one or more of central transfer station 910, pre - cleaning / buffer chamber 920, processing chambers 930, 940, 945, or 960. In some embodiments, there are two or more controllers 950 coupled to individual chambers or stations, and a main control processor is coupled to each of the separate processors to control system 900. Controller 950 can be one of any form of general - purpose computer processor, micro - controller, micro - processor, etc. that can be used in an industrial environment to control various chambers and sub - processors.

[0044]

[0046] At least one controller 950 can have a processor 952, a memory 954 coupled to the processor 952, an input / output device 956 coupled to the processor 952, and a support circuit 958 for communication between different electronic components. Memory 954 can include one or more of temporary memory (e.g., random - access memory) and non - temporary memory (e.g., storage).

[0045]

[0047] The memory 954 of the processor or the computer - readable medium can be one or more of random - access memory (RAM), read - only memory (ROM), floppy disk, hard disk, or any other form of digital storage, local or remote, easily accessible memory. Memory 954 can hold an instruction set operable by processor 952 to control the parameters and components of system 900. Support circuit 958 is coupled to processor 952 to support the processor in a conventional manner. The circuit can include, for example, cache, power supply, clock circuit, input / output circuit, subsystems, etc.

[0046]

[0048] The process can generally be stored in memory as a software routine that, when executed by a processor, causes the process of the present disclosure to be executed in a process chamber. The software routine can also be stored and / or executed by a second processor (not shown) that is remotely located from the hardware controlled by the processor. Some or all of the methods of the present disclosure may also be executed in hardware. Thus, the process can be implemented in software, using a computer system, or in hardware, such as, for example, as an application specific integrated circuit or other type of hardware implementation, or as a combination of software and hardware. When executed by a processor, the software routine converts a general purpose computer into a specific purpose computer (controller) that controls chamber operation such that the process is executed.

[0047]

[0049] In some embodiments, the controller 950 has one or more configurations for executing individual processes or sub - processes to perform the method. The controller 950 can be connected to intermediate components and configured to operate the intermediate components to perform the functions of the method. For example, the controller 950 can be connected to and configured to control one or more of a gas valve, an actuator, a motor, a slit valve, a vacuum control, etc.

[0048]

[0050] The controller 950 of some embodiments has one or more configurations selected from a configuration for moving a substrate on a robot between a plurality of processing chambers and a measurement station, a configuration for loading and / or unloading the substrate from the system, a configuration for depositing a dopant film, a configuration for annealing the substrate, and a configuration for depositing a semiconductor material.

[0049]

[0051] Throughout this specification, references to "one embodiment", "a particular embodiment", "one or more embodiments", or "an embodiment" mean that a particular feature, structure, material, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of the phrases "in one or more embodiments", "in a particular embodiment", "in one embodiment", or "in an embodiment" in various places throughout this specification are not necessarily referring to the same embodiment of the present disclosure. Furthermore, the particular features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments.

[0050]

[0052] The disclosure of this specification has been described with reference to particular embodiments, but those skilled in the art will understand that the described embodiments are merely examples of the principles and applications of the present disclosure. It will be apparent to those skilled in the art that various modifications and variations can be made to the methods and apparatuses of the present disclosure without departing from the spirit and scope of the present disclosure. Accordingly, the present disclosure may include modifications and variations within the scope of the appended claims and their equivalents.

Claims

1. A method of forming an electronic device, comprising: Selectively depositing a dopant film, which consists essentially of a dopant and is substantially conformal, on a first exposed surface of a semiconductor material at a temperature in the range of 600°C to 900°C with respect to a second surface containing an oxide material; Annealing the electronic device to drive dopant atoms from the dopant film into the semiconductor material, and forming a conformally doped semiconductor material with substantially no dopant atoms driven into the oxide material; Including: The method, wherein the first surface includes a portion where the exposed surface of the semiconductor material faces downward.

2. The method according to claim 1, wherein the downward-facing portion is a portion where the surface of the fin faces downward.

3. The method according to claim 1 or 2, wherein selectively depositing the dopant film includes exposing the first surface and the second surface to a boron precursor at a temperature in the range of 600°C to 900°C, and the dopant film consists essentially of boron.

4. The method according to claim 3, wherein the boron precursor includes one or more of borane, diborane, triborane, tetraborane, or pentaborane.

5. The method according to any one of claims 1 to 4, wherein annealing is performed at a temperature in the range of 1000°C to 1300°C.

6. The method according to any one of claims 1 to 5, wherein the dopant film has a thickness in the range of 2 to 10 monolayers.

7. The method according to any one of claims 1 to 6, wherein the dopant atoms are driven into the semiconductor material to a depth of 1 nm or more.

8. The conformally doped semiconductor material has two boron atoms at the first surface of the semiconductor material. ２０ pieces / cm ３ 8. The method of claim 1 , having a dopant concentration of at least 100% by mass.

9. The conformally doped semiconductor material has a dopant concentration of 5 boron atoms / cm ２０ or more at the first surface, according to any one of claims 1 to 8. ２０ per cm ３ ３ ​

10. The method according to claim 1 or 2, wherein the dopant film consists essentially of phosphorus.

11. The method according to claim 1 or 2, wherein the dopant film consists essentially of arsenic.

12. A method of forming an electronic device, comprising: Providing a substrate having a first surface containing a semiconductor material and a second surface containing an oxide material, wherein the first surface includes a portion where the exposed surface of the semiconductor material faces downward. Exposing the first surface and the second surface to a boron precursor at a temperature in the range of 700°C to 800°C to selectively deposit a conformal dopant film, wherein the conformal dopant film is deposited on the first surface so as to exceed the second surface, and the conformal dopant film consists essentially of boron, selectively depositing a conformal dopant film; Annealing the electronic device by millisecond annealing at a temperature in the range of 1150°C to 1200°C to drive boron atoms from the conformal dopant film into the semiconductor material, and conformally doping the semiconductor material with substantially no dopant atoms driven into the oxide material; A method comprising.

13. wherein the boron precursor is borane (BH ３ ), diborane (B ２ H ６ ), chloroborane (BH ２ Cl), trimethylborane (B(CH ３ )) ３ or triethylborane (B(C ２ H ５ )) ３ ), the method according to claim 12, comprising one or more of them.

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