Semiconductor device

Abstract

To provide a semiconductor device capable of reducing a leakage current.SOLUTION: A semiconductor device according to embodiments includes a first electrode, a first conductivity-type first semiconductor region, a second conductivity-type second semiconductor region, a first conductivity-type third semiconductor region, a conductive body, a gate electrode, and a second electrode. The first semiconductor region is provided on the first electrode. The second semiconductor region is provided on the first semiconductor region. The third semiconductor region is provided on a portion of the second semiconductor region. The conductive body is provided inside the first semiconductor region with an insulating part interposed. A lower surface of the conductive body includes a first surface parallel to a second direction orthogonal to a first direction, the first direction being from the first electrode toward the first semiconductor region, and a second surface linked to the first surface, the second surface being oblique to the first and second directions. The gate electrode is provided inside the insulating part, the gate electrode facing the second semiconductor region via a gate insulating layer in the second direction. The second electrode is provided on the second and third semiconductor regions.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor devices.

Background Art

[0002] Semiconductor devices such as Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) are used, for example, in power conversion. Reduction of leakage current is required for semiconductor devices.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] The problem to be solved by the present invention is to provide a semiconductor device capable of reducing leakage current.

Means for Solving the Problems

[0005] The semiconductor device according to the embodiment includes a first electrode, a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type, a conductor, a gate electrode, and a second electrode. The first semiconductor region is provided on the first electrode and is electrically connected to the first electrode. The second semiconductor region is provided on the first semiconductor region. The third semiconductor region is provided on a part of the second semiconductor region. The conductor is provided in the first semiconductor region via an insulating portion. The lower surface of the conductor includes a first surface parallel to a second direction orthogonal to a first direction from the first electrode toward the first semiconductor region, and a second surface connected to the first surface and inclined with respect to the first direction and the second direction. The gate electrode is provided in the insulating portion and faces the second semiconductor region in the second direction with a gate insulating layer interposed therebetween. The second electrode is provided on the second semiconductor region and the third semiconductor region and is electrically connected to the second semiconductor region and the third semiconductor region.

Brief Description of the Drawings

[0006]

Figure 1

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Embodiments for Carrying Out the Invention

[0007] Hereinafter, each embodiment of the present invention will be described with reference to the drawings. The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the ratio of the sizes between parts, etc. are not necessarily the same as the actual ones. Even when representing the same part, there are cases where their dimensions and ratios are represented differently in the drawings. In the present specification and each figure, the same elements as those already described are denoted by the same reference numerals, and detailed descriptions are omitted as appropriate. In the following description and drawings, n + , n - , p + , and the notations of p represent the relative levels of the respective impurity concentrations. That is, the notation with “+” attached has a relatively higher impurity concentration than the notation without either “+” or “-” attached, and the notation with “-” attached indicates that the impurity concentration is relatively lower than the notation without either attached. When both p-type impurities and n-type impurities are included in each region, these notations represent the relative levels of the net impurity concentration after these impurities compensate for each other. Regarding each embodiment described below, each embodiment may be implemented by inverting the p-type and n-type of each semiconductor region.

[0008] FIG. 1 is a perspective cross-sectional view showing a part of a semiconductor device according to an embodiment. As shown in FIG. 1, the semiconductor device 100 according to the embodiment includes an n - -type (first conductivity type) drift region 1 (first semiconductor region), a p-type (second conductivity type) base region 2 (second semiconductor region), an n + -type source region 3 (third semiconductor region), a p + -type contact region 4, an n +It includes an n-shaped drain region 5, a conductor 10, an insulating portion 21, a gate electrode 30, a drain electrode 41 (first electrode), and a source electrode 42 (second electrode). The semiconductor device 100 is, for example, a MOSFET.

[0009] In the description of the embodiment, an XYZ orthogonal coordinate system is used. The direction from the drain electrode 41 toward the n - -shaped drift region 1 is defined as the Z direction (first direction). One direction orthogonal to the Z direction is defined as the X direction (second direction). The direction orthogonal to both the X direction and the Z direction is defined as the Y direction. Also, here, the direction from the drain electrode 41 toward the n - -shaped drift region 1 is referred to as "up", and the opposite direction is referred to as "down". These directions are based on the relative positional relationship between the drain electrode 41 and the n - -shaped drift region 1 and are independent of the direction of gravity.

[0010] The drain electrode 41 is provided on the lower surface of the semiconductor device 100. The n + -shaped drain region 5 is provided above the drain electrode 41 and is electrically connected to the drain electrode 41. The n - -shaped drift region 1 is provided above the n + -shaped drain region 5. The n-type impurity concentration in the n - -shaped drift region 1 is lower than the n-type impurity concentration in the n + -shaped drain region 5. The n - -shaped drift region 1 is electrically connected to the drain electrode 41 via the n + -shaped drain region 5.

[0011] The p-type base region 2 is provided above the n - -shaped drift region 1. The p + -shaped source region 3 is provided on a part of the p-type base region 2. The p + -shaped contact region 4 is provided on another part of the p-type base region 2. The p-type impurity concentration in the p + -shaped contact region 4 is higher than the p-type impurity concentration in the p-type base region 2.

[0012] The conductor 10 is provided in the n - -type drift region 1 via the insulating portion 21. The gate electrode 30 is provided in the insulating portion 21 and is located above the conductor 10. The gate electrode 30 is provided in the insulating portion 21 and faces the p-type base region 2 via the gate insulating layer 31 in the X direction. The gate insulating layer 31 is a part of the insulating portion 21. In the illustrated example, the gate electrode 30 also faces a part of the n - -type drift region 1 and a part of the n + -type source region 3.

[0013] The source electrode 42 is provided on the n + -type source region 3 and the p + -type contact region 4, and is electrically connected to the n + -type source region 3 and the p + -type contact region 4. In the illustrated example, a part of the source electrode 42 extends downward and is provided between a pair of n + -type source regions 3 arranged in the X direction. The p-type base region 2 is electrically connected to the source electrode 42 via the p + -type contact region 4. The gate electrode 30 is electrically separated from the source electrode 42 by the gate insulating layer 31.

[0014] Each of the p-type base region 2, the n + -type source region 3, the p + -type contact region 4, the conductor 10, and the gate electrode 30 extends in the Y direction and a plurality of them are provided in the X direction. The end portion of the conductor 10 in the Y direction is pulled upward and is electrically connected to the source electrode 42. Alternatively, the insulating portion 21 may not be provided between the conductor 10 and the gate electrode 30, and the conductor 10 may be electrically connected to the gate electrode 30.

[0015] FIG. 2 is an enlarged cross-sectional view of a part of FIG. 1. As shown in FIG. 2, the lower surface of the conductor 10 includes a first surface S1, a second surface S2, and a third surface S3. The first surface S1 is parallel to the X-Y plane. The second surface S2 and the third surface S3 are connected to the first surface S1 and are inclined with respect to the X direction and the Z direction. The position of the first surface S1 in the X direction is between the position of the second surface S2 in the X direction and the position of the third surface S3 in the X direction.

[0016] More specifically, the conductor 10 includes a first conductive portion 11, a second conductive portion 12, and a third conductive portion 13. The first conductive portion 11 is located at the lower end of the conductor 10. The second conductive portion 12 is provided above the first conductive portion 11. The third conductive portion 13 is provided above the second conductive portion 12.

[0017] The first conductive portion 11 has the first surface S1 to the third surface S3. The width (length in the X direction) W1 of the first conductive portion 11 is longer than the width W2 of the second conductive portion 12. The width W2 of the second conductive portion 12 may be shorter than the width W3 of the third conductive portion 13. The width W2 of the second conductive portion 12 may be the same as the width W3 of the third conductive portion 13.

[0018] The first conductive portion 11 includes a first portion 11a and a second portion 11b. The first portion 11a has the first surface S1 to the third surface S3. The second portion 11b is provided above the first portion 11a. The width of the first portion 11a becomes longer upward. The width of the second portion 11b becomes shorter upward. For example, the length of the first portion 11a in the Z direction is shorter than the length of the second portion 11b in the Z direction.

[0019] As shown in the figure, a void V may be provided in the first conductive portion 11. The void V provided in the first conductive portion 11 extends in the Y direction. Or, in the Y direction, a plurality of voids V may be scattered.

[0020] The operation of the semiconductor device 100 will be described. With a positive voltage applied to the drain electrode 41 with respect to the source electrode 42, a voltage equal to or higher than the threshold value is applied to the gate electrode 30. As a result, a channel (inversion layer) is formed in the p-type base region 2, and the semiconductor device 100 is turned on. Electrons flow from the source electrode 42 to the drain electrode 41 through the channel. When the voltage applied to the gate electrode 30 becomes lower than the threshold value, the channel in the p-type base region 2 disappears, and the semiconductor device 100 turns off.

[0021] When the semiconductor device 100 switches to the off state, the positive voltage applied to the drain electrode 41 with respect to the source electrode 42 increases. At this time, due to the potential difference between the drain electrode 41 and the source electrode 42 or the potential difference between the drain electrode 41 and the gate electrode 30, a depletion layer spreads from the interface between the insulating portion 21 and the n - -type drift region 1 toward the n - -type drift region 1. Due to the spread of this depletion layer, the breakdown voltage of the semiconductor device 100 can be increased. Alternatively, while maintaining the breakdown voltage of the semiconductor device 100, the n-type impurity concentration in the n - -type drift region 1 can be increased to reduce the on-resistance of the semiconductor device 100.

[0022] An example of the material of each component of the semiconductor device 100 will be described. n - -type drift region 1, p-type base region 2, n + -type source region 3, p + -type contact region 4, and n + -type drain region 5 contain a semiconductor material. As the semiconductor material, silicon, silicon carbide, gallium nitride, or gallium arsenide can be used. When silicon is used as the semiconductor material, arsenic, phosphorus, or antimony can be used as the n-type impurity. Boron can be used as the p-type impurity.

[0023] The insulating portion 21 contains an insulating material. For example, the insulating portion 21 contains silicon oxide, silicon nitride, or silicon oxynitride. The conductor 10 and the gate electrode 30 contain a conductive material such as polysilicon. n-type or p-type impurities may be added to the conductor 10 and the gate electrode 30. The drain electrode 41 and the source electrode 42 contain a metal such as titanium, tungsten, or aluminum.

[0024] Figs. 3 to 6 are cross-sectional views showing a method of manufacturing a semiconductor device according to an embodiment. With reference to Figs. 3 to 6, an example of a method of manufacturing the semiconductor device 100 according to the embodiment will be described. First, a semiconductor substrate Sub including an n-type semiconductor layer 5a is prepared. As shown in Fig. 3(a), an n-type semiconductor layer 1a is formed by epitaxially growing silicon on the n-type semiconductor layer 5a. + As shown in Fig. 3(a), an n-type semiconductor layer 1a is formed by epitaxially growing silicon on the n-type semiconductor layer 5a. + On the n-type semiconductor layer 5a, an n-type semiconductor layer 1a is formed by epitaxially growing silicon. - On the n-type semiconductor layer 5a, an n-type semiconductor layer 1a is formed by epitaxially growing silicon.

[0025] As shown in Fig. 3(b), a plurality of trenches T1 are formed on the upper surface of the n-type semiconductor layer 1a by photolithography and reactive ion etching (RIE). When performing RIE, an etching gas with gentle anisotropy is used. Thereby, the lower surface of the trench T1 can be curved. On this curved surface, {100} plane, {110} plane, etc. of silicon appear. As the etching gas, sulfur hexafluoride (SF - ) can be used. 6 ) can be used.

[0026] As shown in Fig. 4(a), n -An insulating layer 21a is formed along the upper surface of the V-shaped semiconductor layer 1a and the inner surface of the trench T1. The insulating layer 21a is formed by thermal oxidation. At this time, oxidation proceeds along the

[0100] direction and the

[0110] direction of silicon. As a result, a flat surface S1a, an inclined surface S2a, and an inclined surface S3a are formed on the lower surface of the trench T2 surrounded by the insulating layer 21a. The {100} plane of silicon oxide appears on the flat surface S1a. The {110} plane of silicon oxide appears on the inclined surfaces S2a and S3a. Also, when the insulating layer 21a is formed, the width of the bottom of the trench T2 becomes wider than that of its upper part. This is considered to be affected by the stress during thermal oxidation, as will be described later.

[0027] Note that for silicon and silicon oxide, the {100} plane indicates any one of the mutually equivalent (100) plane, (010) plane, or (001) plane. Also, the {110} plane indicates any one of the mutually equivalent (110) plane, (011) plane, or (101) plane.

[0028] A conductive layer 10a for filling the trench T2 is formed on the insulating layer 21a. The conductive layer 10a is formed by chemical vapor deposition (CVD) of a conductive material such as polysilicon. When the conductive layer 10a is formed, voids V are formed at the bottom of the trench T2. A part of the conductive layer 10a is removed by chemical dry etching (CDE) or the like to retreat the upper surface of the conductive layer 10a. As a result, a plurality of conductive layers 10a are formed separately in the plurality of trenches T2. As shown in Fig. 4(b), an insulating layer 21b is formed by CVD on the insulating layer 21a and the plurality of conductive layers 10a. The conductive layer 10a has a first surface S1 in contact with the flat surface S1a. Also, the conductive layer 10a has a second surface S2 and a third surface S3 in contact with the inclined surfaces S2a and S3a, respectively.

[0029] By wet etching, the upper surface of the insulating layer 21a and the upper surface of the insulating layer 21b are retreated. As a result, part of the upper surface of the V-shaped semiconductor layer 1a and the side surface of the trench T1 are exposed. By thermal oxidation, the exposed V-shaped semiconductor layer 1a - and a part of the side surface of the trench T1 are exposed. By thermal oxidation, the exposed V-shaped semiconductor layer 1a -An insulating layer 31a is formed on the upper surface of the n-shaped semiconductor layer 1a and the side surfaces of the trenches T1. The thickness of the insulating layer 31a is smaller than the thickness of the insulating layer 21a. A conductive layer 30a is formed on the insulating layer 31a. As shown in FIG. 5(a), the upper surface of the conductive layer 30a is recessed by CDE or wet etching, and the conductive layer 30a is formed inside each trench T1.

[0030] n between the trenches T1 - p-type impurities and n-type impurities are sequentially ion-implanted into the upper portion of the n-shaped semiconductor layer 1a to form a p-type semiconductor region 2a and an n + -shaped semiconductor region 3a. As shown in FIG. 5(b), an insulating layer 31b is formed to cover the plurality of conductive layers 30a.

[0031] An opening OP is formed that penetrates the insulating layer 31b, the insulating layer 31a, and the n + -shaped semiconductor region 3a and reaches the p-type semiconductor region 2a. P-type impurities are ion-implanted into the p-type semiconductor region 2a through the opening OP, and as shown in FIG. 6(a), a p + -shaped semiconductor region 4a is formed.

[0032] A metal layer 42a is formed on the insulating layer 31b to fill the opening OP. Thereafter, the lower surface of the semiconductor substrate Sub is ground until the n + -shaped semiconductor layer 5a reaches a predetermined thickness. As shown in FIG. 6(b), a metal layer 41a is formed on the ground lower surface. Through the above steps, the semiconductor device 100 shown in FIG. 1 is manufactured.

[0033] The n shown in FIG. 6(b) - -shaped semiconductor layer 1a corresponds to the n-shaped drift region 1 shown in FIG. 1. The p-type semiconductor region 2a corresponds to the p-type base region 2. The n - -shaped semiconductor region 3a corresponds to the n + -shaped source region 3. The p + -shaped semiconductor region 4a corresponds to the p + -shaped contact region 4. The n + -shaped semiconductor layer 5a corresponds to the n + -shaped semiconductor layer 5 shown in FIG. 1. +It corresponds to the V-shaped drain region 5. The conductive layer 10a corresponds to the conductor 10. The insulating layers 21a and 21a correspond to the insulating portion 21. The conductive layer 30a corresponds to the gate electrode 30. The insulating layers 31a and 31b correspond to the gate insulating layer 31. The metal layer 41a corresponds to the drain electrode 41. The metal layer 42a corresponds to the source electrode 42.

[0034] The advantages of the semiconductor device according to the embodiment will be described. FIG. 7 is a cross-sectional view showing a part of a semiconductor device according to a reference example. In the semiconductor device 100r shown in FIG. 7, the conductor 10r has a bottom surface BS, a side surface SS1, and a side surface SS2. The bottom surface BS is parallel to the X-Y plane. The side surfaces SS1 and SS2 are parallel to the Y-Z plane. Therefore, the angles between the bottom surface BS and the side surface SS1 and between the bottom surface BS and the side surface SS2 are right angles.

[0035] When the semiconductor device 100r is in the off state, due to the potential difference between the drain electrode 41 and the source electrode 42, an electric field is generated between the n - -shaped drift region 1 and the conductor 10r. At this time, electric field concentration occurs at the corner at the lower end of the conductor 10r. Due to the large electric field, a leakage current flows through the insulating portion 21.

[0036] FIG. 8 is a graph schematically showing the characteristics of the semiconductor device. In FIG. 8, the horizontal axis represents the voltage Vds of the drain electrode 41 with respect to the source electrode 42. The vertical axis represents the current Id flowing between the drain electrode 41 and the source electrode 42. The solid line shows the characteristics of the semiconductor device according to the reference example. The broken line shows the characteristics of a desirable semiconductor device.

[0037] In a desirable semiconductor device, the current Id is small until the voltage reaches the breakdown voltage Vbd. When the voltage reaches the breakdown voltage Vbd, the current Id increases steeply. On the other hand, in the semiconductor device 100r according to the reference example, the current Id starts to increase at the voltage V1. The voltage V1 is smaller than the breakdown voltage Vbd. This is due to the leakage current flowing through the insulating portion 21. Also, when the voltage Vds further increases and reaches the voltage V2, the current Id increases steeply. This is due to the occurrence of avalanche breakdown starting from a portion with a high electric field strength in the insulating portion 21. As shown in FIG. 8, due to the leakage current flowing through the insulating portion 21, the substantial breakdown voltage of the semiconductor device 100 decreases from the original breakdown voltage Vbd to the voltage V2.

[0038] Regarding this problem, in the semiconductor device 100 according to the embodiment, the lower surface of the conductor 10 includes a first surface S1 and a second surface S2. The first surface S1 is parallel to the X direction. The second surface S2 connected to the first surface S1 is inclined with respect to the X direction and the Z direction. Therefore, the angle between the first surface S1 and the second surface S2 is less than 90 degrees. Thereby, compared with the semiconductor device 100r, the electric field strength in the vicinity of the lower end of the conductor 10 can be reduced. As a result, the flow of leakage current through the insulating portion 21 can be suppressed, and the breakdown voltage of the semiconductor device 100 can be improved.

[0039] If the angle between the first surface S1 and the second surface S2 is large, the effect of reducing the electric field strength weakens. On the other hand, if the angle is small, the width of the lower end of the conductor 10 becomes long. As a result, it becomes difficult to miniaturize the conductor 10, the insulating portion 21, etc., and the on-resistance of the semiconductor device 100 may increase. Therefore, the angle is preferably greater than 30 degrees and less than 60 degrees.

[0040] Also, the lower surface of the conductor 10 includes a third surface S3 connected to the first surface S1. The third surface S3 is inclined with respect to the X direction and the Z direction. Therefore, the angle between the first surface S1 and the third surface S3 is less than 90 degrees. Thereby, the electric field strength in the vicinity of the lower end of the conductor 10 can be further reduced. The angle between the first surface S1 and the third surface S3 is preferably greater than 30 degrees and less than 60 degrees.

[0041] As shown in FIG. 2, the conductor 10 includes a first conductive portion 11 and a second conductive portion 12. In the X direction, the length of the first conductive portion 11 is longer than the length of the second conductive portion 12. That is, the lower end of the conductor 10 bulges. According to this structure, similar to the structures of the first surface S1 to the third surface S3, the electric field strength in the vicinity of the first conductive portion 11 can be reduced.

[0042] As shown in FIGS. 1 and 2, the first conductive portion 11 preferably includes voids V. When the voids V are provided, the conductor 10 is more likely to deform according to the stress of the insulating portion 21 than when the voids V are not provided. Thereby, the stress of the insulating portion 21 is reduced. The stress applied to the n - type drift region 1 from the insulating portion 21 is reduced. As a result, the generation of crystal defects in the n - type drift region 1 due to stress can be suppressed.

[0043] The voids V preferably extend in the Y direction. In this case, the volume of the voids V becomes larger than when a plurality of voids V are scattered in the Y direction. Thereby, the stress of the insulating portion 21 is further reduced.

[0044] Also, in the semiconductor device 100, the bottom of the insulating portion 21 is located between the conductor 10 and the n - type drift region 1 in the Z direction. The side portion of the insulating portion 21 is located between the conductor 10 and the n - type drift region 1 in the X direction. According to the embodiment, the thickness T2a of the bottom of the insulating portion 21 can be increased, and the difference between the thickness T1a of the side portion of the insulating portion 21 and the thickness T2a can be reduced. As a result, the electric field strength in the insulating portion 21 can be reduced, and the leakage current flowing through the insulating portion 21 can be reduced.

[0045] The reason for the increase in the thickness T2a is considered as follows. When forming the insulating portion 21, a large compressive stress is generated at the bottom of the insulating portion 21. In the semiconductor device 100r shown in FIG. 7, the angle between the bottom surface BS and the side surface SS1 is substantially a right angle, and it is difficult to disperse the compressive stress at the bottom of the insulating portion 21. As a result, in the semiconductor device 100r, the thickness T2b at the bottom of the insulating portion 21 becomes small, and the difference between the thickness T1b and the thickness T2b at the side portion of the insulating portion 21 becomes large. On the other hand, in the semiconductor device 100, the second surface S2 connected to the first surface S1 is inclined with respect to the X direction and the Z direction. The dispersion of the compressive stress is less likely to be inhibited by a right angle. As a result, the compressive stress at the bottom of the insulating portion 21 decreases, and the thickness T2a increases.

[0046] In particular, for silicon oxide, the compressive stress in the

[0110] direction is smaller than the compressive stress in the

[0100] direction. When the insulating portion 21 contains silicon oxide, the {110} plane of silicon oxide exists on the contact surface of the insulating portion 21 with the second surface S2. As a result, the compressive stress at the portion of the insulating portion 21 in contact with the second surface S2 decreases. As a result, the compressive stress at the bottom of the insulating portion 21 is more likely to be dispersed, and the thickness T2a increases.

[0047] (Modification example) FIGS. 9 and 10 are perspective cross-sectional views showing a part of the semiconductor device according to the embodiment. The structure other than the lower end of the conductor 10, the structure of the gate electrode 30, etc. are not limited to the example shown in FIG. 1 and can be appropriately changed. For example, as in the semiconductor device 110 shown in FIG. 9, a plurality of gate electrodes 30 may be provided in one insulating portion 21. In the illustrated example, a pair of gate electrodes 30 are provided above the conductor 10. When viewed from the Z direction, the conductor 10 is located between the pair of gate electrodes 30 in the X direction.

[0048] Alternatively, as in the semiconductor device 120 shown in FIG. 10, the upper part of the conductor 10 may be located between the pair of gate electrodes 30 in the X direction.

[0049] In any form, since the lower surface of the conductor 10 includes the first surface S1 to the third surface S3, it is possible to suppress the leakage current from flowing through the insulating portion 21, and the breakdown voltage of the semiconductor device can be improved.

[0050] The specific shape of the lower surface of the conductor 10 is not limited to the above-described example. For example, the lower surface of the conductor 10 may have a curved shape instead of the first surface S1, the second surface S2, and the third surface S3. Also in this case, the electric field strength in the vicinity of the lower end of the conductor 10 can be reduced.

[0051] Regarding the relative levels of the impurity concentrations between the semiconductor regions in the embodiments described above, for example, it is possible to confirm using a scanning capacitance microscope (SCM). Note that the carrier concentration in each semiconductor region can be regarded as equal to the impurity concentration activated in each semiconductor region. Therefore, the relative levels of the carrier concentrations between the semiconductor regions can also be confirmed using the SCM. The impurity concentration in each semiconductor region can be measured by secondary ion mass spectrometry (SIMS).

[0052] For the analysis of the crystal orientation of the insulating portion 21 in contact with the lower surface of the conductor 10, the electron backscatter diffraction method (EBSD) can be used. For example, the vicinity of the interface between the conductor 10 and the insulating portion 21 is analyzed by EBSD. When the lower surface of the conductor 10 includes the first surface S1 to the third surface S3, in the analysis result, the intensity of the peak corresponding to the {100} plane of silicon oxide is greater than the intensity of the peaks corresponding to the other planes. When the lower surface of the conductor 10 has a curved shape, in the analysis result, a plurality of peaks respectively corresponding to a plurality of planes of silicon oxide appear.

[0053] As described above, several embodiments of the present invention have been illustrated. However, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, changes, etc. can be made without departing from the gist of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalent scope thereof. In addition, the above-described embodiments can be implemented in combination with each other.

Explanation of Reference Numerals

[0054] 1:n - Shape drift region, 1a:n - Shape semiconductor layer, 2:p-type base region, 2a:p-type semiconductor region, 3:n + Shape source region, 3a:n + Shape semiconductor region, 4:p + Shape contact region, 4a:p + Shape semiconductor region, 5:n + Shape drain region, 5a:n + Shape semiconductor layer, 10,10r: Conductor, 10a: Conductive layer, 11: First conductive part, 11a: First part, 11b: Second part, 12: Second conductive part, 13: Third conductive part, 21: Insulating part, 21a,21b: Insulating layer, 30: Gate electrode, 30a: Conductive layer, 31: Gate insulating layer, 31a,31b: Insulating layer, 41: Drain electrode, 41a: Metal layer, 42: Source electrode,, 42a: Metal layer, 100,100r: Semiconductor device, BS: Bottom surface, OP: Opening, S1: First surface, S1a: Flat surface, S2: Second surface, S2a: Inclined surface, S3: Third surface, S3a: Inclined surface, SS1,SS2: Side surface, Sub: Semiconductor substrate, T1,T2: Trench, T1a,T1b,T2a, T2b: Thickness, V: Void

Claims

1. a first electrode; a first semiconductor region of a first conductivity type provided on the first electrode and electrically connected to the first electrode; a second semiconductor region of a second conductivity type provided on the first semiconductor region; a third semiconductor region of a first conductivity type provided on a part of the second semiconductor region; a conductor provided in the first semiconductor region via an insulating portion, wherein a lower surface of the conductor has: a first surface parallel to a second direction orthogonal to a first direction from the first electrode toward the first semiconductor region; a second surface continuous with the first surface and inclined with respect to the first direction and the second direction; and includes: the conductor includes a first conductive portion having the first surface and the second surface, and a second conductive portion provided on the first conductive portion, and in the second direction, a length of the first conductive portion is longer than a length of the second conductive portion; the first conductive portion has: a first portion having the first surface and the second surface and having a longer length in the second direction toward an upper side; a second portion provided on the first portion and having a shorter length in the second direction toward an upper side; and includes the conductor; a gate electrode provided in the insulating portion and facing the second semiconductor region via a gate insulating layer in the second direction; a second electrode provided on the second semiconductor region and the third semiconductor region and electrically connected to the second semiconductor region and the third semiconductor region; a semiconductor device comprising the above.

2. the conductor further includes a third conductive portion provided on the second conductive portion; the semiconductor device according to claim 1, wherein in the second direction, a length of the second conductive portion is shorter than a length of the third conductive portion.

3. a {100} plane of silicon oxide exists on a surface of the insulating portion in contact with the first surface; a {110} plane of silicon oxide exists on a surface of the insulating portion in contact with the second surface; the semiconductor device according to claim 1 or 2.

4. a first electrode; a first semiconductor region of a first conductivity type provided on the first electrode and electrically connected to the first electrode; a second semiconductor region of a second conductivity type provided on the first semiconductor region; a third semiconductor region of a first conductivity type provided on a part of the second semiconductor region; a conductor provided in the first semiconductor region via an insulating portion, wherein a lower surface of the conductor has: a first surface parallel to a second direction orthogonal to a first direction from the first electrode toward the first semiconductor region; A second surface that is continuous with the first surface and is inclined with respect to the first direction and the second direction; including a conductor, wherein a {100} plane of silicon oxide exists on the surface of the insulating portion that contacts the first surface, and a {110} plane of silicon oxide exists on the surface of the insulating portion that contacts the second surface; a gate electrode provided in the insulating portion and facing the second semiconductor region through a gate insulating layer in the second direction; a second electrode provided on the second semiconductor region and the third semiconductor region and electrically connected to the second semiconductor region and the third semiconductor region; A semiconductor device comprising:

5. The conductor includes a first conductive portion having the first surface and the second surface, and a second conductive portion provided on the first conductive portion; The semiconductor device according to claim 4, wherein in the second direction, the length of the first conductive portion is longer than the length of the second conductive portion.

6. The conductor further includes a third conductive portion provided on the second conductive portion; The semiconductor device according to claim 5, wherein in the second direction, the length of the second conductive portion is shorter than the length of the third conductive portion.

7. The semiconductor device according to any one of claims 1 to 6, wherein a void is provided at the lower end of the conductor.

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